M58LW032D11N6T [STMICROELECTRONICS]
2MX16 FLASH 3V PROM, 110ns, PDSO56, 14 X 20 MM, PLASTIC, TSOP-56;型号: | M58LW032D11N6T |
厂家: | ST |
描述: | 2MX16 FLASH 3V PROM, 110ns, PDSO56, 14 X 20 MM, PLASTIC, TSOP-56 可编程只读存储器 光电二极管 内存集成电路 |
文件: | 总50页 (文件大小:277K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M58LW032D
32 Mbit (4Mb x8, 2Mb x16, Uniform Block)
3V Supply Flash Memory
PRODUCT PREVIEW
FEATURES SUMMARY
■ WIDE x8 or x16 DATA BUS for HIGH
Figure 1. Packages
BANDWIDTH
■ SUPPLY VOLTAGE
– V = 2.7 to 3.6V core supply voltage for Pro-
DD
gram, Erase and Read operations
– V
= 1.8 to V for I/O Buffers
DD
DDQ
■ ACCESS TIME
TSOP56 (N)
– Random Read 110ns
14 x 20 mm
– Page Mode Read 110/25ns
■ PROGRAMMING TIME
– 16 Word Write Buffer
TBGA
– 16µs Word effective programming time
■ 32 UNIFORM 64 KWord/128KByte MEMORY
BLOCKS
■ BLOCK PROTECTION/ UNPROTECTION
■ PROGRAM and ERASE SUSPEND
■ 128 bit PROTECTION REGISTER
■ COMMON FLASH INTERFACE
TBGA64 (ZA)
10 x 13 mm
■ 100, 000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code M58LW032D: 8821h
July 2002
1/50
This is preliminary information on a new product now in development. Details are subject to change without notice.
M58LW032D
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. TBGA64 Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enables (E0, E1, E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Status/(Ready/Busy) (STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program/Erase Enable (V
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PEN
V
DD
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input/Output Supply Voltage (V
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DDQ
Ground (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SS
Ground (V
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SSQ
Table 2. Device Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Word/Byte Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M58LW032D
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Configure STS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Word-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Byte-Wide Read Protection Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 19
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VPEN Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Bus Read AC Characteristics.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 31
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M58LW032D
Table 20. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 31
Figure 15. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline. . . . . . . . . . . . . . . 32
Table 21. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data. . . . . . . 32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 26. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 27. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 28. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 29. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 30. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 16. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 40
Figure 17. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 41
Figure 18. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 43
Figure 20. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 21. Block Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 46
Figure 23. Command Interface and Program Erase Controller Flowchart (a). . . . . . . . . . . . . . . . 47
Figure 24. Command Interface and Program Erase Controller Flowchart (b). . . . . . . . . . . . . . . . 48
Figure 25. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 49
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M58LW032D
SUMMARY DESCRIPTION
The M58LW032D is a 32 Mbit (4Mb x 8 or 2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7V to 3.6V)
core supply.
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera-
tions are blocked whenthe Program Erase Enable
input V
is low.
PEN
The memory is divided into 32 blocks of 1Mbit that
can be erased independently so it is possible to
preserve valid data while old data is erased. Pro-
gram and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Programor Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in power-down mode.
The STS pin gives information about the memory
status. It can be configured in two status: to output
a static signal about the status of P/E C (when low
P/E C is busy, when high P/E C is ready for a new
operation) or to give a pulsing signal to indicate
the end of programming or erasing blocks. In this
last configuration it supplies asystem interrupt sig-
nal useful for saving time.
The Bus operations of the device are controlled by
Output Enable, Write Enable and three different
Chip Enables. Refer to Table 2, Device Enable, for
all possible combinations to enable and disable
the device. Together they allow simple, yet power-
ful, connection to most microprocessor, often with-
out additional logic.
The device includes a 128 bit Protection Register.
The Protection Register is divided into two 64 bit
segments, the first one is written by the manufac-
turer (contact STMicroelectronics to define the
code to be written here), while the second one is
programmable by the user. The user programma-
ble segment can be locked.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
Individual block protection against Program or
Erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10x13mm, 1mm pitch) packages.
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M58LW032D
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A21
BYTE
DQ0-DQ15
E0
Address inputs
V
V
DD DDQ
Byte/Word Organization Select
Data Inputs/Outputs
Chip Enable
22
E1
Chip Enable
A0-A21
E2
Chip Enable
V
PEN
G
Output Enable
16
BYTE
W
RP
Reset/Power-Down
Status/(Ready/Busy)
Program/Erase Enable
Write Enable
DQ0-DQ15
STS
M58LW032D
STS
V
PEN
E0
G
W
V
Supply Voltage
DD
RP
E1
E2
V
V
V
Input/Output Supply Voltage
Ground
DDQ
SS
Input/Output Ground
Not Connected Internally
Do Not Use
SSQ
NC
DU
V
V
SS SSQ
AI06234
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M58LW032D
Figure 3. TSOP56 Connections
NC
1
56
NC
W
E1
A21
A20
A19
A18
A17
A16
G
STS
DQ15
DQ7
DQ14
DQ6
V
V
DD
A15
A14
A13
A12
E0
SS
DQ13
DQ5
DQ12
DQ4
14
15
43
42
V
V
DDQ
SSQ
M58LW032D
V
PEN
RP
DQ11
A11
A10
A9
DQ3
DQ10
DQ2
A8
V
DD
V
DQ9
DQ1
DQ8
DQ0
SS
A7
A6
A5
A4
A3
A2
A1
A0
BYTE
NC
E2
28
29
AI06235
7/50
M58LW032D
Figure 4. TBGA64 Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A1
A2
A6
A8
A9
V
A13
A14
V
A18
A19
DU
E1
PEN
E0
DD
V
DU
DU
SS
A3
A7
A10
A11
DQ9
DQ10
DQ2
A12
RP
A15
A20
A21
A17
STS
G
A4
A5
DQ1
DQ0
A0
DU
DU
A16
DQ8
DQ3
DQ11
DQ4
DQ12
DQ5
DQ13
DU
DQ15
DU
BYTE
DU
DU
G
H
V
DQ6
DQ14
DQ7
W
DDQ
E2
DU
V
V
V
DU
DD
SSQ
SS
AI06236
8/50
M58LW032D
Figure 5. Block Addresses
Byte (x8) Bus Width
Word (x16) Bus Width
3FFFFFh
1FFFFFh
1 Mbit or
1 Mbit or
128 KBytes
64 KWords
3E0000h
3DFFFFh
1F0000h
1EFFFFh
1 Mbit or
1 Mbit or
128 KBytes
64 KWords
3C0000h
1E0000h
Total of 32
1 Mbit Blocks
03FFFFh
01FFFFh
1 Mbit or
1 Mbit or
128 KBytes
64 KWords
020000h
01FFFFh
010000h
00FFFFh
1 Mbit or
1 Mbit or
128 KBytes
64 KWords
000000h
000000h
AI06238b
Note: Also see Appendix A, Table 24 for a full listing of the Block Addresses
9/50
M58LW032D
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Reset/Power-Down (RP). The
Down pin can be used to apply a Hardware Reset
to the memory.
Reset/Power-
Address Inputs (A0-A21). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, V , for at least t
. When
PLPH
IL
Reset/Power-Down is Low, V , the Status Regis-
IL
ter information is cleared and the power consump-
tion is reduced to power-down level. The device is
deselected and outputs are high impedance. If Re-
set/Power-Down goes low, V ,during a Block
IL
The device must be enabled (refer to Table 2, De-
vice Enable) when selecting the addresses. The
address inputs are latched on the rising edge of
Write Enable or on the first edge of Chip Enables
E0, E1 or E2 that disable the device, whichever
occurs first.
Erase, a Write to Buffer and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the STS pin
stays low, V , for amaximum timing of t
BH,
+ t
IL
PLPH
PH-
until the completion of the Reset/Power-Down
pulse.
Data Inputs/Outputs (DQ0-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or the first edge of Chip En-
ables E0, E1 or E2 that disable the device, which-
ever occurs first.
After Reset/Power-Down goes High, V , the
IH
memory will be ready for Bus Read and Bus Write
operations after t
. Note that STS does not fall
PHQV
during a reset, see Ready/Busy Output section.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
Erase or Program operation, the memory may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
When the device is enabled and Output Enable is
low, V (refer to Table 2, Device Enable), the data
IL
bus outputs data from the memory array, the Elec-
tronic Signature, the Block Protection status, the
CFI Information or the contents of the Status Reg-
ister. The data bus is high impedance when the
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 bus widths of the
memory. When Byte/Word Organization Select is
device isdeselected, Output Enable is high, V or
Low, V , the memory is in x8 mode, when it is
IH,
IL
the Reset/Power-Down signal is low, V . When
High, V , the memory is in x16 mode.
IL
IH
the Program/Erase Controller is active the Ready/
Status/(Ready/Busy) (STS). The STS signal is
an open drain output that can be used to identify
the Program/Erase Controller status. It can be
configured in two modes:
Busy status is given on DQ7.
Chip Enables (E0, E1, E2). The Chip Enable in-
puts E0, E1 and E2 activate the memory control
logic, input buffers, decoders and sense amplifi-
ers. The device is selected at the first edge of Chip
Enables E0, E1 or E2 that enable the device and
deselected at the first edge of Chip Enables E0,
E1 or E2 that disable the device. Refer to Table 2,
Device Enable for more details.
■ Ready/Busy - the pin is Low, V , during
OL
Program and Erase operations and high
impedance when the memory is ready for any
Read, Program or Erase operation.
■ Status - the pin gives apulsing signal to indicate
the end of a Program or Block Erase operation.
When the Chip Enable inputs deselect the memo-
ry, power consumption is reduced to the Standby
After power-up or reset the STS pin is configured
in Ready/Busy mode. The pin can be configured
for Status mode using the Configure STS com-
mand.
level, I
.
DD1
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
When the Program/Erase Controller is idle, or sus-
pended, STS can float High through a pull-up re-
sistor. The use of an open-drain output allows the
STS pins from several memories to be connected
to a single pull-up resistor (a Low will indicate that
one, or more, of the memories is busy).
a readoperation. WhenOutput Enable, G, is at V
IH
the outputs are high impedance.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able.
10/50
M58LW032D
STS is not Low during a reset unless the reset was
applied when the Program/Erase controller was
active.
Input/Output Supply Voltage (V
). The In-
DDQ
put/Output Supply Voltage, V
, is the input/out-
DDQ
put buffer power supply. All input and output pins
and voltage references are powered and mea-
sured relative to the Input/Output Supply Voltage
Program/Erase Enable (V
). The Program/
is used to protect all
PEN
Erase Enable input, V
PEN,
pin, V
.
DDQ
blocks, preventing Program and Erase operations
from affecting their data.
The Input/Output Supply Voltage, V
, must al-
DDQ
Supply Volt-
ways be equal or less than the V
age, including during Power-Up.
DD
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
A 0.1µF capacitor should be connected between
the Input/Output Supply Voltage, V , and the
DDQ
Ground, V
from the power supply. If V
nected together then only one decoupling capaci-
, to decouple the current surges
SSQ
V
Supply Voltage. The Supply Voltage, V
,
DD
DD
and V are con-
DDQ
DD
is the core power supply. All internal circuits draw
their current from the V
gram/Erase Controller.
pin, including the Pro-
DD
tor is required.
Ground (V ). Ground, V
is the reference for
SS,
SS
A 0.1µF capacitor should be connected between
the Supply Voltage, V , and the Ground, V , to
all core power supply voltages.
DD
SS
decouple the current surges from the power sup-
ply. The PCB track widths must be sufficient to
carry the currents required during all operations of
the parts, see Table 14, DC Characteristics, for
maximum current supply requirements.
Ground (V ). Ground, V
is the reference
SSQ,
SSQ
for input/output voltage measurements. It is es-
sential to connect V and V to the same
SS
SSQ
ground
.
Table 2. Device Enable
E2
E1
E0
Device
V
V
V
V
V
V
V
V
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
IL
IL
IL
IL
IL
IL
IL
V
IH
V
V
V
IH
IH
IL
V
IH
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
V
V
V
V
IH
V
V
IH
IH
IL
V
IH
Note: For single device operations, E2 and E1 can be connected to V
.
SS
11/50
M58LW032D
BUS OPERATIONS
There are 6 bus operations that control the mem-
ory. Each of these is described in this section, see
Tables 3, Bus Operations, for a summary.
On Power-up or after a Hardware Reset the mem-
ory defaults to Read Array mode (Page Read).
puts and enabling the device (refer to Chip Enable
section).
The Address Inputs are latched by the Command
Interface on the rising edge of Write Enable or the
first edge of E0, E1 or E2 that disables the device
(refer to Table 2, Device Enable). The Data Input/
Outputs are latched by the Command Interface on
the rising edge of Write Enable or the first edge of
E0, E1 or E2 that disable the device whichever oc-
curs first .
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers (Electronic Sig-
nature, Status Register, CFI and Block Protection
Status) in the Command Interface.
Output Enable must remain High, V , during the
IH
whole Bus Write operation. See Figures 11, and
12, Write AC Waveforms, and Tables 17 and 18,
Write and Chip Enable Controlled Write AC Char-
acteristics, for details of the timing requirements.
A valid bus operation involves setting the desired
address on the Address inputs, enabling the de-
vice (refer to Table 2, Device Enable), applying a
Output Disable. The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Low signal, V , to Output Enable and keeping
IL
Write Enable High, V .
IH
The Data Inputs/Outputs will output the value, see
Figure 9, Bus Read AC Waveforms, and Table 15,
Bus Read AC Characteristics, for details of when
the output becomes valid.
Page Read. Page Read operations are used to
read from several addresses within the same
memory page.
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high imped-
ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Standby Supply Current, I
.
DD1
During Program or Erase operations the memory
will continue to use the Program/Erase Supply
Each memory page is a 4 Words or 8 Bytes and
has thesame A3-A21. In x8 mode only A0, A1 and
A2 may change, in x16 mode only A1 and A2 may
change.
Current, I
, for Program or Erase operations un-
DD3
til the operation completes.
Automatic Low Power. If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the memory
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Valid bus operations are the same as Bus Read
operations but with different timings. The first read
operation within the page has identical timings,
subsequent reads within the same page have
much shorter access times. If the page changes
then the normal, longer timings apply again. See
Figure 10, Page Read AC Waveforms and Table
16, Page Read AC Characteristics for details on
when the outputs become valid.
Bus Write. Bus Write operations write to the
Command Interface in order to send commands to
the memory or to latch addresses and input data
to program.
Supply Current, I
. The Data Inputs/Outputs will
DD5
still output data if a Bus Read operation is in
progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
, and the outputs are high impedance,
DD2
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
independent of Chip Enable, Output Enable or
Write Enable.
12/50
M58LW032D
Table 3. Bus Operations
Bus Operation
E
G
W
RP
A0-A21
Address
Address
Address
X
DQ0-DQ15
Data Output
Data Output
Data Input
High Z
V
V
V
Bus Read
Page Read
Bus Write
High
High
High
High
High
IL
IL
IL
IL
IL
IL
IH
IH
V
V
V
V
V
V
V
V
IH
IH
IL
IH
V
V
Output Disable
Standby
X
X
X
High Z
IH
V
Power-Down
X
X
X
X
High Z
IL
Note: 1. X = Don’t Care V or V . High = V or V .
HH
IL
IH
IH
13/50
M58LW032D
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. The Commands are summarized in Table
4, Commands. Refer to Table 4 in conjunction with
the text descriptions below.
The Status Register information is present on the
output data bus (DQ1-DQ7) when the device is en-
abled and Output Enable is Low, V .
IL
See the section on the Status Register and Table
10 for details on the definitions of the Status Reg-
ister bits
After power-up or a Reset operation the memory
enters Read mode.
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Erase, Block Protect, Block
Unprotect or Protection Register Program com-
mand is issued. If any error occurs then it is essen-
tial to clear any error bits in the Status Register by
issuing the Clear Status Register command before
attempting a new Program, Erase or Resume
command.
Read Memory Array Command. The Read Mem-
ory Array command is used to return the memory
to Read mode. One Bus Write cycle is required to
issue the Read Memory Array command and re-
turn the memory to Read mode. Once the com-
mand is issued the memory remains in Read
mode until another command is issued. From
Read mode Bus Read operations will access the
memory array. After power-up or a reset the mem-
ory defaults to Read Array mode (Page Read).
While the Program/Erase Controller is executing a
Program, Erase, Block Protect, Blocks Unprotect
or Protection Register Program operation the
memory will not accept the Read Memory Array
command until the operation completes.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Protection Register.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once the com-
mand is issued subsequent Bus Read operations
read the Manufacturer Code, the Device Code, the
Block Protection Status or the Protection Register
until another command is issued. Refer to Table 6,
Read Electronic Signature, Tables 7 and 8, Word
and Byte-wide Read Protection Register and Fig-
ure 6, Protection Register Memory Map for infor-
mation on the addresses.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. It sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.
Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address in the internal state machine and
starts the Program/Erase Controller. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register. See the section on
the Status Register for details on the definitions of
the Status Register bits.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 9.
Read Query Command. The Read Query Com-
mand is used to read data from the Common Flash
Interface (CFI) Memory Area. One Bus Write cycle
is required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations read from the Common Flash In-
terface Memory Area. See Appendix B, Tables 25,
26, 27, 28, 29 and 30 for details on the information
contained in the Common Flash Interface (CFI)
memory area.
Read Status Register Command. The Read Sta-
tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued.
See Appendix C, Figure 18, Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.
Word/Byte Program Command. The
Word/
Byte Program command is used to program a sin-
gle Word or Byte in the memory array. Two Bus
Write operations are required to issue the com-
mand; the first write cycle sets up the Word Pro-
gram command, the second write cycle latches the
address and data to be programmed in the internal
state machine and starts the Program/Erase Con-
troller.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
14/50
M58LW032D
ing the Blocks Unprotect command or by using the
Blocks Temporary Unprotect feature of the Reset/
Power-Down pin, RP.
Write to Buffer and Program Command. The
Write to Buffer and Program command is used to
program the memory array.
gram or Write to Buffer and Program command if
the Program/Erase Controller is running.
One Bus Write cycle is required to issue the Pro-
gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con-
tinue to output the Status Register until another
command is issued.
Up to 16 Words/32 Bytes can be loaded into the
Write Buffer and programmed into the memory.
Each Write Buffer has the same A5-A21 address-
es. In Byte-wide mode only A0-A4 may change in
Word-wide mode only A1-A4 may change, in .
Four successive steps are required to issue the
command.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (bit 7) indicates that the Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter-
mine if the operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Table 9.
1. One Bus Write operation is required to set up
the Write to Buffer and Program Command. Is-
sue the set up command with the selected
memory Block Address where the program op-
eration should occur (any address in the block
where the values will be programmed can be
used). AnyBus Read operations will start to out-
put the Status Register after the 1st cycle.
2. Use one Bus Write operation to write the same
block address along with the value N on the
Data Inputs/Output, where N+1 is the number of
Words/Bytes to be programmed.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Write to Buffer and
Program, and the Program Suspend commands
will also be accepted. When a program operation
is completed inside a Block Erase Suspend the
Read Memory Array command must be issued to
reset the device in Read mode, then the Erase Re-
sume command can be issued to complete the
whole sequence. Only the blocks not being erased
may be read or programmed correctly.
3. Use N+1 Bus Write operations to load the ad-
dress and data for each Word into the Write
Buffer. See the constraints on the address com-
binations listed below. The addresses must
have the same A5-A21.
4. Finally, useone Bus Write operation to issue the
final cycle to confirm the command and start the
Program operation.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the oper-
ation without affecting the data in the memory ar-
ray. The Status Register should be cleared before
re-issuing the command.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command.
See Appendix C, Figure 17, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
19, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after
Pro-
See Appendix C, Figure 16, Write to Buffer and
Program Flowchart and Pseudo Code, for a sug-
gested flowchart on using the Write to Buffer and
Program command.
a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command. Once the com-
mand is issued subsequent Bus Read operations
read the Status Register.
Block Protect Command. The Block Protect
command is used to protect a block and prevent
Program or Erase operations from changing the
data in it. Two Bus Write cycles are required to is-
sue the Block Protect command; the second Bus
Write cycle latches the block address in the inter-
Program/Erase Suspend Command. The
Pro-
gram/Erase Suspend command is used to pause a
Word/Byte Program, Write to Buffer and Program
or Erase operation. The command will only be ac-
cepted during a Program or an Erase operation. It
can be issued at any time during an Erase opera-
tion but will only be accepted during a Word Pro-
15/50
M58LW032D
nal state machine and starts the Program/Erase
Controller. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister. See the section on the Status Register for
details on the definitions of the Status Register
bits.
The user-programmable segment can be locked
by programming bit 1 of the Protection Register
Lock location to ‘0’ (see Table 7 and x for Word-
wide and Byte-wide protection addressing). Bit 0
of the Protection Register Lock location locks the
factory programmed segment and is programmed
to ‘0’ in the factory. The locking of the Protection
Register is not reversible, once the lock bits are
programmed no further changes can be made to
the values stored in the Protection Register, see
Figure 6, Protection Register Memory Map. At-
tempting to program a previously protected Pro-
tection Register will result in a Status Register
error.
During the Block Protect operation the memory will
only accept the Read Status Register command.
All other commands will be ignored. Typical Block
Protection times are given in Table 9.
The Block Protection bits are non-volatile, once
set they remain set through reset and power-
down/power-up. They are cleared by a Blocks Un-
protect command.
The Protection Register Program cannot be sus-
pended. See Appendix C, Figure 22, Protection
Register Program Flowchart and Pseudo Code,
for the flowchart for using the Protection Register
Program command.
See Appendix C, Figure 20, Block Protect Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Protect command.
Blocks Unprotect Command. The Blocks Un-
protect command is used to unprotect all of the
blocks. Two Bus Write cycles are required to issue
the Blocks Unprotect command; the second Bus
Write cycle starts the Program/Erase Controller.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits.
Configure STS Command.
The Configure STS command is used to configure
the Status/(Ready/Busy) pin. After power-up or re-
set the STS pin is configured in Ready/Busy
mode. The pin can be configured in Status mode
using the Configure STS command (refer to Sta-
tus/(Ready/Busy) section for more details.
Two write cycles are required to issue the Config-
ure STS command.
■ The first bus cycle sets up the Configure STS
During the Block Unprotect operation the memory
will only accept the Read Status Register com-
mand. All other commands will be ignored. Typical
Block Protection times are given in Table 9.
command.
See Appendix C, Figure 21, Block Unprotect Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Unprotect command.
■ The second specifies one of the four possible
configurations (refer to Table 5, Configuration
Codes):
Protection Register Program Command. The
Protection Register Program command is used to
Program the 64 bit user segment of the Protection
Register. Two write cycles are required to issue
the Protection Register Program command.
– Ready/Busy mode
– Pulse on Erase complete mode
– Pulse on Program complete mode
– Pulse on Erase or Program complete mode
■ The first bus cycle sets up the Protection
The device will not accept the Configure STS com-
mand while the Program/Erase controller is busy
or during Program/Erase Suspend. When STS pin
is pulsing it remains Low for a typical time of
250ns. Any invalid Configuration Code will set an
error in the Status Register.
Register Program command.
■ The secondlatches the Address and theData to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
16/50
M58LW032D
Table 4. Commands
Command
Bus Operations
1st Cycle
2nd Cycle
Addr.
Subsequent
Final
Op. Addr. Data Op.
Data Op. Addr. Data Op. Addr. Data
Read Memory Array
≥ 2 Write
X
X
X
X
FFh Read
90h Read
70h Read
98h Read
RA
RD
(2)
(2)
Read Electronic Signature ≥ 2 Write
IDA
IDD
Read Status Register
Read Query
2
Write
X
SRD
(3)
(3)
≥ 2 Write
QA
QD
Clear Status Register
Block Erase
1
2
Write
Write
X
X
50h
20h Write
BA
PA
D0
PD
40h
Word/Byte Program
2
Write
X
Write
10h
Write to Buffer and
Program
4 + N Write BA
E8h Write
BA
N
Write PA PD Write
X
D0h
Program/Erase Suspend
Program/Erase Resume
Block Protect
1
1
2
2
Write
Write
X
X
B0h
D0h
Write BA
60h Write
60h Write
BA
X
01h
D0h
Blocks Unprotect
Write
Write
Write
X
X
X
Protection Register
Program
2
2
C0h Write
B8h Write
PRA
X
PRD
CC
Configure STS command
Note: 1. X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program
Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, PRA Protection register address,
PRD Protection Register Data, CC Configuration Code.
2. For Identifier addresses and data refer to Table 6, Read Electronic Signature.
3. For Query Address and Data refer to Appendix B, CFI.
Table 5. Configuration Codes
Configuration
DQ1 DQ2
Mode
STS Pin
Description
Code
V
during P/E
The STS pin is Low during Program and
Erase operations and high impedance when
the memory is ready for any Read, Program
or Erase operation.
OL
operations
Hi-Z when the
memory is ready
00h
0
0
Ready/Busy
Pulse on Erase
complete
Supplies a system interrupt pulse at the end
of a Block Erase operation.
01h
02h
0
1
1
0
Pulse Low then
High when
Pulse on
Program
complete
Supplies a system interrupt pulse at the end
of a Program operation.
operation
(2)
completed
Pulse on Erase
or Program
complete
Supplies a system interrupt pulse at the end
of a Block Erase or Program operation.
03h
1
1
Note: 1. DQ2-DQ7 are reserved
2. When STS pin is pulsing it remains Low for a typical time of 250ns.
17/50
M58LW032D
Table 6. Read Electronic Signature
Code
(3)
Data (DQ15-DQ0)
0020h
Address (A21-A1)
000000h
Manufacturer Code
Device Code
000001h
8821h
0000h (Block Unprotected)
0001h (Block Protected)
(1)
Block Protection Status
Protection Register
SBA +02h
(2)
(1)
000080h
PRD
Note: 1. SBA is the Start Base Address of each block, PRD is Protection Register Data.
2. Base Address, refer to Figure 6 and Tables 7 and 8 for more information.
3. A0 is not used in Read Electronic Signature in either x8 or x16 mode. The data is always presented on the lower byte in x16 mode.
Figure 6. Protection Register Memory Map
WORD
ADDRESS
88h
User Programmable
85h
84h
Unique device number
81h
Protection Register Lock
1
0
80h
AI05501
Table 7. Word-Wide Read Protection Register
Word
Use
Factory, User
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
User
A8
1
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
Lock
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
User
1
0
0
0
0
1
1
0
User
1
0
0
0
0
1
1
1
User
1
0
0
0
1
0
0
0
18/50
M58LW032D
Table 8. Byte-Wide Read Protection Register
Word
Use
Factory, User
Factory, User
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
User
A8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Lock
Lock
0
1
2
3
4
5
6
7
8
9
User
A
User
B
User
C
D
E
User
User
User
F
User
Table 9. Program, Erase Times and Program Erase Endurance Cycles
M58LW032D
Parameters
Unit
Typical after
100k W/E Cycles
Min
Typ
Max
Block (1Mb) Erase
Chip Program
1.7
s
s
(2)
t.b.a.
Program Write Buffer
260
µs
µs
Program Suspend Latency Time
Erase Suspend Latency Time
Block Protect Time
20
25
µs
18
µs
Blocks Unprotect Time
0.75
s
Program/Erase Cycles (per block)
100,000
Note: 1. (T = 0 to 70°C; V = 2.7V to 3.6V; V =1.8V)
DDQ
cycles
A
DD
2. t.b.a. to be announced
19/50
M58LW032D
STATUS REGISTER
The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
pleted its operation; when the bit is High, V , a
OH
Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The EraseStatus bit can be
used to identify if the memory has failed to verify
that the block has erased correctly or that all
blocks have been unprotected successfully. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
To read the Status Register the Read Status Reg-
ister commandcan be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Re-
sume commands. The Status Register can be
read from any address.
The contents of the Status Register can be updat-
ed during an Erase or Program operation by tog-
gling the Output Enable pin or by dis-activating
and then reactivating the device (refer to Table 2,
Device Enable).
Status Register bits 5, 4, 3 and 1 are associated
with various error conditions and can only be reset
with the Clear Status Register command. The Sta-
tus Register bits are summarized in Table 10, Sta-
tus Register Bits. Refer to Table 10 in conjunction
with the following text descriptions.
When the Erase Status bit is Low, V , the mem-
OL
ory has successfully verified that the block has
erased correctly or all blocks have been unprotect-
ed successfully. When the Erase Status bit is
High, V , the erase operation has failed. De-
OH
pending on the cause of the failure other Status
Register bits may also be set to High, V
.
OH
■ If only the Erase Status bit (bit 5) is set High,
, then the Program/Erase Controller has
V
OH
Program/Erase Controller Status (Bit 7). ThePro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
applied the maximum number of pulses to the
block and still failed to verify that the block has
erased correctly or that all the blocks have been
unprotected successfully.
Low, V , the Program/Erase Controller is active
OL
■ If the failure is due to an erase or blocks
and all other Status Register bits are High Imped-
unprotect withV
low, V , thenV
Status
PEN
OL
PEN
ance; when the bit is High, V , the Program/
OH
bit (bit 3) is also set High, V
.
OH
Erase Controller is inactive.
■ If the failure is due to an erase on a protected
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Control-
ler Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Con-
troller completes the operation and the bit is High.
block then Block Protection Status bit (bit 1) is
also set High, V
.
OH
■ If the failure is due to a program or erase
incorrect command sequence then Program
Status bit (bit 4) is also set High, V
.
OH
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program or Block Protect fail-
ure. The Program Status bit should be read once
the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
After the Program/Erase Controller completes its
operation the Erase Status, Program Status and
Block Protection Status bits should be tested for
errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is High (Program/Erase Controller
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Status bit is Low, V , the
OL
memory has successfully verified that the Write
Buffer has programmed correctly or the block is
protected. When the Program Status bit is High,
V
, the program or block protect operation has
OH
failed. Depending on the cause of the failure other
Status Register bits may also be set to High, V
.
OH
■ If only the Program Status bit (bit 4) is set High,
, then the Program/Erase Controller has
V
OH
When the Erase Suspend Status bit is Low, V
,
OL
applied the maximum number of pulses to the
the Program/Erase Controller is active or has com-
20/50
M58LW032D
byte and still failed to verify that the Write Buffer
has programmed correctly or that the Block is
protected.
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive); after a Program/Erase Suspend
command is issued the memory may still complete
the operation rather than entering the Suspend
mode.
■ If the failure is due to a program or block protect
with V
low, V , then V
Status bit (bit 3)
PEN
OL
PEN
is also set High, V
.
OH
■ If the failure is due to a program on a protected
block then Block Protection Status bit (bit 1) is
When the Program Suspend Status bit is Low,
also set High, V
.
OH
V
, the Program/Erase Controller is active or has
OL
■ If the failure is due to a program or erase
completed its operation; when the bit is High, V
,
OH
incorrect command sequence then Erase
a Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
Status bit (bit 5) is also set High, V
.
OH
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
When a Program/Erase Resume command is is-
sued theProgram Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a protected block.
V
Status (Bit 3). The V
Status bit can be
PEN
PEN
used to identify if a Program, Erase, Block Protec-
tion or Block Unprotection operation has been at-
When the Block Protection Status bit is Low, V
,
OL
tempted when V
is Low, V .
PEN
IL
no Program or Erase operations have been at-
tempted to protected blocks since the last Clear
Status Register command or hardware reset;
When the V
Status bit is Low, V , no Pro-
OL
PEN
gram, Erase, Block Protection or Block Unprotec-
tion operations have been attempted with V
PEN
when the Block Protection Status bit is High, V
,
OH
Low, V , since the last Clear Status Register com-
IL
a Program (Program Status bit 4 set High) or
Erase (Erase Status bit 5 set High) operation has
been attempted on a protected block.
mand, or hardware reset. When the V
Status
PEN
bit is High, V , a Program, Erase, Block Protec-
OH
tion or Block Unprotection operation has been at-
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
tempted with V
Low, V .
PEN
IL
Once set High, the V
Status bit can only be re-
PEN
set by a Clear Status Register command or a hard-
ware reset. If set High it should be reset before a
new Program, Erase, Block Protection or Block
Unprotection command is issued, otherwise the
new command will appear to fail.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
21/50
M58LW032D
Table 10. Status Register Bits
OPERATION
Result
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Program/Erase Controller active
Write Buffer not ready
0
0
1
1
1
1
Hi-Z
Hi-Z
N/A
N/A
80h
C0h
84h
C4h
Write Buffer ready
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Write Buffer ready in Erase Suspend
Program suspended
Program suspended in Erase Suspend
Program/Block Protect completed
successfully
1
1
1
1
1
0
1
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
80h
C0h
B0h
F0h
98h
Program completed successfully in Erase
Suspend
Program/Block protect failure due to incorrect
command sequence
Program failure due to incorrect command
sequence in Erase Suspend
Program/Block Protect failure due to V
error
PEN
Program failure due to V
Suspend
error in Erase
PEN
1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
D8h
92h
D2h
Program failure due to Block Protection
Program failure due to Block Protection in
Erase Suspend
Program/Block Protect failure due to cell
failure
1
0
0
1
0
0
0
90h
Program failure due to cell failure in Erase
Suspend
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
D0h
C0h
80h
Erase Suspended
Erase/Blocks Unprotect completed
successfully
Erase/Blocks Unprotect failure due to
incorrect command sequence
1
0
1
1
0
0
0
B0h
Erase/Blocks Unprotect failure due to V
error
PEN
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
A8h
A2h
A0h
Erase failure due to Block Protection
Erase/Blocks Unprotect failure due to failed
cells in Block
Configure STS error due to invalid
configuration code
1
0
1
1
0
0
0
B0h
22/50
M58LW032D
MAXIMUM RATING
Stressing the device above the ratings listed in Ta-
ble 11, Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 11. Absolute Maximum Ratings
Value
Symbol
Parameter
Temperature Under Bias
Unit
Min
–40
–55
–0.6
–0.6
Max
125
150
T
BIAS
°C
°C
V
T
STG
Storage Temperature
Input or Output Voltage
Supply Voltage
V
V
+0.6
DDQ
IO
V
, V
DD DDQ
5.0
V
23/50
M58LW032D
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 12,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Parameter
M58LW032D
Units
Min
Max
Supply Voltage (V
)
2.7
1.8
0
3.6
V
V
DD
Input/Output Supply Voltage (V
)
V
DDQ
DD
Grade 1
Grade 6
70
85
°C
°C
pF
V
Ambient Temperature (T )
A
–40
Load Capacitance (C )
30
L
0 to V
Input Pulses Voltages
DDQ
Input and Output Timing Ref. Voltages
0.5 V
V
DDQ
Figure 7. AC Measurement Input Output
Waveform
Figure 8. AC Measurement Load Circuit
1.3V
1N914
V
DDQ
V
DD
3.3kΩ
V
DDQ
0.5 V
DDQ
DEVICE
UNDER
TEST
DQ
S
0V
C
L
AI00610
0.1µF
0.1µF
C
includes JIG capacitance
L
AI03459
Table 13. Capacitance
Symbol
Parameter
Test Condition
Typ
6
Max
8
Unit
pF
pF
C
V
= 0V
= 0V
Input Capacitance
IN
IN
C
V
OUT
Output Capacitance
8
12
OUT
Note: 1. T = 25°C, f = 1 MHz
A
2. Sampled only, not 100% tested.
24/50
M58LW032D
Table 14. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
±1
±5
20
Unit
µA
I
0V≤ V ≤ V
Input Leakage Current
LI
IN
DDQ
I
I
Output Leakage Current
0V≤ V
≤V
DDQ
µA
LO
OUT
E = V , G = V
IH
Supply Current (Random Read)
Supply Current (Standby)
mA
µA
DD
IL
I
I
I
E = V , RP = V
40
DD1
DD5
DD2
IH
IH
IH
E = V , RP = V
Supply Current (Auto Low-Power)
Supply Current (Reset/Power-Down)
40
µA
IL
RP = V
40
µA
IL
Supply Current (Program or Erase,
Block Protect, Block Unprotect)
Program or Erase operation in
progress
I
I
30
mA
DD3
DD4
Supply Current
(Erase/Program Suspend)
E = V
40
µA
IH
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.5
2
0.8
V
V
V
V
IL
V
V
V
+ 0.5
DDQ
IH
I
= 100µA
OL
0.2
2
OL
V
OH
I
= –100µA
V
–0.2
DDQ
OH
V
Supply Voltage (Erase and
DD
V
V
LKO
Program lockout)
25/50
M58LW032D
Figure 9. Bus Read AC Waveforms
tAVAV
VALID
A0-A21
tELQV
tELQX
tAXQX
(1)
E2, E1, E0
tGLQV
tGLQX
tEHQZ
tEHQX
G
tAVQV
tGHQZ
tGHQX
DQ0-DQ15
OUTPUT
AI06239
Note: 1. V = Device Disabled (first edge of E0, E1 or E2), V = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
IH
IL
details.
Table 15. Bus Read AC Characteristics.
M58LW032D
Symbol
Parameter
Test Condition
Unit
110
110
110
0
t
E = V , G = V
IL
Address Valid to Address Valid
Min
Max
Min
Max
Min
Max
Min
Min
Min
Max
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
IL
IL
t
E = V , G = V
Address Valid to Output Valid
AVQV
IL
t
G = V
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Transition
Output Enable High to Output Transition
Address Transition to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
ELQX
IL
t
G = V
110
0
ELQV
IL
t
E = V
GLQX
IL
t
t
E = V
25
0
GLQV
EHQX
GHQX
IL
G = V
IL
t
E = V
0
IL
t
t
t
E = V , G = V
0
AXQX
EHQZ
IL
IL
G = V
25
15
IL
E = V
GHQZ
IL
26/50
M58LW032D
Figure 10. Page Read AC Waveforms
A1-A2
VALID
VALID
A3-A21
VALID
tAVQV
tELQV
tELQX
tAXQX
(1)
E2, E1, E0
tAVQV1
tAXQX1
tEHQZ
tEHQX
tGLQV
tGLQX
G
tGHQZ
tGHQX
DQ0-DQ15
OUTPUT
OUTPUT
AI06240
Note: 1. V = Device Disabled (first edge of E0, E1 or E2), V = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
IH
IL
details.
Table 16. Page Read AC Characteristics
M58LW032D
Symbol
Parameter
Test Condition
Unit
110
6
t
E = V , G = V
IL
Address Transition to Output Transition
Address Valid to Output Valid
Min
ns
ns
AXQX1
IL
t
E = V , G = V
IL IL
Max
25
AVQV1
Note: For other timings see Table 15, Bus Read AC Characteristics.
27/50
M58LW032D
Figure 11. Write AC Waveform, Write Enable Controlled
A0-A21
VALID
tAVWH
tWHAX
(1)
E2, E1, E0
tELWL
tGHWL
tWHEH
G
tWHGL
tWLWH
tWHWL
W
tDVWH
INPUT
DQ0-DQ15
tWHDX
STS
(Ready/Busy mode)
tVPHWH
tWHBL
V
PEN
AI06241
Note: 1. V = Device Disabled (first edge of E0, E1 or E2), V = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
IH
IL
details.
Table 17. Write AC Characteristics, Write Enable Controlled
M58LW032D
Symbol
Parameter
Test Condition
Unit
110
50
50
0
t
E = V
E = V
Address Valid to Write Enable High
Min
Min
Min
Min
Min
Max
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVWH
IL
IL
t
Data Input Valid to Write Enable High
Chip Enable Low to Write Enable Low
Program/Erase Enable High to Write Enable High
Write Enable High to Address Transition
Write Enable High to Status/(Ready/Busy) low
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
DVWH
t
ELWL
t
0
VPHWH
t
E = V
E = V
0
WHAX
IL
IL
t
500
0
WHBL
t
WHDX
t
0
WHEH
t
20
35
30
70
GHWL
t
WHGL
t
WHWL
t
E = V
WLWH
IL
28/50
M58LW032D
Figure 12. Write AC Waveforms, Chip Enable Controlled
A0-A21
VALID
tAVEH
tEHAX
W
G
tWLEL
tEHWH
tGHEL
tELEH
tEHEL
tEHGL
(1)
E2, E1, E0
DQ0-DQ15
tDVEH
INPUT
tEHDX
tEHBL
STS
(Ready/Busy mode)
tVPHEH
V
PEN
AI06242
Note: 1. V = Device Disabled (first edge of E0, E1 or E2), V = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
IH
IL
details.
Table 18. Write AC Characteristics, Chip Enable Controlled.
M58LW032D
Symbol
Parameter
Test Condition
Min
Unit
110
10
50
50
0
t
Address Validto Latch Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLH
t
W = V
IL
Address Validto Chip Enable High
Min
Min
Min
Min
Min
Max
Min
Min
Min
Min
Min
Min
Min
AVEH
t
W = V
IL
Data Input Valid to Chip Enable High
Write Enable Low to Chip Enable Low
Program/Erase Enable High to Chip Enable High
Chip Enable High to Address Transition
Chip Enable High to Status/(Ready/Busy) low
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Output Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Chip Enable Low
Chip Enable Low to Chip Enable High
Chip Enable Low to Latch Enable High
DVEH
t
WLEL
t
0
VPHEH
t
W = V
IL
5
EHAX
t
t
500
5
EHBL
W = V
EHDX
EHWH
IL
t
0
t
20
35
30
70
10
GHEL
EHGL
t
t
t
EHEL
ELEH
W = V
IL
t
W = V
IL
ELLH
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M58LW032D
Figure 13. Reset, Power-Down and Power-up AC Waveform
W
(1)
E2, E1, E0 , G
DQ0-DQ15
tPHQV
STS
(Ready/Busy mode)
tPLBH
RP
tVDHPH
tPLPH
V
, V
DD DDQ
Power-Up
and Reset
Reset during
Program or Erase
AI06217
Note: 1. V = Device Disabled (first edge of E0, E1 or E2), V = Device Enabled (first edge of E0, E1 or E2). Refer to Table 2 for more
IH
IL
details.
Table 19. Reset, Power-Down and Power-up AC Characteristics
M58LW032D
Symbol
Parameter
Reset/Power-Down High to Data Valid
Unit
110
150
100
30
t
Max
Min
Max
Min
ns
ns
µs
µs
PHQV
t
Reset/Power-Down Low to Reset/Power-Down High
Reset/Power-Down Low to Status/(Ready/Busy) High
Supply Voltages High to Reset/Power-Down High
PLPH
t
PLBH
t
0
VDHPH
30/50
M58LW032D
PACKAGE MECHANICAL
Figure 14. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
Table 20. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
mm
inches
Symbol
Typ
Min
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
14.10
–
Typ
Min
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
0.5551
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
13.90
–
0.0020
0.0374
0.0067
0.0039
0.7795
0.7205
0.5472
–
C
D
D1
E
e
0.50
0.0197
L
0.50
0°
0.70
5°
0.0197
0°
0.0276
5°
α
N
56
56
CP
0.10
0.0039
31/50
M58LW032D
Figure 15. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline
D
D1
FD
FE
SD
SE
E
E1
ddd
BALL ”A1”
A
e
b
A2
A1
BGA-Z23
Note: Drawing is not to scale.
Table 21. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.350
0.850
0.500
10.100
–
Typ
Max
A
A1
A2
b
0.0472
0.300
0.200
0.0118
0.0079
0.0138
0.0335
0.400
9.900
–
0.0157
0.3898
–
0.0197
D
10.000
7.000
0.3937
0.2756
0.3976
D1
ddd
e
–
0.100
–
0.0039
1.000
13.000
7.000
1.500
3.000
0.500
0.500
–
0.0394
0.5118
0.2756
0.0591
0.1181
0.0197
0.0197
–
–
E
12.900
13.100
–
0.5079
0.5157
E1
FD
FE
SD
SE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
32/50
M58LW032D
PART NUMBERING
Table 22. Ordering Information Scheme
Example:
M58LW032D
11
N
1
T
Device Type
M58
Architecture
L = Page Mode
Operating Voltage
W = V = 2.7V to 3.6V; V
= 1.8 to V
DD
DD
DDQ
Device Function
032D = 32 Mbit (x8, x16), Uniform Block
Speed
11 = 110 ns
Package
N = TSOP56: 14 x 20 mm
ZA = TBGA64: 10 x 13 mm, 1mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Note: Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
33/50
M58LW032D
REVISION HISTORY
Table 23. Document Revision History
Date
Version
Revision Details
04-Jun-2002
-01
First Issue
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot.
(revision version 01 becomes 1.0).
16-Jun-2002
1.1
Figure 5 modified. t
and t
modified in Table 17.
WHDX
WHAX
34/50
M58LW032D
APPENDIX A. BLOCK ADDRESS TABLE
Table 24. Block Addresses
Block
Number
Address Range
(x8 Bus Width)
Address Range
(x16 Bus Width)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
3E0000h-3FFFFFh
3C0000h-3DFFFFh
3A0000h-3BFFFFh
380000h-39FFFFh
360000h-37FFFFh
340000h-35FFFFh
320000h-33FFFFh
300000h-31FFFFh
2E0000h-2FFFFFh
2C0000h-2DFFFFh
2A0000h-2BFFFFh
280000h-29FFFFh
260000h-27FFFFh
240000h-25FFFFh
220000h-23FFFFh
200000h-21FFFFh
1E0000h-1FFFFFh
1C0000h-1DFFFFh
1A0000h-1BFFFFh
180000h-19FFFFh
160000h-17FFFFh
140000h-15FFFFh
120000h-13FFFFh
100000h-11FFFFh
0E0000h-0FFFFFh
0C0000h-0DFFFFh
0A0000h-0BFFFFh
080000h-09FFFFh
060000h-07FFFFh
040000h-05FFFFh
020000h-03FFFFh
000000h-01FFFFh
1F0000h-1FFFFFh
1E0000h-1EFFFFh
1D0000h-1DFFFFh
1C0000h-1CFFFFh
1B0000h-1BFFFFh
1A0000h-1AFFFFh
190000h-19FFFFh
180000h-18FFFFh
170000h-17FFFFh
160000h-16FFFFh
150000h-15FFFFh
140000h-14FFFFh
130000h-13FFFFh
120000h-12FFFFh
110000h-11FFFFh
100000h-10FFFFh
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
000000h-00FFFFh
8
7
6
5
4
3
2
1
35/50
M58LW032D
APPENDIX B. COMMON FLASH INTERFACE - CFI
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command (RCFI) is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 25, 26,
27, 28, 29 and 30 show the addresses used to re-
trieve the data.
Table 25. Query Structure Overview
Address
Sub-section Name
Description
x16
x8
0000h
0001h
0010h
001Bh
0027h
10h
11h
20h
36h
4Eh
Manufacturer Code
Device Code
CFI Query Identification String
System Interface Information
Device Geometry Definition
Command set ID and algorithm data offset
Device timing and voltage information
Flash memory layout
Primary Algorithm-specific Extended
Query Table
Additional information specific to the Primary
Algorithm (optional)
(1)
(2)
P(h)
Alternate Algorithm-specific Extended Additional information specific to the Alternate
Query Table
A(h)
Algorithm (optional)
(SBA+02)h
Block Status Register
Block-related Information
Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.
2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
3. SBA is the Start Base Address for each block.
Table 26. CFI - Query Address and Data Output
Address
Data
Description
x16
x8
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
51h
52h
59h
”Q”
”R”
”Y”
51h; ”Q”
52h; ”R”
59h; ”Y”
Query ASCII String
Primary Vendor:
01h
00h
31h
00h
00h
00h
00h
00h
Command Set and Control Interface ID Code
Primary algorithm extended Query Address Table: P(h)
Alternate Vendor:
Command Set and Control Interface ID Code
Alternate Algorithm Extended Query address Table
(2)
34h
001Ah
Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to ’0’.
2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
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M58LW032D
Table 27. CFI - Device Voltage and Timing Specification
Address
Data
Description
x16
x8
(1)
(1)
(2)
(2)
V
V
V
V
Min, 2.7V
001Bh
001Ch
36h
38h
27h
36h
00h
00h
DD
DD
PP
PP
max, 3.6V
min – Not Available
max – Not Available
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
n
04h
2 µs typical time-out for Word, DWord prog – Not Available
n
08h
0Ah
2 µs, typical time-out for max buffer write
n
2 ms, typical time-out for Erase Block
(3)
n
00h
2 ms, typical time-out for chip erase – Not Available
n
04h
04h
04h
2 x typical for Word Dword time-out max – Not Available
n
2 x typical for buffer write time-out max
n
2 x typical for individual block erase time-out maximum
(3)
n
00h
2 x typical for chip erase max time-out – Not Available
Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.
2. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.
3. Not supported.
Table 28. Device Geometry Definition
Address
Data
Description
x16
x8
n
0027h
4Eh
16h
n where 2 is number of bytes memory Size
Device Interface
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
02h
00h
05h
00h
01h
1Fh
00h
00h
02h
Organization Sync./Async.
n
Maximum number of bytes in Write Buffer, 2
Bit7-0 = number of Erase Block Regions in device
Number (n-1) of Erase Blocks of identical size; n=64
Erase Block Region Information
x 256 bytes per Erase block (128K bytes)
37/50
M58LW032D
Table 29. Block Status Register
Address
Data
Selected Block Information
0
1
0
Block Unlocked
Block Locked
bit0
(2)
(1)
Last erase operation ended successfully
(BA+2)h
bit1
(2)
1
0
Last erase operation not ended successfully
Reserved for future features
bit7-2
Note: 1. BA specifies the block address location, A21-A17.
2. Not Supported.
38/50
M58LW032D
Table 30. Extended Query information
Address
Data (Hex)
Description
offset
(P)h
x16
x8
0031h
0032h
0033h
0034h
0035h
62h
64h
66h
68h
6Ah
50h
”P”
”R”
”Y”
(P+1)h
(P+2)h
(P+3)h
(P+4)h
52h
49h
Query ASCII string - Extended Table
31h
31h
Major version number
Minor version number
Optional Feature: (1=yes, 0=no)
bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Lock/Unlock Supported (1=yes)
bit4, Queue Erase Supported (0=no)
bit5, Instant Individual Block locking
bit6, Protection bits supported
(P+5)h
0036h
6Ch
CEh
bit7, Page Read supported
bit8, Synchronous Read supported
Bit 31-9 reserved for future use
(P+6)h
(P+7)h
(P+8)h
0037h
0038h
0039h
6Eh
70h
72h
00h
00h
00h
Synchronous Read supported (0=no)
Optional Features
Function allowed after Suspend:
(P+9)h
003Ah
74h
01h
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use
(2)
(P+A)h
003Bh
76h
Block Status Register Mask
Lock bit, no lock down
01h
(P+B)h
(P+C)h
(P+D)h
(P+E)h
(P+F)h
(P+10)h
003Ch
003Dh
003Eh
003Fh
0040h
0041h
78h
7Ah
7Ch
7Eh
80h
82h
00h
33h
00h
01h
80h
00h
V
V
OPTIMUM Program/Erase voltage conditions
OPTIMUM Program/Erase voltage conditions
DD
PP
OTP protection: No. of protection register fields
Lock bit’s physical low address
Lock bit’s physical high address
n
(P+11)h
(P+12)h
0042h
0043h
84h
86h
03h
03h
03h
00h
n where 2 is number of factory reprogrammed bytes
n
n where 2 is number of user programmable bytes
n
(P+13)h
(P+14)h
(P+15)h
0044h
0045h
0046h
88h
8Ah
8Ch
Page Read: 2 Bytes (n = bits 0-7)
Synchronous mode configuration fields
Reserved for future use
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
2. Not supported.
39/50
M58LW032D
APPENDIX C. FLOW CHARTS
Figure 16. Write to Buffer and Program Flowchart and Pseudo Code
Start
Write to Buffer E8h
Command, Block Address
Read Status
Register
NO
NO
YES
Write to Buffer
Timeout
b7 = 1
YES
(1)
Note 1: N+1 is number of Words
to be programmed
Write N
,
Block Address
Try Again Later
Write Buffer Data,
Start Address
X = 0
YES
X = N
NO
Write Next Buffer Data,
NextProgram Address
Note 2: Next Program Address must
have same A5-A21.
(2)
X = X + 1
Program Buffer to Flash
Confirm D0h
Read Status
Register
NO
b7 = 1
YES
Note 3: A full Status Register Check must be
done to check the program operation’s
success.
Full Status
Register Check
(3)
End
AI05511
40/50
M58LW032D
Figure 17. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
Read Status
Register
– read status register
NO
NO
b7 = 1
YES
while b7 = 1
If b2 = 0, Program completed
b2 = 1
YES
Program Complete
Read Memory Array instruction:
– write FFh
Write FFh
– one or more data reads
from other blocks
Read data from
another block
Program Erase Resume Command:
– write D0h
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).
Write D0h
Write FFh
Read Data
Program Continues
AI00612
41/50
M58LW032D
Figure 18. Erase Flowchart and Pseudo Code
Start
Erase command:
– write 20h
Write 20h
– write D0h to Block Address
(A12-A17)
(memory enters read Status
Register after the Erase command)
Write D0h to
Block Address
NO
do:
Read Status
– read status register
– if Program/Erase Suspend command
given execute suspend erase loop
Register
Suspend
YES
NO
Suspend
Loop
b7 = 1
while b7 = 1
YES
NO
NO
NO
NO
V
Invalid
If b3 = 1, V
invalid error:
PP
Error (1)
PP
– error handler
b3 = 0
YES
Command
Sequence Error
If b4, b5 = 1, Command Sequence error:
– error handler
b4, b5 = 0
YES
Erase
Error (1)
If b5 = 1, Erase error:
– error handler
b5 = 0
YES
Erase to Protected
Block Error
If b1 = 1, Erase to Protected Block Error:
– error handler
b1 = 0
YES
End
AI00613B
Note: 1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase oper-
ations.
42/50
M58LW032D
Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
Read Status
Register
– read status register
NO
NO
b7 = 1
YES
while b7 = 1
If b6 = 0, Erase completed
b6 = 1
YES
Erase Complete
Read Memory Array command:
– write FFh
Write FFh
– one or more data reads
from other blocks
Read data from
another block
or Program
Program/Erase Resume command:
– write D0h to resume the Erase
operation
Write D0h
Write FFh
– if the Program operation completed
then this is not necessary. The device
returns to Read mode as normal
(as if the Program/Erase suspend
was not issued).
Read Data
Erase Continues
AI00615
43/50
M58LW032D
Figure 20. Block Protect Flowchart and Pseudo Code
Start
Write 60h
Block Address
Block Protect Command
– write 60h, Block Adress
– write 01h, Block Adress
Write 01h
Block Address
do:
Read Status Register
– read status register
NO
b7 = 1
while b7 = 1
YES
YES
Invalid Voltage
b3 = 1
If b3 = 1, Invalid Voltage Error
Error
NO
YES
Invalid Command
b4, b5 = 1,1
If b4 = 1, b5 = 1 Invalid Command Sequence
Error
Sequence Error
NO
YES
Block Protect
If b4 = 1, Block Protect Error
b4 = 1
Error
NO
Write FFh
Read Memory Array Command:
– write FFh
Block Protect
Sucessful
AI06157
44/50
M58LW032D
Figure 21. Block Unprotect Flowchart and Pseudo Code
Start
Write 60h
Block Unprotect Command
– write 60h, Block Adress
– write D0h, Block Adress
Write D0h
do:
Read Status Register
– read status register
NO
b7 = 1
while b7 = 1
YES
YES
Invalid Voltage
b3 = 1
If b3 = 1, Invalid Voltage Error
Error
NO
YES
Invalid Command
b4, b5 = 1,1
If b4 = 1, b5 = 1 Invalid Command
Sequence Error
Sequence Error
NO
YES
Block Unprotect
If b5 = 1, Block Unprotect Error
b5 = 1
Error
NO
Write FFh
Read Memory Array Command:
– write FFh
Block Unprotect
Sucessful
AI06158
45/50
M58LW032D
Figure 22. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
Protection Register Program Command
– write C0h
– write Protection Register Address,
Protection Register Data
Write
PR Address, PR Data
do:
Read Status Register
– read status register
NO
b7 = 1
YES
while b7 = 1
YES
YES
If b3 = 1, b4 = 1 Invalid Voltage Error
Invalid Voltage
Error
b3, b4 = 1,1
NO
Protection Register
Program Error
If b1 = 0, b4 = 1 Protection Register
Program Error
b1, b4 = 0,1
NO
YES
Block Unprotect
Error
If b1 = 1, b4 = 1 Program Error due to
Protection Register Protection
b1, b4 = 1,1
NO
Write FFh
Read Memory Array Command:
– write FFh
PR Program
Sucessful
AI06159
Note: PR = Protection Register
46/50
M58LW032D
Figure 23. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE
NO
90h
YES
READ
SIGNATURE
NO
98h
YES
CFI
QUERY
NO
70h
YES
READ
ARRAY
READ
STATUS
NO
50h
YES
CLEAR
STATUS
NO
E8h
YES
PROGRAM
BUFFER
LOAD
NO
(1)
20h
YES
ERASE
NO
FFh
YES
SET-UP
NO
D0h
NO
YES
C
PROGRAM
COMMAND
ERROR
D0h
YES
ERASE
COMMAND
ERROR
A
B
AI03618
Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
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M58LW032D
Figure 24. Command Interface and Program Erase Controller Flowchart (b)
A
B
ERASE
(READ STATUS)
Program/Erase Controller
Status bit in the Status
Register
YES
READ
STATUS
READY
?
NO
READ
ARRAY
NO
B0h
YES
YES
READ
STATUS
NO
FFh
ERASE
SUSPEND
NO
YES
ERASE
SUSPENDED
READY
?
NO
READ
STATUS
YES
WAIT FOR
COMMAND
WRITE
YES
YES
YES
YES
READ
STATUS
70h
NO
READ
SIGNATURE
90h
NO
CFI
QUERY
98h
NO
PROGRAM
BUFFER
LOAD
E8h
NO
NO
PROGRAM
COMMAND
ERROR
YES
READ
STATUS
D0h
D0h
NO
(ERASE RESUME)
YES
READ
ARRAY
c
AI03619
48/50
M58LW032D
Figure 25. Command Interface and Program Erase Controller Flowchart (c).
B
C
PROGRAM
(READ STATUS)
YES
Program/Erase Controller
Status bit in the Status
Register
READ
STATUS
READY
?
NO
READ
ARRAY
NO
B0h
YES
YES
NO
READ
STATUS
FFh
PROGRAM
SUSPEND
NO
YES
PROGRAM
SUSPENDED
READY
?
NO
YES
WAIT FOR
COMMAND
WRITE
READ
STATUS
YES
YES
YES
NO
READ
STATUS
70h
NO
READ
SIGNATURE
90h
NO
CFI
QUERY
98h
NO
YES
READ
ARRAY
READ
STATUS
D0h
(PROGRAM RESUME)
AI00618
49/50
M58LW032D
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