M59BW102N
更新时间：2024-09-18 02:04:20
描述：1 Mbit 64Kb x16, Burst Low Voltage Flash Memory
概述
数据手册M59BW102N 概述
1 Mbit 64Kb x16, Burst Low Voltage Flash Memory 1兆位64Kb的X16 ，突发低电压闪存
M59BW102N 数据手册
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PDF下载M59BW102
1 Mbit (64Kb x16, Burst) Low Voltage Flash Memory
PRELIMINARY DATA
■ 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
■ SEQUENTIAL CYCLE TIME: 25ns
■ RANDOM ACCESS TIME
■ PROGRAMMING TIME: 10µs typical
■ INTERLEAVED ACCESS TIME: 16ns
■ CONTINUOUS MEMORY INTERLEAVING
– Unlimited Linear Access Data Output
■ PROGRAM/ERASE CONTROLLER (P/E.C.)
TSOP40 (N)
10 x 14mm
– Program Word-by-Word
– Status Register bits
■ LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
■ 100,000 PROGRAM/ERASE CYCLES
■ 20 YEARS DATA RETENTION
Figure 1. Logic Diagram
– Defectivity below 1ppm/year
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: C1h
V
CC
DESCRIPTION
The M59BW102 is a non-volatile memory that may
be erased electrically at the chip level and pro-
grammed in-system on a Word-by-Word basis us-
16
16
ing only a single 3V V supply. For Program and
CC
A0-A15
DQ0-DQ15
Erase operations the necessary high voltages are
generated internally. The device can also be pro-
grammed in standard programmers.
The device can be programmed and erased over
100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature, Programming and
Chip Erase are written to the device in cycles of
commands to a Command Interface using stan-
dard microprocessor write timings. The
M59BW102 features an interleaved access mo-
dality which allows extremely fast access time.
The device is offered in TSOP40 (10 x 14mm)
package.
W
E
M59BW102
G
ALE
V
SS
AI02763B
March 2000
1/24
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M59BW102
Figure 2. TSOP Connections
Table 1. Signal Names
A0-A15
Address Inputs
DQ0-DQ7
Data Inputs/Outputs, Command Inputs
Data Inputs/Outputs
Chip Enable
A9
A10
A11
A12
A13
A14
A15
ALE
W
1
40
V
SS
A8
DQ8-DQ15
E
A7
G
Output Enable
A6
A5
W
Write Enable
A4
ALE
Address Latch Enable
Supply Voltage
A3
V
CC
A2
V
Ground
SS
A1
NC
Not Connected Internally
V
10
11
31
30
A0
CC
NC
M59BW102
G
E
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
DQ8
20
21
V
SS
AI02764B
Instructions
Organization
Four instructions are defined to perform Read Ar-
ray, Auto Select (to read the Electronic Signature),
Program, Chip Erase. The internal P/E.C. auto-
matically handles all timing and verification of the
Program and Erase operations. The Status Regis-
ter Data Polling, Toggle and Error bits may be read
at any time, during programming or erase, to mon-
itor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in-
structions (see Table 7). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data or Electronic Signature
for Read operations. In order to give additional
data protection, the instructions for Program and
Chip Erase require further command inputs. For a
Program instruction, the fourth command cycle in-
puts the address and data to be programmed. For
an Erase instruction, the fourth and fifth cycles in-
put a further Coded sequence before the com-
mand confirmation on the sixth cycle.
The M59BW102 is organized as 64K x16 bits. The
memory uses the address inputs A0-A15 and the
Data Inputs/Outputs DQ0-DQ15. Memory control
is provided by Chip Enable E, Output Enable G,
Address Latch Enable ALE and Write Enable W in-
puts.
Erase and Program operations are controlled by
an internal Program/Erase Controller (P/E.C.).
Status Register data output on DQ7 provides a
Data Polling signal, and DQ6 and DQ2 provide
Toggle signals to indicate the state of the P/E.C
operations.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electron-
ic Signature), Write command, Output Disable,
Standby. See Tables 3 and 4.
2/24
M59BW102
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
°C
°C
V
T
A
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
T
–50 to 125
–65 to 150
–0.6 to 5
BIAS
T
STG
(2)
Input or Output Voltage
Supply Voltage
V
IO
V
–0.6 to 5
V
V
CC
(A9, E, G)
(2)
A9, E, G Voltage
–0.6 to 13.5
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
(1))
Table 3. User Bus Operations
Operation
E
G
W
ALE
A0
A1
A6
A9
A12
A15
DQ15-DQ0
Non Linear
Access Mode
V
V
V
Pulse
X
X
X
X
X
X
Data Output
IL
IL
IL
IH
IH
Linear Access
Cycle
Rising
Edge
V
V
V
X
X
X
X
X
X
Data Output
IL
V
V
V
V
V
V
V
Write Word
Output Disable
Standby
A0
X
A1
X
A6
X
A9
X
A12
X
A15
X
Data Input
Hi-Z
IL
IL
IH
IL
IH
V
IH
V
IH
IH
X
X
X
X
X
X
X
X
X
Hi-Z
IH
Note: 1. X = V or V
.
IH
IL
Table 4. Read Electronic Signature (following AS instruction or with A9 = V )
ID
Other
Code
E
G
W
A0
A1
DQ15-DQ8 DQ7-DQ0
Address
Don't Care
Don't Care
V
V
V
IH
V
IL
V
IL
Manufact. Code
Device Code
00h
00h
20h
C1h
IL
IL
IL
IL
V
V
V
IH
V
IH
V
IL
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
the Electronic Signature Manufacturer or Device
codes, the Status register Data Polling bit DQ7,
the Toggle Bits DQ6 and DQ2, the Error bit DQ5
or the Erase Timer bit DQ3. Outputs are valid
when Chip Enable E and Output Enable G are ac-
tive. The output is high impedance when the chip
is deselected or the outputs are disabled.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E High deselects the
memory and reduces the power consumption to
the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at a low level.
Address Inputs (A0-A15). The address inputs
for the memory array are latched during a write op-
eration on the falling edge of Chip Enable E or
Write Enable W. When A9 is raised to V , either a
ID
Read Electronic Signature Manufacturer or Device
Code is enabled depending on the combination of
levels on A0 and A1.
Data Inputs/Outputs (DQ0-DQ15). The input is
data to be programmed in the memory array or a
command to be written to the C.I. Both are latched
on the rising edge of Chip Enable E or Write En-
able W. The output is data from the Memory Array,
3/24
M59BW102
Table 5. Commands
Hex Code
reached by the counters they start again from the
first memory address and continue. The
M59BW102 will provide data output during the LA
cycle determined by G signal.
Each time ALE signal is pulsed and G signal is
High, while the current address is loaded into the
counters, the output buffers are put in Hi-Z condi-
tion and remain in this condition until the first new
valid data comes. The M59BW102 operation in LA
and NLA modes is explained in Figure 3 and the
block diagram is shown in Figure 4.
Write. Write operations are used to give Instruc-
tion Commands to the memory or to latch input
data to be programmed. A write operation is initi-
ated when Address Latch Enable (ALE) is high,
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whichever occurs
last. Commands and Input Data are latched on the
rising edge of W or E whichever occurs first.
Command
00h
10h
20h
80h
90h
A0h
F0h
Invalid/Reserved
Chip Erase Confirm
Reserved
Set-up Erase
Read Electronic Signature
Program
Read Array/Reset
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G and ALE are both High the out-
puts are High impedance.
Write Enable (W). This input controls writing to
the Command Register and Address and Data
latches.
Address Latch Enable (ALE). This input con-
trols the latching of address for reading. When
pulsed, the device operates in the random or non
linear access mode.
Output Disable. The data outputs are high im-
pedance when the Output Enable G and the Ad-
dress Latch Enable (ALE) are both High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G, the Address Latch Enable
(ALE) or the Write Enable W inputs.
V
Supply Voltage. The power supply for all
CC
operations (Read, Program and Erase).
V
Ground. V is the reference for all voltage
SS
SS
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
measurements.
memory.
The
manufacturer’s
code
for
DEVICE OPERATIONS
STMicroelectronics is 20h, the device code is C1h.
These codes allow programming equipment or ap-
plications to automatically match their interface to
the characteristics of the M59BW102. The Elec-
tronic Signature is output by a Read operation
See Tables 3 and 4.
Read (Non Linear Access Mode and Linear Ac-
cess Cycle). The device is internally organized in
two memory banks (named Even and Odd bank).
A0 address bit is asserted as "priority" bit, so that
when A0 = 0 the even bank is the current memory
array under selection and the odd bank is masked.
When A0 = 1 the odd bank is the current array un-
der selection and even bank is masked.
when the voltage applied to A9 is at V and ad-
ID
dress inputs A1 is Low. The manufacturer code is
output when the Address input A0 is Low and the
device code when this input is High. Other Ad-
dress inputs are ignored. The codes are output on
DQ0-DQ7.
To begin a random (or Non Linear) access mode
(NLA), ALE is pulsed high and E is asserted low.
The Electronic Signature can also be read, without
Two internal 15 bit counters store the current ad-
dress for the odd and even banks and increment
alternatively, under the priority bit control, during
each subsequent cycle called sequential (or Lin-
ear) address cycle (LA). The linear cycle (LA) can
be terminated if a new NLA starts or if E is assert-
ed high, putting the device in stand-by mode. In
this last case the linear cycle can be resumed if E
is asserted low again and ALE is low.
raising A9 to V , by giving the memory the In-
struction AS. The codes are output on DQ0-DQ7
with DQ8-DQ15 at 00h.
ID
Table 6. Polling and Toggle Bits
Mode
Program
Erase
DQ7
DQ7
0
DQ6
DQ2
1
Toggle
Toggle
During the LA mode all the memory can be swept,
as there is no physical limits to the linear access
output. When the last address of the memory is
Toggle
4/24
M59BW102
Figure 3. Non Linear and Linear Access Cycle Timing Diagram
5/24
M59BW102
Figure 4. Block Diagram
DQ0-DQ15
A1-A15
A0
EVEN COUNTER
OUTPUT BUFFER
MULTIPLEXER
ODD COUNTER
G
LOGIC
E
ALE
EVEN MATRIX
(16 x 32K)
ODD MATRIX
(16 x 32K)
AI02765
INSTRUCTIONS AND COMMANDS
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt from any address during Pro-
gram or Erase command execution will automati-
cally output these five Status Register bits. The P/
E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6
and DQ7. Other bits (DQ0, DQ1 and DQ4) are re-
served for future use and should be masked. See
Table 8.
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. See Figure 11 for
the Data Polling waveforms and Figure 12 for the
Data Polling flowchart. A Valid Address is the ad-
dress being programmed or any address while
erasing the chip.
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Program, Chip
Erase. Commands are made of address and data
sequences. The instructions require from 1 to 6 cy-
cles, the first or first three of which are always write
operations used to initiate the instruction. They are
followed by either further write cycles to confirm
the first command or execute the command imme-
diately. Command sequencing must be followed
exactly. Any invalid combination of commands will
reset the device to Read Array. The increased
number of cycles has been chosen to assure max-
imum data security. Instructions are initialised by
two initial Coded cycles which unlock the Com-
mand Interface. In addition, for Erase, instruction
confirmation is again preceded by the two Coded
cycles.
Status Register Bits
Toggle Bit (DQ6). When Programming or Eras-
ing operations are in progress, successive at-
tempts to read DQ6 will output complementary
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
6/24
M59BW102
(1)
Table 7. Instructions
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
(3,6)
(3,6)
(3,6)
X
Addr.
Data
1+
3+
3+
Read Memory Array until a new write cycle is initiated.
F0h
Read/Reset
Memory Array
(2,4)
RD
555h
AAh
555h
AAh
2AAh
55h
X
Addr.
Data
Read Memory Array until a new write
cycle is initiated.
F0h
555h
90h
2AAh
55h
Addr.
Data
Read Electronic Signature until a new
write cycle is initiated. See Note 5.
(4)
Auto Select
Program
AS
Program
(3,6)
(3,6)
555h
AAh
2AAh
55h
555h
A0h
Addr.
Data
Address
Read Data Polling or Toggle
PG
4
6
Bit until Program completes.
Program
Data
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
Addr.
Data
CE
Chip Erase
Note 7
Note: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of 10µs is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new
operation.
3. X = Don't Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
mand cycles.
5. Signature Address bits A0, A1, at V will output Manufacturer code (20h). Address bits A0 at V and A1, at V will output Device
IL
IH
IL
code.
6. For Coded cycles address inputs A11-A16 are don't care.
7. Read Data Polling, Toggle bits until Erase completes.
data. DQ6 will toggle following toggling of either G,
or E when G is low. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last pro-
grammed or a ’1’ after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. See Figure 13 for Toggle
Bit flowchart and Figure 14 for Toggle Bit wave-
forms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. During Chip Erase a
read operation will cause DQ2 to toggle since chip
is being erased. DQ2 will be set to ’1’ during pro-
gram operation and when erase is complete.
previously programmed to ’0’. The error bit resets
after a Read/Reset (RD) instruction. In case of
success of Program or Erase, the error bit will be
set to ’0’.
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the Erase command has been en-
tered to the Command Interface and it is awaiting
the Erase start. When the erase timeout period is
finished, after 50µs to 120µs, DQ3 returns to '1'.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address 555h during the
first cycle. During the second cycle the Coded cy-
cles consist of writing the data 55h at address
2AAh. Address lines A0 to A10 are valid; other ad-
dress lines are 'don't care'. The Coded cycles hap-
pen on first and second cycles of the command
write or on the fourth and fifth cycles.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming or chip
erase that results in invalid data in the memory. In
case of an error in program, the chip must be dis-
carded. The DQ5 failure condition will also appear
if a user tries to program a ’1’ to a location that is
7/24
M59BW102
Table 8. Status Register Bits
DQ
Name
Logic Level
Definition
Erase Complete
Note
’1’
’0’
Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits DQ5 for Program or Erase
Success.
Erase On-going
Data
Polling
7
DQ
DQ
Program Complete
Program On-going
’-1-0-1-0-1-0-1-’ Erase or Program On-going
DQ Program Complete
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed.
6
Toggle Bit
’-1-1-1-1-1-1-1-’ Erase Complete
’1’
’0’
Program or Erase Error
Program or Erase On-going
This bit is set to ’1’ in the case of
Programming or Erase failure.
5
4
Error Bit
Reserved
’1’
’0’
Erase Timeout Period Expired P/E.C. Erase operation has started.
Erase
Time Bit
3
2
Erase Timeout Period On-
going
’-1-0-1-0-1-0-1-’ Chip Erase
Program On-going or Erase
Toggle Bit
Indicates the erase status.
’1’
Complete
1
0
Reserved
Reserved
Note: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Instructions
See Table 7.
lines A0 and A1 are Low, the device code, C1h is
output when A0 is High with A1 Low.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the P/
E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if pro-
gramming is on-going and DQ5 allows verification
of any possible error.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read. Read/Reset is not accepted
in Program/Erase operation unless a fail occurred.
Auto Select (AS) Instruction. This
instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. A subsequent read will output
the manufacturer code and the device code de-
pending on the levels of A0 and A1. The manufac-
turer code, 20h, is output when the addresses
Chip Erase (CE) Instruction. This instruction uses
six write cycles. The Set-up command 80h is writ-
8/24
M59BW102
Table 9. AC Measurement Conditions
Figure 6. AC Testing Load Circuit
Load Capacitance (C )
30pF
≤ 10ns
0 to 3V
1.5V
L
1.3V
Input Rise and Fall Times
1N914
Input Pulse Voltages
Input and Output Timing Ref. Voltages
3.3kΩ
Figure 5. AC Testing Input Output Waveform
DEVICE
UNDER
TEST
OUT
C
= 30pF
L
3V
1.5V
0V
AI01417
C
includes JIG capacitance
AI01119
L
(1)
Table 10. Capacitance
(T = 25 °C, f = 1 MHz)
A
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
IN
V
IN
= 0V
= 0V
C
V
OUT
12
pF
OUT
Note: 1. Sampled only, not 100% tested.
ten to address 555h on the third cycle after the two
Coded cycles. The Chip Erase Confirm command
10h is similarly written on the sixth cycle after an-
other two Coded cycles. If the second command
given is not an erase confirm or if the Coded cy-
cles are wrong, the instruction aborts and the de-
vice is reset to Read Array. It is not necessary to
program the array with 0000h first as the P/E.C.
will automatically do this before erasing it to
FFFFh. Read operations after the sixth rising edge
of W or E output the Status Register bits. During
the execution of the erase by the P/E.C., Data
Polling bit DQ7 returns '0', then '1' on completion.
The Toggle bits DQ2 and DQ6 toggle during erase
operation and stop when erase is completed. After
completion the Status Register bit DQ5 returns '1'
if there has been an Erase Failure.
POWER SUPPLY
Power Up
The memory Command Interface is reset on pow-
er up to Read Array. Either E or W must be tied to
V
during Power Up to allow maximum security
IH
and the possibility to write a command on the first
rising edge of E and W. Any write cycle initiation is
blocked when V is below V
.
CC
LKO
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the V rail decoupled with a 0.1µF capacitor
CC
close to the V
and V
pins. The PCB trace
CC
SS
widths should be sufficient to carry the V
gram and erase currents required.
pro-
CC
9/24
M59BW102
Table 11. DC Characteristics
(T = 0 to 70°C; V = 3.0V to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
±1
Unit
µA
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current (Read)
Supply Current (Standby)
LI
IN
CC
I
LO
0V ≤ V ≤ V
OUT CC
±1
µA
I
E = V , G = V , f = 6MHz
10
mA
µA
CC1
IL
IH
I
ALE, E = V
± 0.2V
CC
100
CC2
Byte program or
Chip Erase in progress
(1)
Supply Current (Program or Erase)
20
mA
I
CC3
V
Input Low Voltage
–0.5
2
0.8
V
V
IL
V
V
V
+ 0.3
CC
Input High Voltage
Output Low Voltage
Output High Voltage
A9, E, G High Voltage
A9, E, G High Current
IH
I
= 1.8mA
0.45
V
OL
OL
V
OH
I
= –100µA
V
– 0.4V
V
Oh
CC
V
ID
11.5
1.8
12.5
100
V
I
ID
A9, E, G = V
µA
ID
Supply Voltage (Erase and Program
lock-out)
(1)
2.3
V
V
LKO
Note: 1. Sampled only, not 100% tested.
Table 12. Sequential Read Mode AC Characteristics
(T = 0 to 70°C)
A
M59BW102
25
Symbol
Alt
Parameter
Test Condition
Unit
V
= 3.0V to 3.6V
CC
Min
25
13
12
–2
–2
Typ
Max
t
t
E = V , ALE = V
Sequential Cycle
ns
ns
ns
ns
ns
CYCLE
CY
IL
IL
t
t
GW
Output Enable High to Output Enable Low
Output Enable Low to Output Enable High
Output Enable High to Chip Enable Low
Output Enable High to Chip Enable High
G = Pulse
G = Pulse
GHGL
t
t
GL
GLGH
t
t
ATT
GHEL
t
t
SBY
GHEH
Chip Enable High to Address Latch Enable
High
t
t
3
0
ns
EHALH
AV
Output Enable High to Address Latch
Enable High (following cycle)
t
t
GS
ns
ns
GHALH
(1)
t
Output Enable High to Output Valid
20
t
GACC
GHQV
(1)
t
Chip Enable Low to Output Valid
Chip Enable High to Output Hi-Z
20
12
20
ns
ns
ns
t
EACC
ELQV
t
t
EHQZ
EDF
t
t
Address Latch Enable High to Output Hi-Z
ALHQZ
ADF
Note: 1. This timing refers to a Load Capacitance (C ) of 30pF. If C is higher, add 1 ns for each extra 10pF.
L
L
10/24
M59BW102
Table 13. Random Read Mode AC Characteristics
(T = 0 to 70°C)
A
M59BW102
25
Symbol
Alt
Parameter
Test Condition
Unit
V
= 3.0V to 3.6V
CC
Min
Typ
Max
Address Latch Enable High to Address
Latch Enable Low
t
t
ALE = Pulse
10
ns
ns
ns
ns
ns
ns
ALHALL
ALW
Chip Enable Low to Address Latch Enable
Low
t
t
E
10
6
ELALL
Address Transition to Address Latch
Enable Low
t
t
AXALL
AS
Chip Enable High to Address Latch Enable
High
t
t
ELV
3
EHALH
Address Latch Enable Low to Output
Enable Low
t
t
7.5
0
ALLGL
AG
Output Enable High to Address Latch
Enable High
t
t
GHALH
QP
t
t
GW
Output Enable High to Output Enable Low
Output Enable Low to Output Enable High
G = Pulse
14
48
ns
ns
GHGL
t
t
GL
GLGH
(1)
t
Output Enable Low to Output Valid
30
55
ns
t
GACC
GLQV
(1)
t
Chip Enable Low to Output Valid
ns
ns
ns
ns
ns
ns
ns
ns
t
EACC
ELQV
t
t
Output Enable High to Chip Enable Low
Chip Enable High to Output Hi-Z
–2
GHEL
GE
t
t
12
20
EHQZ
EDF
t
t
Address Latch Enable High to Output Hi-Z
Output Valid to Output Enable High
Output Enable High to Chip Enable High
Chip Enable Low to Output Enable Low
Chip Enable High to Data Hold
ALHQZ
ADF
t
t
10
0
QVGH
GHEH
QV
t
t
GE
t
t
13
0
ELGL
EGL
t
EHQV
Address Latch Enable Low to Address
Transition
t
30
ns
ALLAX
Note: 1. This timing refers to a Load Capacitance (C ) of 30pF. If C is higher, add 1ns for each extra 10pF.
L
L
11/24
M59BW102
Figure 7. Sequential Cycle Waveforms
tCYCLE
tGHALH
ALE
tEHALH
tGHEL
tGHEH
tEHQZ
E
tGHGL
tGLGH
tEHQV
G
tELQV
A0-A15
tGHQV
tALHQZ
DQ0-DQ15
AI02767B
Figure 8. Random Mode Waveforms
tALLAX
tALHALL
ALE
tALLGL
tGLGH
tEHALH
tEHQZ
tEHQV
E
tGHGL
tELGL
tGLQV
G
tGHALH
tGHEL
tELALL
tGHEH
tQVGH
A0-A15
tAXALL
tELQV
tALHQZ
DQ0-DQ15
AI02768B
12/24
M59BW102
Table 14. Write AC Characteristics, Write Enable Controlled
(T = 0 to 70°C)
A
M59BW102
25
Symbol
Alt
Parameter
Unit
V
= 3.0V to 3.6V
CC
Min
55
Max
t
t
t
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AVAV
WC
t
t
0
30
25
0
ELWL
CS
t
WLWH
WP
t
t
DVWH
DS
DH
CH
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
WHDX
t
t
0
WHEH
t
t
20
0
WHWL
WPH
t
t
AVWL
AS
t
t
35
0
WLAX
AH
t
GHWL
t
t
V
CC
High to Chip Enable Low
50
VCHEL
VCS
t
Write Enable High to Output Enable Low
0
ns
t
OEH
WHGL
Figure 9. Write AC Waveforms, W Controlled
tAVAV
VALID
A0-A15
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ15
V
CC
tVCHEL
AI02769
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W; ALE must be High.
13/24
M59BW102
Table 15. Write AC Characteristics, Chip Enable Controlled
(T = 0 to 70°C)
A
M59BW102
25
Symbol
Alt
Parameter
Unit
V
= 3.0V to 3.6V
CC
Min
55
Max
t
t
t
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AVAV
WC
t
0
30
25
0
WLEL
WS
t
t
ELEH
CP
DS
DH
t
t
DVEH
t
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High to Chip Enable Low
EHDX
t
t
WH
0
EHWH
t
t
CPH
20
0
EHEL
t
t
AVEL
AS
t
t
35
0
ELAX
AH
t
GHEL
t
t
V
CC
High to Write Enable Low
50
VCHWL
VCS
t
Chip Enable High to Output Enable Low
0
ns
t
OEH
EHGL
Figure 10. Write AC Waveforms, E Controlled
tAVAV
VALID
A0-A15
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ15
V
CC
tVCHWL
AI02770
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E; ALE must be High.
14/24
M59BW102
Table 16. Write AC Characteristics, Write Enable Controlled and Address Latch Enable Pulsed
(T = 0 to 70°C)
A
M59BW102
25
Symbol
Alt
Parameter
Unit
V
= 3.0V to 3.6V
CC
Min
55
Max
t
t
t
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
0
30
25
0
ELWL
CS
t
WLWH
WP
t
t
DVWH
DS
DH
CH
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Output Enable High to Write Enable Low
WHDX
t
t
0
WHEH
(1)
t
20
0
t
WPH
WHWL
t
GHWL
t
t
V
CC
High to Chip Enable Low
50
0
VCHEL
VCS
t
t
Write Enable High to Output Enable Low
WHGL
OEH
t
Address Latch Enable High to Write Enable Low
Address Valid to Address Latch Enable Low
Chip Enable Low to Address Latch Enable Low
Address Latch Enable Low to Address Transition
Write Enable High to Address Latch Enable Low
Chip Enable High to Output Enable Low
10
5
ALHWL
t
AVALL
t
10
35
50
10
ELALL
t
ALLAX
(1)
t
WHALL
t
EHGL
Note: 1. These parameters are applicable only if the following cycle is for the same device.
Figure 11. Write AC Waveforms, W Controlled and Address Latch Enable Pulsed
tAVAV
A0-A15
VALID
tALLAX
tAVALL
tWHEH
tWHGL
tEHGL
E
tELWL
G
W
tGHWL
tWLWH
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ15
V
CC
tVCHEL
tELALL
tALHWL
tWHALL
ALE
AI03041B
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
15/24
M59BW102
Table 17. Suspend and Resume Last Linear Cycle Characteristics
(T = 0 to 70°C)
A
M59BW102
25
Symbol
Alt
Parameter
Unit
V
= 3.0V to 3.6V
CC
Min
15
Max
t
Address Latch Enable Low to Chip Enable Low
ns
ALLEL
Figure 12. Suspend and Resume Linear Cycle Waveforms with Bus Idle
ALE
tEHALH
tALLEL
E
tGHEH
G
Fetch
Idle
Fetch
Idle
Fetch
Idle
A0-A15
DQ0-DQ15
Even
Odd
Odd
Even
AI03248
16/24
M59BW102
Table 18. Suspend and Resume Next Linear Cycle Characteristics
(T = 0 to 70°C)
A
M59BW102
25
Symbol
Alt
Parameter
Unit
V
= 3.0V to 3.6V
CC
Min
15
Max
t
Address Latch Enable Low to Chip Enable Low
ns
ALLEL
Figure 13. Suspend and Resume Linear Cycle Waveforms without Bus Idle
ALE
tEHALH
tALLEL
E
tGHEH
G
Fetch
Even
Idle
Fetch
Idle
Fetch
Idle
Fetch
A0-A15
DQ0-DQ15
Odd
Even
Odd
AI03249
17/24
M59BW102
(1)
Table 19. Data Polling and Toggle Bit AC Characteristics
(T = 0 to 70°C)
A
M59BW102
25
Symbol
Parameter
Unit
V
= 3.0V to 3.6V
CC
Min
10
1
Max
2400
30
Write Enable High to DQ7 Valid (Program, W Controlled)
Write Enable High to DQ7 Valid (Chip Erase, W Controlled)
Chip Enable High to DQ7 Valid (Program, E Controlled)
Chip Enable High to DQ7 Valid (Chip Erase, E Controlled)
DQ7 Valid to Output Valid (Data Polling)
µs
sec
µs
t
WHQ7V
10
1
2400
30
t
EHQ7V
sec
ns
t
25
Q7VQV
Write Enable High to Output Valid (Program)
10
1
2400
30
µs
t
WHQV
Write Enable High to Output Valid (Chip Erase)
Chip Enable High to Output Valid (Program)
sec
µs
10
1
2400
30
t
EHQV
Chip Enable High to Output Valid (Chip Erase)
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
18/24
M59BW102
Figure 14. Data Polling DQ7 AC Waveform
19/24
M59BW102
Figure 15. Data Polling Flowchart
Figure 16. Data Toggle Flowchart
START
START
READ
DQ2, DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
NO
DQ2, DQ6
=
DQ7
=
DATA
YES
TOGGLE
NO
YES
NO
NO
DQ5
= 1
DQ5
= 1
YES
YES
READ DQ7
READ DQ2, DQ6
DQ7
=
DATA
YES
NO
DQ2, DQ6
=
TOGGLE
NO
YES
FAIL
PASS
FAIL
PASS
AI01369B
AI01873
Table 20. Program, Erase Times and Program, Erase Endurance Cycles
(T = 0 to 70°C; V = 3.0V to 3.6V)
A
CC
M59BW102
Typ
Parameter
Unit
Typical after
100k W/E Cycles
Min
Chip Erase (Preprogrammed)
Chip Erase
0.7
1.5
0.7
10
0.7
1.5
0.7
10
sec
sec
Chip Program
sec
Word Program
µs
Program/Erase Cycles
100,000
cycles
20/24
M59BW102
Figure 17. Data Toggle DQ6, DQ2 AC Waveforms
21/24
M59BW102
Table 21. Ordering Information Scheme
Example:
M59BW102
25
N
1
T
Device Type
M59
Architecture
B = Burst Mode
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
102 = 1 Mbit (64Kb x16)
Speed
25 = 25 ns sequential cycle time, 55 ns random access time
Package
N = TSOP40: 10 x 14 mm
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
22/24
M59BW102
Table 22. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
14.20
12.50
10.10
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.5591
0.4921
0.3976
–
A
A1
A2
B
0.05
0.95
0.17
0.10
13.80
12.30
9.90
–
0.0020
0.0374
0.0067
0.0039
0.5433
0.4843
0.3898
–
C
D
D1
E
e
0.50
0.0197
L
0.50
0°
0.70
5°
0.0197
0°
0.0276
5°
α
N
40
40
CP
0.10
0.0039
Figure 18. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
23/24
M59BW102
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
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Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
24/24
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