M68AF127BL70NK6T [STMICROELECTRONICS]
1Mbit 128K x8, 5V Asynchronous SRAM; 为1Mbit 128K ×8 ， 5V异步SRAM
| 型号： | M68AF127BL70NK6T |
| 厂家： | 
ST |
| 描述： | 1Mbit 128K x8, 5V Asynchronous SRAM |
| 文件： | 总23页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M68AF127B
1Mbit (128K x8), 5V Asynchronous SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
SUPPLY VOLTAGE: 4.5 to 5.5V
Figure 1. Packages
128K x 8 bits SRAM with OUTPUT ENABLE
EQUAL CYCLE and ACCESS TIMES: 55ns
LOW STANDBY CURRENT
LOW V DATA RETENTION: 2V
CC
TRI-STATE COMMON I/O
LOW ACTIVE and STANDBY POWER
SO32 (MC)
32
1
PDIP32 (B)
TSOP32 (NK)
8 x 13.4mm
TSOP32 (N)
8 x 20mm
September 2004
1/23
M68AF127B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . 11
Figure 11.Chip Enable Controlled, Standby Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14.E1 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
Figure 15.E2 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
Table 9. Low V Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . 17
Figure 17.PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . . 18
Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data . . . . . . . . . . . . 18
Figure 18.TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Outline. . . . . . . . 19
2/23
M68AF127B
Table 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Mechanical
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19.TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outline . . . . . . . . . . . 20
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Mechanical Data . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M68AF127B
SUMMARY DESCRIPTION
The M68AF127B is a 1Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
4.5 to 5.5V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AF127B is available in SO32, PDIP32,
TSOP32 (8x13.4mm) and TSOP32 (8x20mm)
packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A16
Address Inputs
Data Input/Output
Chip Enable
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
DQ0-DQ7
V
CC
E1
E2
G
17
8
A0-A16
DQ0-DQ7
W
W
E1
E2
G
V
CC
M68AF127B
V
SS
V
SS
AI05472B
4/23
M68AF127B
Figure 3. SO Connections
Figure 5. TSOP Connections
NC
A16
A14
A12
A7
1
32
V
A11
A9
1
32
G
CC
A15
E2
A10
E1
A8
W
A13
W
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A8
A6
E2
A5
A9
A15
A4
8
9
25
24
A11
G
V
8
9
25
24
CC
NC
M68AF127B
M68AF127B
A3
V
SS
A2
A10
E1
A16
A14
A12
A7
DQ2
DQ1
DQ0
A0
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
A6
A1
A5
A2
V
16
17
A4
16
17
A3
SS
AI07270B
AI05473d
Figure 4. DIP Connections
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32
V
CC
31 A15
30 E2
29
W
28 A13
27 A8
26 A9
25 A11
A6
A5
A4
M68AF127B
A3
24
G
A2 10
A1 11
23 A10
22 E1
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0 13
DQ1 14
DQ2 15
V
16
SS
AI07203B
5/23
M68AF127B
Figure 6. Block Diagram
A16
ROW
DECODER
MEMORY
ARRAY
A7
DQ7
I/O CIRCUITS
COLUMN
DECODER
DQ0
E1
E2
Ex
A0
A6
W
G
AI05471
6/23
M68AF127B
OPERATION
The M68AF127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Opera-
tional modes are determined by device control in-
puts W and E1 as summarized in the Operating
Modes table (Table 2).
Read Mode
The M68AF127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
within t
after the last stable address, provid-
AVQV
ing G is Low and E1 is Low. If Chip Enable or Out-
put Enable access times are not met, data access
will be measured from the limiting parameter
(t
or t
) rather than the address. Data out
ELQV
GLQV
may be indeterminate at t
lines will always be valid at t
and t
, but data
GLQX
ELQX
.
AVQV
Write Mode
The M68AF127B is in the Write mode whenever
the W and E1 pins are Low and the E2 pin is High.
Either the Chip Enable input (E1) or the Write En-
able input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of E1 being ac-
tive with W low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
The Write cycle can be terminated by the earlier
rising edge of E1, or W.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within t
of its falling edge. Care must
WLQZ
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for t
the rising edge of Write Enable, or for t
before
before
DVWH
DVEH
t
and t
, respectively, and is determined
the rising edge of E1, whichever occurs first, and
AVWL
AVEH
by the latter occurring edge.
remain valid for t
or t
.
WHDX
EHDX
Table 2. Operating Modes
Operation
E1
E2
W
G
DQ0-DQ7
Power
V
V
V
V
Active (I
CC
)
)
)
Read
Hi-Z
IL
IH
IH
IH
V
IL
V
IH
V
IH
V
Active (I
Active (I
Read
Data Output
Data Input
Hi-Z
IL
CC
CC
V
IL
V
IH
V
IL
Write
X
X
X
V
IH
Standby (I
Standby (I
)
)
Deselect
Deselect
X
X
SB
SB
V
X
X
Hi-Z
IL
Note: X = V or V .
IH
IL
7/23
M68AF127B
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
20
Unit
mA
°C
°C
V
(1)
Output Current
I
O
T
A
Ambient Operating Temperature
Storage Temperature
Supply Voltage
–55 to 125
–65 to 150
–0.5 to 6.5
T
STG
V
CC
(2)
–0.5 to V +0.5
Input or Output Voltage
Power Dissipation
V
V
CC
IO
P
1
W
D
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating V of 6.0V only.
CC
8/23
M68AF127B
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter
M68AF127B
V
CC
Supply Voltage
4.5 to 5.5V
Range 1
Range 6
0 to 70°C
–40 to 85°C
100pF
Ambient Operating Temperature
Load Capacitance (C )
L
Output Circuit Protection Resistance (R )
3.0kΩ
1
Load Resistance (R )
3.1kΩ
2
Input Rise and Fall Times
1ns/V
0 to V
Input Pulse Voltages
CC
V
/2
Input and Output Timing Ref. Voltages
Output Transition Timing Ref. Voltages
CC
V
= 0.3V ; V = 0.7V
CC RH CC
RL
Figure 7. AC Measurement I/O Waveform
Figure 8. AC Measurement Load Circuit
V
CC
I/O Timing Reference Voltage
R
1
V
CC
V
/2
CC
DEVICE
UNDER
TEST
OUT
0V
C
L
Output Transition Timing Reference Voltage
R
2
V
CC
0.7V
0.3V
CC
CC
0V
AI04831
C
includes JIG capacitance
L
AI05814
9/23
M68AF127B
Table 5. Capacitance
Symbol
Test
Condition
(1,2)
Min
Max
Unit
Parameter
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
6
8
pF
pF
IN
IN
C
V
OUT
OUT
Note: 1. Sampled only, not 100% tested.
2. At T = 25°C, f = 1MHz, V = 3.0V.
A
CC
Table 6. DC Characteristics
Symbol
Parameter
Test Condition
= 5.5V, f = 1/t
Min
Typ
Max
20
Unit
mA
mA
55
70
7.5
6.0
V
CC
,
AVAV
(1,2)
Supply Current
I
CC1
I
= 0mA
OUT
15
V
CC
= 5.5V, f = 1MHz,
(3)
Operating Supply Current
2
mA
I
CC2
I
= 0mA
OUT
I
0V ≤V ≤V
IN CC
Input Leakage Current
Output Leakage Current
–1
–1
1
1
µA
µA
LI
(4)
0V ≤V
≤V
CC
I
OUT
LO
V
CC
= 5.5V, E1 ≥ V – 0.2V,
CC
I
SB
Standby Supply Current CMOS
2.5
15
µA
E2 ≤0.2V, f = 0
V
V
+ 0.3
CC
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
2.2
–0.3
2.4
V
V
V
V
IH
V
0.8
IL
V
OH
I
I
= –1mA
= 2.1mA
OH
V
OL
0.4
OL
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. E1 = V , E2 = V , V = V or V .
IL
IH
IN
IH
IL
3. E1 ≤0.2V or E2 ≥ V –0.2V, V ≤0.2V or VIN ≥ V –0.2V.
CC
IN
CC
4. Output disabled.
10/23
M68AF127B
Figure 9. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
AI05474
Note: E1 = Low, E2 = High, G = Low, W = High.
Figure 10. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E1
E2
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI05476
Note: Write Enable (W) = High.
11/23
M68AF127B
Figure 11. Chip Enable Controlled, Standby Mode AC Waveforms
E1
E2
tPU
tPD
I
CC
50%
I
SB
AI05477
12/23
M68AF127B
Table 7. Read and Standby Mode AC Characteristics
M68AF127B
Symbol
Parameter
Unit
55
55
55
70
70
70
t
Read Cycle Time
Min
Max
Min
ns
ns
ns
AVAV
t
Address Valid to Output Valid
AVQV
(1)
Data hold from address change
5
20
55
5
5
25
70
5
t
AXQX
(2,3)
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
Chip Enable or UB/LB High to Power Down
Chip Enable or UB/LB Low to Power Up
Max
Max
Min
ns
ns
ns
ns
ns
ns
ns
ns
t
t
EHQZ
t
ELQV
(1)
t
ELQX
(2,3)
Max
Max
Min
20
25
5
25
35
5
GHQZ
t
GLQV
(2)
t
GLQX
Max
Min
55
0
70
0
t
PD
t
PU
Note: 1. Test conditions assume transition timing reference level = 0.3V or 0.7V
.
CC
CC
2. At any given temperature and voltage condition, t
is less than t
and t
is less than t
for any given device.
ELQX
GHQZ
GLQX
EHQZ
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
13/23
M68AF127B
Figure 12. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVWH
tAVEL
tELWH
tWHAX
E1
E2
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI05478
Figure 13. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVEH
tELEH
tAVEL
tEHAX
E1
E2
tAVWL
tWLEH
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI05479
14/23
M68AF127B
Table 8. Write Mode AC Characteristics
M68AF127B
Symbol
Parameter
Unit
55
55
45
0
70
70
60
0
t
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
Input Valid to Chip Enable High
AVEH
t
AVEL
t
45
0
60
0
AVWH
t
AVWL
t
25
25
0
30
30
0
DVEH
t
Input Valid to Write Enable High
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to Chip Enable High
Chip Enable Low to Write Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Output Transition
Write Enable Low to Chip Enable High
Write Enable Low to Output Hi-Z
DVWH
t
EHAX
t
0
0
EHDX
t
45
45
0
60
60
0
ELEH
t
ELWH
t
WHAX
t
0
0
WHDX
(1)
5
5
t
WHQX
t
45
20
45
60
20
60
WLEH
(1,2)
t
WLQZ
t
Write Enable Low to Write Enable High
Min
ns
WLWH
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WLQZ
WHQX
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
15/23
M68AF127B
Figure 14. E1 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
5.5V
V
4.5V
CC
V
> 2.0V
DR
E1
tCDR
tR
E1 ≥ V
– 0.2V
DR
AI07204
Figure 15. E2 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
5.5V
V
4.5V
CC
V
> 2.0V
DR
E2
tCDR
tR
E2 ≤ 0.2V
AI07205B
Table 9. Low V Data Retention Characteristics
CC
Symbol
Parameter
Test Condition
Min
Max
4.5
Unit
V
CC
= 2.0V, E1 ≥ V –0.2V or
CC
(1)
Supply Current (Data Retention)
µA
I
CCDR
E2 ≤0.2V, f = 0
(1,2)
Chip Deselected to Data Retention Time
Operation Recovery Time
0
ns
ns
V
t
CDR
(2)
t
t
R
AVAV
(1)
E1 ≥ V –0.2V or E2 ≤0.2V, f = 0
Supply Voltage (Data Retention)
2.0
V
DR
CC
Note: 1. All other Inputs at V ≥ V –0.2V or V ≤0.2V.
IH
CC
IL
2. Tested initially and after any design or process that may affect these parameters. t
AVAV
is Read cycle time.
3. No input may exceed V +0.2V.
CC
16/23
M68AF127B
PACKAGE MECHANICAL
Figure 16. SO32 - 32 lead Plastic Small Outline, Package Outline
D
16
1
E
E1
17
32
A2
A
C
L
CP
A1
B
e
L1
SO-C
Note: Drawing is not to scale.
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data
millimeters
Symbol
inches
Min
Typ
Min
Max
0.51
3.00
Typ
Max
0.020
0.118
B
A
0.36
0.014
A1
A2
C
0.10
2.57
0.15
0.004
0.101
0.006
2.82
0.30
0.10
20.75
11.43
14.38
–
0.111
0.012
0.004
0.817
0.450
0.566
–
CP
D
20.14
11.18
13.87
–
0.793
0.440
0.546
–
E
E1
e
1.27
0.050
L
0.58
1.19
32
0.99
1.60
0.023
0.047
32
0.039
0.063
L1
N
17/23
M68AF127B
Figure 17. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2
A1
A
L
α
c
b1
b
e
eA
D2
D
S
N
1
E1
E
PDIP-C
Note: Drawing is not to scale.
Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
4.83
0.190
0.38
0.015
3.81
0.150
0.41
1.14
0.23
41.78
–
0.53
1.65
0.38
42.29
–
0.016
0.045
0.009
1.645
–
0.021
0.065
0.015
1.665
–
b1
c
D
eA
e
15.24
2.54
0.600
0.100
–
–
–
–
E
15.24
13.46
3.05
1.65
0°
15.88
13.97
3.56
2.21
15°
0.600
0.530
0.120
0.065
0°
0.625
0.550
0.140
0.087
15°
E1
L
S
α
N
32
32
18/23
M68AF127B
Figure 18. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
Table 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
Typ
Max
A
A1
A2
B
0.0472
0.0059
0.0413
0.05
0.91
0.0020
0.0358
0.22
0.0087
C
0.10
0.21
0.10
–
0.0039
0.0083
CP
D
0.0039
13.40
11.80
8.00
–
–
0.5276
0.4646
0.3150
0.0197
–
–
D1
E
–
–
–
–
–
–
–
–
–
e
0.50
–
–
L
0.40
0°
32
0.60
5°
0.0157
0°
0.0236
5°
α
N
32
19/23
M68AF127B
Figure 19. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
α
L
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.250
0.210
0.100
20.200
18.500
–
Typ
Max
0.0472
0.0059
0.0413
0.0098
0.0083
0.0039
0.7953
0.7283
–
A
A1
A2
B
0.050
0.950
0.170
0.100
0.0020
0.0374
0.0067
0.0039
C
CP
D
19.800
18.300
–
0.7795
0.7205
–
D1
e
0.500
0.0197
E
7.900
0.500
0°
8.100
0.700
5°
0.3110
0.0197
0°
0.3189
0.0276
5°
L
α
N
32
32
20/23
M68AF127B
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M68AF127
B
L
55 MC
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
F = 4.5 to 5.5V
Array Organization
127 = 1Mbit (128K x8)
Option 1
B = 2 Chip Enable
Option 2
L = L-Die
M = M-Die
Speed Class
55 = 55ns
70 = 70ns
Package
MC = SO32
B = PDIP32
NK = TSOP32 8x13.4mm
N = TSOP32 8x20mm
Operative Temperature
1 = 0 to 70°C
6 = –40 to 85°C
Shipping
T = Tape & Reel Packing
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
21/23
M68AF127B
REVISION HISTORY
Table 15. Document Revision History
Date
Version
1.0
Revision Details
August 2001
18-Oct-2001
29-Nov-2001
06-Mar-2002
17-May-2002
First Issue.
2.0
SO32 Package Mechanical and Data added (Figure 1, 3 and 16, Table 10).
Note removed from Ordering Information Scheme.
Document status changed to Data Sheet.
3.0
4.0
5.0
Document globally revised.
PDIP32 Package added (Figure 1, 4 and 17, Table 11).
31-May-2002
09-Sep-2002
6.0
6.1
Chip Enable Low V Data Retention clarified (Figure 14 and 15, Table 9).
CC
TSOP32 8x13.4mm and TSOP32 8x20mm packages added (Figure 1, 5, 18 and 19,
Table 12, 13 and 14).
Commercial code clarified.
02-Oct-2002
09-Oct-2002
16-Apr-2003
6.2
6.3
6.4
Title and header layout modified.
Datasheet number simplified.
Label corrected on “E2 Controlled, Low V Data Retention AC Waveforms” figure.
CC
TSOP Package connections modified (Figure 5).
Test conditions for ICCDR modified in Table 9, Low V Data Retention
Characteristics.
08-Aug-2003
21-Aug-2003
6.5
6.6
CC
TSOP Package connections modified (Figure 5).
Document structure modified:
–
–
Chapter OPERATION moved before chapter MAXIMUM RATING.
AC Characteristics Tables and waveforms moved to the DC/AC PARAMETERS
section.
24-Sep-2004
7
t
ad t updated in Table 7.
PU
PD
22/23
M68AF127B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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23/23
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