M68AR512DL55ZB6T [STMICROELECTRONICS]
512KX16 STANDARD SRAM, 55ns, PBGA48, 8 X 10 MM, 0.75 MM PITCH, TFBGA-48;
| 型号： | M68AR512DL55ZB6T |
| 厂家： | 
ST |
| 描述： | 512KX16 STANDARD SRAM, 55ns, PBGA48, 8 X 10 MM, 0.75 MM PITCH, TFBGA-48 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M68AR512D
8 Mbit (512Kb x16) 1.8V Asynchronous SRAM
FEATURES SUMMARY
I SUPPLY VOLTAGE: 1.65V to 1.95V
Figure 1. Package
I 512Kb x16 bit SRAM with OUTPUT ENABLE
I EQUAL CYCLE and ACCESS TIMES: 55ns,
70ns
I SINGLE BYTE READ/WRITE
I LOW STANDBY CURRENT
BGA
I LOW V
DATA RETENTION: 1.0V
CC
I TRI-STATE COMMON I/O
I AUTOMATIC POWER DOWN
I DUAL CHIP ENABLE for EASY DENSITY
EXPANSION
TGA48 (ZB)
6 x 7mm
February 2004
1/19
M68AR512D
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Standby/Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . 10
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . 10
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.UB/LB Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.E1 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
Figure 14.E2 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
Table 9. Low V Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15.TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . 16
Table 10. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 16
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/19
M68AR512D
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SUMMARY DESCRIPTION
The M68AR512D is an 8 Mbit (8,388,608 bit)
CMOS SRAM, organized as 524,288 Words by 16
bits.
Table 1. Signal Names
A0-A18
Address Inputs
It has a fully static operation and so requires no ex-
ternal clock or timing strobe. The device has equal
address access and cycle times, and it operates
from a single 1.8V ( 150mV) voltage supply.
The M69AR512D features two Chip Enable pins
(E1 and E2), which makes memory expansion
easy. It also has an automatic standby mode in
which power consumption is reduced by over
99%.
The M68AR512D is available in TFBGA48
(6 x 7mm, 6x8 active ball array, 0.75mm ball pitch)
packages. See Table 11., Ordering Information
Scheme, for details.
DQ0-DQ15
Data Input/Output
Chip Enable
E1, E2
G
Output Enable
W
Write Enable
UB
LB
Upper Byte Enable Input
Lower Byte Enable Input
Supply Voltage
V
CC
V
SS
Ground
Figure 2. Logic Diagram
NC
DU
Not Connected
Don’t Use as Internally Connected
V
CC
19
16
A0-A18
W
DQ0-DQ15
E1
E2
M68AR512D
G
UB
LB
V
SS
AI03953C
3/19
M68AR512D
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A2
E1
E2
A
B
C
D
E
F
LB
G
A0
A3
A1
A4
A6
DQ8
DQ9
DQ0
DQ2
UB
DQ10
DQ11
DQ12
DQ13
NC
A5
DQ1
DQ3
DQ4
DQ5
W
A7
V
A17
V
SS
CC
V
V
A16
A15
A13
A10
V
CC
SS
SS
DQ14
DQ15
A18
A14
A12
A9
DQ6
DQ7
DU
G
H
A8
A11
AI03960
4/19
M68AR512D
Figure 4. Block Diagram
A18
A8
ROW
DECODER
MEMORY
ARRAY
DQ15
UB
(8)
(8)
I/O CIRCUITS
COLUMN
DECODER
DQ0
LB
E1
E2
Ex
UB
LB
A0
A7
(8)
(8)
UB
LB
W
G
AI05452
5/19
M68AR512D
OPERATION
The device has four standard operationg modes:
Output Disabled, Read, Write and Standby/Pow-
er-Down. These modes are determined by the
control inputs G, W, E1, LB and UB as summa-
rized in Table 2., Operating Modes.
Data out may be indeterminate at t
BLQX
, t
and
AVQV
ELQX GLQX
, but data lines will always be valid at t
t
.
Write Mode. Write operations are used to write
data to the SRAM.
The M68AR512D is in Write mode whenever the
Output Disabled. The Output Enable signal, G,
provides high-speed tri-state control of DQ0-
DQ15, allowing fast read/write cycles on the com-
mon I/O data bus. The device is in Output Dis-
abled mode when Output Enable, G, is High. In
this mode, LB and UB are Don’t care and DQ0-
DQ15 are high impedance.
device is selected (Chip Enable E1 at V and Chip
IL
Enable E2 at V ), W is at V , G is Don’t Care and
IH
IL
at least one of the Byte Enable inputs, UB and LB,
is at V .
IL
If only one of the Byte Enable inputs is at V , the
IL
M68AR512D is in Byte Write mode. If the two Byte
Enable inputs are at V , the M68AR512D is in
IL
Read Mode. Read operations are used to output
the contents of the SRAM Array.
Word Write mode
If the Output is enabled (G = Low, E1 = Low, E2 =
High, UB and/or LB = Low), then W will return the
The M68AR512D is in Read mode whenever the
device is selected (Chip Enable E1 at V and Chip
IL
outputs to high impedance within t
of its fall-
WLQZ
Enable E2 at V ), Write Enable, W, is at V , Out-
IH
IH
ing edge. Care must be taken to avoid bus conten-
put Enable, G, is at V and at least one of the Byte
IL
tion in this type of operation. Data input must be
Enable inputs, UB and LB, is at V .
IL
valid t
DVEH
before the rising edge of Write Enable,
DVWH
If only one of the Byte Enable inputs is at V , the
t
before the rising edge of E1 or t
before
IL
DVBH
M68AR512D is in Byte Read mode. If the two Byte
the rising edge of UB/LB, whichever occurs first,
and remain valid for t
tively.
Enable inputs are at V , the M68AR512D is in
, t
or t
respec-
IL
WHDX EHDX
BHDX
Word Read mode. So depending on the status of
the UB and LB signals, valid data will be available
on the lower eight, the upper eight or all sixteen
Standby/Power-Down Mode. The M68AR512D
has a Power Down feature which invokes an auto-
matic standby mode whenever the device is dese-
lected, that is, whenever Chip Enable E1 is High,
Chip Enable E2 is Low, or UB/LB are High UB/LB.
ouptput pins, t
after the last stable address.
AVQV
If either of E1, E2, G and UB/LB is asserted after
has elapsed, data access will be measured
t
AVQV
from the limiting parameter (t
, t
or t
)
ELQV GLQV
BLQV
rather than the address.
Table 2. Operating Modes
Operation
E1
E2
W
G
LB
UB
DQ0-DQ7
Hi-Z
DQ8-DQ15
Hi-Z
Power
V
IL
V
V
IH
Active (I
CC
)
)
Output Disabled
X
X
X
IH
V
V
V
V
V
V
Hi-Z
Data Output
Hi-Z
IL
IH
IH
IL
IH
IL
V
IL
V
V
V
V
IL
V
V
IH
Active (I
Read
Data Output
IH
IH
IH
IL
CC
CC
V
IL
V
V
IL
V
V
IL
Data Output Data Output
IH
IL
V
IL
V
V
V
V
V
V
IH
X
X
X
X
X
X
Data Input
Hi-Z
Hi-Z
Data Input
Data Input
Hi-Z
IH
IL
IL
IL
IL
V
IL
V
V
IH
V
IL
Active (I
)
Write
IH
V
IL
V
V
V
IL
Data Input
Hi-Z
IH
IL
V
X
X
X
X
X
X
IH
V
Standby (I
)
SB
Standby/Power-Down
X
X
X
X
Hi-Z
Hi-Z
IL
V
IH
V
IH
X
Hi-Z
Hi-Z
Note: X = V or V .
IH
IL
6/19
M68AR512D
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
20
Unit
mA
°C
°C
V
(1)
Output Current
I
O
T
A
Ambient Operating Temperature
Storage Temperature
Supply Voltage
–55 to 125
–65 to 150
–0.5 to 2.5
T
STG
V
CC
(2)
–0.5 to V +0.5
Input or Output Voltage
Power Dissipation
V
V
CC
IO
P
1
W
D
Note: 1. One output at a time, not to exceed 1 second duration.
2.Up to a maximum operating V of 1.95V only.
CC
7/19
M68AR512D
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter
M68AR512D
Unit
55
1.65 to 1.95
0 to 70
–40 to 85
30
70
1.65 to 1.95
0 to 70
–40 to 85
30
V
CC
Supply Voltage
V
°C
°C
pF
kΩ
kΩ
ns/V
V
Range 1
Range 6
Ambient Operating Temperature
Load Capacitance (C )
L
Output Circuit Protection Resistance (R )
15.3
15.3
1
Load Resistance (R )
11.3
11.3
2
Input Rise and Fall Times
1
1
0 to V
0 to V
Input Pulse Voltages
CC
CC
V
/2
V
/2
CC
Input and Output Timing Ref. Voltages
V
CC
V
V
= 0.3V
= 0.7V
;
V
V
= 0.3V
CC
= 0.7V
RH CC
;
RL
CC
RL
Output Transition Timing Ref. Voltages
V
RH
CC
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
V
CC
I/O Timing Reference Voltage
R
1
V
CC
V
/2
CC
DEVICE
UNDER
TEST
OUT
0V
C
L
Output Timing Reference Voltage
R
2
V
CC
0.7V
0.3V
CC
CC
0V
AI04831
C
includes probe and 1TTL capacitance
L
AI03853
8/19
M68AR512D
Table 5. Capacitance
Symbol
Test
Condition
(1,2)
Min
Max
Unit
Parameter
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
6
8
pF
pF
IN
IN
C
V
OUT
OUT
Note: 1. Sampled only, not 100% tested.
2.At T = 25°C, f = 1 MHz, V = 1.8V.
A
CC
Table 6. DC Characteristics
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
70ns (L-Die)
55ns (N-Die)
12
15
V
CC
= 1.95V, f = 1/t
,
AVAV
(1,2)
Operating Supply Current
mA
mA
I
CC1
I
= 0mA
OUT
V
CC
= 1.95V, f = 1MHz,
(3)
Operating Supply Current
2
I
CC2
I
= 0mA
OUT
I
0V ≤ V ≤ V
IN CC
Input Leakage Current
Output Leakage Current
–1
–1
1
1
µA
µA
LI
(4)
0V ≤ V
≤ V
CC
I
I
OUT
LO
V
= 1.95V,
CC
E1 ≥ V –0.2V or
Standby Supply Current
CMOS
CC
(3)
1
20
µA
SB
E2 ≤ 0.2V or
UB=LB ≥ V –0.2V, f = 0
CC
V
V
CC
+ 0.4
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.4
–0.5
1.5
V
V
V
V
IH
V
0.4
0.2
IL
V
OH
I
= –100µA
OH
V
OL
I
OL
= 100µA
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. E1 = V , E2 = V , UB or/and LB = V , V = V or V .
IL
IH
IL
IN
IH
IL
3. E1 ≤ 0.2V or E2 ≥ V –0.2V, LB or/and UB ≤ 0.2V, V ≤ 0.2V or VIN ≥ V –0.2V.
CC
IN
CC
4. Output disabled.
9/19
M68AR512D
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A18
VALID
tAVQV
tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI03961b
Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low.
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
A0-A18
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E1
E2
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ15
VALID
tBLQV
tBHQZ
UB, LB
tBLQX
AI05994b
Note: Write Enable (W) = High
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
E1, UB, LB
E2
tPU
tPD
I
CC
50%
I
SB
AI05990
10/19
M68AR512D
Table 7. Read and Standby Mode AC Characteristics
M68AR512D
Symbol
Parameter
Unit
55
70
70
70
t
Read Cycle Time
Min
55
55
ns
ns
AVAV
t
Address Valid to Output Valid
Max
AVQV
(1)
Data hold from address change
Min
Max
Max
Min
5
20
55
5
5
25
70
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AXQX
(2, 3)
Upper/Lower Byte Enable High to Output Hi-Z
Upper/Lower Byte Enable Low to Output Valid
Upper/Lower Byte Enable Low to Output Transition
Chip Enable High to Output Hi-Z
t
t
t
BHQZ
t
BLQV
(1)
t
BLQX
(2, 3)
Max
Max
Min
20
55
5
25
70
5
EHQZ
t
Chip Enable Low to Output Valid
ELQV
(1)
Chip Enable Low to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
Chip Enable High to Power Down
t
ELQX
(2, 3)
Max
Max
Min
20
25
5
25
35
5
GHQZ
t
GLQV
(1)
t
GLQX
(4)
Max
Min
0
0
t
PD
t
PU
(4)
Chip Enable Low to Power Up
55
70
Note: 1. Test conditions assume transition timing reference level = 0.3V
to 0.7V
.
CCQ
CCQ
2. At any given temperature and voltage condition, t
is less than t
, t
is less than t
and t
is less than t
for
GHQZ
GLQX BHQZ
BLQX
EHQZ
ELQX
any given device.
3. These parameters are defined as the times at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4.Tested initially and after any design or process changes that may affect these parameters.
11/19
M68AR512D
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVWH
tAVEL
tELWH
tWLWH
tWHAX
E1
E2
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ15
UB, LB
DATA INPUT
tDVWH
tBLBH
AI05995b
12/19
M68AR512D
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVEH
tELEH
tAVEL
tEHAX
E1
E2
tAVWL
tWLEH
W
tEHDX
DQ0-DQ15
UB, LB
DATA INPUT
tDVEH
tBLBH
AI05996b
Figure 12. UB/LB Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVBH
tBHAX
E1
E2
tAVWL
tWLBH
W
tWLQZ
tBHDX
DQ0-DQ15
DATA (1)
DATA INPUT
tDVBH
tAVBL
tBLBH
UB, LB
AI05997b
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
13/19
M68AR512D
Table 8. Write Mode AC Characteristics
M68AR512D
55
Symbol
Parameter
Unit
70
70
60
0
t
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
55
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to LB, UB High
AVBH
t
Address Valid to LB, UB Low
AVBL
t
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
LB, UB High to Address Transition
LB, UB High to Input Transition
LB, UB Low to LB, UB High
45
0
60
0
AVEH
t
AVEL
t
45
0
60
0
AVWH
t
AVWL
t
0
0
BHAX
t
0
0
BHDX
t
45
45
45
25
25
25
0
60
60
60
30
30
30
0
BLBH
t
LB, UB Low to Chip Enable High
LB, UB Low to Write Enable High
Input Valid to LB, UB High
BLEH
t
BLWH
t
DVBH
t
Input Valid to Chip Enable High
Input Valid to Write Enable High
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to LB, UB High
Chip Enable Low to Chip Enable High
Chip Enable Low to Write Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Output Transition
Write Enable Low to LB, UB High
Write Enable Low to Chip Enable High
DVEH
t
DVWH
t
EHAX
t
0
0
EHDX
t
45
45
45
0
60
60
60
0
ELBH
t
ELEH
t
ELWH
t
WHAX
t
0
0
WHDX
(1)
5
5
t
WHQX
t
45
45
60
60
WLBH
t
WLEH
(1, 2)
Write Enable Low to Output Hi-Z
Max
Min
20
40
20
60
ns
ns
t
WLQZ
t
Write Enable Low to Write Enable High
WLWH
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WLQX
WHQZ
2.These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
14/19
M68AR512D
Figure 13. E1 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
1.95V
V
1.8V
CC
V
> 1.0V
DR
tCDR
tR
E1 ≥ V
DR
– 0.2V or UB,LB ≥ V
– 0.2V
DR
E1
UB, LB
AI05455b
Figure 14. E2 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
1.95V
V
1.65V
CC
V
> 1.0V
DR
tCDR
tR
E2
E2 ≤ 0.2V
AI05475
Table 9. Low V
Symbol
Data Retention Characteristics
CC
Parameter
Test Condition
Min
Typ
Max
Unit
V
= 1.0V, E1 ≥ V –0.2V or
CC
CC
(1)
E2 ≤ 0.2V or
Supply Current (Data Retention)
0.1
8
µA
I
CCDR
(3)
UB/LB ≥ V –0.2V, f = 0
CC
Chip deselected to Data
Retention Time
(2)
0
ns
ns
t
CDR
(2)
t
Operation Recovery Time
t
R
AVAV
E1 ≥ V –0.2V or
CC
E2 ≤ 0.2V or
(1)
Supply Voltage (Data Retention)
1.0
V
V
DR
UB/LB ≥ V –0.2V,
CC
f = 0
Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.
IH
CC
IL
2.Tested initially and after any design or process changes that may affect these parameters. t
is Read cycle time.
AVAV
3.No input may exceed V +0.3V.
CC
15/19
M68AR512D
PACKAGE MECHANICAL
Figure 15. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z43
Note: Drawing is not to scale.
Table 10. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.400
Typ
Max
A
A1
A2
b
0.0472
0.0157
0.250
0.0098
0.790
0.400
6.000
3.750
0.0311
0.0157
0.2362
0.1476
0.350
5.900
0.450
6.100
0.0138
0.2323
0.0177
0.2402
D
D1
ddd
E
0.100
7.100
0.0039
0.2795
7.000
5.250
0.750
1.125
0.875
0.375
0.375
6.900
0.2756
0.2067
0.0295
0.0443
0.0344
0.0148
0.0148
0.2717
E1
e
–
–
–
–
FD
FE
SD
SE
–
–
–
–
–
–
–
–
16/19
M68AR512D
PART NUMBERING
Table 11. Ordering Information Scheme
Example:
M68AR512
D
N
70 ZB
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
R = 1.65 to 1.95V
Array Organization
512 = 8 Mbit (512K x16)
Option 1
D = 2 Chip Enable; Write and Standby from UB and LB
Option 2
L = L-Die
N = N-Die
Speed Class
55 = 55ns
70 = 70ns
Package
(1)
ZB = TFBGA48, 6x7mm, 6x8 ball array 0.75 mm pitch
Operative Temperature
1 = 0 to 70 °C
6 = –40 to 85 °C
Shipping
T = Tape & Reel Packing
Note: 1. TFBGA48, 6x7mm is available only for the M68AR512DN part (N-Die).
2. TFBGA48, 8x10mm is available only for the M68AR512DL part (L-Die).
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
17/19
M68AR512D
REVISION HISTORY
Table 12. Document Revision History
Date
Version
-01
Revision Details
August 2001
08-Oct-2001
First Issue
-02
Document status moved to Preliminary Data
Document status moved to Data Sheet
Temperature range 1 (0 to 70°C) added
Tables 4, 6, 2, 7, 8 and 9 clarified
18-Mar-2002
17-May-2002
02-Oct-2002
-03
-04
4.1
Figures 7, 8, 9, 10, 11 and 12 clarified
Document globally revised
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 04 equals 4.0).
Part number changed.
Part number changed and new sales type added
TFBGA48 8x10mm package added (Figure 16, Table 11)
09-Oct-2002
19-Feb-2004
4.2
5.0
55ns speed class added. I parameter modified in Table 6., DC Characteristics.
SB
t
parameter modified in Table 8., Write Mode AC Characteristics.
WLWH
Drawings clarified. TFBGA48 8x10mm package removed.
18/19
M68AR512D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
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19/19
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