M68AW127BM10NK6T [STMICROELECTRONICS]
1Mbit 128K x8, 3.0V Asynchronous SRAM; 为1Mbit 128K ×8 , 3.0V异步SRAM型号: | M68AW127BM10NK6T |
厂家: | ST |
描述: | 1Mbit 128K x8, 3.0V Asynchronous SRAM |
文件: | 总20页 (文件大小:309K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M68AW127B
1Mbit (128K x8), 3.0V Asynchronous SRAM
FEATURES SUMMARY
■ SUPPLY VOLTAGE: 2.7 to 3.6V
Figure 1. Packages
■ 128K x 8 bits SRAM with OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIMES: 70ns
■ LOW STANDBY CURRENT
■ LOW V
DATA RETENTION: 1.5V
CC
■ TRI-STATE COMMON I/O
■ LOW ACTIVE and STANDBY POWER
SO32 (MC)
TSOP32
8 x 20 mm
(N)
TSOP32
8 x 13.4 mm
(NK)
August 2003
1/20
M68AW127B
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 6
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . 9
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. E1 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Figure 14. E2 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . 15
TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline. . . . . . . . . . . . . . . . . . . . . . . . 16
TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data . . . . . . . . . . . . . . . . 16
TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . 17
TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data . . . . . . . . . . . . . . 17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19
2/20
M68AW127B
SUMMARY DESCRIPTION
The M68AW127B is a 1Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
2.7 to 3.6V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AW127B is available in SO32, TSOP32
8x20mm and TSOP32 8x13.4mm packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A16
Address Inputs
Data Input/Output
Chip Enable
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
DQ0-DQ7
V
CC
E1
E2
G
17
8
A0-A16
DQ0-DQ7
W
W
E1
E2
G
V
CC
M68AW127B
V
SS
V
SS
AI05972b
3/20
M68AW127B
Figure 3. SO Connections
Figure 4. TSOP Connections
A11
A9
1
32
G
NC
A16
A14
A12
A7
1
32
V
CC
A15
A10
E1
A8
E2
A13
W
DQ7
DQ6
DQ5
DQ4
DQ3
W
A13
A8
E2
A6
A15
A5
A9
V
8
9
25
24
CC
NC
A4
8
9
25
24
A11
G
M68AW127B
M68AW127B
V
SS
A3
A16
A14
A12
A7
DQ2
DQ1
DQ0
A0
A2
A10
E1
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
A6
A1
A5
A2
A4
16
17
A3
V
16
17
SS
AI05973c
AI05931b
4/20
M68AW127B
Figure 5. Block Diagram
A16
ROW
DECODER
MEMORY
ARRAY
A7
DQ7
I/O CIRCUITS
COLUMN
DECODER
DQ0
E1
E2
Ex
A0
A6
W
G
AI05471
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
20
Unit
mA
°C
°C
V
(1)
Output Current
I
O
T
A
Ambient Operating Temperature
Storage Temperature
Supply Voltage
–55 to 125
–65 to 150
–0.3 to 4.6
T
STG
V
CC
(2)
–0.5 to V +0.5
Input or Output Voltage
Power Dissipation
V
V
IO
CC
P
D
1
W
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating V of 3.6V only.
CC
5/20
M68AW127B
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M68AW127B
V
CC
Supply Voltage
2.7 to 3.6V
Range 1
Range 6
0 to 70°C
–40 to 85°C
100pF
Ambient Operating Temperature
Load Capacitance (C )
L
Output Circuit Protection Resistance (R )
3.0kΩ
1
Load Resistance (R )
3.1kΩ
2
Input Rise and Fall Times
1ns/V
0 to V
Input Pulse Voltages
CC
V
/2
Input and Output Timing Ref. Voltages
Output Transition Timing Ref. Voltages
CC
V
RL
= 0.3V ; V = 0.7V
CC RH CC
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
V
CC
I/O Timing Reference Voltage
R
1
V
CC
V
/2
CC
DEVICE
UNDER
TEST
OUT
0V
C
L
Output Transition Timing Reference Voltage
R
2
V
CC
0.7V
0.3V
CC
CC
0V
AI04831
C
includes JIG capacitance
L
AI05814
6/20
M68AW127B
Table 4. Capacitance
Symbol
Test
Condition
(1,2)
Min
Max
Unit
Parameter
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
6
8
pF
pF
IN
IN
C
V
OUT
OUT
Note: 1. Sampled only, not 100% tested.
2. At T = 25°C, f = 1MHz, V = 3.0V.
A
CC
Table 5. DC Characteristics
Symbol
Parameter
Test Condition
= 3.6V, f = 1/t
Min
Typ
Max
Unit
mA
mA
70
6.0
25
15
35
V
,
AVAV
CC
(1,2)
Supply Current
I
CC1
I
= 0mA
OUT
100
V
= 3.6V, f = 1MHz,
CC
Operating Supply Current
70
2
5
mA
mA
mA
I
= 0mA
OUT
Operating Supply Current
(READ)
(3)
I
1.5
10
CC2
V
CC
= 3.6V, f = 1MHz,
= 0mA
100
I
OUT
Operating Supply Current
(WRITE)
15
I
0V ≤ V ≤ V
IN CC
Input Leakage Current
Output Leakage Current
–1
–1
1
1
µA
µA
LI
(4)
0V ≤ V
≤ V
CC
I
OUT
LO
70
2.5
0.3
15
10
µA
µA
V
V
CC
= 3.6V, E1 ≥ V – 0.2V,
E2 ≤ 0.2V, f = 0
Standby Supply Current
CMOS
CC
I
SB
100
V
V
+ 0.3
Input High Voltage
Input Low Voltage
2.2
–0.3
–0.3
2.4
IH
CC
70
100
70
0.8
0.6
V
V
IL
V
I
= –1mA
V
OH
V
Output High Voltage
Output Low Voltage
OH
100
2.2
V
V
I
OL
= 2.1mA
0.4
V
OL
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. E1 = V , E2 = V , V = V or V .
IL
IH
IN
IH
IL
3. E1 ≤ 0.2V or E2 ≥ V –0.2V, V ≤ 0.2V or VIN ≥ V –0.2V.
CC
IN
CC
4. Output disabled.
7/20
M68AW127B
OPERATION
The M68AW127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Opera-
tional modes are determined by device control in-
puts W and E1 as summarized in the Operating
Modes table (Table 6).
Table 6. Operating Modes
Operation
E1
E2
W
G
DQ0-DQ7
Hi-Z
Power
V
V
IH
V
IH
V
IH
Active (I
CC
)
)
)
Read
IL
V
V
V
V
Active (I
Active (I
Read
Data Output
Data Input
Hi-Z
IL
IH
IH
IL
CC
CC
V
IL
V
IH
V
IL
Write
X
V
Standby (I
Standby (I
)
)
Deselect
Deselect
X
X
X
X
IH
SB
SB
V
X
X
Hi-Z
IL
Note: X = V or V .
IH
IL
Read Mode
The M68AW127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
within t
after the last stable address, provid-
AVQV
ing G is Low and E1 is Low. If Chip Enable or Out-
put Enable access times are not met, data access
will be measured from the limiting parameter
(t
ELQV
or t
) rather than the address. Data out
GLQV
may be indeterminate at t
lines will always be valid at t
and t , but data
GLQX
ELQX
.
AVQV
Figure 8. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
AI05474
Note: E1 = Low, E2 = High, G = Low, W = High.
8/20
M68AW127B
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV
A0-A16
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E1
E2
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI05476
Note: Write Enable (W) = High.
Figure 10. Chip Enable Controlled, Standby Mode AC Waveforms
E1
E2
tPU
tPD
I
CC
50%
I
SB
AI05477
9/20
M68AW127B
Table 7. Read and Standby Mode AC Characteristics
M68AW127B
Symbol
Parameter
Unit
70
100
100
100
t
Read Cycle Time
Min
Max
Min
70
70
5
ns
ns
ns
AVAV
t
Address Valid to Output Valid
AVQV
(1)
Data hold from address change
15
30
100
10
30
50
5
t
AXQX
(2,3)
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
Chip Enable or UB/LB High to Power Down
Chip Enable or UB/LB Low to Power Up
Max
Max
Min
25
70
5
ns
ns
ns
ns
ns
ns
ns
ns
t
t
EHQZ
t
ELQV
(1)
t
ELQX
(2,3)
Max
Max
Min
25
35
5
GHQZ
t
GLQV
(2)
t
GLQX
(4)
Max
Min
0
0
t
t
PD
PU
(4)
70
100
Note: 1. Test conditions assume transition timing reference level = 0.3V or 0.7V
.
CC
CC
2. At any given temperature and voltage condition, t
is less than t
and t
is less than t
for any given device.
ELQX
GHQZ
GLQX
EHQZ
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters.
10/20
M68AW127B
Write Mode
The M68AW127B is in the Write mode whenever
the W and E1 pins are Low and the E2 pin is High.
Either the Chip Enable input (E1) or the Write En-
able input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of E1 being ac-
tive with W low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
The Write cycle can be terminated by the earlier
rising edge of E1, or W.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within t
of its falling edge. Care must
WLQZ
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for t
the rising edge of Write Enable, or for t
before
before
DVWH
DVEH
t
and t
, respectively, and is determined
AVWL
AVEH
the rising edge of E1, whichever occurs first, and
remain valid for t or t
by the latter occurring edge.
.
EHDX
WHDX
Figure 11. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVWH
tAVEL
tELWH
tWHAX
E1
E2
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DATA INPUT
tDVWH
DQ0-DQ7
AI05478
11/20
M68AW127B
Figure 12. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVEH
tELEH
tAVEL
tEHAX
E1
E2
tAVWL
tWLEH
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI05479
12/20
M68AW127B
Table 8. Write Mode AC Characteristics
M68AW127B
Symbol
Parameter
Unit
70
70
60
0
100
100
80
0
t
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
Input Valid to Chip Enable High
AVEH
t
AVEL
t
60
0
80
0
AVWH
t
AVWL
t
30
30
0
40
40
0
DVEH
t
Input Valid to Write Enable High
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to Chip Enable High
Chip Enable Low to Write Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Output Transition
Write Enable Low to Chip Enable High
Write Enable Low to Output Hi-Z
DVWH
t
EHAX
t
0
0
EHDX
t
60
60
0
80
80
0
ELEH
t
ELWH
t
WHAX
t
0
0
WHDX
(1)
5
5
t
WHQX
t
60
20
60
70
30
70
WLEH
(1,2)
t
WLQZ
t
Write Enable Low to Write Enable High
Min
ns
WLWH
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WLQZ
WHQX
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
13/20
M68AW127B
Figure 13. E1 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
3.6V
V
2.7V
CC
V
> 1.5V (1)
DR
tCDR
tR
E1 ≥ V
– 0.2V
DR
E1
AI05980
Note: 1. For 100ns speed class V ≥ 2.0V.
DR
Figure 14. E2 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
3.6V
V
2.7V
CC
V
> 1.5V (1)
DR
tCDR
tR
E2
E2 ≤ 0.2V
AI05957B
Note: 1. For 100ns speed class V ≥ 2.0V.
DR
Table 9. Low V Data Retention Characteristics
CC
Parameter
Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
µA
70
4.5
5
V
= 1.5V, E1 ≥ V –0.2V or
CC
CC
(1)
I
CCDR
(Data Retention)
E2 ≤ 0.2V, f = 0
100
µA
Chip Deselected to Data
Retention Time
(1,2)
0
ns
t
CDR
t
70
100
70
ns
ms
V
AVAV
5
(2)
Operation Recovery Time
t
R
1.5
2.0
E1 ≥ V –0.2V or
E2 ≤ 0.2V, f = 0
Supply Voltage
(Data Retention)
CC
(1)
V
DR
100
V
Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.
IH
CC
IL
2. Tested initially and after any design or process that may affect these parameters. t
is Read cycle time.
AVAV
3. No input may exceed V +0.2V.
CC
14/20
M68AW127B
PACKAGE MECHANICAL
Figure 15. SO32 - 32 lead Plastic Small Outline, Package Outline
D
16
1
E
E1
17
32
A2
A
C
L
CP
A1
B
e
L1
SO-C
Note: Drawing is not to scale.
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data
millimeters
Symbol
inches
Min
Typ
Min
Max
Typ
Max
A
A1
A2
b
2.997
0.118
0.102
2.565
0.356
0.152
20.142
11.176
13.868
–
0.004
0.101
0.014
0.006
0.793
0.440
0.546
–
2.819
0.508
0.305
20.752
11.430
14.376
–
0.111
0.020
0.012
0.817
0.450
0.566
–
c
D
E
E1
e
1.270
0.050
L
0.584
1.194
0.991
1.600
0.10
0.023
0.047
0.039
0.063
0.004
L1
CP
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M68AW127B
Figure 16. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
Table 11. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.250
0.210
0.100
20.200
18.500
8.100
–
Typ
Max
0.0472
0.0059
0.0413
0.0098
0.0083
0.0039
0.7953
0.7283
0.3189
–
A
A1
A2
B
0.050
0.950
0.170
0.100
0.0020
0.0374
0.0067
0.0039
C
CP
D
19.800
18.300
7.900
–
0.7795
0.7205
0.3110
–
D1
E
e
0.500
0.0197
L
0.500
0°
0.700
5°
0.0197
0°
0.0276
5°
α
N
32
32
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M68AW127B
Figure 17. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
Table 12. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
Typ
Max
A
A1
A2
B
0.0472
0.0059
0.0413
0.05
0.91
0.0020
0.0358
0.22
0.0087
C
0.10
0.21
0.0039
0.0083
D
13.40
11.80
8.00
–
–
–
–
0.5276
0.4646
0.3150
0.0197
–
–
D1
E
–
–
–
–
–
–
e
0.50
–
–
–
0.0157
0
–
0.0236
5
L
0.40
0
0.60
5
α
N
32
32
CP
0.10
0.0039
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M68AW127B
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M68AW127
B
L
70
N
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
W = 2.7 to 3.6V
Array Organization
127 = 1Mbit (128K x8)
Option 1
B = 2 Chip Enable
Option 2
L = L-Die
M = M-Die
Speed Class
70 = 70ns
10 = 100ns
Package
MC = SO32
N = TSOP32 (8 x 20 mm)
NK = TSOP32 (8 x 13.4 mm)
Operative Temperature
1 = 0 to 70°C
6 = –40 to 85 °C
Shipping
T = Tape & Reel Packing
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
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M68AW127B
REVISION HISTORY
Table 14. Document Revision History
Date
Version
Revision Details
January 2002
1.0
First Issue
DC Characteristics table clarified (Table 5)
E1 Controlled, Low V Data Retention AC Waveforms clarified (Figure 13)
CC
09-May-2002
2.0
Low V Data Retention Characteristics table clarified (Table 9)
CC
Ordering Information Scheme clarified (Table 13)
70ns speed class added
SO32 and TSOP32 8x13.4mm package options added
01-Jul-2002
3.0
11-Sep-2002
02-Oct-2002
09-Oct-2002
16-Apr-2003
21-Aug-2003
4.0
4.1
4.2
4.3
4.4
Commercial code clarified
Title and header layout modified.
Commercial code modified.
Label corrected on “E2 Controlled, Low V Data Retention AC Waveforms” figure
CC
TSOP Package connections modified (Figure 5)
19/20
M68AW127B
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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