M68AW256D55ZB6T [STMICROELECTRONICS]
256KX16 STANDARD SRAM, 55ns, PBGA48, 0.75 MM PITCH, TFBGA-48;
| 型号： | M68AW256D55ZB6T |
| 厂家： | 
ST |
| 描述： | 256KX16 STANDARD SRAM, 55ns, PBGA48, 0.75 MM PITCH, TFBGA-48 静态存储器 |
| 文件： | 总19页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M68AW256D
M68AW256DL
4 Mbit (256K x16) 3.0V Asynchronous SRAM
PRELIMINARY DATA
FEATURES SUMMARY
■ SUPPLY VOLTAGE: 2.7 to 3.6V
Figure 1. Packages
■ 256K x 16 bits SRAM with OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIME: 55ns
■ LOW STANDBY CURRENT
44
■ LOW V DATA RETENTION: 1.0V
CC
1
■ TRI-STATE COMMON I/O
■ AUTOMATIC POWER DOWN
TSOP44 Type II (ND)
■ DUAL CHIP ENABLE for EASY DEPTH
EXPANSION
BGA
TFBGA48 (ZB)
6 x 8 ball array
October 2001
1/19
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M68AW256D, M68AW256DL
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . 10
Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . 10
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Low V Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . . . . . . 16
TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data. . . . . . . 16
TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Bottom View Package Outline . . . . . . . . . . . . . . . . . . 17
TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . 17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
M68AW256D, M68AW256DL
SUMMARY DESCRIPTION
The M68AW256D is a 4 Mbit (4,194,304 bit)
CMOS SRAM, organized as 262,144 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
The M68AW256 is available in TFBGA48 (0.75 mm
pitch) and in TSOP44 Type II packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A17
Address Inputs
V
CC
DQ0-DQ15
Data Input/Output
Chip Enables
E1, E2
G
18
16
Output Enable
A0-A17
W
DQ0-DQ15
W
Write Enable
UB
LB
Upper Byte Enable Input
Lower Byte Enable Input
Supply Voltage
E1
M68AW256D
E2
V
CC
G
V
Ground
SS
UB
LB
NC
DU
Not Connected Internally
Don’t Use as Internally Connected
V
SS
AI05492
3/19
M68AW256D, M68AW256DL
Figure 3. TSOP Connections
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
A2
3
A7
A1
4
G
A0
5
UB
E1
6
LB
DQ0
DQ1
DQ2
DQ3
7
DQ15
DQ14
DQ13
DQ12
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
V
CC
SS
M68AW256D
V
V
SS
CC
DQ4
DQ5
DQ6
DQ7
W
DQ11
DQ10
DQ9
DQ8
E2
A16
A15
A14
A13
A12
A8
A9
A10
A11
A17
AI05493
4/19
M68AW256D, M68AW256DL
Figure 4. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A2
E1
E2
A
B
C
D
E
F
LB
G
A0
A3
A1
A4
A6
A7
DQ8
DQ9
DQ0
DQ2
UB
DQ10
DQ11
DQ12
DQ13
NC
A5
DQ1
DQ3
DQ4
DQ5
W
V
A17
NC
A14
A12
A9
V
SS
CC
V
A16
A15
A13
A10
V
CC
SS
DQ6
DQ7
DU
DQ14
DQ15
NC
G
H
A8
A11
AI05494
5/19
M68AW256D, M68AW256DL
Figure 5. Block Diagram
A17
A8
ROW
DECODER
MEMORY
ARRAY
DQ15
UB
(8)
(8)
I/O CIRCUITS
INPUT
DATA
CTRL
COLUMN
DECODER
DQ0
LB
E1
E2
Ex
UB
LB
A0
A7
(8)
(8)
UB
LB
W
G
AI05495
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
(1)
Output Current
20
mA
I
O
T
Ambient Operating Temperature
Storage Temperature
Supply Voltage
–55 to 125
–65 to 150
–0.5 to 4.6
°C
°C
V
A
T
STG
V
CC
(2)
–0.5 to V +0.5
Input or Output Voltage
Power Dissipation
V
V
CC
IO
P
1
W
D
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating V of 3.6V only.
CC
6/19
M68AW256D, M68AW256DL
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M68AW256D
2.7 to 3.6V
–40 to 85°C
30 or 5pF
1.10kΩ
V
Supply Voltage
CC
Ambient Operating Temperature
Load Capacitance (C )
L
Output Circuit Protection Resistance (R )
1
Load Resistance (R )
1.55kΩ
2
Input Rise and Fall Times
≤ 4ns
0 to V
Input Pulse Voltages
CC
V
/2
Input and Output Timing Ref. Voltages
Input and Output Transition Timing Ref. Voltages
CC
V
= 0.3V ; V
= 0.7V
OL
CC OH CC
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
V
CC
1N914
I/O Timing Reference Voltage
V
CC
R
1
V
/2
CC
0V
DEVICE
UNDER
TEST
OUT
C
L
I/O Transition Timing Reference Voltage
R
2
V
CC
0.7V
0.3V
CC
CC
0V
AI04831
C
includes JIG capacitance
L
AI03853
7/19
M68AW256D, M68AW256DL
Table 4. Capacitance
Test
Condition
(1,2)
Symbol
Min
Max
Unit
Parameter
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
6
8
pF
pF
IN
IN
(3)
V
C
OUT
OUT
Note: 1. Sampled only, not 100% tested.
2. At T = 25°C, f = 1 MHz, V = 3.0V.
A
CC
3. Outputs deselected.
Table 5. DC Characteristics
Symbol
Parameter
Test Condition
= 3.6V, f = 1/t
Min
Typ
Max
Unit
V
,
AVAV
CC
(1)
Operating Supply Current
7
15
mA
I
CC1
I
= 0mA
OUT
V
= 3.6V, f = 1MHz,
CC
I
Operating Supply Current
1
20
2
2
mA
µA
µA
CC2
I
= 0mA
OUT
Standby Supply Current CMOS
(M68AW256D)
V
= 3.6V,
CC
(2)
I
SB
E ≥ V –0.15V, f = 0
CC
Standby Supply Current CMOS
(M68AW256DL)
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Input High Voltage
–1
–1
1
1
µA
µA
V
LI
IN
CC
(3)
I
LO
0V ≤ V
≤ V
OUT
CC
V
V
= 2.7V
= 2.7V
V
+ 0.5
CC
2.2
–0.5
2.4
IH
CC
V
V
CC
Input Low Voltage
0.8
V
IL
V
V
= 2.7V, I
= –100µA
OH
Output High Voltage
Output Low Voltage
V
OH
CC
V
V
= 2.7V, I = 2.1mA
CC OL
0.4
V
OL
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. All other Inputs at V ≤ 0.15V or V ≥ V –0.15V.
IL
IH
CC
3. Output disabled.
8/19
M68AW256D, M68AW256DL
OPERATION
The M68AW256D has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High)
or Chip Select is asserted (E2 = Low), or UB/LB
are de-asserted (UB/LB = High). An Output En-
able (G) signal provides a high speed tri-state con-
trol, allowing fast read/write cycles to be achieved
with the common I/O data bus. Operational modes
are determined by device control inputs W, E1, LB
and UB as summarized in the Operating Modes ta-
ble (see Table 6).
Table 6. Operating Modes
Operation
Deselected/Power-down
Deselected/Power-down
Deselected/Power-down
Lower Byte Read
Lower Byte Write
Output Disabled
E1
E2
W
X
G
X
X
X
LB
X
UB
X
DQ0-DQ7
Hi-Z
DQ8-DQ15
Hi-Z
Power
V
Standby (I
)
)
X
IH
SB
V
Standby (I
Standby (I
X
X
X
X
X
Hi-Z
Hi-Z
IL
SB
V
V
)
SB
X
X
Hi-Z
Hi-Z
IH
IH
V
V
V
V
V
V
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
)
)
)
Data Output
Data Input
Hi-Z
Hi-Z
IL
IH
IH
IL
IL
IH
CC
CC
CC
CC
CC
CC
CC
CC
V
V
V
V
V
X
Hi-Z
IL
IH
IL
IL
IH
V
V
V
V
X
X
Hi-Z
IL
IH
IH
IH
IL
V
V
V
V
Output Disabled
X
X
Hi-Z
Hi-Z
IL
IH
IL
V
V
V
V
V
V
Upper Byte Read
Upper Byte Write
Word Read
Hi-Z
Data Output
Data Input
IL
IH
IH
IL
IH
IL
V
V
V
V
V
V
V
V
X
V
V
V
V
Hi-Z
IL
IL
IL
IH
IH
IH
IL
IH
IL
IL
IL
V
V
V
Data Output Data Output
Data Input Data Input
IH
IL
IL
IL
Word Write
V
X
IL
Note: X = V or V .
IH
IL
Read Mode
The M68AW256D, when Chip Select (E2) is High,
is in the read mode whenever Write Enable (W) is
High with Output Enable (G) Low, and Chip En-
able (E1) is asserted. This provides access to data
from eight or sixteen, depending on the status of
the signal UB and LB, of the 4,194,304 locations in
the static memory array, specified by the 18 ad-
dress inputs. Valid data will be available at the
eight or sixteen output pins within t
after the
AVQV
last stable address, providing G is Low and E1 is
Low. If Chip Enable or Output Enable access
times are not met, data access will be measured
from the limiting parameter (t
, t
or t
)
ELQV GLQV
BLQV
rather than the address. Data out may be indeter-
minate at t
, t
and t
AVQV
, but data lines
BLQX
ELQX GLQX
will always be valid at t
.
Figure 8. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A17
VALID
tAVQV
tAXQX
DQ0-DQ15
DATA VALID
AI03956
Note: Ex = Low, G = Low, W = High, UB = Low and/or LB = Low.
9/19
M68AW256D, M68AW256DL
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV
A0-A17
VALID
tAVQV
tELQV
tAXQX
tEHQZ
Ex
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ15
VALID
tBLQV
tBHQZ
UB, LB
tBLQX
AI05496
Note: Write Enable (W) = High.
Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
Ex, UB, LB
tPU
tPD
I
CC
50%
I
SB
AI05497
10/19
M68AW256D, M68AW256DL
Table 7. Read and Standby Mode AC Characteristics
M68AW256D
Unit
Symbol
Parameter
55
55
55
10
70
70
70
10
t
Read Cycle Time
Min
Max
Min
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
AVQV
t
Data hold from address change
AXQX
(1, 2)
Upper/Lower Byte Enable High to Output Hi-Z
Upper/Lower Byte Enable Low to Output Valid
Upper/Lower Byte Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Max
Max
Min
20
55
5
20
70
10
25
t
t
t
BHQZ
t
BLQV
t
BLQX
(1, 2)
Max
20
EHQZ
t
Chip Enable Low to Output Valid
Max
Min
55
10
70
10
ns
ns
ELQV
t
Chip Enable Low to Output Transition
ELQX
(1, 2)
Output Enable High to Output Hi-Z
Max
20
25
ns
GHQZ
t
t
Output Enable Low to Output Valid
Max
Min
20
5
35
5
ns
ns
GLQV
Output Enable Low to Output Transition
Chip Enable or UB/LB High to Power Down
Chip Enable or UB/LB Low to Power Up
GLQX
t
Max
55
70
ns
PD
t
Min
0
0
ns
PU
Note: 1. At any given temperature and voltage condition, t
any given device.
is less than t
, t
is less than t
and t
is less than t
for
GHQZ
GLQX BHQZ
BLQX
EHQZ
ELQX
2. C = 5pF.
L
11/19
M68AW256D, M68AW256DL
Write Mode
The M68AW256D, when Chip Select (E2) is High,
is in the Write Mode whenever the W and E1 are
Low. Either the Chip Enable Input (E1) or the Write
Enable input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
When E1 or W is Low, and UB or LB is Low, write
cycle begins on the W or E1 falling edge. When E1
and W are Low, and UB = LB = High, write cycle
begins on the first falling edge of UB or LB. There-
fore, address setup time is referenced to Write En-
The Write cycle can be terminated by the earlier
rising edge of E1, W, UB and LB.
If the Output is enabled (E1 = Low, E2 = High, G =
Low, LB or UB = Low), then W will return the
outputs to high impedance within t
of its
WLQZ
falling edge. Care must be taken to avoid bus
contention in this type of operation. Data input
must be valid for t
Write Enable, or for t
before the rising edge of
DVWH
beforethe rising edge of
DVEH
E1 or for t
before the rising edge of UB/LB,
DVBH
able, Chip Enables and UB/LB as t
, t
and
AVWL AVEL
whichever occurs first, and remain valid for t
,
WHDX
t
respectively, and is determined by the latter
AVBL
t
and t
respectively.
EHDX
BHDX
occurring falling edge.
Figure 11. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVWH
tAVEL
tAVWL
tWHAX
Ex
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ15
UB, LB
DATA INPUT
tDVWH
tBLWH
AI05498
12/19
M68AW256D, M68AW256DL
Figure 12. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVEH
tELEH
tAVEL
tEHAX
Ex
tAVWL
W
tEHDX
DQ0-DQ15
DATA INPUT
tDVEH
tBLEH
UB, LB
AI05425
Figure 13. UB/LB Controlled, Write AC Waveforms
tAVAV
A0-A17
Ex
VALID
tAVBH
tBHAX
tAVWL
W
tWLQZ
tBHDX
DATA INPUT
tDVBH
DATA (1)
DQ0-DQ15
tAVBL
tBLBH
UB, LB
AI05426
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
13/19
M68AW256D, M68AW256DL
Table 8. Write Mode AC Characteristics
M68AW256D
Symbol
Parameter
Unit
55
70
70
60
0
t
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
55
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to LB, UB High
AVBH
t
Addess Valid to LB, UB Low
AVBL
t
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
LB, UB High to Address Transition
LB, UB High to Input Transition
LB, UB Low to LB, UB High
40
0
60
0
AVEH
t
AVEL
t
40
0
60
0
AVWH
t
AVWL
BHAX
BHDX
t
0
0
t
0
0
t
40
40
40
20
20
20
0
60
60
60
25
25
25
0
BLBH
BLEH
BLWH
DVBH
DVEH
t
LB, UB Low to Chip Enable High
LB, UB Low to Write Enable High
Input Valid to LB, UB High
t
t
t
Input Valid to Chip Enable High
Input Valid to Write Enable High
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
t
DVWH
t
EHAX
EHDX
t
0
0
t
40
0
60
0
ELEH
t
t
WHAX
0
0
WHDX
(1)
Write Enable High to Output Transition
Write Enable Low to Output Hi-Z
Min
5
5
ns
ns
ns
t
WHQX
(1,2)
Max
20
40
20
50
t
WLQZ
t
Write Enable Low to Write Enable High
Min
WLWH
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WLQZ
WHQX
2. C = 5pF.
L
14/19
M68AW256D, M68AW256DL
Figure 14. E1 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
3.6V
V
3.3V
CC
V
> 1.0V
DR
tCDR
tR
E1 ≥ V
– 0.2V
DR
E1
AI05456
Figure 15. E2 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
3.6V
V
3.3V
CC
V
> 1.0V
DR
tCDR
tR
E2
E2 ≤ 0.2V
AI05457
Table 9. Low V Data Retention Characteristics
CC
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
Supply Current (Data Retention)
(M68AW256D)
(3)
(3)
10
20
µA
V
V
= 1.0V, E ≥ V –0.3V, f = 0
CC
CC
CC
(1)
I
CCDR
Supply Current (Data Retention)
(M68AW256DL)
0.1
1
µA
= 1.0V, E ≥ V –0.3V, f = 0
CC
Chip Deselected to Data
Retention Time
(1,2)
E ≥ V –0.3V, f = 0
0
ns
t
CC
CDR
(2)
Operation Recovery Time
t
ns
V
t
AVAV
R
(1)
E ≥ V –0.3V, f = 0
Supply Voltage (Data Retention)
1.0
3.6
V
CC
DR
Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.
IH
CC
IL
2. See Figure 14 for measurement points. Guaranteed but not tested. t
is Read cycle time.
AVAV
3. No input may exceed V +0.3V.
CC
15/19
M68AW256D, M68AW256DL
PACKAGE MECHANICAL
Figure 16. TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline
D
N
E1
E
1
N/2
ZD
b
e
A2
A
C
α
A1
CP
L
TSOP-d
Note: Drawing is not to scale.
Table 10. TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
Typ
Max
A
A1
A2
b
0.0472
0.0059
0.0413
0.050
0.950
0.0020
0.0374
0.350
0.0138
c
0.120
0.210
0.0047
0.0083
D
18.410
11.760
10.160
0.800
–
–
0.7248
0.4630
0.4000
0.0315
0.0197
0.0317
–
–
E
–
–
–
–
E1
e
–
–
–
–
–
–
0.400
–
–
–
0.0236
–
L
0.500
0.600
–
0.0157
ZD
alfa
CP
N
0.805
–
0
0
5
5
0.100
0.0039
44
44
16/19
M68AW256D, M68AW256DL
Figure 17. TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL ”A1”
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z22
Note: Drawing is not to scale.
Table 11. TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
Min
inches
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.010
1.200
0.0398
0.0102
0.0472
0.260
0.950
0.0374
0.400
7.000
3.750
0.300
6.900
–
0.500
0.0157
0.2756
0.1476
0.0118
0.2717
–
0.0197
D
7.100
0.2795
D1
ddd
E
–
–
0.100
0.0039
8.000
5.250
0.750
1.625
1.375
0.375
0.375
7.900
8.100
0.3150
0.2067
0.0295
0.0640
0.0541
0.0148
0.0148
0.3110
0.3189
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
17/19
M68AW256D, M68AW256DL
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M68AW256
D
L
55 ZB
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
W = 2.7 to 3.6V
Array Organization
256 = 4 Mbit (256K x16)
Option 1
D = 2 Chip Enable; Write and Standby from UB and LB
Option 2
L = Low Leakage
Speed Class
55 = 55 ns
70 = 70 ns
Package
ND = TSOP 44 Type II
ZB = TFBGA48: 0.75 mm pitch
Operative Temperature
6 = –40 to 85 °C
Shipping
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
REVISION HISTORY
Table 13. Document Revision History
Date
Version
Revision Details
October 2001
-01
First Issue
18/19
M68AW256D, M68AW256DL
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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19/19
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