M68AW256DN55ZB1T [STMICROELECTRONICS]
256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TFBGA-48;
| 型号： | M68AW256DN55ZB1T |
| 厂家： | 
ST |
| 描述： | 256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TFBGA-48 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M68AW256D
4 Mbit (256K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY
■ SUPPLY VOLTAGE: 2.7 to 3.6V
Figure 1. Packages
■ 256K x 16 bits SRAM with OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIME: 55ns,
70ns
44
■ SINGLE BYTE READ/WRITE
■ LOW STANDBY CURRENT
■ LOW V
DATA RETENTION: 1.5V
CC
■ TRI-STATE COMMON I/O
1
■ AUTOMATIC POWER DOWN
TSOP44 Type IND)
■ DUAL CHIP ENABLE for EASY DENSITY
EXPANSION
FBGA
TFBGA48 (ZB)
6 x 7 mm
February 2004
1/23
M68AW256D
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . . 13
Figure 10.Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . 13
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13.UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15.E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Low V Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16.TSOP44 II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . . 19
Table 10. TSOP 44 II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . 19
Figure 17.TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . 20
Table 11. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 20
2/23
M68AW256D
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M68AW256D
SUMMARY DESCRIPTION
The M68AW256D is a 4 Mbit (4,194,304 bit)
CMOS SRAM, organized as 262,144 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
The M68AW256D is available in TFBGA48
(0.75 mm pitch) and in TSOP44 Type II packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A17
Address Inputs
V
CC
DQ0-DQ15
Data Input/Output
Chip Enables
E1, E2
G
18
16
Output Enable
A0-A17
W
DQ0-DQ15
W
Write Enable
UB
LB
Upper Byte Enable Input
Lower Byte Enable Input
Supply Voltage
E1
M68AW256D
E2
V
CC
G
V
SS
Ground
UB
LB
NC
DU
Not Connected Internally
Don’t Use as Internally Connected
V
SS
AI05492B
4/23
M68AW256D
Figure 3. TSOP Connections
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
A2
3
A7
A1
4
G
A0
5
UB
E1
6
LB
DQ0
DQ1
DQ2
DQ3
7
DQ15
DQ14
DQ13
DQ12
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
V
V
CC
SS
CC
M68AW256D
V
SS
DQ4
DQ5
DQ6
DQ7
W
DQ11
DQ10
DQ9
DQ8
E2
A16
A15
A14
A13
A12
A8
A9
A10
A11
A17
AI05493B
5/23
M68AW256D
Figure 4. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A2
E1
E2
A
B
C
D
E
F
LB
G
A0
A3
A1
A4
A6
DQ8
DQ9
DQ0
DQ2
UB
DQ10
DQ11
DQ12
DQ13
NC
A5
DQ1
DQ3
DQ4
DQ5
W
A7
V
A17
NC
A14
A12
A9
V
SS
CC
V
A16
A15
A13
A10
V
CC
SS
DQ14
DQ15
NC
DQ6
DQ7
DU
G
H
A8
A11
AI05494
6/23
M68AW256D
Figure 5. Block Diagram
A17
A7
ROW
DECODER
MEMORY
ARRAY
DQ15
UB
(8)
(8)
I/O CIRCUITS
COLUMN
DECODER
DQ0
LB
E1
E2
Ex
UB
LB
A0
A6
(8)
(8)
UB
LB
W
G
AI05495
7/23
M68AW256D
OPERATION
The device has four standard operating modes:
Write Mode
Output Disabled, Read, Write and Standby/Pow-
er-Down. These modes are determined by the
control inputs E1, E2, W, G, LB and UB as sum-
marized in Table 2.Operating Modes.
The M68AW256D, when Chip Select (E2) is High,
is in the Write Mode whenever the W and E1 are
Low. Either the Chip Enable Input (E1) or the Write
Enable input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
When E1 or W is Low, and UB or LB is Low, write
cycle begins on the W or E1 falling edge. When E1
and W are Low, and UB = LB = High, write cycle
begins on the first falling edge of UB or LB. There-
fore, address setup time is referenced to Write En-
Output Disabled
The Output Enable signal, G, provides high-speed
tri-state control of DQ0-DQ15, allowing fast read/
write cycles on the I/O data bus. The device is in
Output Disabled mode when Output Enable, G, is
High. In this mode, LB and UB are Don’t care and
DQ0-DQ15 are high impedance.
able, Chip Enables and UB/LB as t
, t
and
AVWL AVEL
t
respectively, and is determined by the latter
AVBL
Read Mode
occurring falling edge.
The M68AW256D is in Read mode whenever the
The Write cycle can be terminated by the earlier
rising edge of E1, W, UB and LB.
If the Output is enabled (E1 = Low, E2 = High, G =
Low, LB or UB = Low), then W will return the
device is selected (Chip Enable E1 at V and Chip
IL
Enable E2 at V ), Write Enable, W, is at V , Out-
IH
IH
put Enable, G, is at V and at least one of the Byte
IL
Enable inputs, UB and LB, is at V .
IL
outputs to high impedance within t
of its
WLQZ
If only one of the Byte Enable inputs is at V , the
IL
falling edge. Care must be taken to avoid bus
contention in this type of operation. Data input
M68AW256D is in Byte Read mode. If the two
Byte Enable inputs are at V , the M68AW256D is
IL
must be valid for t
Write Enable, or for t
before the rising edge of
DVWH
in Word Read mode. So depending on the status
of the UB and LB signals, valid data will be avail-
able on the lower eight, the upper eight or all six-
before the rising edge of
DVEH
E1 or for t
before the rising edge of UB/LB,
DVBH
whichever occurs first, and remain valid for t
,
WHDX
teen output pins, t
after the last stable
AVQV
t
and t
respectively.
EHDX
BHDX
address.
See Figures 11, 12, 13 and Table 8 for details on
Write mode AC timings and Characteristics.
Standby/Power-Down
If either of E1, E2, G and UB/LB is asserted after
has elapsed, data access will be measured
t
AVQV
from the limiting parameter, t
, t
or t
ELQV GLQV BLQV,
The M68AW256D has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High)
or Chip Select is asserted (E2 = Low), or UB/LB
are de-asserted (UB/LB = High). An Output En-
able (G) signal provides a high speed tri-state con-
trol, allowing fast read/write cycles to be achieved
with the common I/O data bus. Operational modes
are determined by device control inputs W, E1, LB
and UB as summarized in the Operating Modes ta-
ble (see Table 2).
rather than the address.
Data out may be indeterminate at t
, t
and
.
AVQV
ELQX GLQX
t , but data lines will always be valid at t
BLQX
See Figures 8, 9, 10 and Table 7 for details on
Read mode AC timings and Characteristics.
8/23
M68AW256D
Table 2. Operating Modes
Operation
E1
E2
W
X
G
X
X
X
LB
X
UB
X
DQ0-DQ7
Hi-Z
DQ8-DQ15
Hi-Z
Power
V
IH
Standby (I
Standby (I
Standby (I
Active (I
)
)
)
X
SB
Deselected
(Standby/Power-Down)
V
IL
X
X
X
X
X
Hi-Z
Hi-Z
SB
V
IH
V
IH
X
X
Hi-Z
Hi-Z
SB
V
V
IH
V
IH
V
IL
V
IL
V
IH
)
Lower Byte Read
Lower Byte Write
Output Disabled
Upper Byte Read
Upper Byte Write
Word Read
Data Output
Data Input
Hi-Z
Hi-Z
IL
CC
V
V
IH
V
V
V
IL
V
IH
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
)
X
Hi-Z
IL
IL
CC
V
V
IH
V
IH
)
)
)
)
)
)
X
X
Hi-Z
IL
IH
IH
CC
CC
CC
CC
CC
CC
V
V
IH
V
V
V
IH
V
IL
Hi-Z
Data Output
Data Input
IL
IL
IL
IH
V
V
IH
V
V
V
IH
V
IL
X
Hi-Z
IL
IL
V
V
IH
V
V
IL
V
IL
Data Output Data Output
IL
IH
V
V
IH
V
IL
V
IL
V
IL
Word Write
X
Data Input
Hi-Z
Data Input
Hi-Z
IL
V
V
IH
V
Output Disabled
X
X
X
IL
Note: 1. X = V or V .
IH
IL
9/23
M68AW256D
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
(1)
Output Current
20
mA
I
O
T
Ambient Operating Temperature
Storage Temperature
–55 to 125
–65 to 150
°C
°C
°C
V
A
T
STG
(2)
(3)
T
LEAD
Lead Temperature during Soldering
Supply Voltage
260
V
–0.5 to 4.6
CC
(4)
–0.5 to V +0.5
Input or Output Voltage
Power Dissipation
V
V
CC
IO
P
D
1
W
Note: 1. One output at a time, not to exceed 1 second duration.
®
2. Compliant with the ECOPACK 7191395 specification for Lead-free soldering processes.
3. Not exceeding 250°C for more than 30s, and peaking at 260°C.
4.Up to a maximum operating V of 3.6V only.
CC
10/23
M68AW256D
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter
M68AW256D
V
CC
Supply Voltage
2.7 to 3.6V
Range 1
Range 6
0 to 70°C
–40 to 85°C
30pF
Ambient Operating Temperature
Load Capacitance (C )
L
Output Circuit Protection Resistance (R )
3.0kΩ
1
Load Resistance (R )
3.1kΩ
2
Input Rise and Fall Times
1ns/V
0 to V
Input Pulse Voltages
CC
V
/2
Input and Output Timing Ref. Voltages
Output Transition Timing Ref. Voltages
CC
V
RL
= 0.3V ; V = 0.7V
CC RH CC
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
V
CC
I/O Timing Reference Voltage
R
1
V
CC
V
/2
CC
DEVICE
UNDER
TEST
OUT
0V
C
L
I/O Transition Timing Reference Voltage
R
2
V
CC
0.7V
0.3V
CC
CC
0V
AI04831
C
includes probe and 1 TTLcapacitance
L
AI05832
11/23
M68AW256D
Table 5. Capacitance
Symbol
Test
Condition
(1,2)
Min
Max
Unit
Parameter
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
6
8
pF
pF
IN
(3)
IN
V
C
OUT
OUT
Note: 1. Sampled only, not 100% tested.
2. At T = 25°C, f = 1 MHz, V = 3.0V.
A
CC
3.Outputs deselected.
Table 6. DC Characteristics
M68AW256D
Symbol
Parameter
Test Condition
-L
-N
Unit
Min
Max
Min
Max
V
f = 1/t
= 3.6V,
70ns
55ns
20
26
10
mA
mA
CC
(1)
,
Operating Supply Current
Operating Supply Current
I
AVAV
CC1
15
I
= 0mA
OUT
V
CC
= 3.6V,
I
f = 1MHz,
2
2
mA
µA
CC2
I
= 0mA
OUT
V
= 3.6V, f = 0,
CC
E1 ≥ V –0.2V or E2 ≤ 0.2V
Standby Supply Current
CMOS
CC
(2)
20
20
I
I
SB
or
LB=UB ≥V –0.2V
CC
I
LI
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
–1
–1
1
1
–1
–1
1
1
µA
µA
IN
CC
(3)
0V ≤ V
≤ V
CC
OUT
LO
V
V
CC
+ 0.5
V
CC
+ 0.5
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
2.2
–0.5
2.4
2.2
–0.5
2.4
V
V
V
V
IH
V
0.8
0.8
IL
V
OH
I
= –1.0mA
= 2.1mA
OH
V
I
OL
0.4
0.4
OL
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. All other Inputs at V ≤0.2V or V ≥V –0.2V.
IL
IH
CC
3.Output disabled.
Figure 8. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A17
VALID
tAVQV
tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI03956b
Note: E1 = Low, G = Low, W = High, UB = Low and/or LB = Low, E2 = High.
12/23
M68AW256D
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV
A0-A17
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E1
E2
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ15
VALID
tBLQV
tBHQZ
UB, LB
tBLQX
AI05496c
Note: Write Enable (W) = High.
Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
E1, UB, LB
E2
tPU
tPD
I
CC
50%
I
SB
AI05497
13/23
M68AW256D
Table 7. Read and Standby Mode AC Characteristics
M68AW256D
Symbol
Parameter
Unit
55
70
70
70
t
Read Cycle Time
Min
Max
Min
55
55
5
ns
ns
ns
AVAV
t
Address Valid to Output Valid
AVQV
(1)
Data hold from address change
5
25
70
5
t
AXQX
(2,3)
Upper/Lower Byte Enable High to Output Hi-Z
Upper/Lower Byte Enable Low to Output Valid
Upper/Lower Byte Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Max
Max
Min
20
55
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
BHQZ
t
BLQV
(1)
t
BLQX
(2,3)
Max
Max
Min
20
55
5
25
70
5
EHQZ
t
Chip Enable Low to Output Valid
ELQV
(1)
Chip Enable Low to Output Transition
Output Enable High to Output Hi-Z
t
ELQX
(2,3)
Max
Max
Min
20
25
5
25
35
5
GHQZ
t
Output Enable Low to Output Valid
GLQV
(2)
Output Enable Low to Output Transition
Chip Enable or UB/LB High to Power Down
Chip Enable or UB/LB Low to Power Up
t
GLQX
(4)
Max
Min
55
0
70
0
t
t
PD
(4)
PU
Note: 1. Test conditions assume transition timing reference level = 0.3V or 0.7V
.
CC
CC
2. At any given temperature and voltage condition, t
any given device.
is less than t
, t
is less than t
and t
is less than t
for
GHQZ
GLQX BHQZ
BLQX
EHQZ
ELQX
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4.Tested initially and after any design or process changes that may affect these parameters.
14/23
M68AW256D
Figure 11. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVWH
tAVEL
tELWH
tWLWH
tWHAX
E1
E2
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ15
UB, LB
DATA INPUT
tDVWH
tBLBH
AI05498c
Figure 12. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVEH
tELEH
tAVEL
tEHAX
E1
E2
tAVWL
tWLEH
W
tEHDX
DQ0-DQ15
UB, LB
DATA INPUT
tDVEH
tBLBH
AI05425c
15/23
M68AW256D
Figure 13. UB/LB Controlled, Write AC Waveforms
tAVAV
VALID
tAVBH
A0-A17
tBHAX
E1
E2
tAVWL
tWLBH
W
tWLQZ
tBHDX
DQ0-DQ15
DATA (1)
DATA INPUT
tDVBH
tAVBL
tBLBH
UB, LB
AI05426c
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
16/23
M68AW256D
Table 8. Write Mode AC Characteristics
M68AW256D
Symbol
Parameter
Unit
55
55
45
0
70
70
60
0
t
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to LB, UB High
AVBH
t
Addess Valid to LB, UB Low
AVBL
t
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
LB, UB High to Address Transition
LB, UB High to Input Transition
LB, UB Low to LB, UB High
45
0
60
0
AVEH
t
AVEL
t
45
0
60
0
AVWH
t
AVWL
t
0
0
BHAX
t
0
0
BHDX
t
45
45
45
25
25
25
0
60
60
60
30
30
30
0
BLBH
t
LB, UB Low to Chip Enable High
LB, UB Low to Write Enable High
Input Valid to LB, UB High
BLEH
t
BLWH
t
DVBH
t
Input Valid to Chip Enable High
Input Valid to Write Enable High
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to LB, UB High
Chip Enable Low to Chip Enable High
Chip Enable Low to Write Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Output Transition
Write Enable Low to LB, UB High
Write Enable Low to Chip Enable High
Write Enable Low to Output Hi-Z
DVEH
t
DVWH
t
EHAX
t
0
0
EHDX
t
45
45
45
0
60
60
60
0
ELBH
t
ELEH
t
ELWH
t
WHAX
t
0
0
WHDX
(1)
5
5
t
WHQX
t
45
45
20
60
60
20
WLBH
t
WLEH
(1,2)
t
WLQZ
-L version
-N version
Min
Min
45
40
60
50
ns
ns
t
Write Enable Low to Write Enable High
WLWH
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WLQZ
WHQX
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
17/23
M68AW256D
Figure 14. E1 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
3.6V
V
3.3V
CC
V
> 1.5V
DR
tCDR
tR
E1 ≥ V
–0.2V or UB=LB > V –0.2V
DR
DR
E1, UB/LB
AI05456c
Figure 15. E2 Controlled, Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
3.6V
V
3.3V
CC
V
> 1.5V
DR
tCDR
tR
E2
E2 ≤ 0.2V
AI05457c
Table 9. Low V Data Retention Characteristics
CC
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
= 1.5V, E1 ≥ V –0.2V or
CC
CC
(1)
Supply Current (Data Retention)
E2 ≤ 0.2V or UB = LB ≥ V –0.2V,
10
20
µA
I
CC
CCDR
f = 0
Chip Deselected to Data
Retention Time
(1,2)
0
ns
ns
V
t
CDR
(2)
t
Operation Recovery Time
t
R
AVAV
E1 ≥ V –0.2V or E2 ≤ 0.2V or
CC
(1)
Supply Voltage (Data Retention)
1.5
3.6
V
DR
UB = LB ≥ V –0.2V, f = 0
CC
Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.
IH
CC
IL
2. Tested initially and after any design or process changes that may affect these parameters. t
is Read cycle time.
AVAV
3. No input may exceed V +0.2V.
CC
18/23
M68AW256D
PACKAGE MECHANICAL
Figure 16. TSOP44 II - 44 lead Plastic Thin Small Outline Type II, Package Outline
D
N
E1
E
1
N/2
ZD
b
e
A2
A
C
α
A1
CP
L
TSOP-d
Note: Drawing is not to scale.
Table 10. TSOP 44 II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
Typ
Max
A
A1
A2
b
0.0472
0.0059
0.0413
0.050
0.950
0.0020
0.0374
0.350
0.0138
c
0.120
0.210
0.0047
0.0083
D
18.410
11.760
10.160
0.800
–
–
0.7248
0.4630
0.4000
0.0315
0.0197
0.0317
–
–
E
–
–
–
–
E1
e
–
–
–
–
–
–
0.400
–
–
–
0.0236
–
L
0.500
0.600
–
0.0157
ZD
alfa
CP
N
0.805
–
0
0
5
5
0.100
0.0039
44
44
19/23
M68AW256D
Figure 17. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z43
Note: Drawing is not to scale.
Table 11. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.400
Typ
Max
A
A1
A2
b
0.0472
0.0157
0.250
0.0098
0.790
0.400
6.000
3.750
0.0311
0.0157
0.2362
0.1476
0.350
5.900
0.450
6.100
0.0138
0.2323
0.0177
0.2402
D
D1
ddd
E
0.100
7.100
0.0039
0.2795
7.000
5.250
0.750
1.125
0.875
0.375
0.375
6.900
–
0.2756
0.2067
0.0295
0.0443
0.0344
0.0148
0.0148
0.2717
–
E1
e
–
–
FD
FE
SD
SE
–
–
–
–
–
–
–
–
20/23
M68AW256D
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M68AW256
D
L
55 ZB
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
W = 2.7 to 3.6V
Array Organization
256 = 4 Mbit (256K x16)
Option 1
D = 2 Chip Enable; Write and Standby from UB and LB
Option 2
N = N die
L = L die
Speed Class
55 = 55 ns
70 = 70 ns
Package
ND = TSOP 44 Type II
ZB = TFBGA48: 0.75 mm pitch
Operative Temperature
6 = –40 to 85 °C
1 = 0 to 70 °C
Shipping
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
21/23
M68AW256D
REVISION HISTORY
Table 13. Document Revision History
Versio
Date
n
Revision Details
February 2002
14-Mar-2002
-01
-02
First Issue
Tables 4, 6, 7 and 9 clarified
Figures 3, 8, 9, 11, 12, 13 and 14 clarified
I
I
clarified (Table 9)
clarified (Table 6)
CCDR
07-Jun-2002
24-Apr-2003
-03
3.1
SB
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 03 equals 3.0).
Modifications to values of I
and I for the 55 and 70ns devices
CC1
SB
Document promoted to full datasheet
Option 2 updated in Part Numbering section.
25-Nov-2003
20-Feb-2004
3.2
4.0
TLEAD parameter added in Table 3, Absolute Maximum Ratings.
AC, DC Characteristics and waveforms grouped together.
TFBGA48 7x8 replaced by TFBGA48 6x7: Figure 17.TFBGA48 6x7mm - 6x8 ball array,
0.75 mm pitch, Bottom View Package Outline and Table 11.TFBGA48 6x7mm - 6x8 ball
array, 0.75 mm pitch, Package Mechanical Data updated.
I
and I updated in Table 6.DC Characteristics.
CC1
SB
t
updated in Table 8. Write Mode AC Characteristics.
WLWH
V
minimum value changed in Figures 14 and 15 and Table 9.Low V Data Retention
CC
DR
Characteristics.
22/23
M68AW256D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such
information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication
supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support
devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany -
Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore -
Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
23/23
相关型号：
M68AW256DN55ZB6T
256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TFBGA-48
STMICROELECTR
M68AW256DN70ZB1T
256KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TFBGA-48
STMICROELECTR
M68AW256DN70ZB6T
256KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TFBGA-48
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明