M68AW256ML55ZH6T [STMICROELECTRONICS]
4 Mbit (256K x16) 3.0V Asynchronous SRAM; 4兆位（ 256K ×16） 3.0V异步SRAM
| 型号： | M68AW256ML55ZH6T |
| 厂家： | 
ST |
| 描述： | 4 Mbit (256K x16) 3.0V Asynchronous SRAM |
| 文件： | 总23页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M68AW256M
4 Mbit (256K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY
■
■
■
SUPPLY VOLTAGE: 2.7 to 3.6V
256K x 16 bits SRAM with OUTPUT ENABLE
EQUAL CYCLE and ACCESS TIME: 55ns,
70ns
Figure 1. Packges
■
■
■
■
■
■
SINGLE BYTE READ/WRITE
LOW STANDBY CURRENT
LOW VCC DATA RETENTION: 1.5V
TRI-STATE COMMON I/O
AUTOMATIC POWER DOWN
TSOP44, and TFBGA48 PACKAGES
44
1
–
Compliant with Lead-Free Soldering Pro-
cesses
TSOP44 Type II (ND)
–
Standard or Lead-Free Option
FBGA
TFBGA48 (ZH)
6 x 8mm
FBGA
TFBGA48 (ZB)
7 x 8mm
April 2004
1/23
M68AW256M
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . . 12
Figure 10.Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . 12
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.UB/LB Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15.TSOP44 II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . . 18
Table 10. TSOP 44 II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . 18
Figure 16.TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Bottom View Package Outline19
Table 11. TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Package Mechanical Data . . 19
Figure 17.TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . 20
2/23
M68AW256M
Table 12. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M68AW256M
SUMMARY DESCRIPTION
The M68AW256M is a 4 Mbit (4,194,304 bit)
CMOS SRAM, organized as 262,144 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
(7x8mm - 6x8 active ball array, 0.75 mm pitch) and
in TSOP44 Type II packages.
In addition to the standard version, both packages
are also available in Lead-free version, in compli-
ance with the JEDEC Std J-STD-020B, the ST
ECOPACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The M68AW256 is available in TFBGA48 (6x8mm
- 6x8 active ball array, 0.75mm pitch), TFBGA48
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A17
Address Inputs
V
CC
DQ0-DQ15
Data Input/Output
Chip Enable
E
18
16
G
Output Enable
A0-A17
DQ0-DQ15
W
UB
LB
Write Enable
W
E
Upper Byte Enable Input
Lower Byte Enable Input
Supply Voltage
M68AW256M
V
G
CC
V
Ground
SS
UB
LB
NC
DU
Not Connected Internally
Don’t Use as Internally Connected
V
SS
AI04870b
4/23
M68AW256M
Figure 3. TSOP Connections
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
A2
3
A7
A1
4
G
A0
5
UB
E
6
LB
DQ0
DQ1
DQ2
DQ3
7
DQ15
DQ14
DQ13
DQ12
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
V
V
CC
SS
CC
M68AW256M
V
SS
DQ4
DQ5
DQ6
DQ7
W
DQ11
DQ10
DQ9
DQ8
NC
A16
A15
A14
A13
A12
A8
A9
A10
A11
A17
AI04871b
5/23
M68AW256M
Figure 4. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A2
E
NC
A
B
C
D
E
F
LB
G
A0
A3
A1
A4
A6
DQ8
DQ9
DQ0
DQ2
UB
DQ10
DQ11
DQ12
DQ13
NC
A5
DQ1
DQ3
DQ4
DQ5
W
A7
V
A17
NC
A14
A12
A9
V
SS
CC
V
A16
A15
A13
A10
V
CC
SS
DQ14
DQ15
NC
DQ6
DQ7
DU
G
H
A8
A11
AI03955
6/23
M68AW256M
Figure 5. Block Diagram
V
V
CC
SS
A17
A7
ROW
DECODER
MEMORY
ARRAY
DQ15
UB
(8)
(8)
I/O CIRCUITS
COLUMN
DECODER
DQ0
LB
A0
A6
(8)
(8)
UB
LB
W
E
UB
LB
G
AI04833
7/23
M68AW256M
OPERATION
The device has four standard operating modes:
Write Mode. The M68AW256M is in the Write
mode whenever the W and E are Low. Either the
Chip Enable input (E) or the Write Enable input
(W) must be de-asserted during Address
transitions for subsequent write cycles. When E
(W) is Low, and UB or LB is Low, write cycle
begins on the W (E)'s falling edge. When E and W
are Low, and UB = LB = High, write cycle begins
on the first falling edge of UB or LB. Therefore,
address setup time is referenced to Write Enable,
Chip Enable or UB/LB as tAVWL, tAVEL and tAVBL
respectively, and is determined by the latter
occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E, W or UB/LB. If the Output is en-
abled (E = Low, G = Low, LB or UB = Low), then
W will return the outputs to high impedance within
tWLQZ of its falling edge. Care must be taken to
avoid bus contention in this type of operation. Data
input must be valid for tDVWH before the rising
edge of Write Enable, or for tDVEH before the rising
edge of E, or for tDVBH before the rising edge of
UB/LB whichever occurs first, and remain valid for
tWHDX, tEHDX and tBHDX respectively.
Standby/Power-Down. The M68AW256M has a
Chip Enable power down feature which invokes an
automatic standby mode whenever either Chip
Enable is de-asserted (E = High) or LB and UB are
de-asserted (LB and UB = High). An Output En-
able (G) signal provides a high speed tri-state con-
trol, allowing fast read/write cycles to be achieved
with the common I/O data bus. Operational modes
are determined by device control inputs W, E, LB
and UB as summarized in the Operating Modes ta-
ble (see Table 2).
Output Disabled, Read, Write and Standby/Pow-
er-Down. These modes are determined by the
control inputs E, W, G, LB and UB as summarized
in Table 2., Operating Modes.
Output Disabled. The Output Enable signal, G,
provides high-speed tri-state control of DQ0-
DQ15, allowing fast read/write cycles on the I/O
data bus. The device is in Output Disabled mode
when Output Enable, G, is High. In this mode, LB
and UB are Don’t care and DQ0-DQ15 are high
impedance.
Read Mode. The M68AW256M is in the Read
mode whenever Write Enable (W) is High with
Output Enable (G) Low, and Chip Enable (E) is as-
serted.
This provides access to data from eight or sixteen,
depending on the status of the signal UB and LB,
of the 4,194,304 locations in the static memory ar-
ray, specified by the 18 address inputs.If only one
of the Byte Enable inputs is at VIL, the
M68AW256M is in Byte Read mode. If the two
Byte Enable inputs are at VIL, the M68AW256M is
in Word Read mode. So depending on the status
of the UB and LB signals, valid data will be avail-
able on the lower eight, the upper eight or all six-
teen output pins, tAVQV after the last stable
address, providing G is Low and E is Low.
If either of E or G is asserted after tAVQV has
elapsed, data access will be measured from the
limiting parameter (tELQV, tGLQV or tBLQV) rather
than the address. Data out may be indeterminate
at tELQX, tGLQX and tBLQX but data lines will always
be valid at tAVQV
.
Table 2. Operating Modes
Operation
Deselected
E
W
X
G
X
X
LB
UB
DQ0-DQ7
Hi-Z
DQ8-DQ15
Hi-Z
Power
Standby (I
Standby (I
Active (I
V
)
)
X
X
IH
SB
(Standby/Power-Down)
V
V
X
X
Hi-Z
Hi-Z
IH
IH
SB
V
V
IH
V
IL
V
V
)
Lower Byte Read
Lower Byte Write
Output Disabled
Upper Byte Read
Upper Byte Write
Word Read
Data Output
Data Input
Hi-Z
Hi-Z
IL
IL
IL
IL
IL
IL
IL
IL
IH
CC
V
V
V
V
V
V
V
V
IL
V
V
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
)
X
Hi-Z
IL
IH
CC
V
V
IH
)
)
)
)
)
)
X
X
Hi-Z
IH
IH
CC
CC
CC
CC
CC
CC
V
V
IL
V
V
Hi-Z
Data Output
Data Input
Data Output
Data Input
Hi-Z
IH
IL
V
IL
V
V
X
Hi-Z
IH
IL
V
IH
V
IL
V
V
Data Output
Data Input
Hi-Z
IL
IL
V
IL
V
V
Word Write
X
IL
IL
V
IH
Output Disabled
X
X
X
IH
Note: 1. X = V or V .
IH
IL
8/23
M68AW256M
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
20
Unit
mA
°C
°C
°C
V
(1)
Output Current
I
O
T
A
Ambient Operating Temperature
Storage Temperature
–55 to 125
–65 to 150
T
STG
(2)
(3)
T
LEAD
Lead Temperature during Soldering
Supply Voltage
260
V
CC
–0.5 to 4.6
(4)
–0.5 to V +0.5
Input or Output Voltage
Power Dissipation
V
V
CC
IO
P
1
W
D
Note: 1. One output at a time, not to exceed 1 second duration.
®
2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assermbly), the ST ECOPACK 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
3. Not exceeding 250°C for more than 30s, and peaking at 260°C.
4. Up to a maximum operating V of 3.6V only.
CC
9/23
M68AW256M
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter
M68AW256M
V
Supply Voltage
2.7 to 3.6V
CC
Range 1
Range 6
0 to 70°C
–40 to 85°C
30pF
Ambient Operating Temperature
Load Capacitance (C )
L
Output Circuit Protection Resistance (R )
3.0kΩ
1
Load Resistance (R )
3.1kΩ
2
Input Rise and Fall Times
1ns/V
0 to V
Input Pulse Voltages
CC
V
/2
Input and Output Timing Ref. Voltages
Output Transition Timing Ref. Voltages
CC
V
= 0.3V ; V = 0.7V
CC RH CC
RL
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
V
CC
I/O Timing Reference Voltage
R
1
V
CC
V
/2
CC
DEVICE
UNDER
TEST
OUT
0V
C
L
Output Timing Reference Voltage
R
2
V
CC
0.7V
0.3V
CC
CC
0V
AI05831
C
includes probe and 1 TTLcapacitance
L
AI05832
10/23
M68AW256M
Table 5. Capacitance
Symbol
Test
Condition
(1,2)
Min
Max
Unit
Parameter
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
8
pF
pF
IN
IN
C
V
OUT
10
OUT
Note: 1. Sampled only, not 100% tested.
2. At T = 25°C, f = 1 MHz, V = 3.0V.
A
CC
Table 6. DC Characteristics
-L
-N
Symbol
Parameter
Test Condition
Unit
Min
Max
20
Min
Max
70ns
55ns
10
15
mA
mA
V
CC
= 3.6V, f = 1/t
,
AVAV
(1,2)
Operating Supply Current
Operating Supply Current
I
CC1
I
= 0mA
OUT
26
V
= 3.6V, f = 1MHz,
CC
(3)
2
2
mA
µA
I
CC2
I
= 0mA
OUT
V
= 3.6V, f = 0,
CC
Standby Supply Current
CMOS
I
SB
E ≥ V –0.2V or
CC
20
20
LB=UB ≥ V –0.2V
CC
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Input High Voltage
–1
–1
1
1
–1
–1
1
1
µA
µA
V
LI
IN
CC
(4)
I
LO
0V ≤ V
≤ V
OUT
CC
V
V
+ 0.3
V
CC
+ 0.3
2.2
2.2
IH
CC
–
0.3
V
Input Low Voltage
–0.3
2.4
0.6
0.6
0.4
V
IL
V
OH
I
= –1.0mA
= 2.1mA
Output High Voltage
Output Low Voltage
2.4
V
V
OH
V
I
OL
0.4
OL
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. E = V , LB OR/AND UB = V , V = V OR V .
IL
IL
IN
IL
IH
3. E ≤ 0.2V, LB OR/AND UB ≤ 0.2V, V ≤ 0.2V OR V ≥ V –0.2V.
IN
IN
CC
4. Output disabled.
Figure 8. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A17
VALID
tAVQV
tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI03956b
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
11/23
M68AW256M
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV
A0-A17
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ15
VALID
tBLQV
tBHQZ
UB, LB
tBLQX
AI03957c
Note: Write Enable (W) = High.
Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
E, UB, LB
tPU
tPD
I
CC
50%
I
SB
AI03856
12/23
M68AW256M
Table 7. Read and Standby Mode AC Characteristics
M68AW256M
Symbol
Parameter
Unit
55
55
55
70
70
70
t
Read Cycle Time
Min
ns
ns
AVAV
t
Address Valid to Output Valid
Max
AVQV
(1)
Data hold from address change
Min
Max
Max
Min
5
20
55
5
5
25
70
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AXQX
(2,3)
Upper/Lower Byte Enable High to Output Hi-Z
Upper/Lower Byte Enable Low to Output Valid
Upper/Lower Byte Enable Low to Output Transition
Chip Enable High to Output Hi-Z
t
t
t
BHQZ
t
BLQV
(1)
t
BLQX
(2,3)
Max
Max
Min
20
55
5
25
70
5
EHQZ
t
Chip Enable Low to Output Valid
ELQV
(1)
Chip Enable Low to Output Transition
Output Enable High to Output Hi-Z
t
ELQX
(2,3)
Max
Max
Min
20
25
5
25
35
5
GHQZ
t
Output Enable Low to Output Valid
GLQV
(2)
Output Enable Low to Output Transition
Chip Enable or UB/LB High to Power Down
Chip Enable or UB/LB Low to Power Up
t
GLQX
(4)
Max
Min
0
0
t
t
PD
(4)
55
70
PU
Note: 1. Test conditions assume transition timing reference level = 0.3V or 0.7V
.
CC
CC
2. At any given temperature and voltage condition, t
any given device.
is less than t
, t
is less than t
and t
is less than t
for
GHQZ
GLQX BHQZ
BLQX
EHQZ
ELQX
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters.
13/23
M68AW256M
Figure 11. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVWH
tELWH
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ15
UB, LB
DATA INPUT
tDVWH
tBLWH
AI03958c
Figure 12. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tWLEH
W
tEHDX
DQ0-DQ15
DATA INPUT
tDVEH
tBLEH
UB, LB
AI03959c
14/23
M68AW256M
Figure 13. UB/LB Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVBH
tBHAX
tELBH
E
tWLBH
W
tBHDX
DQ0-DQ15
DATA (1)
DATA INPUT
tDVBH
tAVBL
tBLBH
UB, LB
AI03987c
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
15/23
M68AW256M
Table 8. Write Mode AC Characteristics
M68AW256M
Symbol
Parameter
Unit
55
70
70
60
0
t
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
55
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to LB, UB High
AVBH
t
Addess Valid to LB, UB Low
AVBL
t
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
LB, UB High to Address Transition
LB, UB High to Input Transition
LB, UB Low to LB, UB High
45
0
60
0
AVEH
t
AVEL
t
45
0
60
0
AVWH
t
AVWL
t
0
0
BHAX
t
0
0
BHDX
t
45
45
45
25
25
25
0
60
60
60
30
30
30
0
BLBH
t
LB, UB Low to Chip Enable High
LB, UB Low to Write Enable High
Input Valid to LB, UB High
BLEH
t
BLWH
t
DVBH
t
Input Valid to Chip Enable High
Input Valid to Write Enable High
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to LB, UB High
Chip Enable Low to Chip Enable High
Chip Enable Low to Write Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Output Transition
Write Enable Low to LB, UB High
Write Enable Low to Chip Enable High
DVEH
t
DVWH
t
EHAX
t
0
0
EHDX
t
45
45
45
0
60
60
60
0
ELBH
t
ELEH
t
ELWH
t
WHAX
t
0
0
WHDX
(1)
5
5
t
WHQX
t
45
45
60
60
20
WLBH
t
WLEH
(1,2)
Write Enable Low to Output Hi-Z
Max
Min
20
ns
t
WLQZ
-L version
-N version
45
40
60
50
ns
ns
t
Write Enable Low to Write Enable High
WLWH
Min
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WHQX
WLQZ
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
16/23
M68AW256M
Figure 14. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE
3.6V
2.7V
V
CC
V
> 1.5V
DR
tCDR
tR
E ≥ V
– 0.2V or UB=LB ≥ V
– 0.2V
DR
DR
E, UB/LB
AI03989
Table 9. Low VCC Data Retention Characteristics
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
= 1.5V, E ≥ V –0.2V or
CC
CC
(1)
Supply Current (Data Retention)
4.5
9
µA
I
CCDR
(3)
UB = LB ≥ V –0.2V, f = 0
CC
Chip Deselected to Data
Retention Time
(1,2)
0
ns
ns
V
t
CDR
(2)
t
Operation Recovery Time
t
R
AVAV
E ≥ V –0.2V or
CC
(1)
Supply Voltage (Data Retention)
1.5
V
DR
UB = LB ≥ V –0.2V, f = 0
CC
Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.
IH
CC
IL
2. Tested initially and after any design or process changes that may affect these parameters. t
is Read cycle time.
AVAV
3. No input may exceed V +0.2V.
CC
17/23
M68AW256M
PACKAGE MECHANICAL
Figure 15. TSOP44 II - 44 lead Plastic Thin Small Outline Type II, Package Outline
D
N
E1
E
1
N/2
ZD
b
e
A2
A
C
α
A1
CP
L
TSOP-d
Note: Drawing is not to scale.
Table 10. TSOP 44 II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
Typ
Max
A
A1
A2
b
0.0472
0.0059
0.0413
0.050
0.950
0.0020
0.0374
0.350
0.0138
c
0.120
0.210
0.0047
0.0083
D
18.410
11.760
10.160
0.800
–
–
0.7248
0.4630
0.4000
0.0315
0.0197
0.0317
–
–
E
–
–
–
–
E1
e
–
–
–
–
–
–
0.400
–
–
–
0.0236
–
L
0.500
0.600
–
0.0157
ZD
alfa
CP
N
0.805
–
0
0
5
5
0.100
0.0039
44
44
18/23
M68AW256M
Figure 16. TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z26
Note: Drawing is not to scale.
Table 11. TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.260
0.0102
0.900
0.0354
0.350
5.900
–
0.450
0.0138
0.2323
–
0.0177
D
6.000
3.750
6.100
0.2362
0.1476
0.2402
D1
ddd
E
–
–
0.100
0.0039
8.000
5.250
0.750
1.125
1.375
0.375
0.375
7.900
8.100
0.3150
0.2067
0.0295
0.0443
0.0541
0.0148
0.0148
0.3110
0.3189
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
19/23
M68AW256M
Figure 17. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z22
Note: Drawing is not to scale.
Table 12. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.260
0.0102
0.900
0.0354
0.350
6.900
–
0.450
0.0138
0.2717
–
0.0177
D
7.000
3.750
7.100
0.2756
0.1476
0.2795
D1
ddd
E
–
–
0.100
0.0039
8.000
5.250
0.750
1.625
1.375
0.375
0.375
7.900
8.100
0.3150
0.2067
0.0295
0.0640
0.0541
0.0148
0.0148
0.3110
0.3189
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
20/23
M68AW256M
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M68AW256
M
L
55 ZB
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
W = 2.7 to 3.6V
Array Organization
256 = 4 Mbit (256K x16)
Option 1
M = 1 Chip Enable; Write and Standby from UB and LB
Option 2
L = L-Die
N = N-Die
Speed Class
55 = 55 ns
70 = 70 ns
Package
ND = TSOP 44 Type II
ZH = TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch
ZB= TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch
Operative Temperature
1 = 0 to 70 °C
6 = –40 to 85 °C
Shipping
Blank = Standard Packing (Tray)
T = Tape & Reel Packing
E = Lead-Free Package, Standard Packing (Tray)
F = Lead-Free Package, Tape and Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
21/23
M68AW256M
REVISION HISTORY
Table 14. Document Revision History
Date
Version
Revision Details
February 2002
-01
First Issue
Tables 4, 7 and 9 clarified
Figure 14 clarified
13-Mar-2002
17-Jun-2002
-02
-03
I
I
clarified (Table 9)
clarified (Table 6)
CCDR
SB
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 03 equals 3.0).
09-Oct-2002
3.1
Part number modified.
TFBGA48 7x8 replaced by TFBGA48 6x7: Figure 16., TFBGA48 6x8mm - 6x8 active
ball array, 0.75 mm pitch, Bottom View Package Outline and Table 11., TFBGA48
6x8mm - 6x8 active ball array, 0.75 mm pitch, Package Mechanical Data updated.
I
and I updated in Table 6., DC Characteristics.
CC1
SB
20-Feb-2004
27-Apr-2004
4.0
5.0
t
updated in Table 8., Write Mode AC Characteristics .
WLWH
Minor content modifications.
FEATURES SUMMARY, SUMMARY DESCRIPTION, Table 13., Ordering
Information Scheme updated with Package Lead-free information. TLEAD parameter
added in Table 3., Absolute Maximum Ratings.
TFBGA48 7x8mm - 6x8 active ball array, 0.75mm pitch reintroduced.
TFBGA 6x7mm -6x8mm active ball array replaced by TFBGA48 6x8mm- 6x8 active
ball array, 0.75mm pitch.
22/23
M68AW256M
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
®
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany -
Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore -
Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
23/23
相关型号：
©2020 ICPDF网 联系我们和版权申明