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M69AB048BD70W8F [STMICROELECTRONICS]

2MX16 PSEUDO STATIC RAM, 70ns, UUC, ROHS COMPLIANT, WAFER;
M69AB048BD70W8F
型号： M69AB048BD70W8F
厂家： ST    ST
描述：

2MX16 PSEUDO STATIC RAM, 70ns, UUC, ROHS COMPLIANT, WAFER

内存集成电路
文件： 总64页 (文件大小：652K)
中文：  中文翻译
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M69KB048BD  
M69AB048BD  
32 Mbit (2 Mb x16) 1.8 V supply, burst PSRAMs  
Features  
FBGA  
■ Asynchronous SRAM interface  
■ Fast access time: 70 ns  
■ Asynchronous page read  
– Page size: 8 words  
FBGA71 (ZA)  
7 x 11mm  
– First access within page: 70 ns  
– Subsequent read within page: 20 ns  
■ Synchronous burst read/write capability  
– Fixed length (8, or 16 words) or  
continuous mode  
– Output delay: 8 ns max  
– Burst read/write mode: fixed length (8 or 16  
words) or continuous  
■ Low voltage operating condition  
– V = 1.7 to 1.95 V  
CC  
■ Byte control by UB and LB  
■ Low power consumption  
– Active current: 30 mA  
– Standby current: 100 µA  
Wafer  
■ Three power-down modes  
– Deep power-down  
– Partial array refresh of 4 Mbits  
– Partial array refresh of 8 Mbits  
■ Wide operating temperature  
– –30 to +85°C  
®
■ ECOPACK FBGA71 package available  
December 2007  
Rev 2  
1/64  
www.st.com  
1
Contents  
M69KB048BD, M69AB048BD  
Contents  
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
2.9  
Address inputs (A0-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Data inputs/outputs (DQ8-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Chip Enable input (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Chip Enable input (E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Output Enable input (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Write Enable input (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Upper Byte Enable input (UB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Lower Byte Enable input (LB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
2.10 Clock input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
2.11 Latch Enable input (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
2.12 Wait output (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
2.13  
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
2.14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
3.8  
3.9  
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Set Configuration Register sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Asynchronous page read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Asynchronous write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Synchronous burst read and write modes . . . . . . . . . . . . . . . . . . . . . . . . 17  
Synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Synchronous burst read terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Synchronous burst write suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
3.10 Synchronous burst write terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
2/64  
M69KB048BD, M69AB048BD  
Contents  
5
6
7
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
3/64  
List of tables  
M69KB048BD, M69AB048BD  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Table 18.  
Table 19.  
Table 20.  
Table 21.  
Table 22.  
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Bus modes– asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Bus modes– synchronous burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Set CR sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Configuration Register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Burst length definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Asynchronous read AC characteristics (page mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Asynchronous write mode AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Synchronous mode - Clock AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Synchronous mode - address latch AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Synchronous burst read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Synchronous burst write AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Power-down and power-up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
Standby AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
FBGA71 7 x 11 mm - 8 x 12 active ball array, 0.8 mm pitch, package mechanical data . . 61  
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
4/64  
M69KB048BD, M69AB048BD  
List of figures  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
FBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Synchronous burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Burst length definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Latency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Write Enable control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Figure 10. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 11. Asynchronous read basic AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 12. G controlled asynchronous read basic AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 13. LB and UB controlled asynchronous read basic AC waveforms. . . . . . . . . . . . . . . . . . . . . 30  
Figure 14. E1 controlled, asynchronous page read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Figure 15. Asynchronous write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 16. W controlled, asynchronous write AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 17. W, UB and LB controlled, asynchronous write AC waveforms 1 . . . . . . . . . . . . . . . . . . . . 33  
Figure 18. W, UB and LB controlled, asynchronous write AC waveforms 2 . . . . . . . . . . . . . . . . . . . . 34  
Figure 19. W, UB and LB controlled, asynchronous write AC waveforms 3 . . . . . . . . . . . . . . . . . . . . 34  
Figure 20. W, UB and LB controlled, asynchronous write AC waveforms 4 . . . . . . . . . . . . . . . . . . . . 35  
Figure 21. E1 controlled, asynchronous read followed by write AC waveforms . . . . . . . . . . . . . . . . . 35  
Figure 22. E1, W and G controlled, asynchronous read followed by write AC waveforms . . . . . . . . . 36  
Figure 23. W and G controlled, asynchronous read followed by write AC waveforms. . . . . . . . . . . . . 36  
Figure 24. W, G and UB/LB controlled, asynchronous read followed by write AC waveforms . . . . . . 37  
Figure 25. Clock input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 26. Synchronous burst address latch waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 27. G controlled, synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Figure 28. E1 controlled, synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Figure 29. L controlled, synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Figure 30. Synchronous burst read suspend and resume AC waveforms. . . . . . . . . . . . . . . . . . . . . . 44  
Figure 31. Synchronous burst read terminate AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Figure 32. W Level control mode, synchronous burst write AC waveforms. . . . . . . . . . . . . . . . . . . . . 47  
Figure 33. W pulse control mode, synchronous burst write AC waveforms. . . . . . . . . . . . . . . . . . . . . 48  
Figure 34. L controlled, synchronous write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Figure 35. Synchronous burst write suspend and resume AC waveforms . . . . . . . . . . . . . . . . . . . . . 50  
Figure 36. Synchronous burst write terminate AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
Figure 37. E1 controlled synchronous burst read followed by write AC waveforms . . . . . . . . . . . . . . 52  
Figure 38. L controlled synchronous burst read followed by write AC waveforms. . . . . . . . . . . . . . . . 53  
Figure 39. E1 controlled synchronous burst write followed by read AC waveforms . . . . . . . . . . . . . . 54  
Figure 40. L controlled synchronous burst write followed by read AC waveforms. . . . . . . . . . . . . . . . 55  
Figure 41. Power-up AC waveforms - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
Figure 42. Power-up AC waveforms - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
Figure 43. power-down Mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
Figure 44. Standby mode entry AC waveforms, after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
Figure 45. Set Configuration Register sequence (asynchronous mode) AC waveforms. . . . . . . . . . . 58  
Figure 46. Set Configuration Register sequence (synchronous mode) AC waveforms. . . . . . . . . . . . 59  
Figure 47. FBGA71 7 x 11 mm - 8 x 12 active ball array, 0.8 mm pitch, package outline  
(bottom view), . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
5/64  
Description  
M69KB048BD, M69AB048BD  
1
Description  
The M69KB048BD and M69AB048BD are 32 Mbit (33 554 432 bit) CMOS memories,  
organized as 2 097 152 words by 16 bits, and supplied by a single 1.7 V to 1.95 V supply  
voltage range. They are particularly suited for mobile applications such as cellular handsets,  
PDAs and handheld equipment.  
The M69KB048BD and M69AB048BD are members of STMicroelectronics pseudo SRAM  
(PSRAM) family whose memory array is implemented by using one transistor per cell  
topology to achieve bigger array sizes. The internal control logic of the M69KB048BD and  
M69AB048BD automatically handles the periodic refresh cycle without user involvement.  
The devices support asynchronous page read mode and synchronous burst read and write  
modes for fast memory access.  
They feature various kinds of power-down modes for power saving as a user configurable  
option:  
■
The partial array refresh (PAR) performs a limited refresh of the part of the PSRAM  
array (4 Mbits, 8 Mbits) that contains essential data.  
■
The deep power-down mode.  
The M69AB048BD is available in a FBGA71 (0.8 mm pitch) package, and the M69KB048BD  
is offered in unsawn wafer.  
6/64  
M69KB048BD, M69AB048BD  
Description  
Figure 1.  
Logic diagram  
V
CC  
21  
16  
A0-A20  
W
DQ0-DQ15  
WAIT  
E1  
E2  
G
M69AB048BD  
M69KB048BD  
UB  
LB  
K
L
V
SS  
AI11394  
Table 1.  
Signal names  
Name  
Function  
A0-A20  
Address inputs  
Data inputs/outputs  
DQ0-DQ15  
E1  
E2  
G
Chip Enable input (Active Low)  
Chip Enable input (Active High)  
Output Enable input  
Write Enable input  
Upper Byte Enable input  
Lower Byte Enable input  
Clock input  
W
UB  
LB  
K
L
Latch Enable input  
Wait output  
WAIT  
VCC  
VSS  
Core supply voltage  
Ground  
7/64  
Description  
Figure 2.  
M69KB048BD, M69AB048BD  
FBGA connections (top view through package)  
1
2
3
4
5
6
7
8
NC  
A
B
C
D
E
F
NC  
NC  
NC  
NC  
NC  
NC  
A8  
A19  
A9  
A7  
A6  
A5  
A4  
A11  
A12  
A13  
A14  
W
LB  
K
L
A3  
A2  
A1  
A0  
NC  
E1  
UB  
E2  
A15  
NC  
NC  
A18  
A17  
DQ1  
WAIT  
A20  
A10  
DQ6  
G
H
J
V
NC  
A16  
NC  
SS  
DQ15  
G
DQ9  
DQ10  
DQ2  
DQ3  
DQ4  
DQ13  
DQ12  
DQ5  
V
V
V
DQ0  
DQ8  
NC  
DQ7  
DQ14  
NC  
CC  
CC  
SS  
K
L
DQ11  
NC  
NC  
NC  
NC  
NC  
NC  
M
NC  
AI09015c  
8/64  
M69KB048BD, M69AB048BD  
Signals description  
2
Signals description  
See Figure 1: Logic diagram, Figure 3: Block diagram, and Table 1: Signal names for a brief  
overview of the signals connected to this device.  
2.1  
2.2  
2.3  
2.4  
Address inputs (A0-A20)  
The address inputs select the cells in the memory array to access during read and write  
operations. These signals are also used during the set Configuration Register sequence.  
Data inputs/outputs (DQ8-DQ15)  
The Upper Byte Data inputs/outputs carry the data to or from the upper part of the selected  
address during a write or read operation, when Upper Byte Enable (UB) is driven Low.  
Data inputs/outputs (DQ0-DQ7)  
The Lower Byte Data inputs/outputs carry the data to or from the lower part of the selected  
address during a write or read operation, when Lower Byte Enable (LB) is driven Low.  
Chip Enable input (E1)  
When asserted (Low), the Chip Enable input, E1, activates the memory state machine,  
address buffers and decoders, allowing read and write operations to be performed. When  
de-asserted (High), all other pins are ignored, and the device is automatically put in standby  
mode. The transition of E1 from Low to High is also used to terminate a synchronous burst  
operation or during a set Configuration Register sequence (see Figure 31: Synchronous  
burst read terminate AC waveforms and Figure 36: Synchronous burst write terminate AC  
waveforms)  
2.5  
2.6  
Chip Enable input (E2)  
When de-asserted (Low), the Chip Enable input, E2, puts the device in power-down mode  
according to the Configuration Register settings (see Table 5).  
Output Enable input (G)  
The Output Enable, G, provides a high speed tri-state control, allowing fast read/write cycles  
to be achieved with the common I/O data bus. This signal is also used in synchronous burst  
read mode.  
9/64  
Signals description  
M69KB048BD, M69AB048BD  
2.7  
Write Enable input (W)  
The Write Enable, W, controls the bus write operation of the memory’s command interface.  
This signal is also used in synchronous burst read and write mode.  
Two types W control methods are available in synchronous burst write mode:  
■
Level control - The first Clock K rising edge following W falling edge triggers the  
synchronous burst write.  
■
Pulse control- A Write Enable, W, Low pulse during a rising edge of the Clock K triggers  
the synchronous burst write.  
Refer to Figure 8: Write Enable control modes for details on the two W control modes.  
The device is configured to operate in level control mode or pulse control mode through bit  
WC of the Configuration Register (CR) (see Table 5: Configuration Register definition).  
2.8  
Upper Byte Enable input (UB)  
The Upper Byte Enable, UB, gates the data on the Upper Byte Data inputs/outputs (DQ8-  
DQ15) to or from the upper part of the selected address during a write or read operation.  
This signal is only used during asynchronous operations and must be stable in burst mode.  
2.9  
Lower Byte Enable input (LB)  
The Lower Byte Enable, LB, gates the data on the Lower Byte Data inputs/outputs (DQ0-  
DQ7) to or from the lower part of the selected address during a write or read operation.  
2.10  
Clock input (K)  
Clock, K, is an input signal to synchronize the memory to the microcontroller or system bus  
frequency during synchronous burst read and write operations. The Clock input increments  
the device internal address counter. The valid edge of K is the reference for latency counts  
from address latch, burst write data latch, and burst read data out. The K input is required  
during all synchronous operations, except in standby and power-down. The Clock signal is  
‘don’t care’ during asynchronous operations.  
2.11  
Latch Enable input (L)  
The Latch Enable input is used in both asynchronous and synchronous mode to validate the  
address present on A0-A20. All the addresses are latched on the rising edge of L.  
L input is active after E1 becomes Low, V , and is disabled when E1 is High, V .  
IL  
IH  
The address latch is transparent when L is at V and it is inhibited when L is at  
IL  
V . Once the first address has been latched, the state of L controls whether subsequent  
IH  
addresses come from the address lines (L=V ) or from the internal burst counter (L=V ).  
IL  
IH  
10/64  
M69KB048BD, M69AB048BD  
Signals description  
2.12  
Wait output (WAIT)  
WAIT is an output signal used during synchronous burst read operations. It indicates  
whether the data on the output bus are valid. In synchronous read suspend mode, the WAIT  
remains in its previous state.  
The WAIT signal is gated by G and is asserted after a specified delay from the falling edge  
of G. It becomes High one clock cycle before valid data is output.  
When the device is not in synchronous burst read mode, WAIT is high impedance.  
2.13  
VCC supply voltage  
The V supply voltage supplies the power for all operations (read, write, etc.) and for  
CC  
driving the refresh logic, even when the device is not being accessed.  
2.14  
VSS ground  
The V ground is the reference for all voltage measurements.  
SS  
Figure 3.  
Block diagram  
ARBITRATION  
LOGIC  
INTERNAL  
CLOCK  
REFRESH  
GENERATOR  
CONTROLLER  
DYNAMIC  
MEMORY  
ARRAY  
ADDRESS  
DQ0-DQ7  
INPUT/OUTPUT  
BUFFER  
L
E1  
E2  
G
DQ8-DQ15  
COLUMN  
DECODER  
CONTROL  
LOGIC  
W
LB  
UB  
ADDRESS  
BURST  
CONTROLLER  
K
WAIT  
V
POWER  
CONTROLLER  
CC  
V
SS  
AI09016d  
11/64  
Signals description  
M69KB048BD, M69AB048BD  
DQ8-  
Table 2.  
Mode  
Bus modes– asynchronous mode  
E2  
E1  
K
L
W
G
LB  
UB  
A0-A20 DQ0-DQ7  
WAIT  
DQ15  
Standby  
VIH VIH  
X
X
X
X
X
X
X
X
X
X
X
High-Z  
High-Z  
High-Z  
High-Z High-Z  
High-Z High-Z  
High-Z High-Z  
(deselected)  
Output disable(1) VIH VIL  
VIH  
VIH  
VIH  
VIL  
(2)  
(3)  
Output disable  
VIH VIL  
(2)  
(2)  
(2)  
(2)  
VIH  
VIH  
Valid  
Valid  
Valid  
Valid  
(No read)  
Output  
High-Z  
valid  
Upper byte read VIH VIL  
Lower byte read VIH VIL  
X
X
X
VIH  
VIH  
VIL  
VIL  
VIL  
VIH  
VIL  
VIL  
VIL  
VIH  
VIL  
High-Z  
Output  
valid  
High-Z High-Z  
Output  
valid  
Output  
High-Z  
Valid  
Word read  
VIH VIL  
VIH  
VIH  
(4)  
(4)  
Page read  
No write  
VIH VIL  
VIH VIL  
X
X
X
VIL VIL/VIH VIL/VIH  
Valid  
Valid  
High-Z  
(2)  
(5)  
VIL VIH  
VIL VIH  
VIH  
VIH  
VIH  
VIL  
Invalid  
Invalid High-Z  
Input  
(2)  
(2)  
(5)  
(5)  
(5)  
Upper byte write VIH VIL  
Lower byte write VIH VIL  
X
X
Valid  
Valid  
Invalid  
High-Z  
Valid  
Input  
valid  
VIL VIH  
VIL VIH  
VIL  
VIH  
Invalid High-Z  
Input  
valid  
Input  
(2)  
Word write  
VIH VIL  
VIL  
X
X
VIL  
X
VIL  
X
Valid  
X
High-Z  
Valid  
Power-down(6)  
X
X
X
X
High-Z High-Z High-Z  
1. The device must not be kept in the output disable state during more than 1 µs.  
2. The address latch is transparent when L is at VIL. The addresses are latched on the rising edge of L.  
3. Address bits are either at VIL or VIH but must be valid before read or write operation.  
4. Data outputs are either valid or Hi-Z depending on the state of LB/UB inputs.  
5. G can be VIL during a write operation if the following conditions are satisfied:  
a. Write pulse is initiated by E1, or cycle time of the previous operation cycle is satisfied;  
b. G stays VIL during the entire write cycle.  
6. Power-down mode can be entered from standby state and all DQ pins are in High-Z state. Data retention depends on the  
power-down mode selected.  
12/64  
M69KB048BD, M69AB048BD  
Signals description  
DQ8-  
Table 3.  
Mode  
Bus modes– synchronous burst mode  
A0-  
A20  
E2  
E1  
K
L
W
G
LB  
UB  
DQ0-DQ7  
WAIT  
DQ15  
Standby  
VIH VIH  
X
X
X
X
X
X
X
High-Z  
High-Z  
High-Z  
(deselected)  
Initial burst  
\_/  
Valid  
VIH VIL _/ (2)  
VIH VIL _/ (2)  
VIH VIL _/ (2)  
X(4) X(4)  
X(5)  
X(5)  
X(5)  
X(5)  
X(5)  
X(5)  
X(5)  
X
X(5)  
X(5)  
X(5)  
X(5)  
X(5)  
X(5)  
X(5)  
X
High-Z(7) High-Z(7) High-Z(8)  
(6)  
read/write(1)  
ꢀ(3)  
Advanceburst  
read(1)  
Output  
valid(9)  
Output  
valid(9)  
Output  
valid  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
X
VIH  
VIH  
VIH  
VIL  
VIH  
VIL  
VIH  
VIH  
VIH  
X
X
X
X
X
X
X
X
Burst read  
suspend(1)  
High-Z  
High-Z High-Z(10)  
Terminate  
burst read  
VIH  
VIH VIL _/ (2)  
VIH VIL _/ (2)  
_/  
X
High-Z  
Input  
High-Z  
Input  
High-Z  
Advanceburst  
write(1)  
VIL  
(12)  
VIH  
valid(11) valid(11)  
(13)  
Burst write  
suspend(1)  
VIH  
Input  
invalid  
Input  
invalid  
High-Z(10)  
High-Z  
(13)  
Terminate  
burst write  
VIH  
VIL  
_/  
X
X
X
X
X
High-Z  
High-Z  
Power-  
High-Z High-Z  
High-Z  
down(14)  
1. The device must not be kept in the output disable state during more than 4µs.  
2. The valid edge of the Clock signal is configured through the Valid Clock Edge bit (VE) of the Configuration Register. The  
Clock signal must be stable before accessing the memory array.  
3. The address valid input latches the address bits on its rising edge.  
4. W and G can be either at VIL or VIH but must not be both at VIL (prohibited configuration).  
5. LB and UB can be either at VIL or VIH but must be valid before synchronous read or write operation. Once LB and UB are  
set, they must remain stable until the end of the synchronous burst operation.  
6. Once the address is latched, address bits must remain stable while L is Low, VIL.  
7. If G is at VIL, data outputs are either Invalid or Hi-Z depending on the state of LB and UB inputs. If W is at VIL, data input are  
Invalid. If W and G are at VIH, data outputs are Hi-Z.  
8. Data outputs are either valid or invalid depending on the state of G and W inputs.  
9. Data outputs are either valid or Hi-Z depending on the state of LB and UB inputs.  
10. Keep the state of previous cycle.  
11. Data input are either valid or invalid depending on the state of LB and UB inputs.  
12. WAIT remains High, VIH, during advanced burst write operations.  
13. When the device is operating in W pulse control mode, W is ‘don’t care’ once the burst write operation has been triggered  
by a W Low pulse together with address latching. Burst write suspend is not supported in W pulse control mode.  
14. Power-down mode can be entered from standby state and all DQ pins are in High-Z state. Data retention depends on the  
power-down mode selected.  
13/64  
Operation  
M69KB048BD, M69AB048BD  
3
Operation  
The devices support asynchronous page read, page read and synchronous burst read and  
write modes, as well as three kinds of power-down modes for power saving.  
3.1  
Power-up  
The internal control logic of the M69KB048BD and M69AB048B needs to be initialized. The  
following power-up procedure must be followed before the memory is used:  
1. Apply power and attempt to maintain E1=E2=V  
IH  
2. Maintain stable power supply and E1=E2=V for t  
.
IH  
EHEV  
After power-up, the device is configured in asynchronous page read, asynchronous write  
and deep power-down mode (default settings of the CR).  
See Figure 42: Power-up AC waveforms - 2 for details on the power-up timing.  
3.2  
Set Configuration Register sequence  
The Configuration Register (CR) defines the device operating mode. The CR is  
automatically loaded with default settings during power-up. The CR can be loaded by  
latching the values placed on address lines A0 to A20 into the register.  
The device configuration can be updated any time by issuing a Set Configuration Register  
sequence, requiring 6 read/write operations to a unique address. This sequence can be  
issued both in asynchronous and synchronous mode (see Figure 45 and Figure 46 Set  
Configuration Register AC waveforms).  
The first cycle reads from address 1FFFFFh.  
The second and third cycles write back to address 1FFFFFh the same data (RDa) read  
during the first cycle. If the second or third cycle writes to a different address, the set  
Configuration Register sequence is cancelled and the cycles operate as normal write  
operations in the memory array.  
The fourth and fifth cycles write to address 1FFFFFh. The data written during the fourth and  
fifth cycle is ‘don’t-care’. If the fourth and fifth cycles writes to a different address, the set  
Configuration Register sequence is cancelled and the cycles operate as normal write  
operations in the memory array.  
The sixth cycle effectively programs the content of the CR by performing a read operation  
with A0-A20 containing the CR value.  
Between each read or write operation, the device must be put in standby mode by holding  
E1 High.  
Once updated, the value of the CR may be lost. A CR Set sequence should be performed  
prior to regular read/write operation if a device configuration different from the default one is  
requested.  
The definition of the Configuration Register bits is detailed in Table 5: Configuration Register  
definition.  
14/64  
M69KB048BD, M69AB048BD  
Operation  
Table 4.  
Cycle  
Set CR sequence  
Operation  
Address  
Data  
1st  
2nd  
3rd  
4th  
5th  
6th  
Read  
Write  
Write  
Write  
Write  
Read  
1FFFFFh  
1FFFFFh  
1FFFFFh  
1FFFFFh  
1FFFFFh  
CR(2)  
RDa(1)  
RDa(1)  
RDa(1)  
X
X
RDb  
1. RD = Read Data.  
2. CR = Configuration Register value.  
Table 5.  
Configuration Register definition  
Address bits CR Bits  
Definition  
Value  
Description  
8 Mbits partial array refresh(1)  
00  
01  
4 Mbits partial array refresh(1)  
Reserved for future use(2)  
A20-A19  
PS  
Partial size  
10  
11  
Deep power-down mode (default)  
010  
011  
111  
8 words  
16 words  
Continuous  
A18-A16  
A15  
BL  
M
Burst length  
Mode  
The other configurations are reserved for future use (2)  
0
Synchronous burst read/write(3)  
1
Asynchronous (page read/normal write) (default)(3)  
001  
010  
011  
100  
3 clock cycles  
4 clock cycles  
5 clock cycles  
6 clock cycles  
A14-A12  
RL  
Read latency  
Other configuration is reserved for future use(2)  
A11  
A10  
—
—
1
0
1
0
1
0
1
0
1
Unused bit(4)  
Burst read and burst write  
SW  
Single write  
Burst read and single write(5)  
Reserved for future use (2)  
A9  
A8  
A7  
VE  
RP  
WC  
Valid Clock edge  
Reset to page  
Rising Clock edge  
Reset to the device to page mode(6)  
Device remains in the previously selected mode(1)  
W pulse control without write suspend function(5)  
W level control with write suspend function  
Write Enable control  
15/64  
Operation  
Table 5.  
M69KB048BD, M69AB048BD  
Description  
Configuration Register definition (continued)  
Address bits CR Bits  
Definition  
Value  
0
1
Full strength  
A6  
DS  
—
Driver strength bit  
—
Half strength (default)  
A5-A0  
111111 Unused bits(4)  
1. Deep power-down and Partial Array Refresh are effective when RP bit is set to ‘1’.  
2. This value is prohibited.  
3. If the M bit is set to ‘0’ (burst mode selected), all burst mode related CR bits must be initialized simultaneously with  
appropriate values. If it is set to ‘1’, PS and DS bits must be initialized simultaneously with appropriate value while all the  
other CR bits are set to ‘1’.  
4. A11 and A5 to A0 must be set to ‘1’.  
5. Burst read and single write are not supported in W pulse control mode.  
6. If RP bit is set to ‘0’, driving E2 Low, VIL, returns the device to standby and asynchronous mode, regardless of the value of  
PS bits. Deep power-down and partial array refresh are consequently unavailable.  
3.3  
Power-down modes  
Power-down modes are used to put the device in low power idle state when E2 is Low.  
This device has three power down modes:  
■
■
■
Partial array refresh (PAR) on 4 Mbit areas of the memory array  
Partial array refresh (PAR) on 8 Mbit areas of the memory array  
Deep power-down mode  
The power-down mode is selected by issuing a set CR sequence (PS bits).  
In deep power-down mode, all data store in the memory array are lost. In PAR mode, a  
limited refresh of part of the memory array (4 or 8 Mbit) is performed). The data retention  
characteristics of each power-down mode are described in Table 18.  
By default, the power-down mode is “deep power-down”, which corresponds to the lowest  
power consumption.  
Table 6.  
Data retention characteristics  
Mode  
Data retention size  
Retention address  
Deep power-down  
(default)  
No  
N/A  
4 Mbit PAR  
8 Mit PAR  
4 Mbits  
8 Mbits  
00000h to 3FFFFh  
00000h to 7FFFFh  
16/64  
M69KB048BD, M69AB048BD  
Operation  
3.4  
Asynchronous page read mode  
The asynchronous page read mode gives greater performance, even than the traditional  
asynchronous random read mode. The page mode is not available for write operations.  
By default, the device is configured in asynchronous page read mode. L must be driven Low,  
V
during all asynchronous page read operations.  
IL,  
In asynchronous page read mode, a page of data is internally read. Each memory page  
consists of 8 words, and has the same set of values on A3-A20; only the sets of A0 to A2  
should differ. The first read operation within the page has the normal access time (t  
),  
AVQV  
subsequent reads within the same page have much shorter access times (t  
page changes then the normal, longer timings apply again.  
). If the  
AVQV2  
See Figure 14 and Table 12 for details of the asynchronous page read timing requirements.  
3.5  
Asynchronous write mode  
Asynchronous write operations occur when:  
■
■
■
■
Write Enable W is Low and  
Output Enable G is High and  
The two Chip Enable signals are asserted (E1 Low, and E2 High) and  
at least one of the two signals UB or LB is Low.  
The asynchronous write cycle begins t  
, t  
or t  
after the address becomes valid  
AVBL  
AVWL AVEL  
depending on which of the above signals is the last to go Low.  
Data inputs must be valid for t before the rising edge of W, or t  
before the rising  
DVEH  
DVWH  
edge of E1, or t  
before the rising edge of UB/LB whichever occurs first, and remain  
DVBH  
valid for t  
, t  
or t  
.
WHDZ EHDZ  
BHDZ  
The asynchronous write cycle is terminated by the first rising edge on W or E1 signals.  
See Table 13 and Figure 15 to Figure 20 for details of asynchronous write AC timing  
requirements.  
3.6  
Synchronous burst read and write modes  
Burst mode allows high-speed synchronous read and write operations.  
In synchronous burst modes the data is input or output to or from the memory array in bursts  
that are synchronized with the microcontroller or system clock.  
This mode uses K, L, and WAIT control signals (see Section 2: Signals description). In  
synchronous burst mode, the address is latched on the rising edge of L when E1 is Low.  
The minimum values of t  
, duration of L Low pulse and t  
, delay from L falling edge to  
LLLH  
LLKH  
the rising edge of the Clock K that starts the burst address counter, must be respected.  
The address becomes valid t or t after the falling edge of L or E1, whichever occurs  
AVLL  
AVEL  
last. The valid address must remain unchanged while L is Low.  
See Table 16 and Figure 4 for details on synchronous burst read characteristics and  
waveforms and Table 17 and Figure 5 for details on synchronous burst write characteristics  
and waveforms.  
17/64  
Operation  
M69KB048BD, M69AB048BD  
After power-up, a set CR sequence must be issued to put the device in synchronous burst  
mode:  
■
■
Mode bit, M, set ‘1’ puts the device in synchronous burst mode.  
Read latency bit, RL, defines the number of clock cycles between the address being  
latched and the first read data transferred. It can be set to 3, 4, 5, or 6 clock cycles. If  
the read latency has been configured to ‘n’, the write latency, that is the number of  
clock cycles between the address being latched and first write data transferred, is  
automatically set to ‘n-1’ (see Figure 7: Latency definition).  
■
Burst length bit, BL, is the number of words to be input or output during the  
synchronous burst read or write operation. It can be set to fixed length (8 words or 16  
words) or continuous. In synchronous burst mode, the internal burst address counter is  
incremented at each Clock K rising edge starting from the initial address being latched,  
until the end of boundary address is reached and then wraps as shown in Table 7.  
When the number of words defined by the BL bits has been input or output, the  
synchronous operation automatically ends. When the burst length is set to continuous,  
synchronous burst read or write is endless unless a rising edge on E1 occurs. During  
continuous burst read operations, an additional output delay may occur when a burst  
sequence crosses the row boundary. This is the case when the A0-A6 bits of the  
starting address are either ‘7Dh’, ‘7Eh’, or ‘7Fh’ as shown in Table 7: Burst length  
definition. In this case, the WAIT signal is asserted.  
3.7  
Synchronous burst read suspend  
Synchronous burst read operations can be suspended by driving the Output Enable input,  
G, to High.  
The first Clock K rising edge following G rising edge triggers the synchronous burst read  
suspend. The device internal address counter is suspended and data outputs become high  
impedance t  
after G rising edge. It is prohibited to suspend the first data output at the  
GHQZ  
beginning of a synchronous burst read.  
During synchronous burst read suspend, the WAIT output signal remains unchanged from  
the cycle where data were suspended. In this case, it does not indicate data status.  
Synchronous burst read operations can be resumed by driving G Low. Data outputs become  
valid and the device internal address counter is reactivated with a specific delay after G  
falling edge. The last data output being suspended as the result of G going High and the first  
data output after G returns to Low are read from the same memory address.  
3.8  
Synchronous burst read terminate  
Synchronous burst read operations can be terminated by driving E1 to High. If the burst  
length is set to continuous, synchronous burst read operations goes on endlessly unless a  
rising edge on E1 occurs. It is prohibited to terminate a synchronous burst read before the  
first data is output. To ensure the validity of the last data output, a minimum duration of E1  
Low pulse from the rising edge of the Clock K is required.  
18/64  
M69KB048BD, M69AB048BD  
Operation  
3.9  
Synchronous burst write suspend  
Synchronous burst write operations can be suspended by driving the Write Enable input, W,  
to High.  
The first Clock K rising edge following W rising edge triggers the synchronous burst write  
suspend. The device internal address counter is suspended and data inputs become high  
impedance t  
after W rising edge. It is prohibited to suspend the first data input at the  
WHQZ  
beginning of a synchronous burst write.  
Synchronous burst write operations can be resumed by setting W Low. Once W is driven  
Low, data inputs become valid after a specific delay, and internal address counter is  
reactivated.  
After W returns Low, write operation restart from the address at which the synchronous  
burst write suspend occurred.  
Synchronous burst write suspend is available only when the device is operating in Write  
Enable level control mode.  
3.10  
Synchronous burst write terminate  
Synchronous burst write operations can be terminated by driving E1 to High. If the burst  
length is set to continuous, synchronous burst write operations goes on endlessly unless a  
rising edge on E1 occurs. It is prohibited to terminate a synchronous burst write before the  
first data is latched. To ensure the validity of the last data write, a minimum duration of E1  
Low pulse from the rising edge of the Clock K is required.  
Table 7.  
Burst length definition  
Starting  
address  
(A0-A6)(1)  
8 words  
16 words  
Continuous  
00h  
01h  
02h  
03h  
...  
00-01-02-...-06-07  
01-02-03-...-07-00  
02-03-...-07-00-01  
03-...-07-00-01-02  
...  
00-01-02-...-0E-0F  
01-02-03-...-0F-00  
02-03-...-0F-00-01  
03-...-0F-00-01-02  
...  
00-01-02-03-04-...  
01-02-03-04-05-...  
02-03-04-05-06-...  
03-04-05-06-07-...  
...  
7Ch  
7Dh  
7Eh  
7Fh  
7C-...-7F-78-...-7B  
7D-7E-7F-78-...-7C  
7E-7F-78-79-...-7D  
7F-78-79-7A-...-7E  
7C-...-7F-70-...-7B  
7D-7E-7F-70-...-7C  
7E-7F-70-71-...-7D  
7F-70-71-72-...-7E  
7C-7D-7E-7F-80-81-...  
7D-7E-7F-WAIT-80-81-...  
7E-7F-WAIT-WAIT-80-81-...  
7F-WAIT-WAIT-WAIT-80-81  
1. Read address is in hexadecimal format.  
19/64  
Operation  
Figure 4.  
M69KB048BD, M69AB048BD  
Synchronous burst read  
RL (Read Latency) = 5  
K
Address  
Valid  
A0-A20  
Address Valid  
L
E1  
G
High  
W
Hi-Z  
Hi-Z  
Hi-Z  
WAIT  
Hi-Z  
D
D
OUTBL  
DQ0-DQ15  
OUT1  
AI09408b  
1. The above diagram is an example of synchronous burst read waveforms for a latency of 5 clock cycles.  
20/64  
M69KB048BD, M69AB048BD  
Operation  
Figure 5.  
Synchronous burst write  
RL = 5  
K
A0-A20  
VALID  
VALID  
L
E1  
High  
G
W
Hi-Z  
Hi-Z  
WAIT  
D
DQ0-DQ15  
D
D
INBL  
IN1  
IN2  
ai09409c  
1. The above diagram is an example of synchronous burst write waveforms for a latency of 5 clock cycles.  
Figure 6.  
K
Burst length definition  
Address  
Valid  
A0-A20  
L
E1  
G
Read Latency(CR RL bits)  
Hi Z  
Hi Z  
DQ0-DQ15  
D
OUT1  
D
D
OUTBL  
OUT2  
Burst Length (CR BL bits)  
Hi Z  
WAIT  
AI08940d  
21/64  
Operation  
Figure 7.  
M69KB048BD, M69AB048BD  
Latency definition  
K
0
1
2
3
4
5
A0-A20  
L
E1  
RL (Read Latency) = 3  
Hi Z  
Hi Z  
DQ0-DQ15  
(Out)  
D
D
D
D
OUT4  
OUT1  
OUT2  
OUT3  
D
D
D
D
D
IN5  
IN1  
IN2  
IN3  
IN4  
DQ0-DQ15  
(In)  
RL (Read Latency) = 4  
Hi Z  
Hi Z  
D
D
D
OUT3  
DQ0-DQ15  
(Out)  
OUT1  
OUT2  
D
D
D
DQ0-DQ15  
(In)  
D
IN1  
IN2  
IN3  
IN4  
RL (Read Latency) = 5  
Hi Z  
Hi Z  
DQ0-DQ15  
(Out)  
D
D
OUT1  
OUT2  
DQ0-DQ15  
(In)  
D
D
D
IN1  
IN2  
IN3  
RL (Read Latency) = 6  
Hi Z  
Hi Z  
DQ0-DQ15  
(Out)  
D
OUT1  
DQ0-DQ15  
(In)  
D
D
IN1  
IN2  
AI08941f  
22/64  
M69KB048BD, M69AB048BD  
Operation  
Figure 8.  
Write Enable control modes  
RL = 5  
2
K
6
1
3
4
5
0
A0-A20  
VALID  
L
E1  
W Level Control  
tWLKH  
W
tWLTH  
Hi-Z  
WAIT  
D
IN1  
DQ0-DQ15  
D
D
INBL  
IN2  
W Pulse Control  
W
tWLKH1  
tKHWH  
Hi-Z  
WAIT  
tWLTH  
D
IN1  
DQ0-DQ15  
D
IN2  
D
INBL  
ai09410d  
1. The above diagram is given as an example for a latency of 5 clock cycles.  
23/64  
Maximum ratings  
M69KB048BD, M69AB048BD  
4
Maximum ratings  
Stressing the device above the rating listed in Table 8: Absolute maximum ratings may  
cause permanent damage to the device. Exposure to absolute maximum rating conditions  
for extended periods may affect device reliability. These are stress ratings only and  
operation of the device at these or any other conditions above those indicated in the  
operating sections of this specification is not implied. Refer also to the STMicroelectronics  
SURE program and other relevant quality documents.  
Table 8.  
Symbol  
Absolute maximum ratings  
Parameter  
Min  
Max  
Unit  
IO  
TA  
Output current  
−50  
−30  
−55  
−0.5  
−0.5  
50  
85  
mA  
°C  
°C  
V
Ambient operating temperature  
Storage temperature  
Core supply voltage  
Input or output voltage  
TSTG  
VCC  
VIO  
125  
3.6  
3.6  
V
24/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
5
DC and AC parameters  
This section summarizes the operating measurement conditions, and the DC and AC  
characteristics of the device. The parameters in the DC and AC characteristics tables in this  
section are derived from tests performed under the measurement conditions summarized in  
Table 9: Operating and AC measurement conditions. Designers should check that the  
operating conditions in their circuit match the operating conditions when relying on the  
quoted parameters.  
Table 9.  
Operating and AC measurement conditions  
M69KB048BD, M69AB048BD  
Parameter  
Unit  
Min  
Max  
VCC supply voltage(1)  
−1.7  
−30  
1.95  
85  
V
°C  
pF  
Ω
Ambient operating temperature  
Load capacitance (CL)  
50  
50  
Output circuit resistance (R1)  
Input pulse voltages(1)  
0
VCC  
V
Input and output timing ref. voltages(1)  
Output transition timing ref. voltages(1)  
Junction temperature (TJ)  
VCC/ 2  
V
0.3VCC  
–30  
0.7VCC  
90  
V
°C  
1. All voltages are referenced to VSS  
.
Figure 9.  
AC measurement I/O waveform  
I/O Timing Reference Voltage  
V
CC  
V
/2  
CC  
0V  
Output Timing Reference Voltage  
V
CC  
0.7V  
0.3V  
CC  
CC  
0V  
AI04831  
25/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 10. AC measurement load circuit  
V
/2  
CC  
R
1
DEVICE  
UNDER  
TEST  
OUT  
C
L
C
includes JIG capacitance  
AI07222c  
L
Table 10. Capacitance  
Symbol  
Test  
condition  
Parameter(1)  
Min  
Max  
Unit  
CIN1  
CIN2  
CIO  
Address input capacitance  
Control input capacitance  
Data input/output capacitance  
VIN = 0 V  
VIN = 0 V  
VIO = 0 V  
5
5
8
pF  
pF  
pF  
1. TA = 25°C, f = 1 MHz  
Table 11. DC characteristics  
Symbol  
Parameter  
Test condition(1)  
Min  
Max  
Unit  
tAVAX  
minimum  
=
30  
mA  
VCC = 1.95 V, VIN = VIH or VIL,  
E1 = VIL and E2 = VIH,  
ICC  
VCC active current  
tAVAX = 1  
µs  
I
OUT = 0 mA  
3
mA  
mA  
V
CC = 1.95 V, VIN = VIH or VIL,  
ICCP  
VCC active current (page read)  
VCC active current (burst read)  
E1 = VIL and E2 = VIH,  
10  
IOUT = 0 mA, tAVAX2 = min.  
VCC = 1.95 V, VIN = VIH or VIL,  
E1 = VIL and E2 = VIH,  
BL = continuous, tK(2)=tKHKH min  
IOUT = 0 mA  
ICCB  
25  
mA  
26/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Table 11. DC characteristics (continued)  
Symbol  
Parameter  
Test condition(1)  
Min  
Max  
Unit  
VCC power down current in  
deep power-down mode  
(ICCPD)  
10  
µA  
VCC = 1.95 V, VIN = VIH or VIL,  
IPAR VCC power down current in 4  
Mb PAR mode (ICCP4)  
45  
55  
µA  
µA  
E2 ≤0.2 V  
VCC power down current in 8  
Mb PAR mode (ICCP8)  
VCC = 1.95 V,  
VIN (including K) = VIH or VIL,  
1.5  
mA  
µA  
µA  
E1= E2= VIH  
VCC = 1.95 V,  
VIN (including K) ≤0.2 V or  
VIN (including K)≥ VCC - 0.2 V  
ISB  
VCC standby current  
100  
E1= E2 ≥ VCC-0.2 V  
VCC = 1.95 V, tK=tKHKH min(2)  
IN ≤0.2 V or VIN ≥ VCC - 0.2 V  
RL = 6  
RL = 3,4,5  
500  
220  
V
E1=E2 ≥ VCC - 0.2 V  
ILI  
Input leakage current  
Output leakage current  
Input high voltage  
Input low voltage  
0V ≤VIN ≤VCC  
−1.0  
−1.0  
1.0  
1.0  
µA  
µA  
V
ILO  
0V ≤VOUT ≤VCC (output disabled)  
(3)(4)  
VIH  
VIL  
0.8VCC  
−0.3  
V
CC−0.2 V  
(3)(4)  
(3)  
0.2 VCC  
V
VOH  
Output high voltage  
Output low voltage  
VCC = 1.7 V, IOH = −0.5 mA  
1.4  
V
(3)  
VOL  
IOL = 1 mA  
0.4  
V
1. DC characteristics are measured after power-up.  
2. tKHKH is the clock period.  
3. All voltages are referenced to VSS  
.
4. During voltage transitions, input may overshoot to VCC + 1.0 V and undershoot to VSS −1.0 V for a period of up to 5 ns.  
27/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
)
Table 12. Asynchronous read AC characteristics (page mode)  
M69KB048BD, M69AB048BD  
Unit  
Symbol  
Alt.  
Parameter  
Min  
Max  
(1)(2)  
tAVAX  
70  
70  
1000  
1000  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC Read Cycle Time  
tELAX  
(3)  
tELQV  
tCE Chip Enable Low to Output Valid  
tOE Output Enable Low to Output Valid  
tAA Address Valid to Output Valid  
(3)  
tGLQV  
40  
(3)(4)  
tAVQV  
70  
(3)  
tBLQV  
tBA Upper/Lower Byte Enable Low to Output Valid  
tPAA Page Address Access Time  
30  
(3)(5)  
tAVQV2  
20  
tAVAX2, tAVEH  
tPRC Page Read Cycle Time  
20  
1000  
ns  
(1)(5)(6)  
(3)  
tAXQX  
Data hold from address change  
tOH Data hold from Chip Enable High  
Data hold from Chip Enable High  
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(3)  
tEHQX  
(3)  
tGHQX  
5
(7)  
tELQX  
tCLZ Chip Enable Low to Output Transition  
tOLZ Output Enable Low to Output Transition  
tBLZ Upper/Lower Byte Enable Low to Output Transition  
tCHZ Chip Enable High to Output Hi-Z  
tOHZ Output Enable High to Output Hi-Z  
tBHZ Upper/Lower Byte Enable High to Output Hi-Z  
tASC Address Valid to Chip Enable Low  
tASO Address Valid to Output Enable Low  
tAX Address Invalid Time  
5
(7)  
tGLQX  
10  
0
(7)  
tBLQX  
(7)  
tEHQZ  
12  
12  
12  
(7)  
tGHQZ  
(7)  
tBHQZ  
tAVEL  
tAVGL  
–5  
0
(4)(8)  
tAXAV  
10  
ns  
ns  
ns  
ns  
ns  
(9)  
tEHAX  
tCHAH Chip Enable High to Address Invalid  
tOHAH Output Enable High to Address Invalid  
tWHOL Write Enable High to Output Enable Low  
tCP Chip Enable High Pulse Width  
−5  
−5  
10  
5
tGHAX  
(10)  
tWHGL  
1000  
tEHEL  
1. Maximum value is applicable if E1 is kept Low without change of address input of A3 to A20.  
2. Address should not be changed within minimum read cycle time (tAVAX).  
3. See Figure 14.  
4. Applicable to A3 to A20 when E1 is kept Low.  
5. Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access.  
6. In case page read cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4 µs. In other words,  
page read cycle must be closed within 4µs.  
7. The output load capacitance is 5 pF without any other load.  
8. Applicable when at least two of address inputs are switched from previous state.  
9. Minimum read cycle time, tAVAX, and minimum page read cycle time, tAVAX2 must be satisfied.  
10. If tWHGL is shorter than the minimum value specified in Table 12, the address access time, tAVQV of the following read  
operations may become longer by tWHGL(min) −tWHGL  
.
28/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 11. Asynchronous read basic AC waveforms  
A0-A20  
ADDRESS VALID  
VALID  
tAVEL  
tAVEL  
tEHAX  
tELQV  
E1  
tEHEL  
tEHQZ  
tGLQV  
G
tBLQV  
tGHQZ  
tBHQZ  
LB, UB  
tBLQX  
tGLQX  
tEHQX  
tELQX  
DQ0-DQ15  
VALID DATA OUTPUT  
AI08944c  
1. E2 High, W High, L Low.  
Figure 12. G controlled asynchronous read basic AC waveforms  
A0-A20  
ADDRESS VALID  
VALID  
tAVEL  
tAVEL  
tELQV  
tEHAX  
E1  
tEHEL  
tGLQV  
tEHQZ  
tGHQZ  
tBHQZ  
G
tBLQV  
LB, UB  
tBLQX  
tGLQX  
tEHQX  
tELQX  
DQ0-DQ15  
VALID DATA OUTPUT  
AI08944c  
1. E2 High, W High, L Low.  
29/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 13. LB and UB controlled asynchronous read basic AC waveforms  
tAXAV  
tAVAX  
tAXAV  
A0-A20  
ADDRESS VALID  
tAVQV  
Low  
E1, G  
LB  
tBLQV  
tBLQV  
tBLQV  
UB  
tBHQZ  
tBHQX  
tBHQZ  
tBHQX  
tBLQX  
tBLQX  
VALID DATA  
OUTPUT  
VALID DATA  
OUTPUT  
DQ0-DQ7  
(Output)  
tBHQZ  
tBHQX  
tBLQX  
VALID DATA  
OUTPUT  
DQ8-DQ15  
(Output)  
AI11396  
1. E2 High, W High, L Low.  
Figure 14. E1 controlled, asynchronous page read AC waveforms  
tELEH  
A20-A3  
A2-A0  
ADDRESS VALID  
tAVAX2  
tAVAX2  
tAVAX  
tAVEH  
ADDRESS  
VALID  
ADDRESS  
VALID  
ADDRESS VALID  
ADDRESS VALID  
tAVQV2  
tAVQV2  
tAVEL  
tAVQV  
tELAX  
tAVQV2  
tEHAX  
L
E1  
tEHQZ  
tELQV  
G
LB, UB  
DQ0-DQ15  
tELQX  
tAXQX  
tAXQX  
tAXQX  
tEHQX  
AI08945d  
1. Write Enable (W) = High, E2 = High.  
30/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
M69KB048BD,  
Table 13. Asynchronous write mode AC characteristics  
M69AB048BD  
Symbol  
Alt.  
tWC  
tAS  
Parameter  
Unit  
Min  
Max  
(1)(2)  
tAVAX  
70  
70  
0
1000  
1000  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write Cycle Time  
tELAX  
(3)  
tAVBL  
Address Valid to LB, UB Low  
(3)  
tAVEL  
Address Valid to Chip Enable Low  
Address Valid to Write Enable Low  
Chip Enable Low to Chip Enable High  
Latch Enable Low Pulse width  
Latch Enable High Pulse width  
LB / UB Byte Mask Setup Time  
LB / UB Byte Mask Hold Time  
0
(3)  
tAVWL  
0
(3)  
tELEH  
tCW  
tVPL  
tVPH  
tBS  
45  
10  
10  
–5  
–5  
45  
45  
45  
45  
15  
0
(3)  
tLLLH  
(3)  
tLHLL  
(4)  
t
BHEL, tBHLL  
(5)  
tWHBL  
tBH  
(3)  
tWLBH  
Write Enable Low to LB, UB High  
Write Enable Low to Write Enable High  
LB, UB Low to Write Enable High  
LB, UB Low to LB, UB High  
tWP  
tWLWH  
(3)  
tBLWH  
tBW  
(3)  
tBLBH  
(6)  
tEHAX  
tWRC  
tWR  
tBR  
Chip Enable High to Address Transition  
Write Enable High to Address Transition  
LB, UB High to Address Transition  
Input Valid to Chip Enable High  
Input Valid to Write Enable High  
Input Valid to LB, UB High  
(6)  
tWHAX  
(6)  
tBHAX  
15  
15  
15  
15  
0
1000  
tDVEH  
tDVWH  
tDVBH  
tEHDZ  
tWHDZ  
tBHDZ  
tDS  
Chip Enable High to Input High-Z  
Write Enable High to Input High-Z  
LB, UB High to Input High-Z  
tDH  
0
0
(7)  
tGHEL  
tOHCL  
Output Enable High to Chip Enable Low  
–5  
31/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
M69KB048BD,  
Table 13. Asynchronous write mode AC characteristics (continued)  
M69AB048BD  
Symbol  
Alt.  
Parameter  
Unit  
Min  
Max  
(8)  
tGHAV  
tOES  
tBWO  
tCP  
Output Enable High to Address Valid  
LB, UB Low to LB, UB High for page Access  
Chip Enable High to Chip Enable Low  
Write Enable High Pulse Width  
0
30  
5
ns  
ns  
ns  
ns  
tBLBH2  
tEHEL  
tWHWL  
tWHP  
10  
1000  
1. Maximum value is applicable if E1 is kept Low without any address change. If needed by system operation, please contact  
your local ST representative for relaxation of the 1000 ns limitation.  
2. Minimum value must be equal to or greater than the sum of write pulse (tELEH, tWLBH or tBLBH) and write recovery time  
(tEHAX, tWHAX or tBHAX).  
3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last.  
4. Applicable only to LB and UB. LB and UB setup times are defined from the falling edge of Write Enable, W, or Chip Enable,  
E1, whichever occurs last.  
5. Applicable only to LB and UB. LB and UB hold times are defined from the rising edge of Write Enable, W, or Chip Enable,  
E1, whichever occurs first.  
6. Write recovery is defined from write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first.  
7. If G is Low after minimum tGLEH, the read cycle is initiated. In other words, G must be brought High within 5 ns after E1 is  
brought Low. Once the read cycle is initiated, new write pulse should be input after minimum read cycle time, tAVAX, is met.  
8. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or  
before new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time,  
tAVAX, is met.  
Figure 15. Asynchronous write AC waveforms  
tELAX  
A0-A20  
ADDRESS VALID  
tELEH  
ADDRESS VALID  
tEHAX  
tAVEL  
tAVEL  
E1  
tEHEL  
tWHWL  
tBHAX  
tWHAX  
tAVWL  
tAVBL  
tAVWL  
W
tWLWH  
tBLWH  
tAVBL  
LB, UB  
tGHEL  
G
tDVEH  
tDVWH  
tDVBH  
tEHDZ  
tWHDZ  
tBHDZ  
DQ0-DQ15  
VALID DATA INPUT  
ai08946c  
1. E2 = High.  
32/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 16. W controlled, asynchronous write AC waveforms  
tAVAX  
tAVAX  
A0-A20  
ADDRESS VALID  
ADDRESS VALID  
tWHAX  
tGHAX  
tWHAX  
tWHAX  
E1  
W
Low  
tAVWL  
tWLWH  
tAVWL  
tWLWH  
tWHAX  
tWHWL  
LB, UB  
G
tGHAV  
tDVWH  
tGHDZ  
tWHDZ  
tDVWH  
tWHDZ  
VALID DATA  
INPUT  
VALID DATA  
INPUT  
DQ0-DQ15  
AI08947c  
1. E2 = High.  
Figure 17. W, UB and LB controlled, asynchronous write AC waveforms 1  
tAVAX  
tAVAX  
A0-A20  
ADDRESS VALID  
ADDRESS VALID  
tAXAV  
E1  
W
Low  
tAVWL  
tWLBH  
tAVWL  
tWLBH  
tWHWL  
tWHBL  
LB  
tBHAX  
tBHAX  
tBHWL  
UB  
tDVBH  
tBHDZ  
VALID DATA  
INPUT  
DQ0-DQ7  
tDVBH  
tBHDZ  
VALID DATA  
INPUT  
DQ8-DQ15  
AI08948c  
1. E2 = High.  
33/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 18. W, UB and LB controlled, asynchronous write AC waveforms 2  
tAVAX  
tAVAX  
A0-A20  
ADDRESS VALID  
ADDRESS VALID  
E1  
W
Low  
tAVBL  
tBLWH  
tWHAX  
tBLWH  
tWHAX  
tWHBL  
tBHWL  
LB  
tAVBL  
tBHWL  
UB  
tDVWH  
tWHDZ  
VALID DATA  
INPUT  
DQ0-DQ7  
tDVWH  
tWHDZ  
VALID DATA  
INPUT  
DQ8-DQ15  
AI08949c  
1. E2 = High.  
Figure 19. W, UB and LB controlled, asynchronous write AC waveforms 3  
tAVAX  
tAVAX  
A0-A20  
E1  
ADDRESS VALID  
ADDRESS VALID  
Low  
tAVBL  
tBLBH  
tBHAX  
tBLBH  
tBHAX  
W
LB  
tAVBL  
tBHWL  
tWHBL  
tBHWL  
UB  
tDVBH  
tBHDZ  
VALID DATA  
INPUT  
DQ0-DQ7  
tBVWH  
tBHDZ  
VALID DATA  
INPUT  
DQ8-DQ15  
AI08950c  
1. E2 = High.  
34/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 20. W, UB and LB controlled, asynchronous write AC waveforms 4  
tAVAX  
tAVAX  
A0-A20  
E1  
ADDRESS VALID  
ADDRESS VALID  
Low  
W
tBHAX  
tBLBH  
tAVBL  
tAVBL  
tBLBH  
tBHAX  
tBHDZ  
LB  
tBLBH2  
tDVBH  
tAVBL  
tDVBH  
tBHDZ  
VALID DATA  
VALID DATA  
INPUT  
DQ0-DQ7  
UB  
INPUT  
tBHAX  
tBLBH2  
tBLBH  
tBLBH  
tAVBL  
tBHAX  
tDVBH  
tBHDZ tDVBH  
tBHDZ  
VALID DATA  
INPUT  
VALID DATA  
INPUT  
DQ8-DQ15  
AI08951b  
1. E2 = High.  
Figure 21. E1 controlled, asynchronous read followed by write AC waveforms  
tELAX  
tELAX(read)  
A0-A20  
WRITE ADDRESS  
READ ADDRESS  
tAVEL  
(read)  
tEHAX  
(read)  
tAVEL  
tEHAX  
tEHAX(read)  
E1  
W
tEHEL  
tELEH  
tEHEL  
tELQV  
UB, LB  
G
tGHEL  
tEHQZ  
tEHQX  
tELQX  
tDVEH  
tEHDZ  
tEHQX  
READ DATA  
OUTPUT  
WRITE DATA  
INPUT  
DQ0-DQ15  
ai08952b  
1. Write address is valid from either E1 or W of last falling edge.  
35/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 22. E1, W and G controlled, asynchronous read followed by write AC waveforms  
tELAX  
tELAX(read)  
A0-A20  
WRITE ADDRESS  
READ ADDRESS  
tAVEL  
(read)  
tEHAX  
(read)  
tAVEL  
tWHAX  
tEHAX(read)  
E1  
W
tEHEL  
tELEH  
tEHEL  
tELQV  
tWLWH  
UB, LB  
G
tGHEL  
tGHQV  
tEHQZ  
tEHQX  
tGLQX  
tWHDZ  
tDVWH  
tEHQX  
READ DATA  
OUTPUT  
WRITE DATA  
INPUT  
DQ0-DQ15  
ai08953b  
1. G can be hold Low during E1, W, G controlled Write operation.  
Figure 23. W and G controlled, asynchronous read followed by write AC waveforms  
tAVAX  
tAVAX(read)  
A0-A20  
WRITE ADDRESS  
READ ADDRESS  
tGHAX  
tAVQV  
tGHAX  
Low  
E1  
W
tWLWH  
tAVWL  
tWHAX  
tWHGL  
tGHAV  
UB, LB  
G
tAVGL  
tGLQV  
tGHQZ  
tGHQX  
tGLQX  
tWHDZ  
tGHQZ  
tGHQX  
tDVWH  
DATA  
OUT  
DATA  
IN  
DATA  
OUT  
DQ0-DQ15  
ai08954c  
1. E1 can be hold Low for W and G controlled operations. When E1 is hold Low, the data outputs are exclusively controlled by  
G.  
36/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 24. W, G and UB/LB controlled, asynchronous read followed by write AC waveforms  
tAVAX  
tAVAX(read)  
A0-A20  
WRITE ADDRESS  
READ ADDRESS  
tGHAX  
tGHAX  
Low  
tAVQV  
E1  
W
tWHGL  
tBHAX  
tAVBL  
tBLBH  
tBLQV  
UB, LB  
G
tGHAV  
tAVGL  
tBHQZ  
tBHQX  
tBHQZ  
tBHQX  
tBLQX  
tBHDZ  
tDVBH  
DATA  
OUT  
DATA  
IN  
DATA  
OUT  
DQ0-DQ15  
ai08955c  
1. E1 can be hold Low for W and G controlled operation. When E1 is hold Low, data outputs are exclusively controlled by G.  
37/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Table 14. Synchronous mode - Clock AC characteristics  
Symbol  
Alt  
Description  
Min  
Max  
Unit  
RL=6  
RL=5  
RL=4  
RL=3  
12  
15  
18  
30  
ns  
ns  
ns  
ns  
tKHKH  
tCK  
Clock period  
tKHKL  
tKLKH  
tCKH  
tCKL  
Clock High to Clock Low  
Clock Low to Clock High  
3.5  
ns  
ns  
Clock Rise Time  
Clock Fall Time  
(1)  
tF, tR  
tCKT  
1.5  
1. Clock rise and fall times are defined between VIH min. and VIL Max.  
Table 15. Synchronous mode - address latch AC characteristics  
Symbol  
Alt  
Description  
Address Valid to L Low  
Min  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(1)  
tAVLL  
tASVL  
tASCL  
tAHV  
tVPL  
−3  
−3  
0
(1)  
tAVEL  
Address Valid to Chip Enable Low  
L High to Address Transition  
L Low to L High  
tLHAX  
(2)  
tLLLH  
7
RL=5, 6  
3.5  
5
(3)  
tLLKH  
tVSCK  
L Low to Clock High  
RL=3, 4  
RL=5, 6  
RL=3, 4  
3.5  
5
Chip enable Low to Clock  
High  
(3)  
tELKH  
tCLCK  
L High Hold Time from Clock Rising Edge.  
tKHLL, KHEL  
t
tVHVL  
TBD(4)  
ns  
Chip Enable High Hold Time from Clock Rising  
Edge.  
(3)  
tKHLH  
tCKVH  
Larch Enable Low Hold Time from Clock  
2.5  
ns  
1. tAVEL is applicable if E1 is brought to Low after L is brought to Low with tLLEL time respected. Both tAVEL and tAVLL must be  
respected if tLLEL is not respected.  
2. tLLLH is defined from the falling edge of either E1 or L, whichever comes last. At least one valid Clock edge must occur  
when L is Low.  
3. Applicable to the first valid clock edge.  
4. TBD stands for To Be Defined.  
38/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Table 16. Synchronous burst read AC characteristics  
Symbol  
Alt  
Description  
Min  
Max  
Unit  
Burst Read Cycle Time  
t
ELEH, tLLLL  
tRCB  
8000  
ns  
Address Valid Low to Address Valid Low  
Clock Access Time  
RL=5, 6  
RL=3, 4  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(1)  
tKHQV  
tAC  
10  
(1)  
tKHQX  
tCKQX  
tCLTL  
tVLTL  
tCLZ  
Output Hold Time from Clock  
3
5
(1)  
tELTL  
Chip Enable Low to WAIT Low  
Latch Enable Low to WAIT Low  
Chip Enable Low to Output Transition  
Output Enable Low to WAIT Low  
Output Enable Low to Output Transition  
20  
20  
(1)  
tLLTL  
5
(2)  
tELQX  
5
(1)  
tGLTL  
tOLTL  
tOLZ  
tCKTV,  
0
20  
12  
(2)  
tGLQX  
10  
tKHTL  
tKHTH  
,
Clock high to WAIT High  
3
ns  
(1)  
tCKTX  
tGLKH  
tOLQ  
tBLQ  
tOHZ  
Output Enable Low to Clock High  
LB, UB High to Clock High  
30  
30  
ns  
ns  
ns  
(3)  
tBLKH  
tGHQZ  
tEHQZ  
tEHTZ  
Output Enable High to Output Hi-Z  
20  
20  
12  
,
Chip Enable High to Output Hi-Z  
Chip Enable High to WAIT Hi-Z  
tCHZ  
ns  
(1)  
tGHTZ  
tGHKH  
tKHGH  
tKHEH  
tKHBH  
tEHEL  
tOHTZ  
tOSCK  
tCKOH  
Output Enable High to WAIT Hi-Z  
Output Enable High to Clock High  
ns  
ns  
ns  
ns  
ns  
ns  
5
5
Output Enable Low Hold Time from Clock High  
tCKCLH Chip Enable Low Hold Time from Clock High  
5
tCKBH  
tCP  
LB, UB Low Hold Time from Clock High  
Chip Enable High to Chip Enable Low  
5
15  
Burst length = 8,  
16 words  
30  
70  
ns  
ns  
(4)  
tEHLL  
tTRB  
Burst Terminate Recovery Time  
Burst length =  
continuous  
1. See Figure 25.  
2. The output load capacitance is 5 pF without any other load.  
3. Once set, it must not change before the end of the burst operation.  
4. Defined from the rising edge of E1 to the falling edge of either L or E1, whichever occurs last.  
39/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 25. Clock input waveform  
K
tKLKH  
tR  
tF  
tKHKH  
tKHKL  
AI08956  
1. The Clock K input must be available and stable before the first read or write access to the memory following a set CR  
sequence. It is prohibited to change the clock frequency during a read or write access to the memory.  
2. tF, tR is defined between VIH min. and VIL max.  
Figure 26. Synchronous burst address latch waveforms  
Case 1  
Case 2  
K
Address  
Valid  
Address  
Valid  
A0-A20  
L
E1  
Low  
AI08957b  
1. Case 1 describes the address latch waveform when E1 is driven Low after L is driven Low.  
Case 2 describes the address latch waveform when L is driven Low after E1 is driven Low.  
2. tLLLH is defined from the falling edge of E1 or L , whichever occurs first.  
At least one valid clock edge must occur during L low.  
3. tLLKH and tELKL apply to the first valid clock edge during L Low.  
40/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 27. G controlled, synchronous read AC waveforms  
RL (Read Latency) = 4  
K
Address  
A0-A20  
Address Valid  
Valid  
tAVLL  
tLLKH  
tAVLL  
tLLKH  
tLHAX  
L
tLLLH  
tLLLH  
tAVEL  
tAVEL  
tEHEL  
tELEH  
E1  
G
tELKH  
High  
tELKH  
tKHLL  
tGLKH  
tKHGH  
tKHBH  
W
tBLKH  
LB/UB  
tGHQZ  
tGLTL  
tKHTH  
tKHTL  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
WAIT  
tKHQV  
tKHQV  
tKHQV  
Q
1
Q
DQ0-DQ15  
BL  
tGLQX  
tKHQX  
tKHQX  
AI08958e  
1. The above diagram is an example of synchronous burst read waveforms for a latency of 4 clock cycles, and a burst length  
of 8 or 16 words. Chip Enable E2 is held High, VIH  
.
41/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 28. E1 controlled, synchronous read AC waveforms  
RL (Read Latency) = 4  
K
Address  
A0-A20  
Address Valid  
Valid  
tAVLL  
tLLKH  
tAVLL  
tLLKH  
tLHAX  
tLHAX  
L
tLLLH  
tLLLH  
tKHEH  
tAVEL  
tAVEL  
tELEH  
tEHEL  
E1  
G
tELKH  
tKHLL  
tELKH  
High  
W
tKHBH  
LB/UB  
tEHQZ  
tKHTH  
tKHTL  
tELTL  
Hi-Z  
Hi-Z  
WAIT  
tKHQV  
tKHQV  
tKHQX  
tKHQV  
tELQX  
Q
Q
BL  
DQ0-DQ15  
1
tELQX, tELTL  
tKHQX  
AI08959d  
1. The above diagram is an example of synchronous burst read waveforms for a latency of 4 clock cycles and a burst length  
of 8 or 16 words. Chip Enable E2 is held High, VIH  
42/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 29. L controlled, synchronous read AC waveforms  
RL = 4  
K
tLLKH  
A0-A20  
VALID  
VALID  
tAVLL  
tLHAX  
tAVLL  
tLHAX  
tLLKH  
tLLLL  
L
tLLLH  
tKHLL  
tLLLH  
Low  
E1  
G
Low  
High  
W
Low  
LB,UB  
tLLTL  
tKHTZ  
tLLTL  
WAIT  
tKHQV  
tKHQX  
tKHQV  
tKHQX  
tKHQV  
Q
Q
DQ0-DQ15  
1
BL  
ai08493d  
1. The above diagram is an example of synchronous burst read waveforms for a latency of 4 clock cycles.  
43/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 30. Synchronous burst read suspend and resume AC waveforms  
RL = 4  
K
tLLKH  
tELKH  
A0-A20  
VALID  
tLHAX  
tAVEL  
tAVLL  
L
tLLLH  
E1  
tKHGH  
tKHGL  
G
tGHKH  
tGLKH  
High  
W
LB,UB  
WAIT  
tELQVtKHTH  
tELTL  
tKHQV  
tGHQZ  
tGLQX  
tKHQV  
tKHQV  
tKHQV  
tKHQX  
tELQV  
tKHQX  
DQ0-DQ15  
Q
Q
Q
3
1
2
tKHQX  
ai08494c  
1. The above diagram is an example of synchronous burst read suspend and resume waveforms for a latency of 4 clock  
cycles.  
44/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 31. Synchronous burst read terminate AC waveforms  
K
A0-A20  
VALID  
tLHAX  
tAVLL  
tAVEL  
tKHEL  
L
tLLKH  
tELKH  
tKHEH  
tEHLL  
tLLLH  
E1  
tEHKH  
tEHEL  
G
High  
W
tKHBH  
LB,UB  
WAIT  
tEHTZ  
tELTL  
tLLTL  
tKHTH  
tKHQV  
tELQX  
tLLQX  
tKHQZ  
tKHQX  
Q
Q
2
DQ0-DQ15  
1
tKHQX  
ai09206b  
45/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Table 17. Synchronous burst write AC characteristics  
Symbol  
Alt  
Description  
Min  
Max  
Unit  
tELEH  
tLLLL  
tLLEH  
tWCB  
Burst Write Cycle Time  
8
µs  
Input Valid to Clock High  
Clock High to Input Valid  
tDVKH  
tDSCK  
7
ns  
tKHDZ, KHDX  
t
tDHCK  
tWLD  
Clock high to Input Transition or Input High Z  
Write Enable Low to First Input Valid  
3
ns  
ns  
tWLDV  
30  
LB, UB Low to Chip Enable Low  
LB, UB Low to Address Valid Low  
LB, UB Low to Write Enable Low  
tBLEL, tBLLL  
tBLWL  
,
tBS  
−5  
ns  
(1)  
t
WLKH1, tWHKH  
tWSCK  
tCKWH  
Write Enable Setup Time to Clock High  
5
5
ns  
ns  
Write Enable Hold Time (Low, High) from Clock  
High  
tKHWL, tKHWH  
tKHEH  
tEHKH  
tKHBH  
tCKCLH  
tCHCK  
tCKBH  
tWRB  
Chip Enable Low Hold Time from Clock High  
Chip Enable High to Clock High  
LB, UB Low Hold Time from Clock High  
Burst Write Recovery Time  
5
5
ns  
ns  
ns  
ns  
5
(2)  
tKHEL  
30  
Burst length = 8,  
30  
70  
ns  
ns  
16 words  
Burst Terminate Recovery Time  
Burst length =  
continuous  
Chip Enable High to Chip Enable Low  
Write Enable Low to WAIT High  
(3)  
tEHLL  
tTRB  
tEHEL  
tWLTH  
tWHTZ  
tEHTZ  
tELTH  
tCP  
15  
0
ns  
ns  
ns  
ns  
ns  
tWLTH  
tWHTZ  
tCHTZ  
tCLTH  
20  
20  
12  
15  
Write Enable High to WAIT High-Z  
Chip Enable High to WAIT High-Z  
Chip Enable E1 Low to WAIT High  
5
1. Defined from the valid input edge to the falling edge of either L, E1 or W , whichever occurs last. Once set, it must not  
change before the end of the burst operation.  
2. Defined from the rising edge of the Clock K where the last data inputs have been latched at the end of the burst write  
operation to the falling edge of either L or E1 , whichever occurs last for the next access.  
3. Defined from the rising edge of E1 to the falling edge of either L or E1 , whichever occurs last for the next access.  
46/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 32. W Level control mode, synchronous burst write AC waveforms  
RL = 4  
K
tLLKH  
tLLKH  
VALID  
A0-A20  
VALID  
tAVLL  
tLHAX  
tAVLL  
tLHAX  
tELEH  
L
tLLLH  
tLLLH  
tELKH  
tKHLL, tKHEL  
tAVEL  
tAVEL  
E1  
G
tELKH  
tEHEL  
High  
tWLKH  
tKHWH  
W
tBLWL  
tBLWL  
tKHBH  
LB,UB  
tWLTH  
tWHTZ  
Hi-Z  
Hi-Z  
WAIT  
tDVKH  
tKHDX  
tDVKH  
tDVKH  
D
DQ0-DQ15  
D
D
BL  
1
2
tKHDZ  
ai08960e  
1. The above diagram is an example of synchronous burst Write waveforms for a Latency of 4 clock cycles.  
47/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 33. W pulse control mode, synchronous burst write AC waveforms  
RL = 4  
K
tLLKH  
tLLKH  
VALID  
A0-A20  
VALID  
tAVLL  
tLHAX  
tAVLL  
tLHAX  
tELEH  
L
tLLLH  
tLLLH  
tELKH  
tKHLL, tKHEL  
tAVEL  
tAVEL  
E1  
G
tEHEL  
tELKH  
High  
tWLKH1  
tWLKH1  
tKHWH  
tKHWH  
tWLTH  
W
tKHBH  
tBLWL  
tBLWL  
LB,UB  
tWLTH  
Hi-Z  
tEHTZ  
WAIT  
tDVKH  
tDVKH  
tDVKH  
D
DQ0-DQ15  
D
D
BL  
1
2
tKHDX  
tKHDZ  
ai09413d  
1. The above diagram is an example of synchronous burst write waveforms for a latency of 4 clock cycles.  
48/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 34. L controlled, synchronous write AC waveforms  
RL = 4  
K
tLLKH  
tLLKH  
VALID  
A0-A20  
VALID  
tAVLL  
tLHAX  
tAVLL  
tLHAX  
tLLLL  
L
tLLLH  
tLLLH  
tKHLL, tKHEL  
E1  
tEHEL  
tKHEH  
High  
G
W
tBLEL  
tBLEL  
tKHBH  
LB,UB  
WAIT  
Hi-Z  
tDVKH  
tDVKH  
tDVKH  
D
DQ0-DQ15  
D
D
BL  
1
2
tKHDX  
tKHDZ  
ai08962c  
1. The above diagram is an example of synchronous burst write waveforms for a latency of 4 clock cycles.  
49/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 35. Synchronous burst write suspend and resume AC waveforms  
RL = 4  
K
tLLKH  
tELKH  
A0-A20  
VALID  
tLHAX  
tAVEL  
tAVLL  
L
tLLLH  
E1  
High  
G
tKHWH  
tKHWL  
W
tBLEL  
tBLLL  
tWHKH  
tWLKH  
LB,UB  
WAIT  
Hi-Z  
tDVKH  
tKHDX  
tDVKH  
tDVKH  
tDVKH  
tKHDZ  
D
D
D
D
4
DQ0-DQ15  
1
2
3
tKHDX  
tKHDX  
ai09205c  
1. The above diagram is an example of synchronous burst write suspend and resume waveforms for a latency of 4 clock  
cycles.  
50/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 36. Synchronous burst write terminate AC waveforms  
K
A0-A20  
VALID  
tLHAX  
tAVLL  
tAVEL  
tKHLL  
L
tLLKH  
tELKH  
tKHEH  
tEHLL  
tLLLH  
E1  
tEHKH  
tEHEL  
High  
G
W
tKHBH  
tBLEL  
LB,UB  
WAIT  
tKHDX  
tDVKH  
DQ0-DQ15  
tKHDZ  
tDVKH  
tKHDX  
tDVKH  
D
1
D
D
2
1
ai08499b  
51/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 37. E1 controlled synchronous burst read followed by write AC waveforms  
RL (Read Latency) = 4  
K
tLLEH  
Address  
A0-A20  
Valid  
tAVLL  
tLHAX  
tLLKH  
tKHEH  
L
tKHLL  
tAVEL  
tLLLH  
tKHLH  
tKHEH  
E1  
G
tEHEL  
tELKH  
W
tKHBH  
tKHBH  
tBHEL  
LB/UB  
tELTH  
tEHTZ  
tEHQZ  
Hi-Z  
tDVKH  
tDVKH  
WAIT  
tDVKH  
tKHDX  
tKHDX  
tKHQV  
tDVKH  
Q
Q
D
D
D
D
BL  
DQ0-DQ15  
tKHQX  
BL-1  
BL  
1
2
3
tKHQX  
tKHDX  
tKHDZ  
AI11397  
1. The above diagram assumes that E2 is high, VIH, the valid clock edge is the rising edge and the burst length is of 8 or 16  
words.  
52/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 38. L controlled synchronous burst read followed by write AC waveforms  
RL (Read Latency) = 4  
K
Address  
A0-A20  
Valid  
tAVLL  
tLHAX  
tLLKH  
L
tKHLL  
tLLLH  
tKHLH  
Low  
E1  
G
tKHGH  
tWLDV  
tBHWL  
tKHWH  
tKHBH  
W
tKHBH  
LB/UB  
tWLTH  
tGHTZ  
tGHQZ  
Hi-Z  
tDVKH  
tDVKH  
WAIT  
tDVKH  
tKHDX  
tKHDX  
tKHQV  
tDVKH  
Q
Q
D
D
D
D
BL  
DQ0-DQ15  
tKHQX  
BL-1  
BL  
1
2
3
tKHQX  
tKHDX  
tKHDZ  
AI11398  
1. The above diagram assumes that E2 is high, VIH, the valid clock edge is the rising edge and the burst length is of 8 or 16  
words.  
53/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 39. E1 controlled synchronous burst write followed by read AC waveforms  
RL (Read Latency) = 4  
K
Address  
Valid  
A0-A20  
tAVLL  
tAVEL  
tLHAX  
tLLKH  
L
tLLLH  
tKHLH  
tKHEH  
E1  
G
tEHEL  
tKHEL  
tELKH  
W
tKHBH  
LB/UB  
tEHTZ  
tELTL  
tKHTH  
Hi-Z  
WAIT  
tKHQV  
tELQX  
tKHQV  
tKHDV  
D
D
Q
Q
2
DQ0-DQ15  
tKHDX  
BL-1  
BL  
1
tKHQX  
tKHQX  
tKHDX  
AI11399  
1. The above diagram assumes that E2 is high, VIH, the valid clock edge is the rising edge and the burst length is of 8 or 16  
words.  
54/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 40. L controlled synchronous burst write followed by read AC waveforms  
RL (Read Latency) = 4  
K
Address  
Valid  
A0-A20  
tAVLL  
tLHAX  
tLLKH  
L
tLLLH  
tKHLH  
Low  
E1  
G
tGLKH  
tKHWH  
W
tBLKH  
tKHBH  
LB/UB  
tWHTZ  
tGLTL  
tKHTH  
Hi-Z  
WAIT  
tKHQV  
tGLQX  
tKHQV  
tKHDV  
D
D
Q
Q
2
DQ0-DQ15  
tKHDX  
BL-1  
BL  
1
tKHQX  
tKHQX  
tKHDX  
AI11500  
1. The above diagram assumes that E2 is high, VIH, the valid clock edge is the rising edge and the burst length is of 8 or 16  
words.  
55/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Table 18. Power-down and power-up AC characteristics  
M69KB048BD,  
Unit  
M69AB048BD  
Symbol  
Alt.  
Parameter  
Min  
Max  
tCLEL  
tCSP  
E2 Low Setup Time for Power Down Entry  
E2 Low Hold Time after Power Down Entry  
20  
70  
ns  
ns  
(1)  
tELCH  
tC2LP  
E2 Low Hold Time for Reset to Asynchronous  
Mode  
tELCH2  
tC2LPR  
70  
300  
70  
ns  
µs  
ns  
E1 High Hold Time following E2 High after Power-  
Up or power-down Exit (Deep power-down Mode  
only) or E2 High to E1 Low  
tEHEL, CHCL  
t
tCHH  
(2)  
tCHEL  
E1 High Hold Time following E2 High after power-  
down Exit (not in Deep power-down Mode)  
(3)  
tCHCL2  
tCHHP  
E1 High Setup Time following E2 High after  
power-down Exit  
(2)  
tEHCH  
tCHS  
0
ns  
µs  
tVHCH  
tC2LH  
E2 Low Hold Time after Power-up  
50  
1. Applicable when RP=0 (reset to page mode).  
2. Applicable also to power-up.  
3. Applicable when 4 Mbit and 8 Mbit partial mode is programmed.  
Table 19. Standby AC characteristics  
M69KB048BD,  
M69AB048BD  
Unit  
Symbol  
Alt.  
Parameter  
Min  
Max  
tEHGL  
tCHOX  
tCHWX  
tτ  
E1 High to G Low for standby mode  
E1 High to W Low for standby mode  
Input Transition Time  
10  
10  
1
ns  
ns  
ns  
(1)  
tEHWL  
tτ (2)(3)  
25  
1. Data might be written into any address location if tEHWL minimum value is not respected.  
2. Except for Clock input transition time.  
3. The input transition in AC conditions is 1 ns/V (see Table 9: Operating and AC measurement conditions). If it is lower than  
1ns/V, it may violate AC specification of some timing parameters.  
Figure 41. Power-up AC waveforms - 1  
E1  
tEHCH  
tVHCH  
tCHEL  
E2  
V
CCmin  
V
CC  
AI10028  
1. tE2HE1L is defined from VCC reaching VCC min to the falling edge of E1.  
56/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 42. Power-up AC waveforms - 2  
E1  
tEHEL, tCHCL  
E2  
V
CCmin  
V
CC  
AI08963b  
1. tEHEV is defined from VCC reaching VCC min. to E1, E2 falling edge.  
Figure 43. power-down Mode AC waveforms  
E1  
E2  
tEHCH  
tCHCL  
(tCHCL2)  
tCLEL  
tELCH,  
tELCH2  
D0-D15  
Hi-Z  
Power-Down Power-Down Mode Power-Down  
Entry Exit  
AI08964b  
1. Power-down can also be used as a reset if the power-up timing described above (see Figure 42) was not respected and if  
a power-down operation has not been performed before this reset.  
Figure 44. Standby mode entry AC waveforms, after read  
E1  
tEHGL  
tEHWL  
G
W
Read Active  
Standby  
Write Active  
Standby  
AI08965  
1. Both tEHGL and tEHWL define the minimum time to enter standby mode.  
If one of the two timing is not respected, the device enters standby mode tAVAX min after the rising edge of E1.  
57/64  
DC and AC parameters  
M69KB048BD, M69AB048BD  
Figure 45. Set Configuration Register sequence (asynchronous mode) AC waveforms  
tAVAX  
tAVAX  
tAVAX  
tAVAX  
tAVAX  
tAVAX  
CR(2)  
ADD(1)  
ADD(1)  
ADD(1)  
ADD(1)  
ADD(1)  
A0-A20  
E1  
tEHEL  
tEHEL  
tEHEL  
tEHEL  
tEHEL  
tEHEL  
G
W
UB, LB  
DQ0-DQ15  
RDa  
RDa  
RDa  
X
X
RDb  
Cycle 2: Write Cycle 3: Write Cycle 4: Write Cycle 5: Write Cycle 6: Read  
Cycle 1: Read  
ai09411  
1. All address inputs, ADD, must be High from cycle 1 to cycle 5.  
2. CR is the Configuration Register settings. It must be compliant with the format specified in Table 5: Configuration Register  
definition otherwise the data programmed during the set Configuration Register sequence may be incorrect.  
3. tEHEL or tAVAX after the end of Cycle 6, the set Configuration Register sequence is completed and the device returns to  
normal operation. tEHEL and tAVAX are also applicable in synchronous mode.  
58/64  
M69KB048BD, M69AB048BD  
DC and AC parameters  
Figure 46. Set Configuration Register sequence (synchronous mode) AC waveforms  
1. All address inputs, ADD, must be High from cycle 1 to cycle 5.  
2. CR is the Configuration Register settings. It must be compliant with the format specified in Table 5: Configuration Register  
definition otherwise the data programmed during the Set Configuration Register sequence may be incorrect.  
3. tEHLL after the end of Cycle 6, the Set Configuration Register sequence is completed and the device returns to normal  
operation.  
59/64  
Package mechanical  
M69KB048BD, M69AB048BD  
6
Package mechanical  
®
To meet environmental requirements, ST offers the M69AB048BD in a FBGA71 ECOPACK  
package. ECOPACK packages have a lead-free second level interconnect. The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC standard JESD97. The maximum ratings related to soldering  
conditions are also marked on the inner box label. ECOPACK is an ST trademark, and  
specifications are available at: www.st.com.  
Figure 47. FBGA71 7 x 11 mm - 8 x 12 active ball array, 0.8 mm pitch, package outline  
(bottom view),  
D
D1  
SD  
FD  
e
ddd  
SE  
E
E1  
BALL "A1"  
FE  
e
b
A
A2  
A1  
BGA-Z58  
1. Drawing is not to scale.  
60/64  
M69KB048BD, M69AB048BD  
Package mechanical  
Table 20. FBGA71 7 x 11 mm - 8 x 12 active ball array, 0.8 mm pitch, package mechanical data  
Millimeters  
Min  
Inches  
Min  
Symbol  
Typ  
Max  
Typ  
Max  
A
A1  
A2  
b
1.200  
0.0472  
0.250  
0.0098  
0.900  
0.450  
7.100  
0.0354  
0.0177  
0.2795  
0.350  
6.900  
0.0138  
0.2717  
D
7.000  
5.600  
0.2756  
0.2205  
D1  
ddd  
E
0.100  
0.0039  
0.4370  
11.000  
8.800  
0.800  
0.700  
1.100  
0.400  
0.400  
10.900  
–
11.100  
0.4331  
0.3465  
0.0315  
0.0276  
0.0433  
0.0157  
0.0157  
0.4291  
–
E1  
e
–
–
FD  
FE  
SD  
SE  
61/64  
Part numbering  
M69KB048BD, M69AB048BD  
7
Part numbering  
Table 21. Ordering information scheme  
Example:  
M69AB048  
B
D
70 ZA 8 T  
Device type  
M69 = 1T/1C memory cell architecture  
Mode  
A = packaged device  
K = wafer form  
Operating voltage  
B = VCC = 1.7 to 1.95 V, burst, address/data bus standard x16  
Array Organization  
048 = 32 Mbit (2 M x16)  
Option 1  
B = 2 Chip Enable; no write and standby from UB and LB  
Option 2  
D = D die  
Speed class  
70 = 70 ns  
Package  
ZA = FBGA71, 0.8 mm pitch  
W = unsawn wafer  
Operative temperature  
8 = –30 to 85 °C  
Shipping  
T = tape and reel packing  
F = Leadfree and RoHS package, tape and reel packing  
For a list of available options (speed, package, etc.) or for further information on any aspect  
of this device, please contact your nearest STMicroelectronics sales office.  
62/64  
M69KB048BD, M69AB048BD  
Revision history  
8
Revision history  
Table 22. Document revision history  
Date  
Revision  
Changes  
15-Jan-2007  
1
Initial release.  
Changed the parameter tEHEL from 15 ns to 5 ns in Table 12:  
Asynchronous read AC characteristics (page mode), and from 10 ns  
to 5 ns in Table 13: Asynchronous write mode AC characteristics.  
5-Dec-2007  
2
63/64  
M69KB048BD, M69AB048BD  
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64/64  

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