M69KB096AB [STMICROELECTRONICS]
64 Mbit (4Mb x 16), 104MHz Clock Rate, 1.8V Supply, Bare Die, Burst PSRAM; 64兆位（4MB ×16 ） ， 104MHz的时钟速率， 1.8V电源，裸模，突发PSRAM
| 型号： | M69KB096AB |
| 厂家： | 
ST |
| 描述： | 64 Mbit (4Mb x 16), 104MHz Clock Rate, 1.8V Supply, Bare Die, Burst PSRAM |
| 文件： | 总73页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M69KB096AB
64 Mbit (4 Mb x16), 104MHz Clock Rate,
1.8V Supply, Bare Die, Burst PSRAM
PRELIMINARY DATA
Features summary
■ Supply Voltage
– VCC = 1.7 to 1.95V core supply voltage
– VCCQ = 1.7 to 1.95V for I/O buffers
■ User-selectable Operating Modes
– Asynchronous Modes: Random Read, and
Write, Page Read
– Synchronous Modes: NOR-Flash, Full
Synchronous (Burst Read and Write)
■ Asynchronous Random Read
– Access Time: 70ns
■ Asynchronous Page Read
– Page Size: 4, 8 or 16 Words
– Subsequent Read Within Page: 20ns
Wafer
■ Burst Read
– Fixed Length (4, 8, 16 or 32 Words) or
Continuous
– Maximum Clock Frequency: 104MHz
– Output delay: 7ns at 104MHz
■ Low Power Consumption
– Active Current: < 25mA
– Standby Current: 140µA
– Deep Power-Down Current: < 10µA
■ Low Power Features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– Automatic Temperature-compensated Self-
Refresh
■ Operating Temperature
– –30°C to +85°C
The M69KB096AB is only available as part of a multi-chip package Product.
Rev 1
1/73
November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
M69KB096AB
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ8-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Upper Byte Enable (UB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Lower Byte Enable (LB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10 Configuration Register Enable (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13
2.14
2.15
2.16
V
V
V
V
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CCQ
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SS
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SSQ
3
4
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Automatic Temperature Compensated Self Refresh . . . . . . . . . . . . . . . . . . . 14
5
Standard Asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
5.3
Asynchronous Read and Write modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Page Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Configuration Registers Asynchronous Read and Write . . . . . . . . . . . . . . . . 16
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M69KB096AB
6
Synchronous Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
6.2
6.3
NOR-Flash Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Full Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Synchronous Burst Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.2 Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3.3 Row Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4
6.5
6.6
Synchronous Burst Read Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Synchronous Burst Write Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Synchronous Burst Read and Write Suspend . . . . . . . . . . . . . . . . . . . . . . . 21
7
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1
Programming and Reading Registers using the CR Controlled Method . . . . 26
7.1.1 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1.2 Program Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2
7.3
Programming and Reading the Registers using the Software Method . . . . . 27
Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.1 Operating Mode Bit (BCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.2 Latency Type (BCR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.3 Latency Counter Bits (BCR13-BCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.4 WAIT Polarity Bit (BCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.5 WAIT Configuration Bit (BCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.6 Driver Strength Bits (BCR5-BCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.7 Burst Wrap Bit (BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3.8 Burst Length Bits (BCR2-BCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4
7.5
Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4.1 Page Mode Operation Bit (RCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4.2 Deep Power-Down Bit (RCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4.3 Partial Array Refresh Bits (RCR2-RCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Wafer and die specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9
10
3/73
M69KB096AB
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11
12
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M69KB096AB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standard Asynchronous Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Frequency versus Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Asynchronous Write Operations (NOR-Flash Synchronous Mode) . . . . . . . . . . . . . . . . . . 22
Synchronous Read Operations (NOR-Flash Synchronous Mode) . . . . . . . . . . . . . . . . . . . 22
Full Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bus Configuration Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Refresh Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Device ID Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Asynchronous Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Asynchronous Write AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Clock Related AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Synchronous Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power-Up and Deep Power-Down AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Bond Pad Location and Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
5/73
M69KB096AB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Latency Configuration (Variable Latency Mode, No Refresh Collision) . . . . . . . . . . . . . . . 24
Latency Configuration (Fixed Latency Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Switching from Asynchronous to Synchronous Write Operation . . . . . . . . . . . . . . . . . . . . 25
Refresh Collision during Synchronous Burst Read in Variable Latency Mode . . . . . . . . . . 25
Set Configuration Register (Software Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Configuration Register (Software Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
WAIT Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. WAIT Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. AC Input Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 14. Asynchronous Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. Latch Enable Controlled, Asynchronous Random Read AC Waveforms . . . . . . . . . . . . . 43
Figure 16. Asynchronous Page Read AC Waveforms (4 Words) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17. CR Controlled Configuration Register Read Followed by Read, Asynchronous Mode . . . 45
Figure 18. Chip Enable Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . 47
Figure 19. Upper/Lower Byte Enable Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . 48
Figure 20. Write Enable Controlled, Asynchronous Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . 49
Figure 21. L Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22. CR Controlled Configuration Register Program, Asynchronous Mode. . . . . . . . . . . . . . . . 51
Figure 23. Clock input AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 24. 4-Word Synchronous Burst Read AC Waveforms (Variable Latency Mode) . . . . . . . . . . . 54
Figure 25. Synchronous Burst Read Suspend and Resume AC Waveforms . . . . . . . . . . . . . . . . . . . 55
Figure 26. Burst Read Showing End-of-Row Condition AC Waveforms (No Wrap) . . . . . . . . . . . . . . 56
Figure 27. Burst Read Interrupted by Burst Read or Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . 57
Figure 28. CR Controlled Configuration Register Read Followed by Read, Synchronous Mode . . . . 58
Figure 29. 4-Word Synchronous Burst Write AC Waveforms (Variable Latency Mode) . . . . . . . . . . . 60
Figure 30. Burst Write Showing End-of-Row Condition AC Waveforms (No Wrap) . . . . . . . . . . . . . . 61
Figure 31. Synchronous Burst Write Followed by Read AC Waveforms (4 Words) . . . . . . . . . . . . . . 62
Figure 32. Burst Write Interrupted by Burst Write or Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 63
Figure 33. CR Controlled Configuration Register Program, Synchronous Mode. . . . . . . . . . . . . . . . . 64
Figure 34. Power-Up AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 35. Deep Power-Down Entry and Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 36. Die Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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M69KB096AB
1 Summary description
1
Summary description
The M69KB096AB is a 64 Mbit (67,108,864 bit) PSRAM, organized as 4,194,304 Words by 16
bits. It uses a high-speed CMOS DRAM technology implemented using a one transistor-per-cell
topology that achieves bigger array sizes. It provides a high-density solution for low-power
handheld applications.
The M69KB096AB is supplied by a 1.7 to 1.95V supply voltage range.
The PSRAM interface supports various operating modes: Asynchronous Random Read and
Write, Asynchronous Page Read and Synchronous mode that increases read/write speed.
In Asynchronous Random Read mode, the M69KB096AB is compatible with low power
SRAMs. In Asynchronous Page mode the device has much shorter access times within the
page that make it is compatible with the industry standard PSRAMs.
Two types of Synchronous modes are available:
■
Flash-NOR: the device operates in Synchronous mode for read operations and
Asynchronous mode for write operations.
■
Full Synchronous: the device supports Synchronous transfers for both read and write
operations.
The M69KB096AB features three configuration registers:
■
Two user-programmable registers used to define the device operation: the Bus
Configuration Register (BCR) and the Refresh Configuration Register (RCR).
■
A read-only Device ID Register (DIDR) containing device identification.
The Bus Configuration Register (BCR) indicates how the device interacts with the system
memory bus. The Refresh Configuration Register (RCR) is used to control how the memory
array refresh is performed. At Power-Up, these registers are automatically loaded with default
settings and can be updated any time during normal operation.
PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh
mechanism that requires no additional support from the system memory microcontroller.
To minimize the value of the Standby current during self-refresh operations, the M69KB096AB
includes three system-accessible mechanisms configured via the Refresh Configuration
Register (RCR):
■
■
■
Partial Array Self Refresh (PASR) performs a limited refresh of the part of the PSRAM
array that contains essential data.
Deep Power-Down (DPD) mode completely halts the refresh operation. It is used when no
essential data is being held in the device.
Automatic Temperature Compensated Self Refresh (TCSR) adjusts the refresh rate
according to the operating temperature.
7/73
1 Summary description
M69KB096AB
Figure 1. Logic Diagram
V
V
CCQ
CC
22
16
A0-A21
DQ0-DQ15
WAIT
W
E
CR
G
M69KB096AB
UB
LB
K
L
V
V
SSQ
SS
AI11565
Table 1.
Signal Names
Address Inputs
A0-A21
DQ0-DQ15
Data Inputs/Outputs
Chip Enable Input
E
CR
G
Configuration Register Enable Input
Output Enable Input
Write Enable Input
W
UB
LB
K
Upper Byte Enable Input
Lower Byte Enable Input
Clock Input
L
Latch Enable Input
Wait Output
WAIT
VCC
Core Supply Voltage
VCCQ
VSS
Input/Output Buffers Supply Voltage
Ground
VSSQ
Input/Output Buffers Ground
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M69KB096AB
1 Summary description
Figure 2. Block Diagram
A21-A0
Address Decoder
Column Decoder
E
W
Bus Configuration
Register (BCR)
CR
DQ0-DQ15
I/O
Buffers
4,096K x 16
Row
Decoder
Memory Array
Synchronous/
Asynchronous
Logic
K
WAIT
E
W
G
Control
Logic
L
CR
LB
UB
AI11299
1. This functional block diagram illustrates simplified device operation.
9/73
2 Signal descriptions
M69KB096AB
2
Signal descriptions
The signals are summarized in Figure 1: Logic Diagram, and Table 1: Signal Names.
2.1
2.2
Address Inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during read and write
operations.
Data Inputs/Outputs (DQ8-DQ15)
The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected
address during a write or read operation, when Upper Byte Enable (UB) is driven Low. When
disabled, the Data Inputs/Outputs are high impedance.
2.3
2.4
Data Inputs/Outputs (DQ0-DQ7)
The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected
address during a write or read operation, when Lower Byte Enable (LB) is driven Low. When
disabled, the Data Inputs/Outputs are high impedance.
Chip Enable (E)
Chip Enable, E, activates the device when driven Low (asserted). When de-asserted (VIH), the
device is disabled and goes automatically in low-power Standby mode or Deep Power-Down
mode, according to the RCR settings.
2.5
2.6
Output Enable (G)
When held Low, VIL, the Output Enable, G, enables the Bus Read operations of the memory.
Write Enable (W)
Write Enable, W, controls the Bus Write operation of the memory. When asserted (VIL), the
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
2.7
Upper Byte Enable (UB)
The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a write or read operation.
10/73
M69KB096AB
2 Signal descriptions
2.8
Lower Byte Enable (LB)
The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7)
to or from the lower part of the selected address during a write or read operation.
If both LB and UB are disabled (High), the device will disable the data bus from receiving or
transmitting data. Although the device will seem to be deselected, it remains in an active mode
as long as E remains Low.
2.9
Clock Input (K)
The Clock, K, is an input signal to synchronize the memory to the microcontroller or system bus
frequency during Synchronous Burst Read and Write operations. The Clock input signal
increments the device internal address counter.
The addresses are latched on the rising edge of the Clock K, when L is Low during
Synchronous Bus operations.
Latency counts are defined from the first Clock rising edge after L falling edge to the first data
input latched or the first data output valid.
The Clock input is required during all synchronous operations and must be kept Low during
asynchronous operations.
2.10 Configuration Register Enable (CR)
When this signal is driven High, VIH, bus read or write operations access either the value of the
Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to
the value of A19.
2.11 Latch Enable (L)
In Synchronous mode, addresses are latched on the rising edge of the Clock K when the Latch
Enable input, L is Low. In Asynchronous mode, addresses are latched on L rising edge.
2.12 Wait (WAIT)
The WAIT output signal provides data-valid feedback during Synchronous Burst Read and
Write operations. The signal is gated by E. Driving E High while WAIT is asserted may cause
data corruption.
Once a read or write operation has been initiated, the WAIT signal goes active to indicate that
the M69KB096AB device requires additional time before data can be transferred.
The WAIT signal also is used for arbitration when a Read or Write operation is launched while
an on-chip refresh is in progress (see Figure 6: Refresh Collision during Synchronous Burst
Read in Variable Latency Mode).
Typically, the WAIT pin of the M69KB096AB can be connected to a shared WAIT signal used by
the processor to coordinate transactions with multiple memories on the synchronous bus.
See Section 3: Power-up for details on the WAIT signal operation.
11/73
2 Signal descriptions
M69KB096AB
2.13 V Supply Voltage
CC
The VCC Supply Voltage is the core supply voltage.
2.14 V
Supply Voltage
CCQ
VCCQ provides the power supply for the I/O pins. This allows all Outputs to be powered
independently from the core power supply, VCC
.
2.15 V Ground.
SS
The VSS Ground is the reference for all voltage measurements.
2.16 V
Ground
SSQ
VSSQ ground is the reference for the input/output circuitry driven by VCCQ. VSSQ must be
connected to VSS
.
12/73
M69KB096AB
3 Power-up
3
Power-up
To guarantee correct operation, a specific Power-Up sequence must be followed to initialize the
M69KB096AB. Power must be applied simultaneously to VCC and VCCQ. Once VCC and VCCQ
have reached a stable level (see Figure 35: Deep Power-Down Entry and Exit AC Waveforms
and Figure 34: Power-Up AC Waveforms), the device will require tVCHEL to complete its self-
initialization process. During the initialization period, the E signal must remain High. Once
initialization has completed, the device is ready for normal operation.
Initialization will load the Bus Configuration Register (BCR) and the Refresh Configuration
Register (RCR) with their default settings (see Table 9: Bus Configuration Register Definition,
and Table 11: Refresh Configuration Register Definition).
4
Low-power modes
4.1
Standby
When the device is in Standby, the current consumption is reduced to the level necessary to
perform the memory array refresh operation. The device will enter Standby when a read or
write operation is completed, depending on the operating mode (Asynchronous, NOR-Flash
Synchronous or Full Synchronous).
For details on how to enter Standby, refer to Table 3: Standard Asynchronous Operating
Modes, Table 5: Asynchronous Write Operations (NOR-Flash Synchronous Mode) and Table 6:
Synchronous Read Operations (NOR-Flash Synchronous Mode).
4.2
Deep Power-Down
Deep Power-Down (DPD) is used by the system memory microcontroller to disable the PSRAM
device when its storage capabilities are not needed. All refresh operations are then disabled.
For the device to enter Deep Power-Down, bit 4 of the RCR must be set to ‘0’ and Chip Enable,
E, must go High, VIH. When the Deep Power-Down is enabled, the data stored in the device
may be corrupted and BCR, RCR and DIDR content are saved.
For the device exits Deep Power-Down by driving Chip Enable, E, Low, VIL. Bit 4 of the RCR will
be automatically set to ‘1’. Once the Deep Power-Down is exited, the device will be available for
normal operations after tVCHEL (time to perform an initialization sequence) During this delay, the
current consumption will be higher than the specified Standby levels, but considerably lower
than the active current. The content of the registers will be restored after Deep Power-Down.
For details on how to enter Deep Power-Down, refer to Table 3: Standard Asynchronous
Operating Modes, Table 5: Asynchronous Write Operations (NOR-Flash Synchronous Mode)
and Table 6: Synchronous Read Operations (NOR-Flash Synchronous Mode).
13/73
4 Low-power modes
M69KB096AB
4.3
Partial Array Self Refresh
The Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM array.
This mechanism enables the device to reduce the Standby current by refreshing only the part of
the memory array that contains essential data. Different refresh options can be defined by
setting the RCR0 to RCR2 bits of the RCR:
■
■
■
■
■
Full array
One eighth of the array
One half of the array
One quarter of the array
None of the array.
These memory areas can be located either at the top or bottom of the memory array.
The WAIT signal is used for arbitration when a read/write operation is launched while an on-
chip refresh is in progress. If locations are addressed while they are undergoing refresh, the
WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see
Figure 6: Refresh Collision during Synchronous Burst Read in Variable Latency Mode). When
the refresh operation is completed, the read or write operation will be allowed to continue
normally.
4.4
Automatic Temperature Compensated Self Refresh
The leakage current of DRAM capacitive storage elements increases with the temperature. At
lower temperatures, the refresh rate can be decreased to minimize the Standby current.
The M69KB096AB is based on DRAM architecture, consequently it requires increasingly
frequent refresh operations to maintain data integrity as the temperature increases. The
Automatic Temperature Compensated Self Refresh mechanism (TCSR) that the devices
feature, automatically adjusts the refresh rate depending on the operating temperature.
14/73
M69KB096AB
5 Standard Asynchronous operating modes
5
Standard Asynchronous operating modes
The M69KB096AB supports Asynchronous Read and Write modes (Random Read, Page
Read, Asynchronous Write).
The device is put in Asynchronous mode by setting bit 15 (BCR15) of the BCR to ‘1’. The Page
mode is controlled by the Refresh Configuration Register (bit RCR7).
During asynchronous operations, the WAIT signal should be ignored and the Clock input signal
K should be held Low, VIL.
Refer to Table 3: Standard Asynchronous Operating Modes for a detailed description of
asynchronous operating modes.
5.1
Asynchronous Read and Write modes
At Power-Up, the device defaults to Asynchronous Random Read mode (bit BCR15 set to ‘1’).
This mode uses the industry standard control bus (E, G, W, LB, UB). Read operations are
initiated by bringing E and G Low, VIL, while keeping W High, VIH. Valid data will be gated
through the output buffers after the specific access time tELQV has elapsed.
Write operations occur when E and W are Low. During Asynchronous Random Write
operations, the G signal is ‘don't care’ and W will override G. The data to be written is latched
on the rising edge of E, W, LB or UB (whichever occurs first). The write operation is terminated
by de-asserting E, W, LB or UB.
The L input can either be used to latch the address or kept Low, VIL, during the entire read/write
operation.
See Figures 14 and 15, and Table 17 for details on Asynchronous Read AC waveforms and
characteristics and Figures 18, 19, 20, and Table 19 for details of Asynchronous Write AC
waveforms and characteristics.
5.2
Asynchronous Page Read mode
Asynchronous Page Read mode is enabled by setting RCR7 to ‘1’. The Latch Enable, L, and
the Chip enable E must be held Low, VIL during Asynchronous Page Read operations.
A Page of data is internally read. A memory page may consist of 4, 8 or 16 Words. During a 4-
Word page access, all the address bits except A0 to A1 should be fixed. During a 8-Word and
16-Word page access, all address bits are fixed except A0 to A2 and A0 to A3, respectively
(see Table 2: Page Mode Characteristics).
The first read operation within the Page has the normal access time (tAVQV), subsequent reads
within the same Page have much shorter access times (tAVQV1). If the Page changes then the
normal, longer timings apply again.
The Page mode is not available for write operations.
See Figure 16 and Table 17 for details of the Asynchronous Page Read timing requirements.
15/73
5 Standard Asynchronous operating modes
M69KB096AB
Table 2.
Page Mode Characteristics
Page Size
Page Read Address
Page Read Start Address
Page Read Direction
4 Words
A0-A1
A0-A2
A0-A3
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
8 Words
16 Words
5.3
Configuration Registers Asynchronous Read and Write
Programming the registers (BCR and RCR) and reading the registers (BCR, RCR and DIDR)
can be performed using the CR controlled method in standard Asynchronous mode.
16/73
M69KB096AB
5 Standard Asynchronous operating modes
Table 3.
Standard Asynchronous Operating Modes
Asynchronous
Modes(1)(2)
A0-A17
A20-A21
Power
E
W
G
UB LB CR A19 A18
DQ0-DQ7 DQ8-DQ15
Output
Valid
Output
Valid
VIL VIL VIL VIL
Word Read
Valid
Lower Byte
Read
Output
Valid
VIH VIL VIH VIL VIL
VIL VIL VIH VIL
Valid
High-Z
Upper Byte
Read
Output
Valid
Valid
Valid
Valid
High-Z
VIL VIL VIL
VIH VIL VIL
Word Write
X
X
Input Valid Input Valid
Lower Byte
Write
Input Valid
Invalid
Invalid
VIL
Active
Upper Byte
Write
(ICC
)
VIL VIH VIL
X
Valid
Input Valid
VIL
Read
Configuration
Register
(CR Controlled
Method)
00(RCR)
BCR/
VIH VIL
X
X
10(BCR)
X
RCR/DIDR
Content
X1(DIDR)
VIH
Program
Configuration
Register (CR
Controlled)(3)
00(RCR)
BCR/
VIL
X
10(BCR)
X
X
X
X
X
X
X
RCR Data
(4)
Active
(ICC
Output Disable/
No Operation
VIH VIH
VIL
X
X
X
X
X
X
X
X
X
High-Z
High-Z
)
Deep
Power-
Down
Deep
Power-Down(5)
VIH
X
X
X
(ICCPD)
Standby
VIH
Standby
X
X
X
X
X
High-Z
(IPASR
)
1. The Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in Standby and
Deep Power-Down modes.
2. The device must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value).
3. BCR and RCR only.
4. A18 and A19 are used to select the BCR, RCR or DIDR registers.
5. Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, V , during Deep Power-
IH
Down mode.
17/73
6 Synchronous Operating modes
M69KB096AB
6
Synchronous Operating modes
The synchronous modes allow high-speed read and write operations synchronized with the
clock.
The M69KB096AB supports two types of synchronous modes:
■
NOR-Flash:- this mode greatly simplifies the interfacing with traditional burst-mode Flash
memory microcontrollers.
■
Full Synchronous: both read and write are performed in Synchronous mode.
All the options related to the synchronous modes can be configured through the Bus
Configuration Register, BCR. In particular, the device is put in Synchronous mode, either NOR-
Flash or Full Synchronous, by setting bit BCR15 of the Bus Configuration Register to ‘0’.
The device will automatically detect whether the NOR-Flash or the Full Synchronous mode is
being used by monitoring the Clock, K, and the Latch Enable, L, signals. If a rising edge of the
Clock K is detected while L is held Low, VIL (active), the device operates in Full Synchronous
mode.
6.1
NOR-Flash Synchronous mode
In this mode, the device operates in synchronous mode for read operations, and in
asynchronous mode for write operations.
Asynchronous write operations are performed at Word level, with LB and UB Low. The data is
latched on E, W, LB, UB, whichever occurs first. RCR and BCR registers can be programmed in
NOR-Flash Asynchronous Write mode, using the CR controlled method (see Section 7.1:
Programming and Reading Registers using the CR Controlled Method). A Program
Configuration Register operation can only be issued if the device is in idle state and no burst
operations are in progress. NOR-Flash Asynchronous Write operations are described in
Table 5: Asynchronous Write Operations (NOR-Flash Synchronous Mode).
Synchronous read operations are also performed at Word level. They are controlled by the
state of E, L, G, W, LB and UB signals when a rising edge of the clock signal, K, occurs. The
initial Burst Read access latches the Burst start address. The number of Words to be output is
controlled by bits 0 to 2 of the BCR. The first data will be output after a number of clock cycles,
also called Latency. NOR-Flash Synchronous Burst Read operations are described in Table 6:
Synchronous Read Operations (NOR-Flash Synchronous Mode).
When a Burst Write operation is initiated or when switching from NOR-Flash mode to Full
Synchronous mode, the delay from E Low to Clock High, tELKH, should not exceed 20ns.
However, when it is not possible to meet these specifications, special care must be taken to
keep addresses stable after driving the Write Enable signal, W, Low.
Write operations are considered as Asynchronous operations until the device detects a valid
clock edge and hence the address setup time of tAVWL must be satisfied (see Figure 5:
Switching from Asynchronous to Synchronous Write Operation).
18/73
M69KB096AB
6 Synchronous Operating modes
6.2
Full Synchronous mode
In Full Synchronous mode, the device performs read and write operations synchronously.
Synchronous Read and Write operations are performed at Word level. The initial Burst Read
and Write access latches the Burst start address. The number of Words to be output or input
during Synchronous Read and Write operations is controlled by bits 0 to 2 of the BCR.
During Burst Read and Write operations, the first data will be output after a number of clock
cycles defined by the Latency value.
Programming the registers (BCR and RCR) and reading the registers (BCR, RCR and DIDR)
can be performed using the CR controlled method in Full Synchronous mode.
Full Synchronous operations are described in Table 7: Full Synchronous Mode.
6.3
Synchronous Burst Read and Write
During Synchronous Burst Read or Write operations, addresses are latched on the rising edge
of the Clock K when L is Low and data are latched on the rising edge of K. The Write Enable,
W, signal indicates whether the operation is going to be a read (W=VIH) or a write (W=VIL).
The WAIT output will be asserted as soon as a Synchronous Burst operation is initiated and will
be de-asserted to indicate when data are to be transferred to (or from) the memory array.
The Burst Length is the number of Words to be output or input during a Synchronous Burst
Read or Write operation. It can be configured as 4, 8, 16 or 32 Words or continuous through bit
BCR0 to BCR2 or the Burst Configuration Register.
The Latency defines the number of clock cycles between the beginning of a Burst Read
operation and the first data output (counting from the first Clock edge where L was detected
Low) or between the beginning of a Burst Write operation and the first data input. The Latency
can be set through bits BCR13 to BCR11 of the Bus Configuration Register (see Table 4:
Operating Frequency versus Latency).
The latency can also be configured to fixed or variable by programming bit BCR14. By default,
the Latency Type is set to variable. Synchronous Read operations are performed in both fixed
and variable latency mode while Synchronous Write operations are only performed with fixed
latency.
See Figures 24, 26, and Figures 30, 31, for details on Synchronous Read and Write AC
waveforms, respectively.
6.3.1 Variable Latency
In Variable Latency mode, the latency programmed in the BCR is not guaranteed and is
maintained only if there is no conflict with a refresh operation. The Latency set in the BCR is
applicable only for an initial burst read access, when no refresh request is pending. For a given
latency value, the Variable Latency mode allows higher operating frequencies than the Fixed
Latency mode (see Table 4: Operating Frequency versus Latency and Figure 3: Latency
Configuration (Variable Latency Mode, No Refresh Collision)).
Burst Write operations are always performed at fixed latency, even if BCR14 is configured to
Variable Latency (see Section 6.3.2: Fixed Latency).
Monitoring of the WAIT signal is recommended for reliable operation in this mode. See Figure
24. and 31 for details on Synchronous Burst Read and Write AC waveforms in Variable Latency
mode.
19/73
6 Synchronous Operating modes
M69KB096AB
6.3.2 Fixed Latency
The latency programmed in the BCR is the real latency. The number of clock cycles is
calculated by taking into account the time necessary for a refresh operation and the time
necessary for an initial Burst access. This limits the operating frequency for a given latency
value (see Table 4: Operating Frequency versus Latency and Figure 4: Latency Configuration
(Fixed Latency Mode)).
It is recommended to use the Fixed Latency mode if the microcontroller cannot monitor the
WAIT signal.
6.3.3 Row Boundary Crossing
The M69KB096AB features 128-Word rows. Row boundary crossings between adjacent rows
may occur during Burst Read and Write operations. Row boundary crossings are not handled
automatically by the PSRAM.
The microcontroller must stop the Burst operation at the row boundary and restart it at the
beginning of the next row. Burst operations must be stopped by driving the Chip Enable signal,
E, High, after the WAIT signal falling edge. E must transition:
■
■
before the third Clock cycle after the WAIT signal goes Low if BCR[8] = 0,
before the fourth Clock cycle after WAIT signal goes Low if BCR[8] = 1.
Refer to Figure 26 and Figure 30 for details on how to manage row boundary crossings during
burst operations.
6.4
Synchronous Burst Read Interrupt
Ongoing Burst Read operations can be interrupted to start a new Burst cycle by either of the
following means:
■
Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended). If
necessary, refresh cycles will be added during the new Burst operation to schedule any
outstanding refresh. If Variable Latency mode is set, additional wait cycles will be added if
a refresh operation is scheduled during the Synchronous Burst Read Interrupt. WAIT
monitoring is mandatory for proper system operation.
■
Starting a new Synchronous Burst Read operation without toggling E.
An ongoing Burst Read operation can be interrupted only after the first valid data is output.
When a new Burst access starts, I/O signals immediately become high impedance.
6.5
Synchronous Burst Write Interrupt
Ongoing Burst Write operations can be interrupted to start a new Burst cycle by either of the
following means:
■
Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended),
■
Starting a new Synchronous Burst Write without toggling E. Considering that Burst Writes
are always performed in Fixed Latency mode, refresh is never scheduled. A maximum
Chip Enable, E, low time (tELEH) must be respected for proper device operation.
An ongoing Burst Write can be interrupted only after the first data is input. When a new Burst
access starts, I/O signals immediately become high impedance.
20/73
M69KB096AB
6 Synchronous Operating modes
See Figure 27: Burst Read Interrupted by Burst Read or Write AC Waveforms and Figure 32:
Burst Write Interrupted by Burst Write or Read AC Waveforms for details on Burst Read and
Burst Write interrupt AC waveforms, respectively.
6.6
Synchronous Burst Read and Write Suspend
Synchronous Burst Read and Write operations can be suspended by halting the Clock K
holding it either High or Low. The status of the I/O signals will depend on the status of Output
enable input, G. The device internal address counter is suspended and data outputs become
high impedance tGHQZ after the rising edge of the Output Enable signal, G. It is prohibited to
suspend the first data output at the beginning of a Synchronous Burst Read.
See Figure 25 for details on the Synchronous Burst Read and Write Suspend mechanisms.
During Synchronous Burst Read and Synchronous Burst Write Suspend operations, the WAIT
output will be asserted. Bit BCR8 of the Bus Configuration Register is used to configure when
the transition of the WAIT output signal between the asserted and the de-asserted state occurs
with respect to valid data available on the data bus.
Table 4.
Operating Frequency versus Latency
Latency (Clock Cycles)
Max Input Clock Frequency (MHz)
Latency
Mode
Configured Latency
(Clock Cycles)
If Refresh
Normal
104 MHz
66
80 MHz
52
Collision
2 (3 clock cycles)
3
4
-
5
7
-
Variable
Latency
3 (4 clock cycles)
(default)
104
80
BCR14 = 0
(Default)
All Others
-
-
2 (3 clock cycles)
3
4
33
33
3 (4 clock cycles)
(default)
52
52
Fixed Latency
BCR14 = 1
4 (5 clock cycles)
5 (6 clock cycles)
6 (7 clock cycles)
All Others
5
6
7
-
66
75
66
75
80
-
104
-
21/73
6 Synchronous Operating modes
M69KB096AB
Table 5.
Asynchronous Write Operations (NOR-Flash Synchronous Mode)
Asynchronous
UB,
LB
DQ0-
DQ15
Power
E
L
W
G
CR A19 A18 A0-A21
Operations(1)(2)
VIL VIL VIL
VIL VIL
Word Write
X
Valid
Input Valid
Program Configuration
Register
(CR Controlled)(3)
RCR/
BCR
Data
Active (ICC
)
00(RCR)
10(BCR)
VIL VIL VIL
VIH
X
X
X
Output Disable/
No Operation
Active (ICC
)
VIL VIH VIH VIH VIL VIL
VIL
High-Z
High-Z
High-Z
Standby (IPASR
)
VIH
VIH
VIL
X
Standby
X
X
X
X
X
X
X
X
X
X
Deep Power-Down
(ICCPD)
Deep Power-Down
1. The device must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value).
2. The Clock signal, K, must remain Low, during asynchronous Write operations and to achieve standby power during
Standby and Deep Power-Down modes.
3. BCR and RCR only.
Table 6.
Synchronous Read Operations (NOR-Flash Synchronous Mode)
Synchronous
Operations(1)
A0-
A21(2)
LB,
UB
DQ15-
DQ0
Power
K
E
L
W
VIH
X
G
CR
VIL
VIL
A19
A18
Initial Burst
Read
VIL
VIL
VIL
VIH
VIL
VIL
!
!
X
Valid Valid
X
Valid
X
Subsequent
Burst Read(3)
Data-
Out
VIL
Active (ICC
)
)
Read
Configuration
Register
RCR/
BCR/
DIDR
00(RCR)
10(BCR)
X1(DIDR)
VIL
VIL
VIH
VIL
VIH
!
X
X
(CR Controlled
Method)
Content
Output
Disable/No
Operation
Active (ICC
Standby
VIL
VIH
VIH
VIH
VIL
X
!
!
X
X
X
X
High-Z
High-Z
VIH
Standby
X
X
X
(IPASR
)
Deep
Power-
Down
Deep Power-
Down
VIL VIH
X
X
X
X
X
X
High-Z
(ICCPD)
1. The device must have been configured to operate in synchronous mode by setting BCR15 to ‘0’ (default value).
2. Except A18 and A19.
3. Burst Read Interrupt and Suspend are described in dedicated paragraph of the Section 6: Synchronous Operating modes.
22/73
M69KB096AB
6 Synchronous Operating modes
Table 7.
Full Synchronous Mode
A0-
A22(1)
Synchronous
Mode
LB,
UB
DQ15-
DQ0
Power
K
E
L
W
G
WAIT
CR
A19
A18
Initial Burst
Read
VIL VIL VIH
VIL
VIL
VIL
VIL
VIL
X
!
!
!
!
X
Valid
X
Valid
Valid
X
Subsequent
Burst Read(2)
Output
Valid
VIL VIH
VIL
X
X
Initial Burst
Write
Input
Valid
VIL VIL VIL VIH
VIL VIH VIH
X
Valid
X
Valid
X
Valid
X
Subsequent
Burst Write
Input
Valid
VIL
X
Active
Program
Configuration
Register
(ICC
)
RCR/
BCR
Data
00(RCR)
Low-Z
VIL VIL VIL VIH
VIH
!
X
X
10(BCR)
(CR
Controlled)
Read
Configuration
Register
(CR
Controlled
Method)
RCR/
BCR/
00(RCR)
10(BCR)
X1(DIDR)
VIL VIL VIH VIL
VIL
VIH
!
!
X
DIDR
Content
Active
(ICC
VIL VIH VIH VIH
VIL
VIL
No Operation
Standby
X
X
X
X
High-Z
High-Z
)
Standby
VIL VIH
X
X
X
X
X
X
(IPASR
)
Deep
Power-
Down
High-Z
Deep Power-
Down
VIL VIH
X
X
X
High-Z
(ICCPD)
1. Except A18 and A19.
2. Burst Read Interrupt, Suspend, Terminate and Burst Write Interrupt, Suspend and Terminate are described in dedicated
paragraph of the Section 6: Synchronous Operating modes.
23/73
6 Synchronous Operating modes
M69KB096AB
Figure 3. Latency Configuration (Variable Latency Mode, No Refresh Collision)
K
0
1
2
3
4
5
6
7
Address
Valid
Addr.
ADV
Latency = 3 Clock Cycles
Hi Z
Hi Z
Q
DQ0-DQ15
Q
Q
Q
Q
Q
4
5
1
2
3
Latency = 4 Clock Cycles
Q
Q
Q
3
DQ0-DQ15
4
1
2
AI11280
Figure 4. Latency Configuration (Fixed Latency Mode)
N-1
Cycle
N
Cycle
K
tAVQV
Address
Valid
Addr.
tLLQV
tELQV
ADV
E
tKHQV2
Hi Z
Q
DQ0-DQ15
OUT
Q
Q
Q
Q
4
5
1
2
3
AI11281b
1. See Table 21: Synchronous Burst Read AC Characteristics for details on the synchronous read AC Characteristics shown
in the above waveforms.
24/73
M69KB096AB
6 Synchronous Operating modes
Figure 5. Switching from Asynchronous to Synchronous Write Operation
K
VALID
Addr.
tAVWL
L
tELKH
E
W
AI10203
Figure 6. Refresh Collision during Synchronous Burst Read in Variable Latency Mode
K
Address
A0-A22
Valid
L
E
G
W
LB/UB
Hi Z
Hi Z
WAIT
DQ0-DQ15
Q0
Q1
Q2
Q3
Additional WAIT states inserted
to allow Refresh completion
AI11275b
1. Additional Wait states are inserted to allow Refresh completion.
The latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT must be active Low, V , (BCR10 = 0) and asserted
IL
during delay (BCR8= 0).
25/73
7 Configuration Registers
M69KB096AB
7
Configuration Registers
The M69KB096AB features three registers:
■
■
■
The Bus Configuration Register (BCR)
The Refresh Configuration Register (RCR)
The Device ID Register (DIDR).
BCR and RCR are user-programmable registers that define the device operating mode. They
are automatically loaded with default settings during Power-Up, and selected by address bits
A18 and A19 (see Table 8: Register Selection).
DIDR is a read-only register that contains information about the device identification. It is
selected by setting address bit A18 to ‘1’ with A19 ‘don’t care’.
The configuration registers (only BCR and RCR) can be programmed and read using two
methods:
■
■
The CR Controlled Method (or Hardware Method)
The Software Method.
7.1
Programming and Reading Registers using the CR Controlled
Method
7.1.1 Read Configuration Register
The content of a register is read by issuing a read operation with Configuration Register Enable
signal, CR, High, VIH. Address bits A18 and A19 select the register to be read (see Table 8:
Register Selection). The value contained in the register is then available on data bits DQ0 to
DQ15.
The BCR, RCR and DIDR can be read either in normal asynchronous or synchronous mode.
The CR pin has to be driven high prior to any access.
See Tables 6 and 7 for a detailed description of Configuration register Read by the CR
Controlled methods and Figures 17 and 28, CR Controlled Configuration Register Read
waveforms in asynchronous and synchronous mode.
7.1.2 Program Configuration Register
BCR and RCR registers can be programmed by issuing a bus write operation, in asynchronous
or synchronous mode (NOR-Flash or Full Synchronous), with Configuration Register Enable
signal, CR, High, VIH. Address bits A18 and A19 allow to select between BCR and RCR (see
Table 8: Register Selection).
In synchronous mode, the values placed on address lines A0 to A15 are latched on the rising
edge of L, E, or W, whichever occurs first.
In asynchronous mode, a register is programmed by toggling L signal.
LB and UB are ‘don’t care’. The CR pin has to be driven high prior to any access.
26/73
M69KB096AB
7 Configuration Registers
Refer to Tables 5 and 7 for a detailed description of Configuration Register Program by the CR
Controlled method and to Figures 22 and 33, showing CR controlled Configuration Register
Program waveforms in asynchronous and synchronous mode.
Table 8.
Register Selection
Register
Read or Write Operation
A18
A19
RCR
BCR
DIDR
Read/Write
Read/Write
Read-Only
0
0
1
0
1
X
7.2
Programming and Reading the Registers using the Software
Method
All registers (BCR, RCR, DIDR) can be read by issuing a Read Configuration Register
sequence (see Figure 8: Read Configuration Register (Software Method).
BCR and RCR can be programmed by issuing a Set Configuration Register sequence (see
Figure 7: Set Configuration Register (Software Method).
The timings will be identical to those described in Table 17: Asynchronous Read AC
Characteristics. The Configuration Register Enable input, CR, is ‘don’t care’.
Read Configuration Register and Set Configuration Register sequences both require 4 read
and write cycles. These cycles are performed in asynchronous mode, whatever the device
operating mode:
1. 2 bus read and one bus write cycles to a unique address location, 7FFFFFh, indicate that
the next operation will read or write to a configuration register. The data written during the
third cycle must be ‘0000h’ to access the RCR, ‘0001h’ to access the BCR and ‘0002h’ to
access the DIDR during the next cycle.
2. The fourth cycle reads from or writes to the configuration register.
The timings for programming and reading the registers by the software method are identical to
the asynchronous write and read timings.
27/73
7 Configuration Registers
M69KB096AB
Figure 7. Set Configuration Register (Software Method)
Addr.
7FFFFFh
7FFFFFh
7FFFFFh
7FFFFFh
E
tEHEL2
tEHEL2
tEHEL2
G
W
LB, UB
Configuration
DQ0-DQ15
(2)
Register Data
AI09469f
1. Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
2. To program the BCR or the RCR on last bus write cycle, DQ0-DQ15 must be set to ‘0001h’ and ‘0000’ respectively.
3. The highest order address location is not modified during this operation.
4. The control signals E, G, W, LB and UB, must be toggled as shown in the above figure.
Figure 8. Read Configuration Register (Software Method)
Addr.
7FFFFFh
7FFFFFh
tEHEL2
7FFFFFh
tEHEL2
7FFFFFh
E
tEHEL2
G
W
LB, UB
Configuration
Register Data
DQ0-DQ15
(1)
AI09470f
1. To read the BCR, RCR or DIDR on last bus read cycle, DQ0-DQ15 must be set to ‘0001h’, ‘0000’ and ‘0002’ respectively.
2. The highest order address location is not modified during this operation.
3. The control signals E, G, W, LB and UB, must be toggled as shown in the above figure.
28/73
M69KB096AB
7 Configuration Registers
7.3
Bus Configuration Register
The Bus Configuration Register (BCR) defines how the PSRAM interacts with the system
memory bus. All the device operating modes are configured through the BCR, except the Page
mode which is configured through the RCR.
Refer to Table 9 for the description of the Bus Configuration Register Bits.
7.3.1 Operating Mode Bit (BCR15)
The Operating Mode bit allows the Synchronous mode or the Asynchronous mode (default
setting) to be selected. Selecting the Synchronous mode will allow the device to operate either
in NOR Flash mode or in full Synchronous Burst mode.
The device will automatically detect that the NOR Flash mode is being used by monitoring a
rising edge of the Clock signal, K, when L is Low. If this should not be the case, the device
operates in full Synchronous mode.
7.3.2 Latency Type (BCR14)
The Latency Type bit is used to configure the latency type. When the Latency Type bit is set to
‘0’, the device operates in variable latency mode (only available for Synchronous Read mode).
When it is ‘1’, the fixed latency mode is selected and the latency is defined by the values of bits
BCR13 to BCR11.
Refer to Figures 3 and 4 for examples of fixed and variable latency configuration.
7.3.3 Latency Counter Bits (BCR13-BCR11)
The Latency Counter bits are used to set the number of clock cycles between the beginning of
a read or write operation and the first data output or input.
The Latency Counter bits can only assume the values shown in Table 9: Bus Configuration
Register Definition (see also Figures 3 and 4).
7.3.4 WAIT Polarity Bit (BCR10)
The WAIT Polarity bit indicates whether the WAIT output signal is active High or Low. As a
consequence, it also determines whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state (see Figure 10: WAIT Polarity).
By default, the WAIT output signal is active High.
29/73
7 Configuration Registers
M69KB096AB
7.3.5 WAIT Configuration Bit (BCR8)
The system memory microcontroller uses the WAIT signal to control data transfer during
Synchronous Burst Read and Write operations.
The WAIT Configuration bit is used to determine when the transition of the WAIT output signal
between the asserted and the de-asserted state occurs with respect to valid data available on
the data bus.
When the Wait Configuration bit is set to ‘0’, data is valid or invalid on the first Clock rising edge
immediately after the WAIT signal transition to the de-asserted or asserted state.
When the Wait Configuration bit is set to ‘1’ (default settings), the WAIT signal transition occurs
one clock cycle prior to the data bus going valid or invalid.
See Figure 9: WAIT Configuration Example for an example of WAIT configuration.
7.3.6 Driver Strength Bits (BCR5-BCR4)
The Driver Strength bits allow to set the output drive strength to adjust to different data bus
loading. Normal driver strength (full drive) and reduced driver strength (half drive and a quarter
drive) are available.
By default, outputs are configured at ‘half drive” strength.
7.3.7 Burst Wrap Bit (BCR3)
Burst Read operations can be confined inside the 4, 8, 16 or 32 Word boundary (wrap mode). If
the wrap mode is not enabled, the device outputs data sequentially up to the end of the row,
regardless of burst boundaries.
The Burst Wrap bit is used to select between ‘wrap’ and ‘no wrap’ mode.
7.3.8 Burst Length Bits (BCR2-BCR0)
The Burst Length bits set the number of Words to be output or input during a Synchronous
Burst Read or Write operation. They can be set for 4 Words, 8 Words, 16 Words, 32 Words or
Continuous Burst (default settings), where all the Words are output or input sequentially
regardless of address boundaries (see also Table 10: Burst Type Definition).
30/73
M69KB096AB
Table 9. Bus Configuration Register Definition
Address
7 Configuration Registers
Bus
Configuration
Register Bits
Name
Value
Description
Bits
A15
A14
Synchronous Mode (NOR Flash or Full
Synchronous Mode)
0
Operating Mode
Bit
BCR15
BCR14
1
Asynchronous Mode (Default)
Variable Latency (Default)
Fixed Latency
0
Latency Type
1
010
011
100
101
110
3 Clock Cycles
4 Clock Cycles (Default)
5 Clock Cycles
BCR13-
BCR11
Latency Counter
Bits
A13-A11
6 Clock Cycles
7 Clock Cycles
Other Configurations Reserved(1)
0
WAIT Active Low
A10
A9
BCR10
-
WAIT Polarity Bit
-
WAIT Active High (default).See Figure 10:
WAIT Polarity.
1
Reserved(1)
Must be set to ‘0’
0
WAIT Asserted During Delay (see Figure 9:
WAIT Configuration Example).
Wait
Configuration Bit
A8
BCR8
-
WAIT Asserted One Clock Cycle Before Delay
(Default)
1
Reserved(1)
Full Drive
A7-A6
-
Must be set to ‘0’
00
01
1/2 Drive (Default)
1/4 Drive
Driver Strength
Bits
A5-A4
A3
BCR5-BCR4
BCR3
10
Reserved(1)
Wrap
11
0
Burst Wrap Bit
1
No Wrap (default)
4 Words
001
010
011
100
111
8 Words
16 Words
A2-A0
BCR2-BCR0
Burst Length Bit
32 Words
Continuous Burst (default)
Other Configurations Reserved(1)
1. Programming the BCR with reserved value will force the device to use the default register settings.
31/73
7 Configuration Registers
M69KB096AB
Table 10. Burst Type Definition
4 Words
(Sequential)
BCR2-
8 Words
(Sequential)
BCR2-BCR0=010b
16 Words
(Sequential)
BCR2-BCR0=011b
32 Words
(Sequential) BCR2-
BCR0=100b
Start
Add
Continuous Burst
BCR2-BCR0=111b
BCR0=001b
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
...
0-1-2-3-...-14-15
1-2-3-4-...-14-15-0
2-3-4-5-...-15-0-1
3-4-5-...-15-0-1-2
4-5-...-15-0-1-2-3
5-6-7-...-15-0-1-...-4
6-7-8-...-15-0-1-...-5
7-8-9-...15-0-1-...-6
...
0-1-2-3-...-30-31
1-2-3-...-30-31-0
2-3-4-...-31-0-1
3-4-5-...-31-0-1-2
4-5-6-...-31-0-1-2-3
5-6-7-..-31-0-1-..-4
6-7-8-...-31-0-1-...-5
7-8-9-...-31-0-1-...-6
...
0-1-2-3-..-511-.
1-2-3-4-...-510-511-
2-3-4-5-6-...-511-
3-4-5-...-511-
4-5-...-511-
2
3
4
5
5-6-7-...-511-
6-7-8-...-511-
7-8-9-...-511-
...
6
7
...
14
15
...
30
31
0
...
...
14-15-0-1-2-...-13
15-0-1-2-...-14
...
14-15-...-31-0-...-13
15-0-1-...-31-0-...-14
...
14-...511-
15-...511-
...
...
30-31-0-...-28-29
31-0-1-...-29-30
0-1-2-3-...-30-31
1-2-3-4-...-32
30-...-511-
31-...-511-
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
0-1-2-3-...-14-15
1-2-3-..-15-16
2-3-4-...-17
3-4-5-...-18
0-1-2-3-..-511-.
1-2-3-4-...-512-
2-3-4-5-...-513-
3-4-5-...-514-
4-5-6-...-515-
5-6-7-...-516-
6-7-8-...-517-
1
2
2-3-4-5-6-7-8-9
2-3-4-...-33
3
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
3-4-5-...-34
4
4-5-6-...-19
4-5-6-...-35
5
5-6-7-...-20
5-6-7-...-36
6
6-7-8-...-21
6-7-8-...-37
7-8-9-10-11-12-13-
14
7
7-8-9-...-22
7-8-9-...-38
7-8-9-...-518-
...
14
15
...
...
...
...
14-15-...-29
14-15-16-...-46
15-16-17-...-47
14-...-525-
15-...-526-
...
15-16-17-...-30
30
31
30-31-0-...-28-62
31-0-1-...-29-63
30-...-541-
31-...-542-
32/73
M69KB096AB
7 Configuration Registers
Figure 9. WAIT Configuration Example
K
WAIT
DQ0-DQ15
Hi-Z
Hi-Z
BCR8='0', BCR10='1'
Data[0] Data[1]
Data[0]
Data Valid During Current Cycle
DQ0-DQ15
BCR8='1', BCR10='1'
Data Valid During Next Cycle
AI06795b
Figure 10. WAIT Polarity
K
WAIT
Hi-Z
Hi-Z
DQ0-DQ15
Data[0] Data[1]
Data[0] Data[1]
WAIT
DQ0-DQ15
AI09963
33/73
7 Configuration Registers
M69KB096AB
7.4
Refresh Configuration Register
The role of the Refresh Configuration Register (RCR) is:
■
■
■
to define how the self refresh of the PSRAM array is performed,
to select the Deep Power-Down mode,
to enable Page Read operations.
Refer to Table 11 for the description of the Refresh Configuration Register Bits.
7.4.1 Page Mode Operation Bit (RCR7)
The Page Mode operation bit determines whether the Asynchronous Page Read mode is
enabled. At power-up, the RCR7 bit is set to ‘0’, and the Asynchronous Page Read mode is
disabled.
7.4.2 Deep Power-Down Bit (RCR4)
The Deep Power-Down bit enables or disables all refresh-related operations. Deep Power-
Down mode is enabled when the RCR4 bit is set to ‘0’, and remains enabled until this bit is set
to ‘1’. When E goes high, the device enters Deep-Power Down mode and remains in this mode
until the E mean time goes low and stays low for at least 10µs. At power-up, the Deep Power-
Down mode is disabled.
See the Section 4.2: Deep Power-Down for more details.
7.4.3 Partial Array Refresh Bits (RCR2-RCR0)
The Partial Array Refresh bits allow refresh operations to be restricted to a portion of the total
PSRAM array. The refresh options can be full array, one half, one quarter, one eighth or none of
the array. These memory areas can be located either at the top or bottom of the memory array.
By default, the full memory array is refreshed.
34/73
M69KB096AB
7 Configuration Registers
Table 11. Refresh Configuration Register Definition
Refresh
Address
Configuration
Register Bits
Name
Value
Description
Bits
A15-A8
A7
-
-
Must be set to ‘0’ Reserved
0
1
Page Read Mode Disabled (Default)
Page Read Mode Enabled
Page Mode
Operation Bit
RCR7
A6-A5
A4
-
RCR4
-
-
Must be set to ‘0’ Reserved
0
1
Deep Power-Down Enabled
Deep Power-Down Disabled (Default)
Deep Power-
Down Bit
A3
-
Must be set to ‘0’ Reserved
000
001
010
011
100
101
110
111
Full Array Refresh (Default)
Refresh of the Bottom Half of the Array
Refresh of the Bottom Quarter of the Array
Refresh of the Bottom Eighth of the Array
None of the Array
Partial Array
Refresh Bits
A2-A0
RCR2-RCR0
Refresh of the Top Half of the Array
Refresh of the Top Quarter of the Array
Refresh of the Top Eighth of the Array
35/73
7 Configuration Registers
M69KB096AB
7.5
Device ID Register
The Device ID Register (DIDR) is a read-only register that contains the Manufacturer code. It is
preprogrammed by STMicroelectronics and cannot be modified by the user.
Refer to Table 12 for the description of the Bus Configuration Register Bits.
Table 12. Device ID Register Definition
Address
Bits
Device ID
Register Bits
Name
Value
Description
A15
DIDR15
Row Length
0
128 Words
0000
0001
0010
0011
1111
A
B
C
D
P
A14-A11
DIDR14-DIDR11
Design Version
Other Configurations Reserved
000
001
010
011
100
16 Mbits
32 Mbits
64 Mbits
128 Mbits
256 Mbits
A10-A8
A7-A5
A4-A0
DIDR10-DIDR8
DIDR7-DIDR5
DIDR4-DIDR0
Device Density
PSRAM Generation
Device ID
Other Configurations Reserved
001
010
011
1.0
1.5
2.0
Other Configurations Reserved
00001
00010
00011
00100
01111
Cypress
Infineon
Micron
Renesas
STMicroelectronics
Other Configurations Reserved
36/73
M69KB096AB
8 Maximum Rating
8
Maximum Rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause
permanent damage to the device. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
Table 13. Absolute Maximum Ratings
Symbol
TA
Parameter
Min
–30
–55
Max
+85
150
Unit
°C
°C
V
Ambient Operating Temperature
Storage Temperature
TSTG
VCC
VCCQ
VIO
Core Supply Voltage
–0.2
–0.2
–0.2
2.45
2.45
2.45
Input/Output Buffer Supply Voltage
Input or Output Voltage
V
V
37/73
9 DC and AC parameters
M69KB096AB
9
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 14: Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 14. Operating and AC Measurement Conditions
M69KB096AB
Min
Parameter(1)
Unit
Max
1.95
1.95
VCC Supply Voltage
1.7
1.7
V
V
V
CCQ Input/Output Buffer Supply Voltage
Load Capacitance (CL)
30
50
pF
Ω
V
Output Circuit Protection Resistance (R)
Input Pulse Voltages(2)(3)
VCC
0
Input and Output Timing Ref. Voltages(2)(3)
Input Rise Time tr and Fall Time tf(2)(3)
VCC/2
V
1
V/ns
1. All voltages are referenced to V
.
SS
2. Referenced to V
.
SS
3.
V
=V
CC CCQ
Figure 11. AC Measurement I/O Waveform
I/O Timing Reference Voltage
V
CCQ
V
/2
CCQ
V
SSQ
AI09484c
1. Logic states ‘1’ and ‘0’ correspond to AC test inputs driven at V
and V respectively. Input timings begin at V
/2 and
CCQ
SS
CCQ
output timings end at V
/2.
CCQ
Figure 12. AC Input Transitions
VCCTyp
90%
90%
10%
10%
tr
VSS
tf
ai10122
38/73
M69KB096AB
9 DC and AC parameters
Figure 13. AC Measurement Load Circuit
V
/2
CCQ
R
DEVICE
UNDER
TEST
OUT
C
L
AI11289
Table 15. Capacitance
Symbol
CIN
Parameter
Test Condition
Min
2
Max
6
Unit
pF
Input Capacitance
Data Input/Output Capacitance
TA = 25°C, f = 1MHz,
VIN = 0V
CIO
3.5
6
pF
39/73
9 DC and AC parameters
M69KB096AB
Table 16. DC Characteristics
Refreshed
Array
Symbol
Parameter
Test Conditions
Min.
Typ
Max.
Unit
(1)
IOH = –0.2mA
IOL = 0.2mA
0.8VCCQ
Output High Voltage
Output Low Voltage
V
V
VOH
(1)
0.2VCCQ
VOL
VCCQ
0.2
+
(2)
VCCQ −0.4
Input High Voltage
V
VIH
(3)
Input Low Voltage
−0.2
0.4
1
V
VIL
ILI
VIN = 0 to VCCQ
Input Leakage Current
Output Leakage Current
µA
µA
ILO
G = VIH or E = VIH
1
V
IN = 0V or VCCQ
IOUT = 0mA, E = VIL
IN = 0V or VCCQ
IOUT = 0mA, E = VIL
,
Asynchronous Read/Write
Random at tRC min
(4)
25
15
mA
mA
ICC1
V
(4)
Asynchronous Page Read
ICC2
104MHz
80MHz
104MHz
80MHz
104MHz
80MHz
35
30
mA
mA
mA
mA
mA
mA
µA
V
IN = 0V or VCCQ
Burst, Initial Read/Write
Access
(4)
ICC3
IOUT = 0mA, E = VIL
30
V
IN = 0V or VCCQ
IOUT = 0mA, E = VIL
IN = 0V or VCCQ
IOUT = 0mA, E = VIL
(4)
Continuous Burst Read
ICC4R
25
35
V
(4)
Continuous Burst Write
Full Array
ICC4W
30
140
120
110
105
95
1/2 Array
µA
Partial Array
VIN = 0V or VCCQ
(4)
Refresh Standby 1/4 Array
µA
IPASR
E = VCCQ
Current
1/8 Array
µA
None
µA
V
IN = 0V or VCCQ
(5)
Standby Current
140
10
µA
µA
ISB
E = VCCQ
VIN = 0V or VCCQ,
ICCPD
Deep-Power Down Current
3
VCC, VCCQ = 1.95V; TA= +85°C
1. BCR5-BCR4 = 01 (default settings).
2. Input signals may overshoot to V
+ 1.0V for periods of less than 2ns during transitions.
CCQ
3. Output signals may undershoot to V – 1.0V for periods of less than 2ns during transitions.
SS
4. This parameter is specified with all outputs disabled to avoid external loading effects. The user must add the current
required to drive output capacitance expected for the actual system.
5.
I
maximum value is measured at +85°C with PAR set to Full Array. In order to achieve low standby current, all inputs must
SB
be driven either to V
mode.
or V
. I might be slightly higher for up to 500ms after Power-up, or when entering Standby
SSQ SB
CCQ
40/73
M69KB096AB
9 DC and AC parameters
Table 17. Asynchronous Read AC Characteristics
Parameter(1)
Symbol
Alt.
Min
Max
Unit
tAVQV
tLLQV
tLHAX
tLHRL
tAVLH
tRHLH
tAA
Address Valid to Output Valid
70
70
ns
ns
tAADV
Latch Enable Low to Output Valid
Latch Enable High to Address Transition
tAVH
2
5
ns
ns
Latch Enable High to Configuration Register Low
Address Valid to L High
tAVS
Configuration Register High to L High
tBLQV
tBA
Upper/Lower Byte Enable Low to Output Valid
Upper/Lower Byte Enable High to Output Hi-Z
70
8
ns
ns
(2)
tBHZ
tBHQZ
(3)
tBLZ
tCEW
tCO
Upper/Lower Byte Enable Low to Output Transition
Chip Enable Low to WAIT Valid
10
1
ns
ns
ns
ns
tBLQX
tELTV
tELQV
tELLH
7.5
70
Chip Enable Low to Output Valid
Chip Enable Low to L High
tCVS
7
5
Chip Enable High between Subsequent Asynchronous
Operations
tEHEL
tCPH
ns
ns
Output Enable High to Output Hi-Z
Chip Enable High to Output Hi-Z
(2)
tHZ
tLZ
tOE
8
tEHQZ
(3)
Chip Enable Low to Output Transition
Output Enable Low to Output Valid
Output Enable Low to Output Hi-Z
10
ns
ns
ns
tELQX
tGLQV
20
8
(2)
tOHZ
tGHQZ
(3)
tOLZ
tRC
tVP
Output Enable Low to Output Transition
Read Cycle Time
3
70
5
ns
ns
ns
tGLQX
tAVAX
tLLLH
Latch Enable Low Pulse Width
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
2. The Hi-Z timings measure a 100mV transition from either V or V to V /2.
CCQ
OH
OL
3. The Low-Z timings measure a 100mV transition from the Hi-Z (V
/2) level to either V or V
.
OL
CCQ
OH
Table 18. Asynchronous Page Read AC Characteristics
Parameter(1)
Symbol
Alt.
Min
Max
Unit
tAVQV1
tAVAV
tELEH
tAVQX
tAPA
tPC
tCEM
tOH
Page Access Time
Page Cycle Time
20
20
ns
ns
µs
ns
Maximum Chip Enable Pulse Width
Data Hold from Address Change
4
5
1. These timings have been obtained in the measurement conditions described in Figure 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
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9 DC and AC parameters
M69KB096AB
Figure 14. Asynchronous Random Read AC Waveforms
tAVAX
Addr.
VALID ADDRESS
tAVQV
L
tEHEL
tEHQZ
tBHQZ
tGHQZ
E
tELQV
LB/UB
tBLQV
G
tGLQV
W
tGLQX
tBLQX
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VALID
OUTPUT
DQ0-DQ15
tELQX
tELTV
WAIT
AI11276c
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M69KB096AB
9 DC and AC parameters
Figure 15. Latch Enable Controlled, Asynchronous Random Read AC Waveforms
VALID
ADDRESS
Addr.
tAVQV
tAVLH
tLLLH
tLHAX
L
tEHQZ
tEHEL
tLLQV
E
tELQV
tELLH
G
tGHQZ
tGLQV
tGLQX
LB/UB
tBLQV
tBLQX
tBHQZ
Hi-Z
Hi-Z
VALID
OUTPUT
DQ0-DQ15
tELQX
AI11567
43/73
9 DC and AC parameters
M69KB096AB
Figure 16. Asynchronous Page Read AC Waveforms (4 Words)
tAVAX
VALID ADDRESS
A2-A22
Page Address
A0-A1
X
Y
Z
A
tAVAV
tAVAV
tAVAV
L
tELEH
E
tELQV
tBHQZ,
tEHQZ,
tGHQZ
tGLQV, tBLQV
G, LB,UB
tAVQV
tAVQV1
Hi-Z
DQ0-DQ15
DQN+X
DQN+Y
DQN+Z
DQN+A
tAVQX
AI11568
1. Any address can be used as starting address.
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M69KB096AB
9 DC and AC parameters
Figure 17. CR Controlled Configuration Register Read Followed by Read, Asynchronous Mode
Addr.
(Except A18-A19)
ADDRESS
tRHLH
ADDRESS
A18-19
tLHRL
Select Configuration Register
tAVQV
CR
L
tLLLH
tEHEL
tLLQV
Initiate Configuration Register Access
E
tEHQZ
tELQV
G
W
tGLQX
tELQX
LB/UB
Configuration Register
Data Valid
Data Valid
DQ0-DQ15
AI11566
1. A18-A19 must be set to ‘00b’ to select RCR, ‘01b’ to select the BCR and ‘1Xb’ to select the DIDR.
45/73
9 DC and AC parameters
M69KB096AB
Table 19. Asynchronous Write AC Characteristics
Parameter(1)
Symbol
Alt.
Min Max
Unit
tAVBL
tAVEL
tAVWL
tLLWL
tAS
Address Set-up to Beginning of Write Operation
0
ns
tLHAX
tLHRL
tAVLH
tRHLH
Latch Enable High to Address Transition or
tAVH
2
5
ns
ns
Latch Enable High to Configuration Register Low
Address Valid to Latch Enable High
tAVS
Configuration Register High to Latch Enable High
tAVWH
tAVEH
tAVBH
tAW
Address Set-up to End of Write Operation
70
70
ns
ns
tBLBH
tBLEH
tBLWH
tBW
Upper/Lower Byte Enable Low to End of Write Operation
tELTV
tEHEL
tELLH
tCEW
tCPH
tCVS
Chip Enable Low to WAIT Valid
1
5
7
7.5
ns
ns
ns
Chip Enable High between Subsequent Asynchronous Operations
Chip Enable Low to L High
tELWH
tELEH
tELBH
tCW
Chip Enable Low to End of Write Operation
Input Hold from Write
70
0
ns
ns
tEHDX
tWHDX
tBHDX
tDH
tELWH
tDVBH
tDVEH
tDVWH
tDW
Input Valid to Write Setup Time
20
ns
ns
Chip Enable High to WAIT Hi-Z
LB/UB High to WAIT Hi-Z
tEHTZ
tHZ
8
(2)
tBHTZ
Write Enable High to WAIT Hi-Z
tLLWH
tAVAX
tVS
tWC
tOW
Latch Enable Low to Write Enable High
Write Cycle Time
70
70
5
ns
ns
ns
tWHQZ
End of Write to Input Low-Z
tWLBH
tWLEH
tWP
Write Pulse Width
45
ns
(3)
tWLWH
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M69KB096AB
9 DC and AC parameters
Parameter(1)
Write Enable Pulse Width High
Symbol
Alt.
Min Max
Unit
tWHWL
tWPH
10
ns
tWHAX
tEHAX
tBHAX
tWR
Write Recovery Time
0
ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
2. The Hi-Z timings measure a 100mV transition from either V or V to V /2. The Low-Z timings measure a 100mV
CCQ
OH
.
OL
transition from the Hi-Z (V
/2) level to either V
or V
CCQ
OH
OL
3. W Low time must be limited to t
.
EHEL
Figure 18. Chip Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
Addr.
VALID ADDRESS
tAVEH
tEHAX
L
tAVEL,
tAVBL
tELEH
tBLEH
tEHEL
E
LB/UB
G
tWHWL
tLLWL
tWLEH
W
tEHDX
tDVEH
DQ0-DQ15
Hi-Z
VALID INPUT
tELTV
tEHTZ
Hi-Z
WAIT
Hi-Z
AI11284b
1. Data Inputs are Hi-Z if E is High, V
.
IH
47/73
9 DC and AC parameters
M69KB096AB
Figure 19. Upper/Lower Byte Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
Addr.
L
VALID ADDRESS
tAVBH
tBHAX
tELBH
tBLBH
E
LB/UB
G
tWHWL
tLLWL
tWLBH
tDVBH
W
tBHDX
Hi-Z
DQ0-DQ15
IN
VALID INPUT
tELQX
Hi-Z
tWLQZ
DQ0-DQ15
OUT
DON'T CARE
tELTV
tBHTZ
Hi-Z
WAIT
Hi-Z
AI11285b
1. Data Inputs are Hi-Z if E is High, V
.
IH
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M69KB096AB
9 DC and AC parameters
Figure 20. Write Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
Addr.
VALID ADDRESS
tAVWH
tWHAX
L
tELWH
tBLWH
E
LB/UB
G
tWLWH
tWHWL
W
tAVWL
tWHDZ
tWHDX
tDVWH
tLLWL
Hi-Z
DQ0-DQ15
VALID INPUT
tELTV
Hi-Z
WAIT
Hi-Z
AI11569
1. Data Inputs are Hi-Z if E is High, V
.
IH
49/73
9 DC and AC parameters
M69KB096AB
Figure 21. L Controlled, Asynchronous Write AC Waveforms
Addr.
VALID ADDRESS
tAVLH
tLHAX
tLLWH
tLLLH
L
tAVWH
tELWH
E
tBLWH
LB/UB
G
tWLWH
tDVWH
tWHWL
W
tLLWL
tEHDX
DQ0-DQ15
Hi-Z
tELTV
VALID INPUT
WAIT
Hi-Z
Hi-Z
AI11570
1. Data Inputs are Hi-Z if E is High, V
.
IH
50/73
M69KB096AB
9 DC and AC parameters
Figure 22. CR Controlled Configuration Register Program, Asynchronous Mode
(3)
OPCODE
Addr.
(Except A18-A19)
tAVLH
tLHAX
A18-A19
L
00(RCR), 01 (BCR)
tLLLH
E
Access to Configuration Register
G
W
tWLWH
A0-A15 Latched
into Register
CR
tRHLH
tLHRL
LB, UB
AI11571
1. Only the content of the Bus Configuration Register (BCR) and Refresh Configuration Register (RCR) can be modified.
2. Data Inputs/Outputs are not used.
3. The Opcode is the value to be written the configuration register.
4. W must go High after L goes High
5. CR is latched on the rising edge of L. There is no setup requirement of CR with respect to E.
51/73
9 DC and AC parameters
M69KB096AB
Table 20. Clock Related AC Timings
104MHz
80MHz
Symbol
Alt.
Parameter
Unit
Min
Max
Min
Max
fCLk
fCLk
tCLK
tKHKL
Clock frequency
Clock Period
104
1.6
80
MHz
ns
tKHKH
9.62
12.5
tR
tF
Clock Rise Time
Clock Fall Time
1.8
ns
ns
tKHKL
tKLKH
Clock High to Clock Low
Clock Low to Clock High
tKP
3
4
Table 21. Synchronous Burst Read AC Characteristics
104MHz
80MHz
Min
Parameter(1)
Symbol
Alt.
Unit
Min
Max
Max
70
70
46
9
tAVQV
tLLQV
tKHQV1
tKHQV2
tAA
Address Valid to Output Valid (Fixed Latency)
Latch Enable Low to Output Valid (Fixed Latency)
Burst to Read Access Time (Variable Latency)
Clock High to Output Delay
70
70
35
7
ns
ns
ns
ns
tAADV
tABA
tACLK
Delay From Output Enable Low to Output Valid in
Burst mode
tGLQV
tBOE
20
20
ns
Chip Enable High between Subsequent Operations
in Full-Synchronous or NOR-Flash mode.
(2)
tCBPH
tCEM
5
6
ns
µs
tEHEL
(2)
Chip Enable Pulse Width
4
4
tELEH
tELTV
tLLTV
Chip Enable Low to WAIT Valid
Latch Enable Low to WAIT Valid
tCEW
1
3
7.5
70
1
4
7.5
70
ns
tELQV
tELKH
tKHAX
tCO
Chip Enable Low to Output Valid
Chip Enable Low to Clock High
ns
ns
tCSP
tKHBH
tKHWL
tHD
Hold Time From Active Clock Edge
2
2
ns
tKHEH
tKHLH
tKHQX
tEHQZ
tHZ
Chip Enable High to Output Hi-Z or WAIT Hi-Z
8
8
ns
(3)
tEHTZ
tKHTX
tKHTV
tKHTL
tOHZ
Clock High to WAIT Valid
7
8
9
8
ns
ns
(3)
Output Enable High to Output Hi-Z
tGHQZ
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M69KB096AB
9 DC and AC parameters
104MHz
Min Max
80MHz
Unit
Parameter(1)
Symbol
Alt.
Min
Max
(4)
tOLZ
Output Enable Low to Output Transition
3
3
ns
tGLQX
tAVKH
tRHKH
tQVKH
tLLKH
tSP
Set-up Time to Active Clock Edge
3
3
ns
tBLKH
tWHKH
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
2. A refresh opportunity must be offered every t
of K; or if E is High for longer than 15ns.
. A refresh opportunity is possible either if E is High during the rising edge
ELEH
3. The Hi-Z timings measure a 100mV transition from either V or V to V /2.
CCQ
OH
OL
4. The Low-Z timings measure a 100mV transition from the Hi-Z (V
/2) level to either V or V
.
OL
CCQ
OH
Figure 23. Clock input AC Waveform
tKHKL
tKHKH
tr
tf
tKLKH
AI06981
53/73
9 DC and AC parameters
M69KB096AB
Figure 24. 4-Word Synchronous Burst Read AC Waveforms (Variable Latency Mode)
tKHKH
tKHKL
K
tAVKH
tKHAX
VALID
ADDRESS
Addr.
tKHLH
tLLKH
L
tELEH
tELKH
tKHQV1
tEHEL
tKHEH
E
tGLQV
tEHQZ
G
W
tGHQZ
tGLQX
tWHKH
tKHWL
tBLKH
tKHBH
LB/UB
tELTV
tKHTX
Hi-Z
Hi-Z
WAIT
tKHQX
tKHQV2
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Hi-Z
D0-D15
READ Burst Identified
(W = High)
AI11573
1. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted
during delay (BCR8=0).
54/73
M69KB096AB
9 DC and AC parameters
Figure 25. Synchronous Burst Read Suspend and Resume AC Waveforms
tKHKL
K
tAVKH
tAVLH
tKHAX
Valid
Address
Valid
Addr.
L
Address
tLLKH
tEHQZ
tEHEL
tKHLH
tELKH
E
tGHQZ
tGLQV
tGHQZ
tGLQX
G
tWHKH
tBLKH
tKHWL
tKHTX
tKHQV1
tGLQV
DON'T CARE
DON'T CARE
W
LB/UB
WAIT
Hi-Z
Hi-Z
Hi-Z
Valid
Valid
Valid
Valid
Valid
Valid
D0-D15
Output Output Output Output
Output Output
tKHQX
AI11287e
1. The latency Type (BCR14) can be set to fixed or variable during Burst Read Suspend operations.The Latency is set to 3
clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. During Burst Read Suspend operations, the Clock signal must be stable (High or Low).
3. G can be held Low, V , during Burst Suspend operations. If so, data output remain valid.
IL
55/73
9 DC and AC parameters
M69KB096AB
Figure 26. Burst Read Showing End-of-Row Condition AC Waveforms (No Wrap)
tKLKH, tKHKL
K
tKHKH
tF
Addr.
DON'T CARE
High
L
Low
Low
LB/UB
E
Note 2
Low
G
W
DON'T CARE
tKHTV
tEHTZ
tEHTZ
High-Z
WAIT
VALID
VALID
DQ0-DQ15
OUTPUT
OUTPUT
End of Row
AI11574
1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to
1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.
56/73
M69KB096AB
9 DC and AC parameters
Figure 27. Burst Read Interrupted by Burst Read or Write AC Waveforms
1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The
WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). All Burst operations are given for variable
latency and no refresh collision.
2. The Burst Read is interrupted during the first allowable clock cycle, i.e. after the first data is received by the microcontroller.
3. The Chip Enable signal, E, can remain Low, between burst operations, but it must not remain Low for longer than t
.
ELEH
4. If the latency is variable, WAIT is asserted t
falling edge.
after L is clocked Low. If the latency is fixed, WAIT is asserted t
after L
LLTV
KHTV
57/73
9 DC and AC parameters
M69KB096AB
Figure 28. CR Controlled Configuration Register Read Followed by Read, Synchronous Mode
K
Addr.
ADDRESS
(except A18-A19)
tAVKH
tRHKH
tLLKH
tELKH
tKHAX
tKHRL
ADDRESS
tLLKH
A18-A19
CR
tKHLH
L
tEHEL
tKHQV1
E
tEHQZ
tBLKH
G
tGLQV
tGLQV
tGHQZ
High
W
tBLKH
High-Z
UB, LB
WAIT
tELTV
tKHQV2
tGLQX
CR VALID
DATA VALID
DQ0-DQ15
tKHQX
ai10132f
1. A18-A19 must be set to ‘00b’ to select RCR, ‘01b’ to select BCR and ‘1Xb’ to select the DIDR.
58/73
M69KB096AB
9 DC and AC parameters
Table 22. Synchronous Burst Write AC Characteristics
104MHz
80MHz
Unit
Parameter(1)
Symbol Alt.
Min
Max
Min
Max
tAVWL
tAS
Address Set-up to Beginning of Write Operation
0
0
ns
(2)
tLLWL
tLHAX
tAVH
tCBPH
tCEM
Latch Enable High to Address Transition (Fixed Latency)
2
5
2
6
ns
ns
µs
Chip Enable High between Subsequent Operations in
Full-Synchronous or NOR-Flash mode.
(3)
tEHEL
(3)
Maximum Chip Enable Low Pulse
Chip Enable Low to WAIT Valid
Chip Enable Low to Clock High
4
4
tELEH
tELTV
tLLTV
tCEW
tCSP
1
3
7.5
1
4
7.5
ns
ns
tELKH
tKHAX
tKHRL
tKHLH
tKHDX
tKHEH
tKHBH
tKHWH
tHD
Hold Time From Active Clock Edge
2
4
2
6
ns
Last Clock Rising Edge to Latch Enable Low (Fixed
Latency)
tKHLL
tKADV
ns
ns
ns
tEHDZ
tHZ
Chip Enable High to Input Hi-Z or WAIT Hi-Z
Clock High to WAIT Valid or Low
8
7
8
9
(4)
tEHTZ
tKHTV
tKHTL
tKHTX
tAVKH
tDVKH
tWLKH
tLLKH
tSP
Set-up Time to Active Clock Edge
3
3
ns
tBLKH
tWHKH
tWHWL
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 13: AC Measurement Load Circuit.
2.
t
and t
, are required if t
> 20ns.
AVWL
LLWL
ELKH
3. A refresh opportunity must be offered every t
of K; or if E is High for longer than 15ns.
. A refresh opportunity is possible either if E is High during the rising edge
ELEH
4. The Hi-Z timings measure a 100mV transition from either V or V to V /2.
CCQ
OH
OL
59/73
9 DC and AC parameters
M69KB096AB
Figure 29. 4-Word Synchronous Burst Write AC Waveforms (Variable Latency Mode)
tKHKH
K
VALID
ADDRESS
Addr.
tAVKH
tAVWL
tKHAX
tKHLH
tKHLL
tLLWL
L
tLLKH
tKHBH
tBLKH
LB/UB
tELEH
tELKH
tEHEL
E
tKHEH
High
G
tWLKH
tKHWH
W
tKHTX
tEHTZ
Hi-Z
tELTV
Hi-Z
Note 2
tDVKH
WAIT
tKHDX
VALID
INPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
D0-D15
Hi-Z
WRITE Burst Identified
(W = Low)
ai11288
1. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and asserted
during delay (BCR8=0).
2. The WAIT signal must remain asserted for LC clock cycles (LC Latency code), whatever the Latency mode (fixed or
variable).
3.
t
and t
, are required if t
> 20ns.
ELKH
AVLL
LLWL
60/73
M69KB096AB
9 DC and AC parameters
Figure 30. Burst Write Showing End-of-Row Condition AC Waveforms (No Wrap)
tKLKH
K
tKHKH
tF
Addr.
DON'T CARE
L
LB/UB
Note 2
E
High
G
W
DON'T CARE
tKHTV
tKHDX
tEHTZ
tEHTZ
High-Z
WAIT
tDVKH
VALID
INPUT D[n]
VALID
INPUT D[n+1]
DQ0-DQ15
End of Row
(A6-A0 = 7Fh)
ai11575
1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to
1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.
61/73
9 DC and AC parameters
M69KB096AB
Figure 31. Synchronous Burst Write Followed by Read AC Waveforms (4 Words)
1. The Latency type can set to fixed or variable mode. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT
signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. E can remain Low between the Burst Read and Burst Write operation, but it must not be held Low for longer than t
.
ELEH
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M69KB096AB
9 DC and AC parameters
Figure 32. Burst Write Interrupted by Burst Write or Read AC Waveforms
1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The
WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). All Burst operations are given for variable
latency and no refresh collision.
2. The Burst Write is interrupted during the first allowable clock cycle, i.e. after the first Word written to the memory.
3. The Chip Enable signal, E, can remain Low, V , between burst operations, but it must not remain Low for longer than
IL
t
.
ELEH
63/73
9 DC and AC parameters
M69KB096AB
Figure 33. CR Controlled Configuration Register Program, Synchronous Mode
K
Addr.(3)
Opcode
tAVKH
tKHAX
tKHRL
tKHLH
00 (RCR)
01 (BCR)
A18-A19(4)
tRHKH
(5)
CR
tLLKH
tELEH
L
E
G
tWLKH
tKHWH
W
UB, LB
(2)
DQ0-DQ15
tELTV
Hi-Z
WAIT
AI10131d
1. Only the Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
2. Data Inputs/Outputs are not used.
3. The Opcode is the value to be written in the Configuration Register.
4. A19 gives the Configuration Register address.
5. CR initiates the Configuration Register Access.
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M69KB096AB
9 DC and AC parameters
Table 23. Power-Up and Deep Power-Down AC Characteristics
Symbol
tPU
Alt.
tPU
Parameter
Min
150
10
Max
Unit
µs
Initialization delay after Power-Up or Deep Power-Down Exit
Deep Power-Down Entry to Deep Power-Down Exit
Chip Enable Low to Deep Power-Down Exit
tEHEL(DP)
tELEH(DP)
tDPD
tDPDX
µs
10
µs
Figure 34. Power-Up AC Waveforms
E
tPU
1.7V
V
, V
CC CCQ
Device Ready
for Normal Operation
Device Initialization
AI09465d
1. Power must be applied to V prior to or at the same time as V
.
CCQ
CC
Figure 35. Deep Power-Down Entry and Exit AC Waveforms
E
tEHEL(DP)
tELEH (DP)
tPU
Deep Power-Down
Entry (RCR4= 0)
Deep Power-Down Deep Power-Down Device Initialization
Mode Exit
Device Ready
for Normal Operation
AI11306
65/73
10 Wafer and die specifications
M69KB096AB
10 Wafer and die specifications
Table 24. Dimensions
Wafer Diameter
200mm (8")
Wafer Thickness
750± 25µm (29.5±1.0mil)
5,009.365µm x 5,005.795µm
Die Size (stepping interval)
Street Width Along X-Axis (dsw_X) 102µm
Street Width Along Y-Axis (dsw_Y) 102µm
Center of Street (COS) (relative to
X = -222.98µm, Y = 160.08µm (X = -8.779mil, Y = 6.303mil)
Bond Pad 1)
Bond Pad Size
85µm x 100µm (3.35mil x 3.94mil)
75µm x 90µm (2.95mil x 3.54mil)
119.00µm (4.685mil)
71
Passivation Openings (MIN)
Minimum Bond Pad Pitch
Pad Count
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M69KB096AB
10 Wafer and die specifications
Figure 36. Die Outline
dsw_X
dsw_Y
COS
1 2 3 4 5 6 7 8 9 10111213141516171819
20
21222324252627282930313233343536
y
x
-x
Center of Die
-y
Die Orientation with Respect
to Wafer Notch
39 38 37
71 70 69 68 67 66 65 64 62 61 60 59 58 57 56 55
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
Ai11630
1. Die streets are not to scale.
67/73
10 Wafer and die specifications
M69KB096AB
Table 25. Bond Pad Location and Identification
Pad Coordinates from Center of Die
Pad
Signal
X (µm)(1)
Y (µm)(1)
X (inches) (1)
Y (inches)(1)
1
2
3
4
5
6
7
A0
A1
-2,281.70
-2,162.70
-2,043.70
-1,924.70
-1,805.70
-1,686.70
-1,567.70
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
-0.0898306
-0.0851456
-0.0804605
-0.0757755
-0.0710905
-0.0664054
-0.0617204
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
A2
A3
A4
A5
VCCQ
VSSQ
8
-1,448.70
-1,329.70
-1,210.70
-1,091.70
-972.70
-853.70
-734.70
-615.70
-496.70
-377.70
-258.70
-139.70
135.79
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
-0.0570353
-0.0523503
-0.0476653
-0.0429802
-0.0382952
-0.0336101
-0.0289251
-0.0242401
-0.0195550
-0.0148700
-0.0101849
-0.0054999
0.0053460
0.0148097
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
9
A6
A7
A17
A18
A19
E
10
11
12
13
14
15
16
17
18
19
20
21
LB
UB
CR
L
W
K
VCC
376.17
VSS
22
23
24
25
26
27
28
495.17
614.17
733.17
852.17
971.17
1,090.17
1,209.17
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
0.0194948
0.0241798
0.0288649
0.0335499
0.0382349
0.0429200
0.0476050
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
A20
A21
DNU(2)
A8
A9
VSSQ
VCCQ
29
30
31
32
33
1,328.17
1,447.17
1,566.17
1,685.17
1,804.17
2,342.81
2,342.81
2,342.81
2,342.81
2,342.81
0.0522901
0.0569751
0.0616601
0.0663452
0.0710302
0.0922367
0.0922367
0.0922367
0.0922367
0.0922367
A10
A11
A12
A13
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M69KB096AB
10 Wafer and die specifications
34
35
36
37
38
39
40
A14
A15
1,923.17
2,042.17
2,161.17
2,139.96
1,961.46
1,842.46
1,723.46
2,342.81
2,342.81
2,342.81
-2,317.02
-2,317.02
-2,317.02
-2,317.02
0.0757153
0.0922367
0.0922367
0.0922367
-0.0912211
-0.0912211
-0.0912211
-0.0912211
0.0804003
0.0850853
0.0842504
0.0772228
0.0725378
0.0678528
A16
WAIT
DQ15
DQ7
VCCQ
VSSQ
41
42
43
44
45
46
1,604.46
1,485.46
1,366.46
1,247.46
1,128.46
1,009.46
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-2,317.02
0.0631677
0.0584827
0.0537976
0.0491126
0.0444276
0.0397425
-0.0912211
-0.0912211
-0.0912211
-0.0912211
-0.0912211
-0.0912211
DQ14
DQ6
DQ13
DQ5
VCCQ
VSSQ
47
48
49
50
51
890.46
771.46
652.46
533.46
414.46
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-2,317.02
0.0350575
0.0303724
0.0256874
0.0210024
0.0163173
-0.0912211
-0.0912211
-0.0912211
-0.0912211
-0.0912211
DQ12
DQ4
NC
DNU(2)
DNU(2)
52
53
54
55
56
57
295.46
176.46
57.46
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-2,317.02
0.0116323
0.0069472
0.0022622
-0.0071079
-0.0117929
-0.0164780
-0.0912211
-0.0912211
-0.0912211
-0.0912211
-0.0912211
-0.0912211
DNU(2)
VSS
VCC
-180.54
-299.54
-418.54
DNU(2)
DNU(2)
DNU(2)
G
58
59
60
61
62
-537.54
-656.54
-775.54
-894.54
-1,013.54
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-0.0211630
-0.0258480
-0.0305331
-0.0352181
-0.0399031
-0.0912211
-0.0912211
-0.0912211
-0.0912211
-0.0912211
DQ11
DQ3
VSSQ
VCCQ
63
64
65
66
67
68
-1,132.54
-1,251.54
-1,370.54
-1,489.54
-1,608.54
-1,727.54
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-2,317.02
-0.0445882
-0.0492732
-0.0539583
-0.0586433
-0.0633283
-0.0680134
-0.0912211
-0.0912211
-0.0912211
-0.0912211
-0.0912211
-0.0912211
DQ10
DQ2
DQ9
DQ1
VSSQ
69/73
10 Wafer and die specifications
M69KB096AB
VCCQ
69
70
71
-1,846.54
-1,965.54
-2,084.54
-2,317.02
-2,317.02
-2,317.02
-0.0726984
-0.0773835
-0.0820685
-0.0912211
-0.0912211
-0.0912211
DQ8
DQ0
1. Reference from the center of each bond pad to the center of the die (0,0).
2. DNU stands for ‘do not use’.
70/73
M69KB096AB
11 Part numbering
11 Part numbering
Table 26. Ordering Information Scheme
Example:
M69KB096AB
80 C W 8
Device Type
M69 = PSRAM
Mode
K = Bare Die
Operating Voltage
B = VCC = 1.7 to 1.95V, Burst, Address/Data bus standard x16
Array Organization
096 = 64 Mbit (4 Mbit x16)
Option 1
A = 1 Chip Enable
Silicon Revision
B = B Die
Speed Class
80 = 80ns
Maximum clock frequency
C = 80MHz
D = 104MHz
Package
W = Unsawn Wafer
Operating Temperature
8 = –30 to 85 °C
The notation used for the device number is as shown in Table 26. Not all combinations are
necessarily available. For a list of available options (speed, package, etc.) or for further
information on any aspect of this device, please contact your nearest STMicroelectronics Sales
Office.
71/73
12 Revision history
M69KB096AB
12 Revision history
Table 27. Document Revision History
Date
Rev.
Revision Details
29-Nov-2005
1
First Issue
72/73
M69KB096AB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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73/73
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