M72DW64000B70ZT [STMICROELECTRONICS]
64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product; 64Mbit的（ X8 / X16 ，多个银行，引导块）快闪记忆体和16Mbit的SRAM伪， 3V电源，多个存储产品
| 型号： | M72DW64000B70ZT |
| 厂家： | 
ST |
| 描述： | 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product |
| 文件： | 总19页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M72DW64000B
64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and
16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY
■ MULTIPLE MEMORY PRODUCT
Figure 1. Package
– 64Mbit (8M x8 or 4M x16), Multiple Bank, Page,
Boot Block, Flash Memory
– 16Mbit (1M x 16) Pseudo Static RAM
■ SUPPLY VOLTAGE
– V
– V
= V
= 2.7 to 3.3V
CCF
PPF
CCP
= 12V for Fast Program (optional)
FBGA
■ ACCESS TIME: 70, 90ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
LFBGA73 (ZA)
8 x 11.6mm
– Device Code: 227Eh + 2202h + 2201h
FLASH MEMORY
■ ASYNCHRONOUS PAGE READ MODE
– Page Width: 4 Words
– Page Access: 25, 30ns
■ PROGRAMMING TIME
– 10µs per Byte/Word typical
– 4 Words/ 8 Bytes at-a-time Program
■ MEMORY BLOCKS
■ V /WP PIN for FAST PROGRAM and WRITE
PP
PROTECT
■ TEMPORARY BLOCK UNPROTECTION
MODE
– Quadruple Bank Memory Array:
8Mbits + 24Mbits + 24Mbits + 8Mbits
■ COMMON FLASH INTERFACE
– 64 bit Security Code
– Parameter Blocks (at both Top and Bottom)
■ DUAL OPERATIONS
■ EXTENDED MEMORY BLOCK
– While Program or Erase in a group of banks
(from 1 to 3), Read in any of the other banks
– Extra block used as security block or to store
additional information
■ PROGRAM/ERASE SUSPEND and RESUME
■ 100,000 PROGRAM/ERASE CYCLES per
MODES
BLOCK
– Read from any Block during Program
Suspend
PSRAM
■ ACCESS TIME: 70ns
■ DEEP POWER DOWN CURRENT: 10µA
– Read and Program another Block during
Erase Suspend
■ LOW V
DATA RETENTION: 2.3V
CC
■ UNLOCK BYPASS PROGRAM COMMAND
■ LOW STANDBY CURRENT: 70µA
– Faster Production/Batch Programming
October 2003
1/19
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M72DW64000B
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash-1 Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
Write Protect (V WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PP/ PP/
Reset/Block Temporary Unprotect (RPF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Chip Enable inputs (E1P, E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Upper Byte Enable (UBP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
V
V
Supply Voltage (2.7 to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Supply Voltage (2.7 to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CCF
CCP
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SS
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY DEVICES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Flash DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. PSRAM DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/19
M72DW64000B
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline15
Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . . 16
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3/19
M72DW64000B
SUMMARY DESCRIPTION
The M72DW64000B is a low voltage Multiple
Memory Product which combines two memory de-
vices; a 64 Mbit Multiple Bank, Boot Block Flash
memory (M29DW640D) and a 16 Mbit Pseudo
SRAM. This document should be read in conjunc-
tion with the M29DW640D and M69AW024B
datasheets.
Table 1. Signal Names
Address Inputs common to the Flash
Memory and PSRAM Components
A0-A19
DQ0-DQ7
DQ8-DQ14
DQ15A–1
G
Data Inputs/Outputs
Data Inputs/Outputs
Recommended operating conditions do not allow
more than one of the internal memory devices to
be active at the same time.
Data Input/Output or Address Input
Output Enable Input
The memory is offered in an LFBGA73
(8 x 11.6mm, 0.8 mm pitch) package and is sup-
plied with all the bits erased (set to ‘1’).
W
Write Enable Input
V
CCF
Flash Memory Power Supply
Figure 2. Logic Diagram
V
V
/WP
V
/Write Protect
PP
PP
Ground
SS
V
/WP
V
PP
V
CCP
PSRAM Power Supply
Not Connected Internally
V
CCF
CCP
NC
22
Flash Memory Control Functions
A0-A21
A20-A21
Address Inputs
15
E
Flash-1 Chip Enable Input
Reset/Block Temporary Unprotect
Ready/Busy Output
F
DQ0-DQ14
DQ15A–1
E
F
RP
F
G
RB
W
M72DW64000B
BYTE
Byte/Word Organization Select
RB
RP
F
PSRAM Control Functions
BYTE
E1 , E2
Chip Enable Inputs
P
P
UB
Upper Byte Enable Input
Lower Byte Enable Input
E1
P
P
LB
P
E2
P
UB
P
P
LB
V
SS
AI08527
4/19
M72DW64000B
Figure 3. LFBGA Connections (Top view through package)
9
10
1
2
3
4
5
6
7
8
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
V
/WP
PP
A8
A19
A9
A7
A6
A5
A4
A11
A12
A13
A14
NC
W
LB
S
A3
A2
A1
A0
UB
RP
F
E2S
A20
A15
A21
NC
S
A18
A17
DQ1
RB
NC
NC
A10
DQ6
NC
NC
G
H
J
V
A16
SS
DQ15
/A-1
E
F
G
DQ9
DQ10
DQ2
DQ3
DQ4
DQ13
DQ12
DQ5
BYTE
E1
V
V
V
DQ0
DQ8
DQ7
S
CCF
DQ11
NC
CCS
SS
K
M
N
NC
DQ14
NC
NC
NC
NC
NC
AI08528
5/19
M72DW64000B
SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
quired for Program operations. This is achieved
by bypassing the unlock cycles and/or using the
multiple Word (2 or 4 at-a-time) or multiple Byte
Program (2, 4 or 8 at-a-time) commands. The
Write Protect function provides a hardware meth-
od of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the ad-
dress space).
Address Inputs (A0-A21). Address lines A0-A19
are common inputs for the Flash Memory and
PSRAM components. Address line A20-A21 are
inputs for the Flash Memory component. The Ad-
dress Inputs select the cells in the memory array
to access during Bus Read operations. During Bus
Write operations they control the commands sent
to the Command Interface of the internal state ma-
chine. The Flash memory is accessed through the
When V /Write Protect is Low, V , the memory
PP
IL
protects the four outermost boot blocks; Program
and Erase operations in these blocks are ignored
while V /Write Protect is Low, even when RP is
PP
F
Chip Enable (E ) and Write Enable (W) signals,
at V .
F
ID
while the PSRAM is accessed through two Chip
Enable signals (E1S and E2S) and the Write En-
able signal (W).
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
When V /Write Protect is High, V , the memory
PP
IH
reverts to the previous protection status of the four
outermost boot blocks (two at the top, and two at
the bottom of the address space). Program and
Erase operations can now modify the data in these
blocks unless the blocks are protected using Block
Protection.
When V /Write Protect is raised to V the mem-
PP
PP
ory automatically enters the Unlock Bypass mode.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
When V /Write Protect returns to V or V nor-
PP
IH
IL
mal operation resumes. During Unlock Bypass
Program operations the memory draws I from
PP
V . When BYTE is Low, V , these pins are not
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
IH
IL
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
V
than t
to V
VHVPP
and from V
. See the M29DW640D datasheet for
to V must be slower
IH
PP
PP IH
more details.
Never raise V /Write Protect to V from any
PP
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
Data Input/Output or Address Input (DQ15A–
1). When BYTE is High, V , this pin behaves as
IH
PP
a Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V , this pin behaves as an address
IL
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
The V /Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1µF capacitor should be connected be-
PP
tween the V /Write Protect pin and the V
PP
SS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Flash-1 Chip Enable (E ). The Chip Enable in-
Unlock Bypass Program, I
.
PP
F
put activates the memory to which it is attached,
allowing Bus Read and Bus Write operations to be
Reset/Block Temporary Unprotect (RP ). The
F
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
performed. When Chip Enable is High, V , all oth-
IH
er pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the Flash Memory
and PSRAM components.
Note that if V /WP is at V , then the two outer-
PP
IL
most boot blocks will remain protected even if RP
F
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the Flash Memory and
PSRAM components.
is at V .
ID
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V , for at least
IL
V
Write Protect (V /WP). The
V
/Write
PP
t
. After Reset/Block Temporary Unprotect
PP/
PP
PP
PLPX
Protect pin provides two functions. The V func-
goes High, V , the memory will be ready for Bus
IH
tion allows the Flash memory to use an external
high voltage power supply to reduce the time re-
Read and Bus Write operations after t
or
PHEL
6/19
M72DW64000B
t
,
whichever occurs last. See the
M29DW640D datasheet for more details.
Holding RP at V will temporarily unprotect the
gardless of the level of E1 . E1 and E2 can also
P P P
RHEL
be used to control writing to the PSRAM memory
array, while W remains at V It is not allowed to
P
IL.
F
ID
set E at V E1 at V and E2 at V at the
F1
IL,
P
IL
P
IH
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
same time.
The transition from V to V must be slower than
PSRAM Upper Byte Enable (UB ). The Upper
Byte Enable input enables the upper byte for
IH
ID
P
t
.
PHPHH
PSRAM (DQ8-DQ15). UB is active low.
P
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the Flash memory is performing a Program
or Erase operation. During Program or Erase op-
PSRAM Lower Byte Enable (LB ). The Lower
P
Byte Enable input enables the lower byte for
PSRAM (DQ0-DQ7). LB is active low.
P
erations Ready/Busy is Low, V . Ready/Busy is
high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
OL
V
Supply Voltage (2.7 to 3.3V). V
pro-
CCF
CCF
vides the power supply for Flash memory opera-
tions (Read, Program and Erase).
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance.
The Command Interface is disabled when the
V
Supply Voltage is less than the Lockout Volt-
CCF
age, V
. This prevents Bus Write operations
LKO
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
Flash memory. When Byte/Word Organization Se-
from accidentally damaging the data during power
up, power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
CCF
SS
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
lect is Low, V , the Flash memory is in x8 mode,
IL
when it is High, V , the Flash memory is in x16
IH
mode.
Erase operations, I
.
CC3
PSRAM Chip Enable inputs (E1 , E2 ). The
V
Supply Voltage (2.7 to 3.3V). V
CCP
pro-
P
P
CCP
Chip Enable inputs activate the PSRAM control
logic, input buffers and decoders. E1 at V with
vides the power supply for the PSRAM.
P
IH
V
Ground. V is the ground reference for all
SS
SS
E2 at V deselects the memory, reducing the
P
IH
voltage measurements in the Flash and PSRAM
chips.
power consumption to the standby level, whereas
E2 at V deselects the memory and reduces the
P
IL
power consumption to the Power-down level, re-
7/19
M72DW64000B
FUNCTIONAL DESCRIPTION
The Flash Memory and PSRAM components have
a common power supply. The components are dis-
The most common example is simultaneous read
operations on the Flash Memory and PSRAM
components which would result in a data bus con-
tention. Therefore it is recommended, when read-
ing from one memory component, to put the other
in the high impedance state (see Table 2 Main Op-
eration Modes for details).
tinguished by four chip enable inputs: E for the
F
Flash memory, and E1 and E2 for the PSRAM.
P
P
Recommended operating conditions do not allow
more than one component (Flash Memory or
PSRAM) to be in active mode at the same time.
Table 2. Main Operation Modes
(2)
(3)
E
F1
RP
E1
E2
P
G
W
DQ15-DQ0
UB , LB
F
P
Operation Mode
P
P
Flash Memory Data
Output
V
V
V
V
IH
Read
IL
IL
IH
IL
PSRAM must be in Standby
Any PSRAM mode is allowed
Flash Memory Data
Input
V
V
V
V
V
V
V
Write
IH
IH
IL
Output Disable
Standby
X
IH
IH
IH
V
CC
V
IH
X
X
Flash Memory Hi-Z
±0.3
V
IL
Reset
X
X
X
Flash Memory
must be in
Standby
V
V
V
V
V
V
V
V
V
V
V
V
Read
PSRAM Data Output
PSRAM Data Input
IL
IH
IH
IH
IL
IL
IL
IH
IH
IH
IH
IL
IL
V
V
V
V
Write
IL
Output Disable
Standby
X
IH
Any Flash
Memory mode
is allowable
X
X
X
X
PSRAM Hi-Z
IH
V
Deep Power Down
X
X
X
IL
Note: 1. X = Don’t Care (V or V ).
IL
IH
2. UB and LB are tied together.
P
P
3. This table is valid when BYTE = V . This table is also valid when BYTE = V , with the only difference that DQ15-DQ8 are always
IH
IL
high impedance when the Flash Memory components are being accessed.
4. For the Block Protect and Unprotect features, refer to the M29DW640D datasheet. Only the In-System Technique is available in
the stacked product.
5. To read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Block indicator bit, refer to the
“Auto Select Command” in the M29DW640D datasheet.
8/19
M72DW64000B
Figure 4. Functional Block Diagram
V
V
/WP
PPF
CCF
A20-A21
E
F
64 Mbit
Flash
Memory
RB
F
RP
F
BYTE
F
A0-A19
DQ15/A-1 to DQ0
V
DDP
E1
E2
P
16 Mbit
PSRAM
G
W
P
UB
P
LB
P
V
SS
AI08529
9/19
M72DW64000B
FLASH MEMORY DEVICES
The M72DW64000B contains a 64Mbit Flash
memory. For detailed information on how to use it,
see the M29DW640D datasheet, which is avail-
able on the STMicroelectronics web site,
www.st.com.
PSRAM DEVICE
The M72DW64000B contains a 16Mbit Pseudo
SRAM. For detailed information on how to use it,
see the M69AW024B datasheet, which is avail-
able from your local STMicroelectronics distribu-
tor.
10/19
M72DW64000B
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
–40
Max
85
(1)
T
°C
°C
°C
V
A
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Flash Supply Voltage
Identification Voltage
T
–50
125
150
BIAS
T
–65
STG
V
IO
V
+0.3
–0.5
–0.6
–0.6
–0.6
–0.5
CCF
V
4
V
CCF
V
ID
13.5
13.5
3.6
V
V
PPF
Program Voltage
V
V
PSRAM Supply Voltage
V
CCP
Note: 1. Depends on range.
11/19
M72DW64000B
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 4,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
The operating and AC measurement parameters
given in this section (see Table 4 below) corre-
spond to those of the stand-alone Flash Memory
and PSRAM components. For compatibility pur-
poses, the M29DW640D voltage range is restrict-
ed to V
in the stacked product.
CCS
Table 4. Operating and AC Measurement Conditions
Flash Memory
PSRAM
Parameter
Supply Voltage
Units
Min
Max
3.6
–
Min
–
Max
V
V
2.7
–
–
V
V
CCF
Supply Voltage
2.7
–30
3.3
85
CCS
Ambient Operating Temperature
–40
85
°C
pF
ns
V
Load Capacitance (C )
30
50
L
Input Rise and Fall Times
10
4
0 to V
0 to V
V
Input Pulse Voltages
CCF
CCP
V
CCF
/2
/2
Input and Output Timing Ref. Voltages
V
CCP
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
V
CCF
V
CCF
V
/2
CCF
V
PP
0V
V
CCF
25kΩ
AI08186
DEVICE
UNDER
TEST
C
L
25kΩ
0.1µF
0.1µF
C
includes JIG capacitance
AI08187
L
Table 5. Device Capacitance
Symbol
Parameter
Test Condition
Typ
Max
12
Unit
C
V
= 0V, f=1 MHz
= 0V, f=1 MHz
Input Capacitance
Output Capacitance
pF
pF
IN
IN
C
OUT
V
OUT
15
Note: Sampled only, not 100% tested.
12/19
M72DW64000B
Table 6. Flash DC Characteristics
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±1
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
LO
0V ≤ V ≤ V
OUT CC
±1
µA
E = V , G = V ,
F
IL
IH
(2)
Supply Current (Read)
10
100
20
mA
µA
mA
I
CC1
f = 6MHz
E = V ±0.2V,
F
CC
I
Supply Current (Standby)
CC2
RP = V ±0.2V
F
CC
V
V
/WP =
or V
PP
Supply Current (Program/
Erase)
Program/Erase
Controller active
(1,2)
IL
IH
I
CC3
V
/WP = V
PP
20
mA
V
PP
V
V
Input Low Voltage
Input High Voltage
–0.5
0.8
IL
0.7V
V
+0.3
CC
V
IH
CC
Voltage for V /WP Program
PP
Acceleration
V
V
= 3.0V ±10%
11.5
12.5
V
V
I
CC
CC
PP
Current for V /WP Program
PP
Acceleration
= 3.0V ±10%
= 1.8mA
15
mA
PP
V
OL
I
I
Output Low Voltage
Output High Voltage
Identification Voltage
0.45
V
V
V
OL
V
OH
V
–0.4
= –100µA
CC
OH
V
11.5
1.8
12.5
2.3
ID
Program/Erase Lockout Supply
Voltage
V
LKO
V
Note: 1. Sampled only, not 100% tested.
2. In Dual operations the Supply Current will be the sum of I
(read) and I
CC1
(program/erase).
CC3
13/19
M72DW64000B
Table 7. PSRAM DC Characteristics
Symbol
Parameter
Test Condition
= 3.3V,
= V or V ,
IH IL
E1 = V , E2 = V , I = 0mA
IH OUT
Min
Max
Unit
t
t
/t
Min
=
=
RC WC
20
mA
V
DDP
Operating Supply
Current
(1)
V
I
IN
DD1
/t
RC WC
P
IL
P
3.0
1
mA
µA
µA
1µs
Input Leakage
Current
I
LI
0V ≤ V ≤ V
IN DDP
–1
–1
Output Leakage
Current
I
LO
0V ≤ V ≤ V
OUT DDP
1
V
= 3.3V,
= V or V ,
IH IL
DDP
Deep Power Down
Current
I
V
10
1.5
1
µA
mA
mA
PD
IN
E2 ≤ 0.2V
P
3.1V ≤ VDDP ≤ 3.3V,
= V or V ,
V
IN
IH
IL
E1 = V and E2 = V , I
IH OUT
= 0mA
= 0mA
P
IH
P
2.7V ≤ VDDP ≤ 3.1V,
= V or V ,
V
IN
IH
IL
E1 = V and E2 = V , I
IH OUT
P
IH
P
Standby Supply
Current CMOS
3.1V ≤ VDDP ≤ 3.3V,
≤ 0.2V or ≥ V –0.2V,
I
SB
V
IN
DDP
100
70
µA
µA
E1 ≥ V
–0.2V and
DDP
P
E2 ≥ V
–0.2V), I
= 0mA
OUT
P
DDP
2.7V ≤ VDDP ≤ 3.1V,
≤ 0.2V or ≥ V –0.2V,
V
IN
DDP
E1 ≥ V
–0.2V and
DDP
P
E2 ≥ V –0.2V), I
= 0mA
P
CC
OUT
V
V
+ 0.3
3.1V ≤ VDDP ≤ 3.3V
2.7V ≤ VDDP ≤ 3.1V
3.1V ≤ VDDP ≤ 3.3V
2.7V ≤ VDDP ≤ 3.1V
2.6
2.2
V
V
V
V
V
V
V
CC
(2)
(3)
Input High Voltage
Input Low Voltage
V
IH
+ 0.3
CC
–0.3
–0.3
2.5
0.6
V
IL
0.5
3.1V ≤ VDDP ≤ 3.3V, I
= –0.5mA
OH
V
Output High Voltage
Output Low Voltage
OH
2.7V ≤ VDDP ≤ 3.1V, I = –0.5mA
2.2
OH
V
V
= 3V, I = 1mA
OL
0.4
OL
DDP
Note: 1. Average AC current, Outputs open, cycling at t
(min).
AVAX
2. Maximum DC voltage on input and I/O pins is V
+ 0.3V.
DDP
During voltage transitions, input may positive overshoot to V
3. Minimum DC voltage on input or I/O pins is –0.3V.
+ 1.0V for a period of up to 5ns.
DDP
During voltage transitions, input may positive overshoot to V + 1.0V for a period of up to 5ns.
SS
14/19
M72DW64000B
PACKAGE MECHANICAL
Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
e
b
ddd
A
A2
A1
BGA-Z50
Note: Drawing is not to scale.
15/19
M72DW64000B
Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.400
0.0551
0.250
0.0098
0.910
0.400
8.000
7.200
0.0358
0.0157
0.3150
0.2835
0.350
7.900
0.450
8.100
0.0138
0.3110
0.0177
0.3189
D
D1
ddd
E
0.100
0.0039
0.4606
11.600
8.800
0.800
0.400
1.400
0.400
0.400
11.500
–
11.700
0.4567
0.3465
0.0315
0.0157
0.0551
0.0157
0.0157
0.4528
–
E1
e
–
–
FD
FE
SD
SE
–
–
–
–
–
–
–
–
16/19
M72DW64000B
PART NUMBERING
Table 9. Ordering Information Scheme
Example:
M72DW 6 4 0 0 0
B
70 Z T
Device Type
M72 = MMP (Flash + PSRAM)
Architecture
D = Dual Operation
Operating Voltage
W = V
= V
= 2.7V to 3.3V
CCP
CCF
Flash Memory Device Size (Die1 Density)
6 = 64 Mbit
PSRAM Device Size (Die2 Density)
4 = 16 Mbit
Die3
0 = none present
Die4
0 = none present
Flash Memory Specification Details
0 = Multiple Bank
Stacked Specification Details
B=0.15µm Flash Memory and 0.18µm PSRAM
Speed
70 = 70ns
90 = 90ns
Package and Temperature Range
Z = LFBGA73: 8 x 11.6mm, 0.8mm pitch
Option
T = Tape & Reel packing
Note: This product is also available with the Extended Block factory locked. For further details and ordering
information contact your nearest ST sales office.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
17/19
M72DW64000B
REVISION HISTORY
Table 10. Document Revision History
Date
Version
1.0
Revision Details
26-May-2003
24-Sep-2003
First Issue
Voltage supply range extended 2.7V working at all speed options
1.1
18/19
M72DW64000B
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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19/19
相关型号：
M72DW64000B90ZT
64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
STMICROELECTR
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