M74HC40103TTR [STMICROELECTRONICS]
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER; 8 STAGE预置同步DOWN COUNTER
| 型号： | M74HC40103TTR |
| 厂家： | 
ST |
| 描述： | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER |
| 文件： | 总16页 (文件大小：662K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M74HC40103
8 STAGE PRESETTABLE
SYNCHRONOUS DOWN COUNTER
■
■
■
■
■
■
■
HIGH SPEED :
= 38MHz (TYP.) at V = 6V
f
MAX
CC
LOW POWER DISSIPATION:
=4µA(MAX.) at T =25°C
I
CC
A
HIGH NOISE IMMUNITY:
= V = 28 % V (MIN.)
V
NIH
NIL
CC
DIP
SOP
TSSOP
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 4mA (MIN)
OH
OL
BALANCED PROPAGATION DELAYS:
t
t
ORDER CODES
PLH
PHL
WIDE OPERATING VOLTAGE RANGE:
(OPR) = 2V to 6V
PACKAG
E
TUBE
T & R
V
CC
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 40103
DIP
SOP
M74HC40103B1R
M74HC40103M1R M74HC40103RM13TR
M74HC40103TTR
TSSOP
DESCRIPTION
The M74HC40103 is an high speed CMOS
8-STAGE PRESETTABLE SYNCHRONOUS
DOWN COUNTER fabricated with silicon gate
inhibited when the CARRY-IN / COUNTER
ENABLE (CI/CE) input is high. The CARRY-OUT /
ZERO-DETECT (CO/ZD) output goes low when
the count reaches zero if the CI/CE input is low,
and remains low for one full clock period. When
the SYNCHRONOUS PRESET-ENABLE (SPE)
input is low, data at the J input is clocked into the
counter on the next positive clock transition
regardless of the state of the CI/CE input.
When the ASYNCHRONOUS PRESET-ENABLE
(APE) input is low, data at the J inputs is
asynchronously forced into the counter regardless
of the state of the SPE CI/CE or CLOCK inputs. J
input J0-J7 represent a singular 8-bit binary word.
When the CLEAR, CLR input is low, the counter is
asynchronously cleared to its maximum count
2
C MOS technology.
The HC40103 consists of an 8 stage synchronous
down counter with a single output which is active
when the internal count is zero. The HC40103
contains a single 8-bit binary counter. This device
has control inputs for enabling or disabling the
clock, for clearing the counter to its maximum
count, and for presetting the counter either
synchronously or asynchronously. All control
inputs and the CARRY-OUT / ZERO DETECT
output are active low logic. In normal operation the
counter is decremented by one count on each
positive transition of the CLOCK. Counting is
PIN CONNECTION AND IEC LOGIC SYMBOLS
September 2001
1/16
M74HC40103
(255 ) regardless of the state of any other input.
counting sequence of 256 clock pulses long. The
HC40103 may be cascaded using the CI/CE input
and the CO/ZD output, in either a synchronous or
ripple mode. All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.
10
The precedence relationship between control
input is indicated in the truth table. If all control
inputs are high at the time of zero count, the
counters will jump to the maximum count giving a
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
Clock Input (LOW to
HIGH edge triggered)
1
CLOCK
Asynchronous Master
Reset Input (Active Low)
2
3
CLEAR
CI/CE
Terminal Enable Input
4, 5, 6, 7, 10,
11, 12, 13
J0 to J9
Jam Inputs
Asynchronous Preset
Enable Inputs(Active Low)
9
APE
CO/ZD
SPE
Terminal Count Output
(Active Low)
14
15
Synchronous Preset
Enable Input (Active Low)
8
GND
Vcc
Ground (0V)
16
Positive Supply Voltage
TRUTH TABLE
CONTROL INPUTS
MODE
FUNCTIONAL DESCRIPTION
CLEAR APE
SPE
CI/CE
H
H
H
H
H
H
H
L
COUNT INHIBIT
EVEN IF CLOCK IS GIVEN, NO COUNT IS MADE
DOWN COUNT AT RISING EDGE OF CLOCK
REGULAR COUNT
SYNCHRONOUS
PRESET
DATA OF PI TERMINAL IS PRESET AT RISING
EDGE OF CLOCK
H
H
H
L
X
ASYNCHRONOUS
PRESET
DATA OF PI TERMINAL IS ASYNCHRONOUSLY
PRESET TO CLOCK
L
X
X
X
X
L
X
CLEAR
COUNTER IS SET TO MAXIMUM COUNT
X : Don’t Care
Maximum Count is "255"
2/16
M74HC40103
LOGIC DIAGRAM
TIMING CHART
3/16
M74HC40103
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
CC
V
DC Input Voltage
-0.5 to V + 0.5
I
CC
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
± 20
± 20
mA
mA
mA
mA
mW
°C
IK
I
OK
I
± 25
O
I
or I
DC V
or Ground Current
CC
± 50
CC
GND
P
Power Dissipation
500(*)
-65 to +150
300
D
T
Storage Temperature
Lead Temperature (10 sec)
stg
T
°C
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
2 to 6
0 to V
V
V
CC
V
Input Voltage
I
CC
V
Output Voltage
0 to V
CC
V
O
T
Operating Temperature
Input Rise and Fall Time
-55 to 125
0 to 1000
0 to 500
0 to 400
°C
ns
ns
ns
op
V
V
V
= 2.0V
= 4.5V
= 6.0V
CC
CC
CC
t , t
r
f
4/16
M74HC40103
DC SPECIFICATIONS
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
T = 25°C
Symbol
Parameter
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
IH
V
V
V
Low Level Input
Voltage
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
IL
V
High Level Output
Voltage
I =-20 µA
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
1.9
4.4
OH
O
I =-20 µA
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
O
I =-20 µA
5.9
5.9
V
V
O
I =-4.0 mA
4.18 4.31
4.13
5.63
4.10
5.60
O
I =-5.2 mA
5.68
5.8
0.0
0.0
0.0
O
V
Low Level Output
Voltage
I =20 µA
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
O
I =20 µA
O
I =20 µA
0.1
0.1
O
I =4.0 mA
0.17 0.26
0.18 0.26
0.33
0.33
0.40
0.40
O
I =5.2 mA
O
I
Input Leakage
Current
I
V = V
or GND
6.0
6.0
± 0.1
± 1
± 1
µA
µA
I
CC
CC
I
Quiescent Supply
Current
CC
V = V
or GND
4
40
80
I
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6ns)
L
r
f
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
t
t
Output Transition
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
30
8
75
15
95
19
110
22
TLH THL
ns
ns
ns
ns
ns
7
13
16
19
t
t
t
t
t
Propagation Delay
Time
(CK - CO/ZD)
96
24
20
116
29
25
104
26
22
48
12
10
185
37
230
46
280
56
PLH PHL
31
39
47
t
Propagation Delay
Time
(APE - CO/ZD)
225
45
280
56
340
68
PLH PHL
38
48
57
t
Propagation Delay
Time
(CL - CO/ZD)
200
40
250
50
300
60
PLH PHL
34
43
51
t
Propagation Delay
Time
(CI/CE - CO/ZD)
95
120
24
145
29
PLH PHL
19
16
20
24
5/16
M74HC40103
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
f
Maximum Clock
Frequency
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4
20
24
150
30
25
115
20
19
115
20
19
47
9
8
32
38
20
7
3
16
19
195
36
32
140
28
24
140
28
24
62
12
10
90
16
15
175
36
31
92
18
15
0
2.6
13
15
235
45
40
175
35
30
175
35
30
70
13
11
110
20
16
205
42
36
105
20
18
0
MAX
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
Clock Pulse Width
HIGH or LOW
W
W
W
5
CLEAR Pulse
Width LOW
35
12
10
31
11
9
Preset Enable
Pulse Width APE,
LOW
t
Removal time
CLEAR to CLOCK
or APE to CLOCK
12
4
REM
8
3
t
t
t
Set Up Time SPE
to CLOCK
70
13
11
140
27
23
72
14
12
-14
-5
20
7
SETUP
SETUP
SETUP
5
Set Up Time CI/CE
to CLOCK
40
14
12
20
8
Set Up Time Jn to
CLOCK
6
t
t
t
Hold Time SPE to
CLOCK
0
hold
hold
hold
0
0
0
-4
0
0
0
Hold Time CI/CE to 2.0
CLOCK
-30
-11
-9
0
0
0
4.5
0
0
0
6.0
0
0
0
Hold Time Jn to
CLOCK
2.0
4.5
6.0
-17
-6
0
0
0
0
0
0
-5
0
0
0
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
5.0
5
10
10
10
pF
pF
IN
C
Power Dissipation
Capacitance (note
1)
PD
5.0
60
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I
CC(opr)
PD CC IN CC
6/16
M74HC40103
FUNCTIONAL DESCRIPTION
The contents of count jump to maximum count
(255) if clock is given when the readout is "0".
Therefore, operation of 256-frequency division is
carried out when clock input alone is given without
various kinds of preset operation.
This device is an 8-stage presettable synchronous
down counter. Carry Out/Zero Detect (CO/ZD) is
output at the "L" level for the period of 1 bit when
the readout becomes "0". This device adopts
8-bit-binary counter decimal notation, making
setting up to 255 counts possible.
PRESET AND RESET OPERATION
COUNT OPERATION
When Clear (CLEAR) input is set to the "L" level,
the readout is set to the maximum count
At the "H" level of control input of CLEAR, SPE
and APE, the counter carriers out down count
operation one by one at the rise of pulse given to
CLOCK input. Count operation can be inhibited by
setting Carry Input/Clock Enable CI/CE to the "H"
level.
independently
of
other
inputs.
When
Asynchronous Preset Enable (APE) input is set to
the "L" level, readouts given on J0 to J7 can be
preset
asynchronously
to
the
counter
independently of inputs other than CLEAR input.
When Synchronous Preset Enable (SPE) is set to
the "L" level the readouts given on J0 to J7 can be
preset to counter synchronously with the rise of
clock. As to these operation mode, refer to the
truth table.
CO/ZD is output at the "L" level when the readout
becomes "0" but is not output even if the readout
becomes "0" when CI/CE is at the "H" level, thus
maintaining the "H" level.
Synchronous cascade operation can be carried
out by using CI/CE input and CO/ZD output.
INPUTS
OUTPUT
CLEAR
APE
SPE
J
TE
CLOCK
Qn + 1
L
H
H
X
L
L
X
X
X
X
L
X
X
X
X
X
X
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
X
X
X
X
L
H
Qn
H
H
H
H
H
H
X
X
L
Qn
Qn
H
X
7/16
M74HC40103
TYPICAL APPLICATIONS
PROGRAMMABLE DIVIDE-BY-N COUNTER
f
= f / (N+1)
IN
OUT
Timing Chart when N = "3"
(J0, J1 = V , J2-J7 = GND
CC
HC40103 ... 1/2 to 1/256 are dividable
PARALLEL CARRY CASCADING
* At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digit place changes, due to delay arrival.
Therefore, take gate from HC32 or the like, not from C0 output at the rear stage directly
PROGRAMMABLE TIMER
The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the above
formula-1/f ~ The above formula
IN
8/16
M74HC40103
TEST CIRCUIT
C
R
= 50pF or equivalent (includes jig and probe capacitance)
L
T
= Z
of pulse generator (typically 50Ω)
OUT
WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
9/16
M74HC40103
WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME
(f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME
(f=1MHz; 50% duty cycle)
10/16
M74HC40103
WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
WAVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
11/16
M74HC40103
WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
12/16
M74HC40103
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
0.51
0.77
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
17.78
0.335
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
13/16
M74HC40103
SO-16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.003
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8° (max.)
PO13H
14/16
M74HC40103
TSSOP16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0089
0.201
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
5.1
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1
0.19
0.09
4.9
c
D
5
6.4
0.197
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0°
8°
0°
8°
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
15/16
M74HC40103
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
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16/16
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