M74HC573TTR [STMICROELECTRONICS]
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING; 八D型具有三态输出的非反相锁存
| 型号： | M74HC573TTR |
| 厂家： | 
ST |
| 描述： | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 文件： | 总12页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M74HC573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
■
■
■
■
■
■
■
HIGH SPEED:
= 13ns (TYP.) at V = 6V
t
PD
CC
LOW POWER DISSIPATION:
= 4µA(MAX.) at T =25°C
I
CC
A
HIGH NOISE IMMUNITY:
= V = 28 % V (MIN.)
V
NIH
NIL
CC
DIP
SOP
TSSOP
T & R
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 6mA (MIN)
OH
OL
BALANCED PROPAGATION DELAYS:
ORDER CODES
PACKAGE
t
t
PLH
PHL
TUBE
WIDE OPERATING VOLTAGE RANGE:
(OPR) = 2V to 6V
V
DIP
SOP
M74HC573B1R
M74HC573M1R
CC
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
M74HC573RM13TR
M74HC573TTR
TSSOP
DESCRIPTION
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while is at high level the outputs will be
in a high impedance state.
The M74HC573 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C MOS technology.
2
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely. When
LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/12
M74HC573
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
2, 3, 4, 5, 6,
7, 8, 9
D0 to D7
Q0 to Q7
Data Inputs
12, 13, 14,
15, 16, 17,
18, 19
3 State Latch Outputs
11
10
20
LE
Latch Enable Input
Ground (0V)
GND
V
Positive Supply Voltage
CC
TRUTH TABLE
INPUTS
OUTPUTS
Q
OE
LE
D
H
L
L
L
X
L
X
X
L
Z
NO CHANGE (*)
H
H
L
H
H
X: Don’t Care
Z: High Impedance
(*): Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
2/12
M74HC573
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
CC
V
DC Input Voltage
-0.5 to V + 0.5
I
CC
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
± 20
± 20
mA
mA
mA
mA
mW
°C
IK
I
OK
I
± 35
O
I
or I
DC V
or Ground Current
CC
± 70
CC
GND
P
Power Dissipation
500(*)
-65 to +150
300
D
T
Storage Temperature
Lead Temperature (10 sec)
stg
T
°C
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
2 to 6
0 to V
V
V
CC
V
Input Voltage
I
CC
V
Output Voltage
0 to V
CC
V
O
T
Operating Temperature
Input Rise and Fall Time
-55 to 125
0 to 1000
0 to 500
0 to 400
°C
ns
ns
ns
op
V
V
V
= 2.0V
= 4.5V
= 6.0V
CC
CC
CC
t , t
r
f
3/12
M74HC573
DC SPECIFICATIONS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
IH
V
V
V
Low Level Input
Voltage
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
IL
V
High Level Output
Voltage
I =-20 µA
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
1.9
4.4
OH
O
I =-20 µA
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
O
I =-20 µA
5.9
5.9
V
V
O
I =-6.0 mA
4.18 4.31
4.13
5.63
4.10
5.60
O
I =-7.8 mA
5.68
5.8
0.0
0.0
0.0
O
V
Low Level Output
Voltage
I =20 µA
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
O
I =20 µA
O
I =20 µA
0.1
0.1
O
I =6.0 mA
0.17 0.26
0.18 0.26
0.33
0.33
0.40
0.40
O
I =7.8 mA
O
I
Input Leakage
Current
I
V = V
or GND
CC
6.0
6.0
6.0
± 0.1
± 0.5
4
± 1
± 5
40
± 1
± 10
80
µA
µA
µA
I
I
I
High Impedance
Output Leakage
Current
OZ
V = V or V
IL
I
IH
V
= V or GND
CC
O
Quiescent Supply
Current
CC
V = V
or GND
CC
I
4/12
M74HC573
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6ns)
L
r
f
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
T
= 25°C
Symbol
Parameter
A
V
C
L
CC
(V) (pF)
Min. Typ. Max. Min. Max. Min. Max.
t
t
Output Transition
Time
2.0
25
7
60
12
10
115
23
20
155
31
26
110
22
19
150
30
26
140
28
24
180
36
31
125
25
21
75
15
13
50
10
9
75
15
13
145
29
25
195
39
33
140
28
24
190
38
32
175
35
30
225
45
38
155
31
26
95
19
16
65
13
11
90
18
15
175
35
30
235
47
40
165
33
28
225
45
38
210
42
36
270
54
46
190
38
32
110
22
19
75
15
13
5
TLH THL
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
t
t
t
Propagation Delay
Time
50
15
13
60
20
17
42
14
12
57
19
16
55
17
14
66
22
19
40
17
15
40
8
PLH PHL
(LE - Q)
150
50
t
Propagation Delay
Time
PLH PHL
(D - Q)
150
50
t
t
High Impedance
Output Enable
Time
PZL PZH
R = 1 KΩ
L
R = 1 KΩ
150
50
L
t
t
High Impedance
Output Disable
Time
PLZ PHZ
R = 1 KΩ
L
t
t
Minimum Pulse
Width
W(L)
50
W(H)
7
t
t
Minimum Set-up
Time
16
5
s
50
3
Minimum Hold
Time
5
5
h
50
5
5
5
5
5
5
5/12
M74HC573
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
5
10
10
10
pF
pF
IN
Output
Capacitance
C
10
OUT
C
Power Dissipation
Capacitance (note
1)
PD
51
pF
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I /8 (per Flip
CC(opr)
PD CC IN CC
Flop) and the C when n pcs of Flip Flop operate, can be gained by the following equation: C
= 33 + 18 x n (pF)
PD
PD(TOTAL)
TEST CIRCUIT
TEST
SWITCH
t
t
t
, t
Open
PLH PHL
, t
V
CC
PZL PLZ
, t
GND
PZH PHZ
C = 50pF/150pF or equivalent (includes jig and probe capacitance)
L
R = 1KΩ or equivalent
1
T
R
= Z
of pulse generator (typically 50Ω)
OUT
6/12
M74HC573
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
7/12
M74HC573
WAVEFORM 3: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
8/12
M74HC573
Plastic DIP-20 (0.25) MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
0.254
1.39
MAX.
MIN.
0.010
0.055
MAX.
a1
B
b
1.65
0.065
0.45
0.25
0.018
0.010
b1
D
E
e
25.4
1.000
8.5
2.54
22.86
0.335
0.100
0.900
e3
F
7.1
0.280
0.155
I
3.93
L
3.3
0.130
Z
1.34
0.053
P001J
9/12
M74HC573
SO-20 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
2.65
0.2
MIN.
MAX.
0.104
0.008
0.096
0.019
0.012
A
a1
a2
b
0.1
0.004
2.45
0.49
0.32
0.35
0.23
0.014
0.009
b1
C
0.5
0.020
c1
D
45° (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.020
0.300
0.050
0.029
L
M
S
8° (max.)
PO13L
10/12
M74HC573
TSSOP20 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0089
0.260
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
6.6
0.002
0.031
0.007
0.004
0.252
0.244
0.169
0.004
0.039
1
0.19
0.09
6.4
c
D
6.5
6.4
0.256
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0°
8°
0°
8°
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
0087225C
11/12
M74HC573
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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12/12
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