M74HCT74C1R [STMICROELECTRONICS]
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR; 带预置和清除两个D型触发器![M74HCT74C1R](http://pdffile.icpdf.com/pdf1/p00086/img/icpdf/M74HCT74_455682_icpdf.jpg)
型号: | M74HCT74C1R |
厂家: | ![]() |
描述: | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR |
文件: | 总11页 (文件大小:251K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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M54HCT74
M74HCT74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
.
.
.
.
.
.
.
HIGH SPEED
fMAX = 53 MHz (TYP.) AT VCC = 5 V
LOW POWER DISSIPATION
ICC = 2 µA (MAX.) AT TA = 25 °C
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
PIN AND FUNCTION COMPATIBLE
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
WITH 54/74LS74
ORDER CODES :
DESCRIPTION
M54HCT74F1R
M74HCT74M1R
The M54/74HCT74 is a high speed CMOS DUAL D
TYPE FLOP WITH PRESET AND CLEAR fabri-
cated in silicon gate C2MOS technology. It has the
same high speed performance of LSTTL combined
with trueCMOSlow power consumption. A signal on
the DINPUT is transferred to the Q OUTPUTduring
the positive going transition of the clock pulse.
CLEAR and PRESET are independent of the clock
and accomplished by alow on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age. This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M54/74HCT devices are de-
signed to directly interface HSC2MOS systems with
TTL and NMOS components. They are also plug in
replacements for LSTTL devices giving a reduction
of power consumption.
M74HCT74B1R
M74HCT74C1R
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
NC =
No Internal
Connection
February 1993
1/11
M54/M74HCT74
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
L
PR
D
X
X
X
L
CK
X
Q
L
Q
H
L
H
L
CLEAR
H
X
H
H
L
PRESET
L
L
X
H
H
L
H
H
H
H
H
H
X
H
Qn
H
Qn
NO CHANGE
X: Don’t Care
PIN DESCRIPTION
IEC LOGIC SYMBOL
PIN No
SYMBOL
NAME AND FUNCTION
1, 13
1CLR,
2CLR
Asyncronous Reset -
Direct Input
2, 12
3, 11
1D, 2D
Data Inputs
1CK, 2CK
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
4, 10
1PR, 2PR
Asyncronous Set - Direct
Input
5, 9
6, 8
1Q, 2Q
1Q, 2Q
True Flip-Flop Outpus
Complement Flip-Flop
Outputs
7
GND
VCC
Ground (0V)
14
Positive Supply Voltage
LOGIC DIAGRAM
2/11
M54/M74HCT74
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
Unit
Supply Voltage
-0.5 to +7
V
DC Input Voltage
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
V
V
VO
DC Output Voltage
IIK
DC Input Diode Current
DC Output Diode Current
DC Output Source Sink Current Per Output Pin
mA
mA
mA
mA
mW
oC
IOK
± 20
IO
± 25
ICC or IGND DC VCC or Ground Current
± 50
PD
Tstg
TL
Power Dissipation
500 (*)
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
oC
Absolute MaximumRatingsare those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
4.5 to 5.5
0 to VCC
0 to VCC
Unit
V
Supply Voltage
Input Voltage
Output Voltage
V
VO
V
Top
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
oC
oC
tr, tf
Input Rise and Fall Time (VCC = 4.5 to 5.5V)
0 to 500
ns
3/11
M54/M74HCT74
DC SPECIFICATIONS
Test Conditions
VCC
Value
TA = 25 oC
54HC and 74HC
-40 to 85 oC -55 to 125 oC
Symbol
VIH
Parameter
Unit
V
74HC
54HC
(V)
Min. Typ. Max. Min. Max. Min. Max.
High Level Input
Voltage
4.5
to
2.0
2.0
2.0
5.5
VIL
Low Level Input
Voltage
4.5
to
0.8
0.8
0.8
V
5.5
VOH
High Level
VI = IO=-20 µA
4.4
4.5
4.4
4.4
Output Voltage
VIH
or
VIL
4.5
V
V
IO=-4.0 mA 4.18 4.31
4.13
4.10
VOL
Low Level Output
Voltage
VI = IO= 20 µA
VIH
or
VIL
0.0
0.1
0.1
0.33
±1
0.1
0.4
±1
4.5
5.5
IO= 4.0 mA
0.17 0.26
II
Input Leakage
Current
VI = VCC or GND
±0.1
2
µA
µA
ICC
Quiescent Supply 5.5 VI = VCC or GND
Current
20
40
∆ICC
Additional worst
case supply
current
5.5
Per Input pin
VI = 0.5V or
VI = 2.4V
2.0
2.9
3.0
mA
Other Inputs at
VCC or GND
IO= 0
4/11
M54/M74HCT74
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Test Conditions
Value
-40 to 85 oC -55 to 125 oC
74HC 54HC
TA = 25 oC
54HC and 74HC
Symbol
Parameter
Unit
VCC
(V)
4.5
Min. Typ. Max. Min. Max. Min. Max.
tTLH
tTHL
tPLH
tPHL
Output Transition
Time
8
15
19
22
ns
ns
Propagation
Delay Time
(CLOCK - Q)
4.5
4.5
21
33
41
50
tPLH
tPHL
Propagation
Delay Time
(CL, PR - Q, Q)
18
30
38
45
ns
MHz
ns
fMAX
Maximum Clock
Frequency
4.5
4.5
27
48
6
22
18
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
15
15
19
19
23
23
tW(L)
Minimum Pulse
Width
(CL, PR)
4.5
8
7
ns
ts
th
Minimum Set-up
Time
4.5
4.5
4.5
15
0
19
0
23
0
ns
ns
Minimum Hold
Time
tREM
Minimum
1
5
5
6
5
8
Removal Time
(CL, PR)
ns
CIN
Input Capacitance
5
10
10
10
pF
pF
CPD (*) Power Dissipation
Capacitance
32
(*) CPD isdefined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the followingequation. ICC(opr) = CPD • VCC • fIN + ICC/2 (per FLIP/FLOP)
5/11
M54/M74HCT74
SWITCHING CHARACTERISTICS TEST
WAVEFORM
TEST CIRCUIT ICC (Opr.)
INPUTTRANSIENTTIMEISTHESAMEASTHAT
IN CASE OF SWITCHING CHARACTERISTICS
TEST. F2 = F1/2
SWITCHING CHARACTERISTICS TEST WAVEFORM
6/11
M54/M74HCT74
Plastic DIP14 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.51
1.39
TYP.
MAX.
MIN.
0.020
0.055
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
15.24
0.335
0.100
0.600
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
2.54
0.050
0.100
P001A
7/11
M54/M74HCT74
Ceramic DIP14/1 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
20
MIN.
MAX.
0.787
0.276
A
B
7.0
D
E
3.3
0.130
0.600
0.38
0.015
e3
F
15.24
2.29
0.4
2.79
0.55
1.52
0.31
2.54
10.3
8.05
5.08
0.090
0.016
0.046
0.009
0.060
0.110
0.022
0.060
0.012
0.100
0.406
0.317
0.200
G
H
L
1.17
0.22
1.52
M
N
P
7.8
0.307
Q
P053C
8/11
M54/M74HCT74
SO14 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.003
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
8.55
5.8
8.75
6.2
0.336
0.228
0.344
0.244
E
e
1.27
7.62
0.050
0.300
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.026
G
L
1.27
0.68
M
S
8° (max.)
P013G
9/11
M54/M74HCT74
PLCC20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
9.78
8.89
4.2
TYP.
MAX.
10.03
9.04
MIN.
0.385
0.350
0.165
MAX.
0.395
0.356
0.180
A
B
D
4.57
d1
d2
E
2.54
0.56
0.100
0.022
7.37
8.38
0.290
0.330
0.004
e
1.27
5.08
0.38
0.050
0.200
0.015
e3
F
G
0.101
M
M1
1.27
1.14
0.050
0.045
P027A
10/11
M54/M74HCT74
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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11/11
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M74HCT74MTCX
D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 4.40 MM, MO-153, TSSOP-14
FAIRCHILD
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