M93C56-RBN1_技术文档

M93C86, M93C76, M93C66

M93C56, M93C46, M93C06

16K/8K/4K/2K/1K/256 (x8/x16) Serial Microwire Bus EEPROM

INDUSTRY STANDARD MICROWIRE BUS

1 MILLION ERASE/WRITE CYCLES, with

40 YEARS DATA RETENTION

DUAL ORGANIZATION: by WORD (x16) or by

BYTE (x8)

BYTE/WORD and ENTIRE MEMORY

PROGRAMMING INSTRUCTIONS

SELF-TIMED PROGRAMMING CYCLE with

AUTO-ERASE

8

1

PSDIP8 (BN)

0.25mm Frame

SO8 (MN)

150mil Width

READY/BUSY SIGNAL DURING

PROGRAMMING

SINGLE SUPPLY VOLTAGE:

– 4.5V to 5.5V for M93Cx6 version

– 2.5V to 5.5V for M93Cx6-W version

– 1.8V to 3.6V for M93Cx6-R version

SEQUENTIAL READ OPERATION

5ms TYPICAL PROGRAMMING TIME

8

1

TSSOP8 (DW)

169mil Width

ENHANCED ESD/LATCH-UP

PERFORMANCES

DESCRIPTION

Figure 1. Logic Diagram

This M93C86/C76/C66/C56/C46/C06 specifica-

tion covers a range of 16K/8K/4K/2K/1K/256 bit

serial EEPROM products respectively. In this text,

products are referred to as M93Cx6. The M93Cx6

is an Electrically Erasable Programmable Memory

(EEPROM) fabricated with STMicroelectronics’s

High Endurance Single Polysilicon CMOS technol-

ogy. The M93Cx6 memory is accessed through a

serial input (D) and output (Q) using the MI-

CROWIRE bus protocol.

V

CC

D

Q

C

S

Table 1. Signal Names

M93Cx6

S

Chip Select Input

Serial Data Input

Serial Data Output

Serial Clock

D

ORG

Q

C

V

SS

AI01928

ORG

V_CC

V_SS

Organisation Select

Supply Voltage

Ground

February 1999

1/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 2A. DIP and SO Pin Connections

Figure 2B. SO 90° Turn Pin Connections

M93Cx6

S

C

D

Q

1

2

3

4

8

V

DU

1

8

ORG

CC

7

DU

V

2

3

4

7

6

V

SS

Q

CC

S

6

5

ORG

V

C

5

D

SS

AI01929B

AI00900

Warning: DU = Don’t Use

Figure 2C. TSSOP Pin Connections

as a data stream from 8 up to 16,384 bits long (for

the M93C86 only), or continuously as the address

counter automatically rolls over to ’00’ when the

highest address is reached.

Programming is internally self-timed (the external

clock signal on C input may be disconnected or left

running after the start of a Write cycle) and does

not require an erase cycle prior to the Write instruc-

tion. The Write instruction writes 8 or 16 bits at one

time into one of the byte or word locations of the

M93Cx6. After the start of the programming cycle,

a Busy/Ready signal is available on the Data output

(Q) when Chip Select (S) is driven High.

M93C06/46/56/66 - W

M93C06/46/56/66 - R

S

C

D

Q

1

2

3

4

8

V

CC

DU

7

6

ORG

5

V

SS

AI02789

An internal feature of the M93Cx6 provides Power-

on Data Protection by inhibiting any operation

when the Supply is too low for reliable operation.

The design of the M93Cx6 and the High Endurance

CMOS technology used for its fabrication give an

Erase/Write cycle Endurance of 1,000,000 cycles

and a data retention of 40 years.

The DU (Don’t Use) pin does not affect the function

of the memory. It is reserved for use by STMi-

croelectronics during test sequences. The pin may

be left unconnected or may be connected to V_CC

or V_SS. Direct connection of DU to V_SSis recom-

mended for the lowest standby power consump-

tion.

Warning: DU = Don’t Use

DESCRIPTION (cont’d)

The M93Cx6 specified at 5V±10%, the M93Cx6-W

specified at 2.5V to 5.5V and the M93Cx6-R speci-

fied at 1.8V to 3.6V.

The M93Cx6 memory array organization may be

divided into either bytes (x8) or words (x16) which

may be selected by a signal applied on the ORG

input. The M93C86/C76/C66/C56/C46/C06 is di-

vided into either 2048/1024/512/256/128/32 x8 bit

bytes or 1024/512/256/128/64/16 x16 bit words

respectively. These memory devices are available

in both PSDIP8, SO8 and TSSOP8 packages.

MEMORY ORGANIZATION

The M93Cx6 is organised in either bytes (x8) or

words (x16). If the ORG input is left unconnected

(or connected to V_CC) the x16 organization is se-

lected; when ORG is connected to Ground (V_SS)

the x8 organization is selected. When the M93Cx6

is in standby mode, the ORG input should be set

to either V_SSor V_CCin order to achieve minimum

power consumption. Any voltage between V_SSand

V_CCapplied to the ORG input pin may increase the

standby current value.

The M93Cx6 memory is accessed by a set of

instructions which includes Read a Byte/Word,

Write a Byte/Word, Erase a Byte/Word, Erase All

and Write All. ARead instruction loads the address

of the first byte/word to be read into an internal

address pointer. The data contained at this address

is then clocked out serially. The address pointer is

automatically incremented after the data is output

and, if the Chip Select input (S) is held High, the

M93Cx6 can output a sequential stream of data

bytes/words. In this way, the memory can be read

2/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

Parameter

Value

Unit

T_A

Ambient Operating Temperature

–40 to 125

°C

T_STG

Storage Temperature

–65 to 150

°C

T_LEAD

Lead Temperature, Soldering

(SO8 package)

(PSDIP8 package)

40 sec

10 sec

215

260

V_IO

Input or Output Voltages (Q = V_OHor Hi-Z)

Supply Voltage

–0.3 to V_CC+0.5

–0.3 to 6.5

V

V_CC

Electrostatic Discharge Voltage (Human Body model) ⁽²⁾

Electrostatic Discharge Voltage (Machine model) ⁽³⁾

4000

500

V

V_ESD

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

Table 3. AC Measurement Conditions

Input Rise and Fall Times

≤ 50ns

Input Pulse Voltages (M93Cxx)

0.4V to 2.4V

0.2V_CCto 0.8V_CC

1.0V to 2.0V

0.8V to 2.0V

0.3V_CCto 0.7V_CC

C_L= 100pF

Input Pulse Voltages (M93Cxx-W, M93Cxx-R)

Input Timing Reference Voltages (M93Cxx)

Output Timing Reference Voltages (M93Cxx)

Input and Output Timing Reference Voltages (M93Cxx-W, M93Cxx-R)

Output Load

Note that Output Hi-Z is defined as the point where data is no longer driven.

POWER-ON DATA PROTECTION

Figure 3. AC Testing Input Output Waveforms

In order to prevent data corruption and inadvertent

write operations during power-up, a Power On

Reset (POR) circuit resets all internal programming

circuitry and sets the device in the Write Disable

mode.

M93CXX

2.4V

2V

1V

2.0V

0.8V

– At Power-up and Power-down, the device must

NOT be selected (that is, the S input must be

driven low) until the supply voltage reaches the

operating value V_CCspecified in the AC and DC

tables.

0.4V

INPUT

OUTPUT

M93CXX-W & M93CXX-R

– When V_CCreaches its functional value, the de-

vice is properly reset (in the Write Disable mode)

and is ready to decode and execute an incoming

instruction.

0.8V

CC

0.7V

0.3V

CC

0.2V

For the M93Cx6 specified at 5V, the POR threshold

voltage is around 3V. For all the other M93Cx6

specified at low V_CC(with -W and -R V_CCrange

options), the POR threshold voltage is around 1.5V.

AI02553

3/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 4. Capacitance ⁽¹⁾

(T_A= 25 °C, f = 1 MHz )

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Test Condition

V_IN= 0V

Min

Max

5

Unit

pF

C_OUT

V_OUT= 0V

5

pF

Note: 1. Sampled only, not 100% tested.

Table 5A. DC Characteristics for M93CXX

(T_A= 0 to 70°C or –40 to 85°C; V_CC= 4.5V to 5.5V)

Symbol

I_LI

Parameter

Input Leakage Current

Output Leakage Current

Supply Current

Test Condition

0V ≤ V_IN≤ V_CC

Min

Max

Unit

±2.5

1.5

µA

mA

I_LO

0V ≤ V_OUT≤ V_CC, Q in Hi-Z

V_CC= 5V, S = V_IH, f = 1 MHz

I_CC

V

_CC= 5V, S = V_SS, C = V_SS

,

I_CC1

Supply Current (Standby)

50

µA

ORG = V_SSor V_CC

V_IL

V_IH

Input Low Voltage (D, C, S)

Input High Voltage (D, C, S)

Output Low Voltage (Q)

Output High Voltage (Q)

V_CC= 5V ± 10%

–0.3

2

0.8

V_CC+ 1

0.4

V

V_OL

V_OH

V_CC= 5V, I_OL= 2.1mA

V_CC= 5V, I_OH= –400µA

2.4

Table 5B. DC Characteristics for M93CXX

(T_A= –40 to 125°C; V_CC= 4.5V to 5.5V)

Symbol

I_LI

Parameter

Input Leakage Current

Output Leakage Current

Supply Current

Test Condition

Min

Max

±2.5

1.5

Unit

µA

0V ≤ V_IN≤ V_CC

I_LO

0V ≤ V_OUT≤ V_CC, Q in Hi-Z

µA

I_CC

V_CC= 5V, S = V_IH, f = 1 MHz

mA

V

_CC= 5V, S = V_SS, C = V_SS

,

I_CC1

Supply Current (Standby)

50

µA

ORG = V_SSor V_CC

V_IL

V_IH

Input Low Voltage (D, C, S)

Input High Voltage (D, C, S)

Output Low Voltage (Q)

Output High Voltage (Q)

V_CC= 5V ± 10%

–0.3

2

0.8

V_CC+ 1

0.4

V

V_OL

V_OH

V_CC= 5V, I_OL= 2.1mA

V_CC= 5V, I_OH= –400µA

2.4

4/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 5C. DC Characteristics for M93CXX-W

(T_A= 0 to 70°C or –40 to 85°C; V_CC= 2.5V to 5.5V)

Symbol

I_LI

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

0V ≤ V_IN≤ V_CC

Min

Max

±2.5

1.5

Unit

µA

I_LO

0V ≤ V_OUT≤ V_CC, Q in Hi-Z

V_CC= 5V, S = V_IH, f = 1 MHz

µA

mA

I_CC

Supply Current (CMOS Inputs)

Supply Current (Standby)

V

_CC= 2.5V, S = V_IH, f = 1 MHz

1

V

_CC= 2.5V, S = V_SS, C = V_SS

,

I_CC1

10

µA

ORG = V_SSor V_CC

V_IL

V_IH

Input Low Voltage (D, C, S)

Input High Voltage (D, C, S)

–0.3

0.2 V_CC

V_CC+ 1

0.4

V

0.7 V_CC

V_CC= 5V, I_OL= 2.1mA

V_OL

Output Low Voltage (Q)

Output High Voltage (Q)

V

_CC= 2.5V, I_OL= 100µA

V_CC= 5V, I_OH= –400µA

_CC= 2.5V, I_OH= –100µA

0.2

2.4

V_OH

V

V_CC– 0.2

Table 5D. DC Characteristics for M93CXX-R ⁽¹⁾

(T_A= 0 to 70°C or –20 to 85°C; V_CC= 1.8V to 3.6V)

Symbol

I_LI

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

0V ≤ V_IN≤ V_CC

Min

Max

±2.5

1.5

Unit

µA

I_LO

0V ≤ V_OUT≤ V_CC, Q in Hi-Z

µA

V_CC= 3.6V, S = V_IH, f = 1 MHz

mA

I_CC

Supply Current (CMOS Inputs)

Supply Current (Standby)

V

_CC= 1.8V, S = V_IH, f = 1 MHz

1

V

_CC= 1.8V, S = V_SS, C = V_SS

,

I_CC1

5

µA

ORG = V_SSor V_CC

V_IL

V_IH

Input Low Voltage (D, C, S)

Input High Voltage (D, C, S)

Output Low Voltage (Q)

Output High Voltage (Q)

–0.3

0.2 V_CC

V_CC+ 1

0.2

V

0.8 V_CC

V_OL

V_OH

V_CC= 1.8V, I_OL= 100µA

V_CC= 1.8V, I_OH= –100µA

V_CC– 0.2

Note: 1. This is preliminary data.

5/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 6A. AC Characteristics

M93C86/76/66/56/46/06

V

_CC= 4.5V to 5.5V,

V_CC= 4.5V to 5.5V,

T = –40 to 125 C

Symbol

Alt

Parameter

Unit

T = 0 to 70 C,

°

A

°

A

T = –40 to 85 C

°

A

Min

Max

Min

Max

Chip Select Set-up Time

50

ns

M93C06, M39C46, M93C56, M93C66

t_SHCH

t_CSS

Chip Select Set-up time

M93C76, M93C86

100

t_CLSH

t_DVCH

t_CHDX

t_CHQL

t_CHQV

t_CLSL

t_SLCH

t_SKS

t_DIS

Clock Set-up Time (relative to S)

Data In Set-up Time

100

ns

t_DIH

t_PD0

t_PD1

t_CSH

Data In Hold Time

ns

Delay to Output Low

400

ns

Delay to Output Valid

ns

Chip Select Hold Time

Chip Select Low to Clock High

Chip Select Low to Chip Select High

Chip Select to Ready/Busy Status

Chip Select Low to Output Hi-Z

Clock High Time

0

ns

250

ns

(1)

t_SLSH

t_CS

t_SV

ns

t_SHQV

t_SLQZ

400

200

400

200

ns

t_DF

ns

(2)

t_CHCL

t_SKH

t_SKL

t_WP

f_SK

250

ns

(2)

t_CLCH

Clock Low Time

ns

t_W

f_C

Erase/Write Cycle time

Clock Frequency

10

1

10

1

ms

MHz

0

Notes: 1. Chip Select must be brought low for a minimum of tSLSH between consecutive instruction cycles.

2. The Clock frequency specification calls for a minimum clock period of 1/fC, therefore the sum of the timings tCHCL + tCLCH

must be greater or equal to 1/fC.

6/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 6B. AC Characteristics

M93C86/76/66/56/46/06

V

_CC= 2.5V to 5.5V,

V

_CC= 1.8V to 3.6V,⁽³⁾

T = 0 to 70 C,

Symbol

Alt

Parameter

Unit

T = 0 to 70 C,

°

A

T = –40 to 85 C

T = –20 to 85 C

°

A

°

A

Min

100

Max

Min

200

100

200

Max

t_SHCH

t_CLSH

t_DVCH

t_CHDX

t_CHQL

t_CHQV

t_CLSL

t_SLCH

t_CSS

t_SKS

t_DIS

Chip Select Set-up Time

Clock Set-up Time (relative to S)

Data In Set-up Time

ns

t_DIH

t_PD0

t_PD1

t_CSH

Data In Hold Time

ns

Delay to Output Low

400

700

ns

Delay to Output Valid

ns

Chip Select Hold Time

Chip Select Low to Clock High

Chip Select Low to Chip Select High

Chip Select to Ready/Busy Status

Chip Select Low to Output Hi-Z

Clock High Time

0

ns

250

1000

250

1000

ns

(1)

t_SLSH

t_CS

t_SV

ns

t_SHQV

t_SLQZ

400

200

700

200

ns

t_DF

ns

(2)

t_CHCL

t_SKH

t_SKL

t_WP

f_SK

350

250

800

ns

(2)

t_CLCH

Clock Low Time

ns

t_W

f_C

Erase/Write Cycle time

Clock Frequency

10

1

10

ms

MHz

0

0.5

Notes: 1. Chip Select must be brought low for a minimum of tSLSH between consecutive instruction cycles.

2. The Clock frequency specification calls for a minimum clock period of 1/fC, therefore the sum of the timings tCHCL + tCLCH

must be greater or equal to 1/fC.

3. This is preliminary data.

Figure 4. Synchronous Timing, Start and Op-Code Input

tCLSH

tCHCL

C

S

D

tSHCH

tCLCH

tDVCH

START

tCHDX

OP CODE

START

OP CODE INPUT

AI01428

7/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 5. Synchronous Timing, Read or Write

C

S

tCLSL

tDVCH

tCHDX

tCHQV

tSLSH

A0

D

Q

An

tSLQZ

tCHQL

Hi-Z

Q15/Q7

Q0

ADDRESS INPUT

DATA OUTPUT

AI00820C

tSLCH

C

S

D

Q

tCLSL

tDVCH

tCHDX

A0/D0

tSLSH

An

tSHQV

BUSY

tSLQZ

READY

Hi-Z

tW

ADDRESS/DATA INPUT

WRITE CYCLE

AI01429

8/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

INSTRUCTIONS

the power-on reset Threshold voltage. To protect

the memory contents from accidental corruption, it

The M93C86/C76/C66/C56/C46/C06 have seven

instructions, as shown in Table 7. Each instruction

is preceded by the rising edge of the signal applied

on the S input (assuming that the clock C is low).

After the device is selected, the internal logic waits

for the start bit, which defines the beginning of the

instruction bit stream. The startbit is the first’1’read

on the D input during the rising edge of the clock

C. Following the start bit, the op-codes of the

instructions are made up of the 2 following bits.

Note that some instructions use only these first two

bits, others use also the first two bits of the address

to define the op-code. The op-code is then followed

by the address of the byte/word to be accessed.

For the M93C06 and M93C46, the address is made

up of 6 bits for the x16 organization or 7 bits for the

x8 organization (see Table 7A). For the M93C56

and M93C66, the address is made up of 8 bits for

the x16 organization or 9 bits for the x8 organization

(see Table 7B). For the M93C76 and M93C86, the

address is made up of 10 bits for the x16 organiza-

tion or 11 bits for the x8 organization (see Table

7C).

is advisable to issue the EWDS instruction after

every write cycle. The READ instruction is not

affected by the EWEN or EWDS instructions.

Erase

The Erase instruction (ERASE) programs the ad-

dressed memory byte or word bits to ’1’. Once the

address is correctly decoded, the falling edge of the

Chip Selectinput (S) startsa self-timed erase cycle.

If the M93Cx6 is still performing the erase cycle,

the Busy signal (Q = 0) will be returned if S is driven

high after the t_SLSHdelay, and the M93Cx6 will

ignore any data on the bus. When the erase cycle

is completed, the Ready signal (Q = 1) will indicate

(if S is driven high) that the M93Cx6 is ready to

receive a new instruction.

Write

The Write instruction (WRITE) is composed of the

Op-Code followed by the address and the 8 or 16

data bits to be written. Data input is sampled on the

Low to High transition of the clock. After the last

data bit has been sampled, Chip Select (S) must

be brought Low before the next rising edge of the

clock (C) in order to start the self-timed program-

ming cycle. This is important as, if S is brought low

before or after this specific frame window, the

addressed location will not be programmed.

The M93Cx6 is fabricated in CMOS technologyand

is therefore able to run from 0Hz (static input sig-

nals) up to the maximum ratings (specified in Table

6).

Read

If the M93Cx6 is still performing the write cycle, the

Busy signal (Q = 0) will be returned if S is driven

high after the t_SLSHdelay, and the M93Cx6 will

ignore any data on the bus. When the write cycle

is completed, the Ready signal (Q = 1) will indicate

(if S is driven high) that the M93Cx6 is ready to

receive a new instruction. Programming is inter-

nally self-timed (the external clock signal on C input

may be disconnected or left running after the start

of a Write cycle). The Write instruction includes an

automatic Erase cycle before writing the data, it is

therefore unnecessary to execute an Erase instruc-

tion before a Write instruction execution.

The Read instruction (READ) outputs serial data

on the Data Output (Q). When a READ instruction

is received, the instruction and address are de-

coded and the data from the memory is transferred

into an outputshift register. Adummy ’0’bit isoutput

first followed by the 8 bit byte or the 16 bit word with

the MSB first. Output data changes are triggered

by the Low to High transition of the Clock (C). The

M93Cx6 will automatically increment the address

and will clock out the next byte/word as long as the

Chip Select input (S) is held High. In this case the

dummy ’0’ bit is NOT output between bytes/words

and a continuous stream of data can be read.

Erase All

Erase/Write Enable and Disable

The Erase/Write Enable instruction (EWEN)

authorizes the following Erase/Write instructions to

be executed. The Erase/Write Disable instruction

(EWDS) disables the execution of the following

Erase/Write instructions and the internal program-

ming cycle cannot run. When power is first applied,

the M93Cx6 is in Erase/Write Disable mode and all

Erase/Write instructions are inhibited. When the

EWEN instruction is executed, Erase/Write instruc-

tions remain enabled until an Erase/Write Disable

instruction (EWDS) is executed or V_CCfalls below

The Erase All instruction (ERAL) erases the whole

memory (all memory bits are set to ’1’). A dummy

address is input during the instruction transfer and

the erase is made in the same way as the ERASE

instruction above. If the M93Cx6 is still performing

the erase cycle, the Busy signal (Q = 0) will be

returned if S is driven high after the t_SLSHdelay, and

the M93Cx6 will ignore any data on the bus. When

the erase cycle is completed, the Ready signal (Q

= 1) will indicate (if S is driven high) that the

M93Cx6 is ready to receive a new instruction.

9/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 7A. Instruction Set for the M93C06 and M93C46

x8 Org

Req.

x16 Org

Address

Req.

Clock

Cycles

Start

bit

Op-

Instr.

Description

Address

Data

Clock

Data

Code

(ORG = 0) ^{(1, 2)}

Cycles (ORG = 1) ^{(1, 3)}

Read Data from

Memory

READ

WRITE

EWEN

EWDS

ERASE

1

10

01

00

A6-A0

Q7-Q0

D7-D0

A5-A0

Q15-Q0

D15-D0

Write Data to

Memory

18

10

A5-A0

25

9

Erase/Write

Enable

11X XXXX

00X XXXX

11 XXXX

00 XXXX

Erase/Write

Disable

9

Erase Byte or

Word

1

11

00

A6-A0

10

18

A5-A0

9

ERAL Erase All Memory

10X XXXX

01X XXXX

10 XXXX

01 XXXX

Write All Memory

WRAL

D7-D0

D15-D0

25

with same Data

Notes: 1. X = don’t care bit.

2. Address bits A6 and A5 are not decoded by the M93C06.

3. Address bits A5 and A4 are not decoded by the M93C06.

Table 7B. Instruction Set for the M93C56 and M93C66

x8 Org

Req.

x16 Org

Address

Req.

Clock

Cycles

Start

bit

Op-

Instr.

Description

Address

Data

Clock

Data

Code

(ORG = 0) ^{(1, 2)}

Cycles (ORG = 1) ^{(1, 3)}

Read Data from

Memory

READ

WRITE

EWEN

EWDS

ERASE

1

10

01

00

A8-A0

Q7-Q0

D7-D0

A7-A0

Q15-Q0

D15-D0

Write Data to

Memory

20

12

A7-A0

27

11

Erase/Write

Enable

1 1XXX XXXX

0 0XXX XXXX

11XX XXXX

00XX XXXX

Erase/Write

Disable

Erase Byte or

Word

1

11

00

A8-A0

12

20

A7-A0

11

27

ERAL Erase All Memory

1 0XXX XXXX

10XX XXXX

01XX XXXX

Write All Memory

WRAL

0 1XXX XXXX D7-D0

D15-D0

with same Data

Notes: 1. X = don’t care bit.

2. Address bit A8 is not decoded by the M93C56.

3. Address bit A7 is not decoded by the M93C56.

10/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 7C. Instruction Set for the M93C76 and M93C86

x8 Org

Address

Req.

x16 Org

Address

Req.

Clock

Cycles

Start

bit

Op-

Code

Instr.

Description

Data

Clock

Data

(ORG = 0) ^{(1, 2)}

Cycles (ORG = 1) ^{(1, 3)}

Read Data from

Memory

READ

WRITE

EWEN

EWDS

ERASE

1

10

01

00

A10-A0

Q7-Q0

D7-D0

A9-A0

Q15-Q0

D15-D0

Write Data to

Memory

22

14

A9-A0

29

13

Erase/Write

Enable

11X XXXX XXXX

00X XXXX XXXX

11 XXXX XXXX

00 XXXX XXXX

Erase/Write

Disable

Erase Byte or

Word

1

11

00

A10-A0

14

22

A9-A0

13

29

ERAL Erase All Memory

10X XXXX XXXX

10 XXXX XXXX

Write All Memory

WRAL

01X XXXX XXXX D7-D0

01 XXXX XXXX D15-D0

with same Data

Notes: 1. X = don’t care bit.

2. Address bit A10 is not decoded by the M93C76.

3. Address bit A9 is not decoded by the M93C76.

Write All

put (Q) indicates the Ready/Busy status of the

memory when the Chip Select is driven High. Once

the M93Cx6 is Ready, the Data Output is set to ’1’

until a new start bit is decoded or the Chip Select

is brought Low.

The Write All instruction (WRAL) writes the Data

Input byte or word into all the addresses of the

memory device. As for the Erase All instruction, a

dummy address is input during the instruction

transfer.

COMMON I/O OPERATION

If the M93Cx6 is still performing the write cycle, the

Busy signal (Q = 0) will be returned if S is driven

high after the t_SLSHdelay, and the M93Cx6 will

ignore any data on the bus. When the write cycle

is completed, the Ready signal (Q = 1) will indicate

(if S is driven high) that the M93Cx6 is ready to

receive a new instruction.

The Data Output (Q) and Data Input (D) signals can

be connected together, through a current limiting

resistor, to form a common, one wire data bus.

Some precautions must be taken when operating

the memory with this connection, mostly to prevent

a short circuit between the last entered address bit

(A0) and the first data bit output by Q. The reader

should refer to the STMicroelectronics application

note AN394 "MICROWIRE EEPROM Common

I/O Operation".

READY/BUSY Status

During every programming cycle (after a WRITE,

ERASE, WRAL or ERAL instruction) the Data Out-

11/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 6. READ, WRITE, EWEN, EWDS Sequences

READ

S

D

Q

1 1 0 An

A0

Qn

Q0

ADDR

DATA OUT

OP

CODE

WRITE

S

D

Q

CHECK

STATUS

1 0 1 An

A0 Dn

D0

ADDR

DATA IN

BUSY

READY

OP

CODE

ERASE

WRITE

ENABLE

S

D

ERASE

WRITE

DISABLE

S

1 0 0 1 1 Xn X0

D

1 0 0 0 0 Xn X0

OP

CODE

AI00878C

Note: An, Xn, Qn, Dn: Refer to Table 6a for the M93C06 and M93C46; to Table 6b for the M93C56 and M93C66; to Table 6c for the

M93C76 and M93C86.

12/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 7. ERASE, ERAL Sequences

ERASE

S

D

Q

CHECK

STATUS

1 1 1 An

A0

ADDR

BUSY

READY

OP

CODE

ERASE

ALL

S

D

Q

CHECK

STATUS

1 0 0 1 0 Xn X0

ADDR

OP

BUSY

READY

CODE

AI00879B

Note: An, Xn: Refer to Table 7a for the M93C06 and M93C46; to Table 7b for the M93C56 and M93C66; to Table 7c for the M93C76 and

M93C86.

Figure 8. WRAL Sequence

WRITE

ALL

S

D

Q

CHECK

STATUS

1 0 0 0 1 Xn X0 Dn

D0

ADDR

OP

DATA IN

BUSY

READY

CODE

AI00880C

Note: Xn, Dn: Refer to Table 7a for the M93C06 and M93C46; to Table 7b for the M93C56 and M93C66; to Table 7c for the M93C76 and

M93C86.

13/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 9. WRITE Sequence with One Clock Glitch

S

C

D

An

An-1

Glitch

An-2

START

"0"

"1"

D0

ADDRESS AND DATA

ARE SHIFTED BY ONE BIT

WRITE

AI01395

CLOCK PULSE COUNTER

Selectsignal (1 Start bit+ 2 Op-code bit+ 9Address

bit+ 8 Data bit = 20):ifso, the M93C56 (orM93C66)

executes the WRITE instruction; if the number of

clock pulses is not equal to 20, the instruction will

not be executed (and data will not be corrupted).

In the same way, when the organisation x16 is

selected with the M93C56 (or M93C66), the num-

ber of clock pulses incoming to the counter must

be exactly 27 (1 Start bit + 2 Op-code bit + 8

Address bit + 16 Data bit = 27) from the Start bit to

the falling edge of Chip Select signal: if so, the

M93C56 (or M93C66) executes the WRITEinstruc-

tion; if the number of clock pulses is not equal to

27, the instruction will not be executed (and data

will not be corrupted). The clock pulse counter is

active on the WRITE, ERASE, ERAL and WRALL

instructions.

The M93Cx6 offers a functional security block

which filters glitches on the clock input (C), the

clock pulse counter. In a normal environment, the

M93Cx6 expects to receive the exact number of

data bits on the D input (start bit, Op-Code, Ad-

dress, Data); that is the exact amount of clock

pulses on the C input.

In a noisy environment, the number of pulses re-

ceived (on the clock input C) may be greater than

the clock pulses delivered by the Master (Microcon-

troller) driving the M93Cx6. In such a case, a part

of the instruction can be delayed by one or more

bits (see Figure 9), and may induce an erroneous

write of data at an invalid address. The M93Cx6

has an on-chip counter which counts the clock

pulses from the Start bit until the falling edge of the

Chip Select signal.

In order to determine the exact number of clock

pulses needed for all the M93Cx6 family on ERASE

and WRITE instructions, refer to the Tables 7A, 7B

and 7C, in the column: Requested Clock Cycles.

For the WRITE instructions with a M93C56 (or

M93C66), the number of clock pulses incoming to

the counter must be exactly 20 (with the organisa-

tion x8) from the Start bit to the falling edge of Chip

14/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

ORDERING INFORMATION SCHEME

Example:

M93C86 – T W MN

6

T

Memory Density

86 16 Kbit

76 ⁽¹⁾8 Kbit

Option

T

Tape & Reel

Packing

66 4 Kbit

56 2 Kbit

46 1 Kbit

06 256 bit

Turned Mode

T ⁽⁵⁾90° Turned die

blank Standard

Operating Voltage

Package

Temperature Range

1 ⁽²⁾0 to 70 °C

blank 4.5V to 5.5V

BN PSDIP8

0.25mm Frame

W

2.5V to 5.5V

5

–20 to 85 °C

–40 to 85 °C

MN SO8

150mil Width

DW TSSOP8 ⁽⁶⁾

169mil Width

R ⁽⁴⁾1.8V to 3.6V

6

3 ⁽³⁾–40 to 125 C

°

Notes: 1. This is preliminary information on a new product now in development. Details are subject to change without notice.

2. Temperature range on request only.

3. Produced with High Reliability Certified Flow (HRCF), in V_CCrange 4.5V to 5.5V at 1MHz only.

4. -R version (1.8V to 3.6V) are only available in temperature ranges 5 or 1.

5. Turned die option is not available for all devices. Please contact the STMicroelectronics Sales Office nearest to you.

6. TSSOP8 package available for M93C06, 46, 56, 66 low voltage (-W and -R) only.

Devices are shipped from the factory with the memory content set at all "1’s" (FFFFh for x16, FFh for x8).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect

of this device, please contact the STMicroelectronics Sales Office nearest to you.

15/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm

Min

3.90

0.49

3.30

0.36

1.15

0.20

9.20

–

inches

Min

Symb

Typ

Max

5.90

–

Typ

Max

0.232

–

A

A1

A2

B

0.154

0.019

0.130

0.014

0.045

0.008

0.362

–

5.30

0.56

1.65

0.36

9.90

–

0.209

0.022

0.065

0.014

0.390

–

B1

C

D

E

7.62

2.54

0.300

0.100

E1

e1

eA

eB

L

6.00

–

6.70

–

0.236

–

0.264

–

7.80

–

0.307

–

10.00

3.80

0.394

0.150

3.00

8

0.118

8

N

A2

A

L

A1

e1

B

C

eA

eB

B1

D

N

1

E1

E

PSDIP-a

Drawing is not to scale

16/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

SO8 - 8 lead Plastic Small Outline, 150 mils body width

mm

Min

1.35

0.10

0.33

0.19

4.80

3.80

–

inches

Min

Symb

Typ

Max

1.75

0.25

0.51

0.25

5.00

4.00

–

Typ

Max

0.069

0.010

0.020

0.010

0.197

0.157

–

A

A1

B

0.053

0.004

0.013

0.007

0.189

0.150

–

C

D

E

e

1.27

0.050

H

h

5.80

0.25

0.40

0°

6.20

0.50

0.90

8°

0.228

0.010

0.016

0°

0.244

0.020

0.035

8°

L

α

N

CP

8

0.10

0.004

h x 45˚

C

A

B

CP

e

D

N

1

E

H

A1

α

L

SO-a

Drawing is not to scale

17/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

TSSOP8 - 8 lead Plastic Shrink Small Outline, 169 mils body width

mm

Min

inches

Min

Symb

Typ

Max

1.10

0.15

0.95

0.30

0.20

3.10

6.50

4.50

–

Typ

Max

0.043

0.006

0.037

0.012

0.008

0.122

0.256

0.177

–

A

A1

A2

B

0.05

0.85

0.19

0.09

2.90

6.25

4.30

–

0.002

0.033

0.007

0.004

0.114

0.246

0.169

–

C

D

E

E1

e

0.65

0.026

L

0.50

0°

0.70

8°

0.020

0°

0.028

8°

α

N

8

CP

0.08

0.003

D

DIE

N

C

E1

E

1

N/2

α

A1

L

A

A2

B

e

CP

TSSOP

Drawing is not to scale

18/19

M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

® MICROWIRE is a registered trademark of National Semiconductor Corp.

STMicroelectronics GROUP OF COMPANIES

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Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

http://www.st.com

19/19


型号：	M93C56-RBN1
厂家：	ST
描述：	128X16 MICROWIRE BUS SERIAL EEPROM, PDIP8, PLASTIC, SDIP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总19页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M93C56-RBN1 [STMICROELECTRONICS]

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