M93C66-DW3TP/S

更新时间:2024-10-29 07:17:08
描述:16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM

M93C66-DW3TP/S 概述

16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 16千位,千位8 , 4千位,千位2和1千位( 8位或16位宽) MICROWIRE㈢串行EEPROM的访问 EEPROM

M93C66-DW3TP/S 规格参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.15
Is Samacsys:N备用内存宽度:8
最大时钟频率 (fCLK):2 MHzJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.4 mm
内存密度:4096 bit内存集成电路类型:EEPROM
内存宽度:16湿度敏感等级:1
功能数量:1端子数量:8
字数:256 words字数代码:256
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:256X16
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
串行总线类型:MICROWIRE最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mm最长写入周期时间 (tWC):5 ms
Base Number Matches:1

M93C66-DW3TP/S 数据手册

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M93C86, M93C76, M93C66  
M93C56, M93C46  
16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide)  
MICROWIRE® serial access EEPROM  
Features  
Industry standard MICROWIRE bus  
Single supply voltage:  
4.5 V to 5.5 V for M93Cx6  
2.5 V to 5.5 V for M93Cx6-W  
1.8 V to 5.5 V for M93Cx6-R  
PDIP8 (BN)  
Dual organization: by word (x16) or byte (x8)  
Programming instructions that work on: byte,  
word or entire memory  
Self-timed programming cycle with auto-  
erase: 5 ms  
READY/BUSY signal during programming  
2 MHz clock rate  
SO8 (MN)  
150 mil width  
Sequential read operation  
Enhanced ESD/latch-up behavior  
More than 1 million write cycles  
More than 40 year data retention  
Packages  
TSSOP8 (DW)  
169 mil width  
ECOPACK® (RoHS compliant)  
Table 1.  
Reference  
Product list  
Part  
Part  
number  
UFDFPN8 (MB)  
2 x 3 mm (MLP)  
Reference  
number  
M93C86  
M93C56  
M93C86 M93C86-W  
M93C86-R  
M93C56 M93C56-W  
M93C56-R  
M93C66  
M93C46  
M93C66 M93C66-W  
M93C66-R  
M93C46 M93C46-W  
M93C46-R  
M93C76  
M93C76  
M93C76-W  
July 2007  
Rev 7  
1/38  
www.st.com  
1
Contents  
M93C86, M93C76, M93C66, M93C56, M93C46  
Contents  
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
3.1  
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
3.1.1  
3.1.2  
3.1.3  
3.1.4  
Operating supply voltage V  
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
4
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
5.1  
5.2  
5.3  
5.4  
5.5  
5.6  
Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
6
READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
7
8
9
10  
11  
12  
2/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Contents  
13  
14  
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
3/38  
List of tables  
M93C86, M93C76, M93C66, M93C56, M93C46  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Table 18.  
Table 19.  
Table 20.  
Table 21.  
Table 22.  
Table 23.  
Table 24.  
Product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Instruction set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Operating conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Operating conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
AC measurement conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
AC measurement conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . 22  
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
DC characteristics (M93Cx6, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
DC characteristics (M93Cx6, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
DC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
DC characteristics (M93Cx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
DC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
AC characteristics (M93Cx6, device grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
AC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
AC characteristics (M93Cx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
AC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package  
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . 30  
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . 31  
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32  
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Available M93C46-x products (package, voltage range, temperature grade). . . . . . . . . . . 34  
Available M93C56-x products (package, voltage range, temperature grade). . . . . . . . . . . 34  
Available M93C66-x products (package, voltage range, temperature grade). . . . . . . . . . . 34  
Available M93C76-x products (package, voltage range, temperature grade). . . . . . . . . . . 34  
Available M93C86-x products (package, voltage range, temperature grade). . . . . . . . . . . 35  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Table 25.  
Table 26.  
Table 27.  
Table 28.  
Table 29.  
Table 30.  
Table 31.  
Table 32.  
Table 33.  
Table 34.  
4/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
List of figures  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
DIP, SO, TSSOP and MLP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
READ, WRITE, WEN, WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Figure 10. Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 11. Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package  
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 30  
Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline 31  
Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32  
5/38  
Description  
M93C86, M93C76, M93C66, M93C56, M93C46  
1
Description  
The M93C86, M93C76, M93C66, M93C56 and M93C56 are electrically erasable  
programmable memory (EEPROM) devices. They are accessed through a Serial Data input  
(D) and Serial Data output (Q) using the MICROWIRE bus protocol.  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. ECOPACK® packages are lead-free and RoHS compliant. ECOPACK is an ST  
trademark. ECOPACK specifications are available at: www.st.com.  
Figure 1.  
Logic diagram  
V
CC  
D
Q
C
S
M93Cx6  
ORG  
V
SS  
AI01928  
Table 2.  
Signal names  
Signal name  
Function  
Direction  
S
Chip Select  
Input  
Input  
Output  
Input  
Input  
D
Serial Data input  
Q
Serial Data output  
Serial Clock  
C
ORG  
VCC  
VSS  
Organisation Select  
Supply voltage  
Ground  
The memory array organization may be divided into either bytes (x8) or words (x16) which  
may be selected by a signal applied on Organization Select (ORG). The bit, byte and word  
sizes of the memories are as shown in Table 3.  
6/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Description  
Table 3.  
Device  
Memory size versus organization  
Number of bits  
Number of 8-bit bytes  
Number of 16-bit words  
M93C86  
M93C76  
M93C66  
M93C56  
M93C46  
16384  
8192  
4096  
2048  
1024  
2048  
1024  
512  
1024  
512  
256  
128  
64  
256  
128  
The M93Cx6 is accessed by a set of instructions, as summarized in Table 4., and in more  
detail in Table 5. to Table 7.).  
Table 4.  
Instruction set for the M93Cx6  
Description  
Instruction  
Data  
Byte or Word  
READ  
WRITE  
WEN  
Read Data from Memory  
Write Data to Memory  
Write Enable  
Byte or Word  
WDS  
Write Disable  
ERASE  
ERAL  
Erase Byte or Word  
Erase All Memory  
Byte or Word  
Write All Memory  
with same Data  
WRAL  
A Read Data from Memory (READ) instruction loads the address of the first byte or word to  
be read in an internal address register. The data at this address is then clocked out serially.  
The address register is automatically incremented after the data is output and, if Chip Select  
Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In  
this way, the memory can be read as a data stream from eight to 16384 bits long (in the  
case of the M93C86), or continuously (the address counter automatically rolls over to 00h  
when the highest address is reached).  
Programming is internally self-timed (the external clock signal on Serial Clock (C) may be  
stopped or left running after the start of a Write cycle) and does not require an Erase cycle  
prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the  
byte or word locations of the M93Cx6. After the start of the programming cycle, a  
Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is  
driven High.  
An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when  
the supply is too low.  
7/38  
Description  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 2.  
DIP, SO, TSSOP and MLP connections (top view)  
M93Cx6  
S
C
D
Q
1
8
V
CC  
DU  
2
3
4
7
6
5
ORG  
V
SS  
AI01929B  
1. See Package mechanical section for package dimensions, and how to identify pin-1.  
2. DU = Don’t Use.  
The DU (do not use) pin does not contribute to the normal operation of the device. It is  
reserved for use by STMicroelectronics during test sequences. The pin may be left  
unconnected or may be connected to V or V  
.
CC  
SS  
8/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Connecting to the serial bus  
2
Connecting to the serial bus  
Figure 3.  
Bus master and memory devices on the serial bus  
V
V
SS  
CC  
SDO  
SDI  
SCK  
Bus master  
V
V
V
CC  
C
Q
D
C
Q
D
C Q D  
CC  
CC  
V
V
V
SS  
SS  
SS  
M93xxx  
memory device  
M93xxx  
memory device  
M93xxx  
memory device  
R
R
R
CS3 CS2 CS1  
S
S
S
ORG  
ORG  
ORG  
AI14377  
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.  
Only one device is selected at a time, so only one device drives the Serial Data Output (Q)  
line at a time, the other devices are high impedance.  
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the  
Bus Master leaves the S line in the high impedance state.  
9/38  
Operating features  
M93C86, M93C76, M93C66, M93C56, M93C46  
3
Operating features  
3.1  
Supply voltage (VCC)  
3.1.1  
Operating supply voltage V  
CC  
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage  
CC  
within the specified [V (min), V (max)] range must be applied. In order to secure a stable  
CC  
CC  
DC supply voltage, it is recommended to decouple the V line with a suitable capacitor  
CC  
(usually of the order of 10 nF to 100 nF) close to the V /V package pins.  
CC SS  
This voltage must remain stable and valid until the end of the transmission of the instruction  
and, for a Write instruction, until the completion of the internal write cycle (t ).  
W
3.1.2  
3.1.3  
Power-up conditions  
When the power supply is turned on, V rises from V to V . During this time, the Chip  
Select (S) line is not allowed to float and should be driven to V , it is therefore  
recommended to connect the S line to V via a suitable pull-down resistor.  
CC  
SS  
CC  
SS  
CC  
The V rise time must not vary faster than 1 V/µs.  
CC  
Power-up and device reset  
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)  
circuit is included. At power-up (continuous rise of V ), the device does not respond to any  
CC  
instruction until V has reached the power on reset threshold voltage (this threshold is  
CC  
lower than the minimum V operating voltage defined in Table 9, Table 10 and Table 11).  
CC  
When V passes the POR threshold, the device is reset and is in the following state:  
CC  
Standby Power mode  
deselected (assuming that there is a pull-down resistor on the S line)  
3.1.4  
Power-down  
At power-down (continuous decrease in V ), as soon as V drops from the normal  
CC  
CC  
operating voltage to below the power on reset threshold voltage, the device stops  
responding to any instruction sent to it.  
During power-down, the device must be deselected and in the Standby Power mode (that is,  
there should be no internal Write cycle in progress).  
10/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Memory organization  
4
Memory organization  
The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization  
Select (ORG) is left unconnected (or connected to V ) the x16 organization is selected;  
CC  
when Organization Select (ORG) is connected to Ground (V ) the x8 organization is  
SS  
selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set  
either to V or V for minimum power consumption. Any voltage between V and V  
SS  
CC  
SS  
CC  
applied to Organization Select (ORG) may increase the Standby current.  
11/38  
Instructions  
M93C86, M93C76, M93C66, M93C56, M93C46  
5
Instructions  
The instruction set of the M93Cx6 devices contains seven instructions, as summarized in  
Table 5. to Table 7.. Each instruction consists of the following parts, as shown in Figure 4.:  
Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock  
(C) being held low.  
A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of  
Serial Clock (C).  
Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock  
(C). (Some instructions also use the first two bits of the address to define the op-code).  
The address bits of the byte or word that is to be accessed. For the M93C46, the  
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization  
(see Table 5.). For the M93C56 and M93C66, the address is made up of 8 bits for the  
x16 organization or 9 bits for the x8 organization (see Table 6.). For the M93C76 and  
M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8  
organization (see Table 7.).  
The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as  
slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 20. to  
Table 23..  
Table 5.  
Instruction set for the M93C46  
x8 origination (ORG = 0)  
x16 origination (ORG = 1)  
Start Op-  
Required  
clock  
Required  
Address  
Instruction  
Description  
Address  
bit  
code  
Data  
Data  
clock  
(1)  
(1)  
cycles  
cycles  
Read Data from  
Memory  
READ  
WRITE  
WEN  
1
1
1
1
1
1
1
10  
01  
00  
00  
11  
00  
00  
A6-A0  
A6-A0  
Q7-Q0  
D7-D0  
A5-A0  
A5-A0  
Q15-Q0  
D15-D0  
Write Data to  
Memory  
18  
10  
10  
10  
10  
18  
25  
9
11X  
XXXX  
Write Enable  
Write Disable  
11 XXXX  
00 XXXX  
A5-A0  
00X  
XXXX  
WDS  
9
Erase Byte or  
Word  
ERASE  
ERAL  
WRAL  
A6-A0  
9
10X  
XXXX  
Erase All Memory  
10 XXXX  
9
Write All Memory  
with same Data  
01X  
XXXX  
D7-D0  
01 XXXX D15-D0  
25  
1. X = Don't Care bit.  
12/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Instructions  
Table 6.  
Instruction set for the M93C56 and M93C66  
x8 origination (ORG = 0)  
x16 origination (ORG = 1)  
Start Op-  
bit code  
Instruction  
Description  
Address  
Required Address  
clock cycles  
Required  
clock cycles  
Data  
Data  
(1) (2)  
(1) (3)  
Read Data from  
Memory  
READ  
WRITE  
WEN  
1
1
1
1
1
1
1
10  
01  
00  
00  
11  
00  
00  
A8-A0  
A8-A0  
Q7-Q0  
D7-D0  
A7-A0 Q15-Q0  
A7-A0 D15-D0  
Write Data to  
Memory  
20  
12  
12  
12  
12  
20  
27  
11  
11  
11  
11  
27  
1 1XXX  
XXXX  
11XX  
XXXX  
Write Enable  
Write Disable  
0 0XXX  
XXXX  
00XX  
XXXX  
WDS  
Erase Byte or  
Word  
ERASE  
ERAL  
WRAL  
A8-A0  
A7-A0  
Erase All  
Memory  
1 0XXX  
XXXX  
10XX  
XXXX  
Write All Memory  
with same Data  
0 1XXX  
XXXX  
01XX  
D7-D0  
D15-D0  
XXXX  
1. X = Don't Care bit.  
2. Address bit A8 is not decoded by the M93C56.  
3. Address bit A7 is not decoded by the M93C56.  
Table 7.  
Instruction set for the M93C76 and M93C86  
x8 Origination (ORG = 0)  
x16 Origination (ORG = 1)  
Start Op-  
bit code  
Required  
clock  
Required  
Address  
Instruction  
Description  
Address(1),  
Data  
Data  
clock  
(2)  
(1) (3)  
cycles  
cycles  
Read Data from  
Memory  
READ  
WRITE  
WEN  
1
1
1
10  
01  
00  
A10-A0  
A10-A0  
Q7-Q0  
D7-D0  
A9-A0 Q15-Q0  
A9-A0 D15-D0  
Write Data to  
Memory  
22  
14  
29  
13  
11X XXXX  
XXXX  
11XXXX  
XXXX  
Write Enable  
00X XXXX  
XXXX  
00XXXX  
XXXX  
WDS  
Write Disable  
1
1
1
00  
11  
00  
14  
14  
14  
13  
13  
13  
ERASE  
ERAL  
Erase Byte or Word  
Erase All Memory  
A10-A0  
A9-A0  
10X XXXX  
XXXX  
10XXXX  
XXXX  
Write All Memory  
with same Data  
01X XXXX  
XXXX  
01XXXX  
D15-D0  
XXXX  
WRAL  
1
00  
D7-D0  
22  
29  
1. X = Don't Care bit.  
2. Address bit A10 is not decoded by the M93C76.  
3. Address bit A9 is not decoded by the M93C76.  
13/38  
Instructions  
M93C86, M93C76, M93C66, M93C56, M93C46  
5.1  
Read Data from Memory  
The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).  
When the instruction is received, the op-code and address are decoded, and the data from  
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed  
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are  
triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the  
internal address register and clocks out the next byte (or word) as long as the Chip Select  
Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words)  
and a continuous stream of data can be read.  
5.2  
Write Enable and Write Disable  
The Write Enable (WEN) instruction enables the future execution of erase or write  
instructions, and the Write Disable (WDS) instruction disables it. When power is first  
applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After  
an Write Enable (WEN) instruction has been executed, erasing and writing remains enabled  
until an Write Disable (WDS) instruction is executed, or until V falls below the power-on  
CC  
reset threshold voltage. To protect the memory contents from accidental corruption, it is  
advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read  
Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write  
Disable (WDS) instructions.  
14/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Instructions  
Figure 4.  
READ, WRITE, WEN, WDS sequences  
Read  
S
D
Q
1 1 0 An  
A0  
Qn  
Q0  
ADDR  
DATA OUT  
OP  
CODE  
Write  
S
D
Q
CHECK  
STATUS  
1 0 1 An  
A0 Dn  
D0  
ADDR  
DATA IN  
BUSY  
READY  
OP  
CODE  
Write  
Enable  
S
D
Write  
Disable  
S
1 0 0 1 1 Xn X0  
D
1 0 0 0 0 Xn X0  
OP  
OP  
CODE  
CODE  
AI00878d  
1. For the meanings of An, Xn, Qn and Dn, see Table 5., Table 6. and Table 7..  
5.3  
Erase Byte or Word  
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or  
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip  
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be  
detected by monitoring the READY/BUSY line, as described in the READY/BUSY status  
section.  
15/38  
Instructions  
M93C86, M93C76, M93C66, M93C56, M93C46  
5.4  
Write  
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and  
address bits. These form the byte or word that is to be written. As with the other bits, Serial  
Data Input (D) is sampled on the rising edge of Serial Clock (C).  
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before  
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after  
this specific time frame, the self-timed programming cycle will not be started, and the  
addressed location will not be programmed. The completion of the cycle can be detected by  
monitoring the READY/BUSY line, as described later in this document.  
Once the Write cycle has been started, it is internally self-timed (the external clock signal on  
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is  
automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase  
instruction before a Write Data to Memory (WRITE) instruction.  
Figure 5.  
ERASE, ERAL sequences  
ERASE  
S
D
Q
CHECK  
STATUS  
1 1 1 An  
A0  
ADDR  
BUSY  
READY  
OP  
CODE  
ERASE  
ALL  
S
D
Q
CHECK  
STATUS  
1 0 0 1 0 Xn X0  
ADDR  
OP  
BUSY  
READY  
CODE  
AI00879B  
1. For the meanings of An and Xn, please see Table 5., Table 6. and Table 7..  
5.5  
Erase All  
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set  
to 1). The format of the instruction requires that a dummy address be provided. The Erase  
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of  
the cycle can be detected by monitoring the READY/BUSY line, as described in the  
READY/BUSY status section.  
16/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Instructions  
5.6  
Write All  
As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with  
same Data (WRAL) instruction requires that a dummy address be provided. As with the  
Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same  
Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.  
This value is written to all the addresses of the memory device. The completion of the cycle  
can be detected by monitoring the READY/BUSY line, as described next.  
Figure 6.  
WRAL sequence  
WRITE  
ALL  
S
CHECK  
STATUS  
D
Q
1 0 0 0 1 Xn X0 Dn  
D0  
ADDR  
DATA IN  
BUSY  
READY  
OP  
CODE  
AI00880C  
1. For the meanings of Xn and Dn, please see Table 5., Table 6. and Table 7..  
17/38  
READY/BUSY status  
M93C86, M93C76, M93C66, M93C56, M93C46  
6
READY/BUSY status  
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL  
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.  
(Please note, though, that there is an initial delay, of t  
, before this status information  
SLSH  
becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write  
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)  
indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)  
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is  
decoded.  
7
8
Initial delivery state  
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).  
Common I/O operation  
Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a  
current limiting resistor, to form a common, single-wire data bus. Some precautions must be  
taken when operating the memory in this way, mostly to prevent a short circuit current from  
flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output  
(Q). Please see the application note AN394 for details.  
18/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Clock pulse counter  
9
Clock pulse counter  
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater  
than the number delivered by the master (the microcontroller). This can lead to a  
misalignment of the instruction of one or more bits (as shown in Figure 7.) and may lead to  
the writing of erroneous data at an erroneous address.  
To combat this problem, the M93Cx6 has an on-chip counter that counts the clock pulses  
from the start bit until the falling edge of the Chip Select Input (S). If the number of clock  
pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL  
instruction is aborted, and the contents of the memory are not modified.  
The number of clock cycles expected for each instruction, and for each member of the  
M93Cx6 family, are summarized in Table 5. to Table 7.. For example, a Write Data to  
Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the  
x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is:  
1 Start bit  
+ 2 Op-code bits  
+ 9 Address bits  
+ 8 Data bits  
Figure 7.  
Write sequence with one clock glitch  
S
C
D
An  
An-1  
Glitch  
An-2  
START  
"0"  
"1"  
D0  
ADDRESS AND DATA  
ARE SHIFTED BY ONE BIT  
WRITE  
AI01395  
19/38  
Maximum rating  
M93C86, M93C76, M93C66, M93C56, M93C46  
10  
Maximum rating  
Stressing the device above the rating listed in the absolute maximum ratings table may  
cause permanent damage to the device. These are stress ratings only and operation of the  
device at these or any other conditions above those indicated in the operating sections of  
this specification is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE  
Program and other relevant quality documents.  
Table 8.  
Symbol  
Absolute maximum ratings  
Parameter  
Min.  
Max.  
Unit  
TA  
Ambient operating temperature  
Storage temperature  
–40  
–65  
130  
150  
°C  
°C  
°C  
V
TSTG  
TLEAD PDIP-specific lead temperature during soldering  
260(1)  
VCC+0.5  
VCC+1  
6.5  
VOUT  
VIN  
Output range (Q = VOH or Hi-Z)  
Input range  
–0.50  
–0.50  
–0.50  
V
VCC  
Supply voltage  
V
Electrostatic discharge voltage (human body  
model)(2)  
VESD  
–4000  
4000  
V
1. TLEADmax must not be applied for more than 10 s.  
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ).  
20/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
DC and AC parameters  
11  
DC and AC parameters  
This section summarizes the operating and measurement conditions, and the dc and ac  
characteristics of the device. The parameters in the dc and ac characteristic tables that  
follow are derived from tests performed under the measurement conditions summarized in  
the relevant tables. Designers should check that the operating conditions in their circuit  
match the measurement conditions when relying on the quoted parameters.  
Table 9.  
Symbol  
Operating conditions (M93Cx6)  
Parameter  
Min.  
Max.  
Unit  
VCC  
TA  
Supply voltage  
4.5  
–40  
–40  
5.5  
85  
V
Ambient operating temperature (device grade 6)  
Ambient operating temperature (device grade 3)  
°C  
°C  
125  
Table 10. Operating conditions (M93Cx6-W)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
VCC  
Supply voltage  
2.5  
–40  
–40  
5.5  
85  
V
Ambient operating temperature (device grade 6)  
Ambient operating temperature (device grade 3)  
°C  
°C  
TA  
125  
Table 11. Operating conditions (M93Cx6-R)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
VCC  
TA  
Supply voltage  
Ambient operating temperature (device grade 6)  
1.8  
5.5  
85  
V
–40  
°C  
(1)  
Table 12. AC measurement conditions (M93Cx6)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
CL  
Load capacitance  
100  
pF  
ns  
V
Input rise and fall times  
50  
Input pulse voltages  
0.4 V to 2.4 V  
1.0 V and 2.0 V  
0.8 V and 2.0 V  
Input timing reference voltages  
Output timing reference voltages  
V
V
1. Output Hi-Z is defined as the point where data out is no longer driven.  
21/38  
DC and AC parameters  
M93C86, M93C76, M93C66, M93C56, M93C46  
(1)  
Table 13. AC measurement conditions (M93Cx6-W and M93Cx6-R)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
CL  
Load capacitance  
100  
pF  
ns  
V
Input rise and fall times  
50  
Input pulse voltages  
0.2VCC to 0.8VCC  
0.3VCC to 0.7VCC  
0.3VCC to 0.7VCC  
Input timing reference voltages  
Output timing reference voltages  
V
V
1. Output Hi-Z is defined as the point where data out is no longer driven.  
Figure 8.  
AC testing input output waveforms  
M93CXX  
2.4V  
2V  
2.0V  
0.8V  
1V  
0.4V  
INPUT  
OUTPUT  
M93CXX-W & M93CXX-R  
0.8V  
0.2V  
CC  
CC  
0.7V  
CC  
0.3V  
CC  
AI02553  
(1)  
Table 14. Capacitance  
Symbol  
COUT  
CIN  
Parameter  
Test condition  
Min  
Max  
Unit  
pF  
pF  
Output capacitance  
Input capacitance  
VOUT = 0V  
VIN = 0V  
5
5
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 1 MHz.  
Table 15. DC characteristics (M93Cx6, device grade 6)  
Symbol  
Parameter  
Test condition  
Min.  
Max.  
Unit  
ILI  
Input leakage current  
Output leakage current  
0V VIN VCC  
±2.5  
±2.5  
µA  
µA  
ILO  
0V VOUT VCC, Q in Hi-Z  
V
CC = 5 V, S = VIH, f = 2 MHz,  
ICC  
Supply current  
2
mA  
µA  
Q = open  
V
CC = 5 V, S = VSS, C = VSS  
,
ICC1  
Supply current (Standby)  
ORG = VSS or VCC  
,
15  
pin7 = VCC, VSS or Hi-Z  
(1)  
VIL  
Input low voltage  
Input high voltage  
Output low voltage  
Output high voltage  
VCC = 5 V ± 10%  
–0.45  
2
0.8  
V
V
V
V
(1)  
VIH  
VCC = 5 V ± 10%  
VCC + 1  
0.4  
(1)  
VOL  
VCC = 5 V, IOL = 2.1 mA  
VCC = 5 V, IOH = –400 µA  
(1)  
VOH  
2.4  
1. The input and output levels are compatible with TTL logic levels.  
22/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
DC and AC parameters  
Table 16. DC characteristics (M93Cx6, device grade 3)  
Symbol  
Parameter  
Test condition  
Min.  
Max.  
Unit  
ILI  
Input leakage current  
Output leakage current  
0V VIN VCC  
±2.5  
±2.5  
µA  
µA  
ILO  
0V VOUT VCC, Q in Hi-Z  
VCC = 5 V, S = VIH, f = 2 MHz,  
Q = open  
ICC  
Supply current  
2
mA  
µA  
VCC = 5 V, S = VSS, C = VSS  
,
ICC1  
Supply current (Standby)  
ORG = VSS or VCC  
,
15  
pin7 = VCC, VSS or Hi-Z  
VIL  
VIH  
Input low voltage  
Input high voltage  
Output low voltage  
Output high voltage  
VCC = 5 V ± 10%  
–0.45  
2
0.8  
VCC + 1  
0.4  
V
V
V
V
VCC = 5 V ± 10%  
VOL  
VOH  
VCC = 5 V, IOL = 2.1 mA  
VCC = 5 V, IOH = –400 µA  
2.4  
Table 17. DC characteristics (M93Cx6-W, device grade 6)  
Symbol  
Parameter  
Test condition  
Min.  
Max.  
Unit  
ILI  
Input leakage current  
Output leakage current  
0V VIN VCC  
±2.5  
±2.5  
µA  
µA  
ILO  
0V VOUT VCC, Q in Hi-Z  
VCC = 5 V, S = VIH, f = 2 MHz,  
Q = open  
2
1
mA  
mA  
Supply current (CMOS  
inputs)  
ICC  
VCC = 2.5 V, S = VIH, f = 2 MHz,  
Q = open  
V
CC = 2.5 V, S = VSS, C = VSS  
ORG = VSS or VCC  
pin7 = VCC, VSS or Hi-Z  
,
ICC1  
Supply current (Standby)  
,
5
µA  
VIL  
Input low voltage (D, C, S)  
Input high voltage (D, C, S)  
–0.45 0.2 VCC  
V
V
V
V
V
V
VIH  
0.7 VCC VCC + 1  
V
CC = 5 V, IOL = 2.1 mA  
CC = 2.5 V, IOL = 100 µA  
CC = 5 V, IOH = –400 µA  
VCC = 2.5 V, IOH = –100 µA  
0.4  
VOL  
Output low voltage (Q)  
Output high voltage (Q)  
V
0.2  
V
2.4  
VOH  
VCC–0.2  
23/38  
DC and AC parameters  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 18. DC characteristics (M93Cx6-W, device grade 3)  
Symbol  
Parameter  
Test condition  
Min.(1) Max. (1) Unit  
ILI  
Input leakage current  
Output leakage current  
0V VIN VCC  
±2.5  
±2.5  
µA  
µA  
ILO  
0V VOUT VCC, Q in Hi-Z  
VCC = 5 V, S = VIH, f = 2 MHz,  
Q = open  
2
1
mA  
mA  
Supply current (CMOS  
inputs)  
ICC  
VCC = 2.5 V, S = VIH, f = 2 MHz,  
Q = open  
VCC = 2.5 V, S = VSS, C = VSS  
ORG = VSS or VCC  
pin7 = VCC, VSS or Hi-Z  
,
ICC1  
Supply current (Standby)  
,
5
µA  
Input low voltage (D, C,  
S)  
VIL  
VIH  
–0.45  
0.2 VCC  
V
V
Input high voltage (D, C,  
S)  
0.7 VCC VCC + 1  
V
CC = 5 V, IOL = 2.1 mA  
CC = 2.5 V, IOL = 100 µA  
CC = 5 V, IOH = –400 µA  
VCC = 2.5 V, IOH = –10 0µA  
0.4  
V
V
V
V
VOL  
Output low voltage (Q)  
Output high voltage (Q)  
V
0.2  
V
2.4  
VOH  
VCC–0.2  
1. New product: identified by Process Identification letter W or G or S.  
Table 19. DC characteristics (M93Cx6-R)  
Symbol  
Parameter  
Test condition  
Min.(1) Max. (1) Unit  
ILI  
Input leakage current  
Output leakage current  
0V VIN VCC  
±2.5  
±2.5  
µA  
µA  
ILO  
0V VOUT VCC, Q in Hi-Z  
VCC = 5 V, S = VIH, f = 2 MHz,  
Q = open  
2
1
mA  
mA  
Supply current (CMOS  
inputs)  
ICC  
VCC = 1.8 V, S = VIH, f = 1 MHz,  
Q = open  
V
CC = 1.8 V, S = VSS, C = VSS  
,
ICC1  
Supply current (Standby)  
ORG = VSS or VCC  
,
2
µA  
pin7 = VCC, VSS or Hi-Z  
Input low voltage (D, C,  
S)  
VIL  
VIH  
–0.45 0.2 VCC  
0.8 VCC VCC + 1  
V
V
Input high voltage (D, C,  
S)  
VOL  
VOH  
Output low voltage (Q)  
Output high voltage (Q)  
VCC = 1.8 V, IOL = 100 µA  
VCC = 1.8 V, IOH = –100 µA  
0.2  
V
V
VCC–0.2  
1. This product is under development. For more information, please contact your nearest ST sales office.  
24/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
DC and AC parameters  
Table 20. AC characteristics (M93Cx6, device grade 6 or 3)  
Test conditions specified in Table 12. and Table 9.  
Symbol  
Alt.  
Parameter  
Min.  
Max.  
Unit  
fC  
fSK  
Clock frequency  
D.C.  
50  
2
MHz  
ns  
tSLCH  
Chip Select low to Clock high  
Chip Select setup time  
M93C46, M93C56, M93C66  
50  
50  
ns  
ns  
tSHCH  
tCSS  
Chip Select setup time  
M93C76, M93C86  
(1)  
tSLSH  
tCS  
tSKH  
tSKL  
tDIS  
tDIH  
tSKS  
tCSH  
tSV  
Chip Select low to Chip Select high  
Clock high time  
200  
200  
200  
50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
(2)  
tCHCL  
(2)  
tCLCH  
Clock low time  
tDVCH  
tCHDX  
tCLSH  
tCLSL  
tSHQV  
tSLQZ  
tCHQL  
tCHQV  
tW  
Data in setup time  
Data in hold time  
50  
Clock setup time (relative to S)  
Chip Select hold time  
50  
0
Chip Select to READY/BUSY status  
Chip Select low to output Hi-Z  
Delay to output low  
200  
100  
200  
200  
5
tDF  
tPD0  
tPD1  
tWP  
Delay to output valid  
Erase or Write cycle time  
1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles.  
2. tCHCL + tCLCH 1 / fC.  
Table 21. AC characteristics (M93Cx6-W, device grade 6)  
Test conditions specified in Table 13. and Table 10.  
Symbol  
Alt.  
Parameter  
Clock frequency  
Min.  
Max.  
Unit  
fC  
fSK  
D.C.  
50  
2
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSLCH  
tSHCH  
Chip Select low to Clock high  
Chip Select setup time  
Chip Select low to Chip Select high  
Clock high time  
tCSS  
tCS  
50  
(1)  
tSLSH  
200  
200  
200  
50  
(2)  
tCHCL  
tSKH  
tSKL  
tDIS  
tDIH  
tSKS  
tCSH  
tSV  
(2)  
tCLCH  
Clock low time  
tDVCH  
tCHDX  
tCLSH  
tCLSL  
tSHQV  
Data in setup time  
Data in hold time  
50  
Clock setup time (relative to S)  
Chip Select hold time  
50  
0
Chip Select to READY/BUSY status  
200  
25/38  
DC and AC parameters  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 21. AC characteristics (M93Cx6-W, device grade 6)  
Test conditions specified in Table 13. and Table 10.  
Symbol  
Alt.  
Parameter  
Min.  
Max.  
Unit  
tSLQZ  
tCHQL  
tCHQV  
tW  
tDF  
tPD0  
tPD1  
tWP  
Chip Select low to output Hi-Z  
Delay to output low  
100  
200  
200  
5
ns  
ns  
ns  
ms  
Delay to output valid  
Erase or Write cycle time  
1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles.  
2. tCHCL + tCLCH 1 / fC.  
Table 22. AC characteristics (M93Cx6-W, device grade 3)  
Test conditions specified in Table 13. and Table 10.  
Symbol  
Alt.  
Parameter  
Clock frequency  
Min.  
Max.  
Unit  
fC  
fSK  
D.C.  
50  
2
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
tSLCH  
tSHCH  
Chip Select low to Clock high  
Chip Select set-up time  
Chip Select low to Chip Select high  
Clock high time  
tCSS  
tCS  
50  
(1)  
tSLSH  
200  
200  
200  
50  
(2)  
tCHCL  
tSKH  
tSKL  
tDIS  
tDIH  
tSKS  
tCSH  
tSV  
(2)  
tCLCH  
Clock low time  
tDVCH  
tCHDX  
tCLSH  
tCLSL  
tSHQV  
tSLQZ  
tCHQL  
tCHQV  
tW  
Data in set-up time  
Data in hold time  
50  
Clock set-up time (relative to S)  
Chip Select hold time  
50  
0
Chip Select to READY/BUSY status  
Chip Select low to output Hi-Z  
Delay to output low  
200  
100  
200  
200  
5
tDF  
tPD0  
tPD1  
tWP  
Delay to output valid  
Erase or Write cycle time  
1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles.  
2. tCHCL + tCLCH 1 / fC.  
26/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 23. AC characteristics (M93Cx6-R)  
DC and AC parameters  
Test conditions specified in Table 13. and Table 11.  
Symbol  
Alt.  
Parameter  
Min.(1)  
Max.(1)  
Unit  
fC  
fSK  
Clock frequency  
D.C.  
250  
50  
1
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
tSLCH  
tSHCH  
Chip Select low to Clock high  
Chip Select setup time  
Chip Select low to Chip Select high  
Clock high time  
tCSS  
tCS  
(2)  
tSLSH  
250  
250  
250  
100  
100  
100  
0
(3)  
tCHCL  
tSKH  
tSKL  
tDIS  
tDIH  
tSKS  
tCSH  
tSV  
(3)  
tCLCH  
Clock low time  
tDVCH  
tCHDX  
tCLSH  
tCLSL  
tSHQV  
tSLQZ  
tCHQL  
tCHQV  
tW  
Data in setup time  
Data in hold time  
Clock setup time (relative to S)  
Chip Select hold time  
Chip Select to READY/BUSY status  
Chip Select low to output Hi-Z  
Delay to output low  
400  
200  
400  
400  
10  
tDF  
tPD0  
tPD1  
tWP  
Delay to output valid  
Erase or Write cycle time  
1. This product is under development. For more information, please contact your nearest ST sales office.  
2. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles.  
3. tCHCL + tCLCH 1 / fC.  
Figure 9.  
Synchronous timing (start and op-code input)  
tCLSH  
tCHCL  
C
S
D
tSHCH  
tCLCH  
tDVCH  
START  
tCHDX  
OP CODE  
OP CODE  
START  
OP CODE INPUT  
AI01428  
27/38  
DC and AC parameters  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 10. Synchronous timing (Read or Write)  
C
tCLSL  
S
tDVCH  
tCHDX  
tCHQV  
tSLSH  
A0  
D
Q
An  
tSLQZ  
tCHQL  
Hi-Z  
Q15/Q7  
Q0  
ADDRESS INPUT  
DATA OUTPUT  
AI00820C  
Figure 11. Synchronous timing (Read or Write)  
tSLCH  
C
S
tCLSL  
tDVCH  
tCHDX  
A0/D0  
tSLSH  
D
Q
An  
tSHQV  
BUSY  
tSLQZ  
READY  
Hi-Z  
tW  
ADDRESS/DATA INPUT  
WRITE CYCLE  
AI01429  
28/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Package mechanical  
12  
Package mechanical  
Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package  
outline  
E
b2  
A2  
A1  
A
L
c
b
e
eA  
eB  
D
8
1
E1  
PDIP-B  
1. Drawing is not to scale.  
Table 24. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package  
mechanical data  
millimeters  
Min.  
inches  
Min.  
Symbol  
Typ.  
Max.  
Typ.  
Max.  
A
A1  
A2  
b
5.33  
0.210  
0.38  
2.92  
0.36  
1.14  
0.20  
9.02  
7.62  
6.10  
0.015  
0.115  
0.014  
0.045  
0.008  
0.355  
0.300  
0.240  
3.30  
0.46  
1.52  
0.25  
9.27  
7.87  
6.35  
2.54  
7.62  
4.95  
0.56  
1.78  
0.36  
10.16  
8.26  
7.11  
0.130  
0.018  
0.060  
0.010  
0.365  
0.310  
0.250  
0.100  
0.300  
0.195  
0.022  
0.070  
0.014  
0.400  
0.325  
0.280  
b2  
c
D
E
E1  
e
eA  
eB  
L
10.92  
3.81  
0.430  
0.150  
3.30  
2.92  
0.130  
0.115  
29/38  
Package mechanical  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package  
outline  
h x 45˚  
A2  
A
c
ccc  
b
e
0.25 mm  
D
GAUGE PLANE  
k
8
1
E1  
E
L
A1  
L1  
SO-A  
1. Drawing is not to scale.  
Table 25. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package  
data  
millimeters  
Min  
inches  
Min  
Symbol  
Typ  
Max  
Typ  
Max  
0.069  
A
1.75  
0.25  
A1  
A2  
b
0.10  
1.25  
0.28  
0.17  
0.004  
0.010  
0.049  
0.011  
0.007  
0.48  
0.23  
0.10  
5.00  
6.20  
4.00  
0.019  
0.009  
0.004  
0.197  
0.244  
0.157  
c
ccc  
D
4.90  
6.00  
3.90  
1.27  
4.80  
5.80  
3.80  
0.193  
0.189  
0.228  
0.150  
E
0.236  
0.154  
0.050  
E1  
e
h
0.25  
0°  
0.50  
8°  
0.010  
0°  
0.020  
8°  
k
L
0.40  
1.27  
0.016  
0.050  
L1  
1.04  
0.041  
30/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Package mechanical  
Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead  
2 x 3 mm, outline  
e
b
D
L1  
L3  
E
E2  
L
A
D2  
ddd  
A1  
UFDFPN-01  
1. Drawing is not to scale.  
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be  
allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering  
process.  
Table 26. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead  
2 x 3 mm, data  
millimeters  
Min  
inches  
Min  
Symbol  
Typ  
Max  
Typ  
Max  
A
A1  
b
0.55  
0.02  
0.25  
2.00  
1.60  
0.50  
0.00  
0.20  
1.90  
1.50  
0.60  
0.05  
0.30  
2.10  
1.70  
0.08  
3.10  
0.30  
0.022  
0.001  
0.010  
0.079  
0.063  
0.020  
0.000  
0.008  
0.075  
0.059  
0.024  
0.002  
0.012  
0.083  
0.067  
0.003  
0.122  
0.012  
D
D2  
ddd  
E
3.00  
0.20  
0.50  
0.45  
2.90  
0.10  
0.118  
0.008  
0.020  
0.018  
0.114  
0.004  
E2  
e
L
0.40  
0.50  
0.15  
0.016  
0.020  
0.006  
L1  
L3  
0.30  
0.012  
31/38  
Package mechanical  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline  
D
8
5
c
E1  
E
1
4
α
A1  
L
A
A2  
L1  
CP  
b
e
TSSOP8AM  
1. Drawing is not to scale.  
Table 27. TSSOP8 – 8 lead thin shrink small outline, package mechanical data  
millimeters  
Min.  
inches  
Min.  
Symbol  
Typ.  
Max.  
Typ.  
Max.  
A
1.200  
0.150  
1.050  
0.300  
0.200  
0.100  
3.100  
0.0472  
0.0059  
0.0413  
0.0118  
0.0079  
0.0039  
0.1220  
A1  
0.050  
0.800  
0.190  
0.090  
0.0020  
0.0315  
0.0075  
0.0035  
A2  
1.000  
0.0394  
b
c
CP  
D
3.000  
0.650  
6.400  
4.400  
0.600  
1.000  
2.900  
0.1181  
0.0256  
0.2520  
0.1732  
0.0236  
0.0394  
0.1142  
e
E
6.200  
4.300  
0.450  
6.600  
4.500  
0.750  
0.2441  
0.1693  
0.0177  
0.2598  
0.1772  
0.0295  
E1  
L
L1  
α
0°  
8
8°  
0°  
8
8°  
N (pin number)  
32/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Part numbering  
13  
Part numbering  
Table 28. Ordering information scheme  
Example:  
M93C86  
W MN 6  
T
P /S  
Device type  
M93 = MICROWIRE serial access EEPROM  
Device function  
86 = 16 Kbit (2048 x 8)  
76 = 8 Kbit (1024 x 8)  
66 = 4 Kbit (512 x 8)  
56 = 2 Kbit (256 x 8)  
46 = 1 Kbit (128 x 8)  
Operating voltage  
blank = VCC = 4.5 to 5.5 V  
W = VCC = 2.5 to 5.5 V  
R = VCC = 1.8 to 5.5 V  
Package  
BN = PDIP8  
MN = SO8 (150 mils width)  
MB = UFDFPN8 (MLP8)  
DW = TSSOP8 (169 mils width)  
DS = TSSOP8 (3 x 3 mm body size)  
Device grade  
6 = Industrial temperature range, –40 to 85 °C.  
Device tested with standard test flow  
3 = Device tested with High Reliability Certified Flow(1)  
Automotive temperature range (–40 to 125 °C)  
.
Packing  
blank = standard packing  
T = tape and reel packing  
Plating technology  
P or G = ECOPACK® (RoHS compliant)  
Process(2)  
/W or /S = F6SP36%  
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive  
environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801.  
Please ask your nearest ST sales office for a copy.  
2. Used only for Device Grade 3.  
For a list of available options (speed, package, etc.) or for further information on any aspect  
of this device, please contact your nearest ST sales office.  
The category of second-level interconnect is marked on the package and on the inner box  
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to  
soldering conditions are also marked on the inner box label.  
33/38  
Part numbering  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 29. Available M93C46-x products (package, voltage range, temperature  
grade)  
M93C46  
4.5 V to 5.5 V  
M93C46-W  
2.5 V to 5.5 V  
M93C46-R  
1.8 V to 5.5 V  
Package  
DIP8 (BN)  
SO8 (MN)  
Range 6  
Range3  
Range3  
-
-
-
Range 6  
Range3  
Range 6  
Range3  
Range 6  
Range3  
TSSOP (DW)  
-
Table 30. Available M93C56-x products (package, voltage range, temperature  
grade)  
M93C56  
4.5 V to 5.5 V  
M93C56-W  
2.5 V to 5.5 V  
M93C56-R  
1.8 V to 5.5 V  
Package  
Range 6  
Range3  
Range 6  
Range3  
SO8 (MN)  
Range 6  
TSSOP (DW)  
Range 6  
Table 31. Available M93C66-x products (package, voltage range, temperature  
grade)  
M93C66  
4.5 V to 5.5 V  
M93C66-W  
2.5 V to 5.5 V  
M93C66-R  
1.8 V to 5.5 V  
Package  
Range 6  
Range3  
Range 6  
Range3  
SO8 (MN)  
Range 6  
Range3  
TSSOP (DW)  
UFDFPN 2 x 3 mm (MB)  
Range 6  
Table 32. Available M93C76-x products (package, voltage range, temperature  
grade)  
M93C76  
4.5 V to 5.5 V  
M93C76-W  
2.5 V to 5.5 V  
Package  
Range 6  
Range3  
SO8 (MN)  
Range3  
TSSOP (DW)  
Range 6  
34/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Part numbering  
Table 33. Available M93C86-x products (package, voltage range, temperature  
grade)  
M93C86  
4.5 V to 5.5 V  
M93C86-W  
2.5 V to 5.5 V  
M93C86-R  
1.8 V to 5.5 V  
Package  
DIP8 (BN)  
SO8 (MN)  
Range 6  
Range 6  
Range3  
Range 6  
Range3  
TSSOP (DW)  
Range 6  
35/38  
Revision history  
M93C86, M93C76, M93C66, M93C56, M93C46  
14  
Revision history  
Table 34. Document revision history  
Date  
Revision  
Changes  
Document reformatted, and reworded, using the new template.  
Temperature range 1 removed. TSSOP8 (3x3mm) package added. New  
products, identified by the process letter W, added, with fc(max)  
increased to 1MHz for -R voltage range, and to 2MHz for all other  
ranges (and corresponding parameters adjusted)  
04-Feb-2003  
2.0  
Value of standby current (max) corrected in DC characteristics tables for  
-W and -R ranges  
26-Mar-2003  
04-Apr-2003  
2.1  
2.2  
VOUT and VIN separated from VIO in the Absolute Maximum Ratings  
table  
Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH  
tCLSL) for devices with Process Identification Letter W  
,
23-May-2003  
27-May-2003  
2.3  
2.4  
Standby current corrected for -R range  
Turned-die option re-instated in Ordering Information Scheme  
Table of contents, and Pb-free options added. Temperature range 7  
added. VIL(min) improved to –0.45V.  
25-Nov-2003  
3.0  
MLP package added. Absolute Maximum Ratings for VIO(min) and  
VCC(min) changed. Soldering temperature information clarified for  
RoHS compliant devices. Device grade information clarified. Process  
identification letter “G” information added  
30-Mar-2004  
4.0  
M93C06 removed. Device grade information further clarified. Process  
identification letter “S” information added. Turned-die package option  
removed. Product list summary added.  
16-Aug-2004  
5.0  
current product/new product distinction removed. ICC and ICC1 values for  
current product removed from tables 15, 16 and 17 and AC  
characteristics for current product removed from Tables 20 and 21.  
Clock rate added to Features.  
“Q = open” added to ICC Test conditions in DC Characteristics Tables 15,  
16, 17, 18 and 19.  
27-Oct-2005  
6.0  
Process added to Table 28.: Ordering information scheme. POWER ON  
DATA PROTECTION section removed, replaced by Operating features  
and Active Power and Standby Power modes. Initial delivery state  
added.  
SO8N and TSSOP8 packages updated. PDIP-specific TLEAD added to  
Table 8.: Absolute maximum ratings.  
36/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
Revision history  
Table 34. Document revision history (continued)  
Date  
Revision  
Changes  
Document reformatted. TSSOP8 3 × 3 mm (DS) package removed.  
Erase/Write Enable (EWEN) instruction replaced by Write Enable  
(WEN). Erase/Write Disable (EWDS) instruction replaced by Write  
Disable (WDS).  
Section 7: Initial delivery state modified, ACTIVE POWER AND  
STANDBY POWER MODES section removed.  
ICC1 test conditions modified in Table 15, Table 16, Table 17, Table 18  
and Table 19. Note 1 added to Table 15.  
31-Jul-2007  
7
tW parameter description modified in Table 20, Table 21, Table 22 and  
Table 23..  
SO8 narrow and UFDFPN8 package specifications updated (see  
Section 12: Package mechanical).  
Table 29, Table 30, Table 31, Table 32 and Table 33 added.  
Blank option removed under Plating technology in Table 27: TSSOP8 –  
8 lead thin shrink small outline, package mechanical data.  
Section 2: Connecting to the serial bus added. Device grade 7 removed.  
37/38  
M93C86, M93C76, M93C66, M93C56, M93C46  
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38/38  

M93C66-DW3TP/S 相关器件

型号 制造商 描述 价格 文档
M93C66-DW3TP/W STMICROELECTRONICS 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 获取价格
M93C66-DW6 STMICROELECTRONICS 16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROM 获取价格
M93C66-DW6G STMICROELECTRONICS 16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit 8-bit or 16-bit wide 获取价格
M93C66-DW6G/S STMICROELECTRONICS 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 获取价格
M93C66-DW6G/W STMICROELECTRONICS 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 获取价格
M93C66-DW6P STMICROELECTRONICS 16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit 8-bit or 16-bit wide 获取价格
M93C66-DW6P/S STMICROELECTRONICS 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 获取价格
M93C66-DW6P/W STMICROELECTRONICS 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 获取价格
M93C66-DW6T STMICROELECTRONICS 暂无描述 获取价格
M93C66-DW6TG STMICROELECTRONICS 16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit 8-bit or 16-bit wide 获取价格

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