M93C66-RMB

更新时间:2024-10-29 02:23:41
描述:16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROM

M93C66-RMB 概述

16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROM 16Kbit的, 8Kbit , 4k位, 2Kbit和的1K位( 8位或16位宽) MICROWIRE串行EEPROM的访问

M93C66-RMB 数据手册

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M93C86, M93C76, M93C66  
M93C56, M93C46  
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)  
MICROWIRE® Serial Access EEPROM  
FEATURES SUMMARY  
Industry Standard MICROWIRE Bus  
Figure 1. Packages  
Single Supply Voltage:  
4.5 to 5.5V for M93Cx6  
2.5 to 5.5V for M93Cx6-W  
1.8 to 5.5V for M93Cx6-R  
8
Dual Organization: by Word (x16) or Byte (x8)  
Programming Instructions that work on: Byte,  
Word or Entire Memory  
1
Self-timed Programming Cycle with Auto-  
Erase  
PDIP8 (BN)  
Ready/Busy Signal During Programming  
Speed:  
1MHz Clock Rate, 10ms Write Time  
(Current product, identified by process  
identification letter F or M)  
8
2MHz Clock Rate, 5ms Write Time (New  
Product, identified by process  
1
identification letter W or G or S)  
SO8 (MN)  
150 mil width  
Sequential Read Operation  
Enhanced ESD/Latch-Up Behaviour  
More than 1 Million Erase/Write Cycles  
More than 40 Year Data Retention  
Table 1. Product List  
Part  
Reference  
Part  
Number  
TSSOP8 (DW)  
169 mil width  
Reference  
Number  
M93C86  
M93C56  
M93C86  
M93C76  
M93C66  
M93C86-W  
M93C86-R  
M93C76  
M93C56  
M93C56-W  
M93C56-R  
M93C46  
TSSOP8 (DS)  
3x3mm² body size (MSOP)  
M93C76-W  
M93C76-R  
M93C66  
M93C46  
M93C46-W  
M93C46-R  
UFDFPN8 (MB)  
2x3mm² (MLP)  
M93C66-W  
M93C66-R  
August 2004  
1/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
TABLE OF CONTENTS  
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Table 3. Memory Size versus Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Table 4. Instruction Set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Figure 3. DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Table 5. Instruction Set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Table 6. Instruction Set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Table 7. Instruction Set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Erase/Write Enable and Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Figure 4. READ, WRITE, EWEN, EWDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Figure 5. ERASE, ERAL Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Figure 6. WRAL Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
READY/BUSY STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Figure 7. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Table 9. Operating Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Table 10. Operating Conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Table 11. Operating Conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Table 12. AC Measurement Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . 14  
Figure 8. AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
2/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Table 15. DC Characteristics (M93Cx6, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Table 17. DC Characteristics (M93Cx6-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Table 19. DC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Table 21. AC Characteristics (M93Cx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Table 23. AC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 9. Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 10.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 12.PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 23  
Table 24. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 23  
Figure 13.SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 24  
Table 25. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data  
24  
Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline  
25  
Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data.  
25  
Figure 15.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline  
26  
Table 27. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data  
26  
Figure 16.TSSOP8 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 27  
Table 28. TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 27  
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Table 30. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 29  
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Table 31. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
3/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
SUMMARY DESCRIPTION  
Table 3. Memory Size versus Organization  
These electrically erasable programmable memo-  
ry (EEPROM) devices are accessed through a Se-  
rial Data Input (D) and Serial Data Output (Q)  
using the MICROWIRE bus protocol.  
Number  
of 8-bit  
Bytes  
Number  
of 16-bit  
Words  
Number  
of Bits  
Device  
M93C86  
M93C76  
M93C66  
M93C56  
M93C46  
16384  
8192  
4096  
2048  
1024  
2048  
1024  
512  
1024  
512  
256  
128  
64  
Figure 2. Logic Diagram  
256  
V
CC  
128  
The M93Cx6 is accessed by a set of instructions,  
as summarized in Table 4., and in more detail in  
Table 5. to Table 7.).  
D
Q
C
S
Table 4. Instruction Set for the M93Cx6  
M93Cx6  
Instruction  
READ  
Description  
Data  
Read Data from Memory Byte or Word  
ORG  
WRITE  
EWEN  
Write Data to Memory  
Erase/Write Enable  
Erase/Write Disable  
Erase Byte or Word  
Erase All Memory  
Byte or Word  
Byte or Word  
V
SS  
AI01928  
EWDS  
ERASE  
ERAL  
Write All Memory  
with same Data  
WRAL  
A Read Data from Memory (READ) instruction  
loads the address of the first byte or word to be  
read in an internal address register. The data at  
this address is then clocked out serially. The ad-  
dress register is automatically incremented after  
the data is output and, if Chip Select Input (S) is  
held High, the M93Cx6 can output a sequential  
stream of data bytes or words. In this way, the  
memory can be read as a data stream from eight  
to 16384 bits long (in the case of the M93C86), or  
continuously (the address counter automatically  
rolls over to 00h when the highest address is  
reached).  
Table 2. Signal Names  
S
Chip Select Input  
D
Serial Data Input  
Serial Data Output  
Serial Clock  
Q
C
ORG  
Organisation Select  
Supply Voltage  
Ground  
V
CC  
V
SS  
Programming is internally self-timed (the external  
clock signal on Serial Clock (C) may be stopped or  
left running after the start of a Write cycle) and  
does not require an Erase cycle prior to the Write  
instruction. The Write instruction writes 8 or 16 bits  
at a time into one of the byte or word locations of  
the M93Cx6. After the start of the programming cy-  
cle, a Busy/Ready signal is available on Serial  
Data Output (Q) when Chip Select Input (S) is driv-  
en High.  
The memory array organization may be divided  
into either bytes (x8) or words (x16) which may be  
selected by a signal applied on Organization Se-  
lect (ORG). The bit, byte and word sizes of the  
memories are as shown in Table 3..  
4/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
MEMORY ORGANIZATION  
An internal Power-on Data Protection mechanism  
in the M93Cx6 inhibits the device when the supply  
is too low.  
The M93Cx6 memory is organized either as bytes  
(x8) or as words (x16). If Organization Select  
(ORG) is left unconnected (or connected to V  
the x16 organization is selected; when Organiza-  
tion Select (ORG) is connected to Ground (V  
)
CC  
Figure 3. DIP, SO, TSSOP and MLP  
Connections (Top View)  
)
SS  
the x8 organization is selected. When the M93Cx6  
is in stand-by mode, Organization Select (ORG)  
should be set either to V  
power consumption. Any voltage between V  
or V  
for minimum  
SS  
CC  
M93Cx6  
SS  
and V  
applied to Organization Select (ORG)  
CC  
S
C
D
Q
1
2
3
4
8
V
CC  
DU  
may increase the stand-by current.  
7
6
5
ORG  
V
SS  
AI01929B  
POWER-ON DATA PROTECTION  
To prevent data corruption and inadvertent write  
operations during power-up, a Power-On Reset  
(POR) circuit resets all internal programming cir-  
cuitry, and sets the device in the Write Disable  
mode.  
Note: 1. See PACKAGE MECHANICAL section for package di-  
mensions, and how to identify pin-1.  
2. DU = Dont Use.  
At Power-up and Power-down, the device  
must not be selected (that is, Chip Select Input  
(S) must be driven Low) until the supply  
The DU (Dont Use) pin does not contribute to the  
normal operation of the device. It is reserved for  
use by STMicroelectronics during test sequences.  
The pin may be left unconnected or may be con-  
voltage reaches the operating value V  
CC  
specified in Table 9. to Table 11..  
nected to V  
or V . Direct connection of DU to  
CC  
SS  
When V reaches its valid level, the device is  
CC  
V
is recommended for the lowest stand-by pow-  
SS  
properly reset (in the Write Disable mode) and  
is ready to decode and execute incoming  
instructions.  
er consumption.  
For the M93Cx6 devices (5V range) the POR  
threshold voltage is around 3V. For the M93Cx6-  
W (3V range) and M93Cx6-R (2V range) the POR  
threshold voltage is around 1.5V.  
5/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
INSTRUCTIONS  
The instruction set of the M93Cx6 devices con-  
tains seven instructions, as summarized in Table  
5. to Table 7.. Each instruction consists of the fol-  
lowing parts, as shown in Figure 4.:  
The address bits of the byte or word that is to  
be accessed. For the M93C46, the address is  
made up of 6 bits for the x16 organization or 7  
bits for the x8 organization (see Table 5.). For  
the M93C56 and M93C66, the address is  
made up of 8 bits for the x16 organization or 9  
bits for the x8 organization (see Table 6.). For  
the M93C76 and M93C86, the address is  
made up of 10 bits for the x16 organization or  
11 bits for the x8 organization (see Table 7.).  
Each instruction is preceded by a rising edge  
on Chip Select Input (S) with Serial Clock (C)  
being held Low.  
A start bit, which is the first 1read on Serial  
Data Input (D) during the rising edge of Serial  
Clock (C).  
Two op-code bits, read on Serial Data Input  
(D) during the rising edge of Serial Clock (C).  
(Some instructions also use the first two bits of  
the address to define the op-code).  
The M93Cx6 devices are fabricated in CMOS  
technology and are therefore able to run as slow  
as 0 Hz (static input signals) or as fast as the max-  
imum ratings specified in Table 20. to Table 23..  
Table 5. Instruction Set for the M93C46  
x8 Origination (ORG = 0)  
x16 Origination (ORG = 1)  
Required  
Instruc  
tion  
Start  
bit  
Op-  
Code  
Required  
Clock  
Description  
1
1
Data  
Data  
Clock  
Address  
Address  
Cycles  
Cycles  
Read Data from  
Memory  
READ  
1
1
10  
01  
A6-A0  
A6-A0  
Q7-Q0  
D7-D0  
A5-A0  
A5-A0  
Q15-Q0  
D15-D0  
Write Data to  
Memory  
WRITE  
18  
25  
EWEN Erase/Write Enable  
EWDS Erase/Write Disable  
ERASE Erase Byte or Word  
1
1
1
1
00  
00  
11  
00  
11X XXXX  
00X XXXX  
A6-A0  
10  
10  
10  
10  
11 XXXX  
00 XXXX  
A5-A0  
9
9
9
9
ERAL  
Erase All Memory  
10X XXXX  
10 XXXX  
Write All Memory  
with same Data  
WRAL  
1
00  
01X XXXX D7-D0  
18  
01 XXXX  
D15-D0  
25  
Note: 1. X = Dont Care bit.  
6/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 6. Instruction Set for the M93C56 and M93C66  
x8 Origination (ORG = 0)  
x16 Origination (ORG = 1)  
Required  
Instruc  
tion  
Start  
bit  
Op-  
Code  
Required  
Clock  
Description  
1,2  
1,3  
Data  
Data  
Clock  
Address  
Address  
Cycles  
Cycles  
Read Data from  
Memory  
READ  
1
1
1
10  
01  
00  
A8-A0  
A8-A0  
Q7-Q0  
D7-D0  
A7-A0  
A7-A0  
Q15-Q0  
D15-D0  
Write Data to  
Memory  
WRITE  
20  
12  
27  
11  
1 1XXX  
XXXX  
11XX  
XXXX  
EWEN Erase/Write Enable  
0 0XXX  
XXXX  
00XX  
XXXX  
EWDS Erase/Write Disable  
ERASE Erase Byte or Word  
1
1
1
00  
11  
00  
12  
12  
12  
11  
11  
11  
A8-A0  
A7-A0  
1 0XXX  
XXXX  
10XX  
XXXX  
ERAL  
Erase All Memory  
Write All Memory  
with same Data  
0 1XXX  
XXXX  
01XX  
XXXX  
WRAL  
1
00  
D7-D0  
20  
D15-D0  
27  
Note: 1. X = Dont Care bit.  
2. Address bit A8 is not decoded by the M93C56.  
3. Address bit A7 is not decoded by the M93C56.  
Table 7. Instruction Set for the M93C76 and M93C86  
x8 Origination (ORG = 0)  
x16 Origination (ORG = 1)  
Required  
Instruc  
tion  
Start  
bit  
Op-  
Code  
Required  
Clock  
Description  
1,2  
1,3  
Data  
Data  
Clock  
Address  
Address  
Cycles  
Cycles  
Read Data from  
Memory  
READ  
1
1
1
10  
01  
00  
A10-A0  
A10-A0  
Q7-Q0  
D7-D0  
A9-A0  
A9-A0  
Q15-Q0  
D15-D0  
Write Data to  
Memory  
WRITE  
22  
14  
29  
13  
11X XXXX  
XXXX  
11 XXXX  
XXXX  
EWEN Erase/Write Enable  
00X XXXX  
XXXX  
00 XXXX  
XXXX  
EWDS Erase/Write Disable  
ERASE Erase Byte or Word  
1
1
1
00  
11  
00  
14  
14  
14  
13  
13  
13  
A10-A0  
A9-A0  
10X XXXX  
XXXX  
10 XXXX  
XXXX  
ERAL  
Erase All Memory  
Write All Memory  
with same Data  
01X XXXX  
XXXX  
01 XXXX  
XXXX  
WRAL  
1
00  
D7-D0  
22  
D15-D0  
29  
Note: 1. X = Dont Care bit.  
2. Address bit A10 is not decoded by the M93C76.  
3. Address bit A9 is not decoded by the M93C76.  
7/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Read  
Erase/Write Enable and Disable  
The Read Data from Memory (READ) instruction  
outputs data on Serial Data Output (Q). When the  
instruction is received, the op-code and address  
are decoded, and the data from the memory is  
transferred to an output shift register. A dummy 0  
bit is output first, followed by the 8-bit byte or 16-  
bit word, with the most significant bit first. Output  
data changes are triggered by the rising edge of  
Serial Clock (C). The M93Cx6 automatically incre-  
ments the internal address register and clocks out  
the next byte (or word) as long as the Chip Select  
Input (S) is held High. In this case, the dummy 0 bit  
is not output between bytes (or words) and a con-  
tinuous stream of data can be read.  
The Erase/Write Enable (EWEN) instruction en-  
ables the future execution of erase or write instruc-  
tions, and the Erase/Write Disable (EWDS)  
instruction disables it. When power is first applied,  
the M93Cx6 initializes itself so that erase and write  
instructions are disabled. After an Erase/Write En-  
able (EWEN) instruction has been executed, eras-  
ing and writing remains enabled until an Erase/  
Write Disable (EWDS) instruction is executed, or  
until V  
falls below the power-on reset threshold  
CC  
voltage. To protect the memory contents from ac-  
cidental corruption, it is advisable to issue the  
Erase/Write Disable (EWDS) instruction after ev-  
ery write cycle. The Read Data from Memory  
(READ) instruction is not affected by the Erase/  
Write Enable (EWEN) or Erase/Write Disable  
(EWDS) instructions.  
Figure 4. READ, WRITE, EWEN, EWDS Sequences  
READ  
S
D
Q
1 1 0 An  
A0  
Qn  
Q0  
ADDR  
DATA OUT  
OP  
CODE  
WRITE  
S
D
Q
CHECK  
STATUS  
1 0 1 An  
A0 Dn  
D0  
ADDR  
DATA IN  
BUSY  
READY  
OP  
CODE  
ERASE  
WRITE  
ENABLE  
S
D
ERASE  
WRITE  
DISABLE  
S
D
1 0 0 1 1 Xn X0  
1 0 0 0 0 Xn X0  
OP  
OP  
CODE  
CODE  
AI00878C  
Note: For the meanings of An, Xn, Qn and Dn, see Table 5., Table 6. and Table 7..  
8/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Erase  
After the last data bit has been sampled, the Chip  
Select Input (S) must be taken Low before the next  
rising edge of Serial Clock (C). If Chip Select Input  
(S) is brought Low before or after this specific time  
frame, the self-timed programming cycle will not  
be started, and the addressed location will not be  
programmed. The completion of the cycle can be  
detected by monitoring the Ready/Busy line, as  
described later in this document.  
The Erase Byte or Word (ERASE) instruction sets  
the bits of the addressed memory byte (or word) to  
1. Once the address has been correctly decoded,  
the falling edge of the Chip Select Input (S) starts  
the self-timed Erase cycle. The completion of the  
cycle can be detected by monitoring the Ready/  
Busy line, as described in the READY/BUSY STA-  
TUS section.  
Once the Write cycle has been started, it is inter-  
nally self-timed (the external clock signal on Serial  
Clock (C) may be stopped or left running after the  
start of a Write cycle). The cycle is automatically  
preceded by an Erase cycle, so it is unnecessary  
to execute an explicit erase instruction before a  
Write Data to Memory (WRITE) instruction.  
Write  
For the Write Data to Memory (WRITE) instruction,  
8 or 16 data bits follow the op-code and address  
bits. These form the byte or word that is to be writ-  
ten. As with the other bits, Serial Data Input (D) is  
sampled on the rising edge of Serial Clock (C).  
Figure 5. ERASE, ERAL Sequences  
ERASE  
S
D
Q
CHECK  
STATUS  
1 1 1 An  
A0  
ADDR  
BUSY  
READY  
OP  
CODE  
ERASE  
ALL  
S
D
Q
CHECK  
STATUS  
1 0 0 1 0 Xn X0  
ADDR  
OP  
BUSY  
READY  
CODE  
AI00879B  
Note: For the meanings of An and Xn, please see Table 5., Table 6. and Table 7..  
9/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Erase All  
Write All  
The Erase All Memory (ERAL) instruction erases  
the whole memory (all memory bits are set to 1).  
The format of the instruction requires that a dum-  
my address be provided. The Erase cycle is con-  
ducted in the same way as the Erase instruction  
(ERASE). The completion of the cycle can be de-  
tected by monitoring the Ready/Busy line, as de-  
scribed in the READY/BUSY STATUS section.  
As with the Erase All Memory (ERAL) instruction,  
the format of the Write All Memory with same Data  
(WRAL) instruction requires that a dummy ad-  
dress be provided. As with the Write Data to Mem-  
ory (WRITE) instruction, the format of the Write All  
Memory with same Data (WRAL) instruction re-  
quires that an 8-bit data byte, or 16-bit data word,  
be provided. This value is written to all the ad-  
dresses of the memory device. The completion of  
the cycle can be detected by monitoring the  
Ready/Busy line, as described next.  
Figure 6. WRAL Sequence  
WRITE  
ALL  
S
D
Q
CHECK  
STATUS  
1 0 0 0 1 Xn X0 Dn  
D0  
ADDR  
OP  
DATA IN  
BUSY  
READY  
CODE  
AI00880C  
Note: For the meanings of Xn and Dn, please see Table 5., Table 6. and Table 7..  
10/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
CLOCK PULSE COUNTER  
READY/BUSY STATUS  
While the Write or Erase cycle is underway, for a  
WRITE, ERASE, WRAL or ERAL instruction, the  
Busy signal (Q=0) is returned whenever Chip Se-  
lect Input (S) is driven High. (Please note, though,  
In a noisy environment, the number of pulses re-  
ceived on Serial Clock (C) may be greater than the  
number delivered by the master (the microcontrol-  
ler). This can lead to a misalignment of the instruc-  
tion of one or more bits (as shown in Figure 7.) and  
may lead to the writing of erroneous data at an er-  
roneous address.  
To combat this problem, the M93Cx6 has an on-  
chip counter that counts the clock pulses from the  
start bit until the falling edge of the Chip Select In-  
put (S). If the number of clock pulses received is  
not the number expected, the WRITE, ERASE,  
ERAL or WRAL instruction is aborted, and the  
contents of the memory are not modified.  
that there is an initial delay, of t  
, before this  
SLSH  
status information becomes available). In this  
state, the M93Cx6 ignores any data on the bus.  
When the Write cycle is completed, and Chip Se-  
lect Input (S) is driven High, the Ready signal  
(Q=1) indicates that the M93Cx6 is ready to re-  
ceive the next instruction. Serial Data Output (Q)  
remains set to 1 until the Chip Select Input (S) is  
brought Low or until a new start bit is decoded.  
The number of clock cycles expected for each in-  
struction, and for each member of the M93Cx6  
family, are summarized in Table 5. to Table 7.. For  
example, a Write Data to Memory (WRITE) in-  
struction on the M93C56 (or M93C66) expects 20  
clock cycles (for the x8 organization) from the start  
bit to the falling edge of Chip Select Input (S). That  
is:  
COMMON I/O OPERATION  
Serial Data Output (Q) and Serial Data Input (D)  
can be connected together, through a current lim-  
iting resistor, to form a common, single-wire data  
bus. Some precautions must be taken when oper-  
ating the memory in this way, mostly to prevent a  
short circuit current from flowing when the last ad-  
dress bit (A0) clashes with the first data bit on Se-  
rial Data Output (Q). Please see the application  
note AN394 for details.  
1 Start bit  
+ 2 Op-code bits  
+ 9 Address bits  
+ 8 Data bits  
Figure 7. Write Sequence with One Clock Glitch  
S
C
D
An  
An-1  
Glitch  
An-2  
START  
"0"  
"1"  
D0  
ADDRESS AND DATA  
ARE SHIFTED BY ONE BIT  
WRITE  
AI01395  
11/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
MAXIMUM RATING  
Stressing the device above the rating listed in the  
Absolute Maximum Ratings" table may cause per-  
manent damage to the device. These are stress  
ratings only and operation of the device at these or  
any other conditions above those indicated in the  
Operating sections of this specification is not im-  
plied. Exposure to Absolute Maximum Rating con-  
ditions for extended periods may affect device  
reliability. Refer also to the STMicroelectronics  
SURE Program and other relevant quality docu-  
ments.  
Table 8. Absolute Maximum Ratings  
Symbol  
Parameter  
Min.  
Max.  
Unit  
°C  
°C  
V
T
Storage Temperature  
65  
150  
STG  
1
TLEAD  
VOUT  
VIN  
Lead Temperature during Soldering  
See note  
Output range (Q = V or Hi-Z)  
0.50  
0.50  
0.50  
4000  
VCC+0.5  
VCC+1  
6.5  
OH  
Input range  
V
V
CC  
Supply Voltage  
V
2
VESD  
4000  
V
Electrostatic Discharge Voltage (Human Body model)  
®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and  
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU  
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )  
12/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
DC AND AC PARAMETERS  
This section summarizes the operating and mea-  
surement conditions, and the DC and AC charac-  
teristics of the device. The parameters in the DC  
and AC Characteristic tables that follow are de-  
rived from tests performed under the Measure-  
ment Conditions summarized in the relevant  
tables. Designers should check that the operating  
conditions in their circuit match the measurement  
conditions when relying on the quoted parame-  
ters.  
Table 9. Operating Conditions (M93Cx6)  
Symbol  
Parameter  
Min.  
4.5  
Max.  
5.5  
Unit  
V
V
CC  
Supply Voltage  
Ambient Operating Temperature (Device Grade 6)  
Ambient Operating Temperature (Device Grade 7)  
Ambient Operating Temperature (Device Grade 3)  
40  
40  
40  
85  
°C  
°C  
°C  
TA  
105  
125  
Table 10. Operating Conditions (M93Cx6-W)  
Symbol  
Parameter  
Min.  
2.5  
Max.  
5.5  
Unit  
V
V
CC  
Supply Voltage  
Ambient Operating Temperature (Device Grade 6)  
Ambient Operating Temperature (Device Grade 7)  
Ambient Operating Temperature (Device Grade 3)  
40  
40  
40  
85  
°C  
°C  
°C  
TA  
105  
125  
Table 11. Operating Conditions (M93Cx6-R)  
Symbol  
Parameter  
Min.  
1.8  
Max.  
5.5  
Unit  
V
V
CC  
Supply Voltage  
Ambient Operating Temperature (Device Grade 6)  
TA  
40  
85  
°C  
13/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 12. AC Measurement Conditions (M93Cx6)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
pF  
ns  
V
C
Load Capacitance  
100  
L
Input Rise and Fall Times  
50  
Input Pulse Voltages  
0.4 V to 2.4 V  
1.0 V and 2.0 V  
0.8 V and 2.0 V  
Input Timing Reference Voltages  
Output Timing Reference Voltages  
V
V
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.  
Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
pF  
ns  
V
C
Load Capacitance  
100  
L
Input Rise and Fall Times  
50  
0.2V to 0.8V  
Input Pulse Voltages  
CC  
CC  
CC  
CC  
0.3V to 0.7V  
Input Timing Reference Voltages  
Output Timing Reference Voltages  
V
CC  
0.3V to 0.7V  
V
CC  
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.  
Figure 8. AC Testing Input Output Waveforms  
M93CXX  
2.4V  
2V  
2.0V  
0.8V  
1V  
0.4V  
INPUT  
OUTPUT  
M93CXX-W & M93CXX-R  
0.8V  
0.2V  
CC  
0.7V  
CC  
0.3V  
CC  
CC  
AI02553  
Table 14. Capacitance  
Symbol  
Parameter  
Test Condition  
= 0V  
Min  
Max  
Unit  
COUT  
Output  
Capacitance  
5
pF  
V
OUT  
CIN  
Input  
Capacitance  
5
pF  
V
= 0V  
IN  
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 1MHz.  
A
14/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 15. DC Characteristics (M93Cx6, Device Grade 6)  
Symbol  
ILI  
Parameter  
Test Condition  
Min.  
Max.  
±2.5  
±2.5  
Unit  
µA  
0V V V  
Input Leakage Current  
Output Leakage Current  
IN  
CC  
0V V  
V , Q in Hi-Z  
CC  
ILO  
µA  
OUT  
V
= 5V, S = V , f = 1 MHz, Current  
CC  
IH  
1.5  
2
mA  
mA  
µA  
1
Product  
ICC  
Supply Current  
V
= 5V, S = V , f = 2 MHz, New  
CC  
IH  
2
Product  
V
= 5V, S = V , C = V  
,
SS  
CC  
SS  
50  
1
ORG = V or V , Current Product  
SS  
CC  
ICC1  
Supply Current (Stand-by)  
V
= 5V, S = V , C = V  
,
SS  
CC  
SS  
15  
µA  
2
ORG = V or V , New Product  
SS  
CC  
V
= 5V ± 10%  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
0.45  
0.8  
V
V
V
V
CC  
V
= 5V ± 10%  
V
+ 1  
2
CC  
CC  
V
= 5V, I = 2.1mA  
OL  
VOL  
VOH  
0.4  
CC  
V
= 5V, I  
= 400µA  
2.4  
CC  
OH  
Note: 1. Current product: identified by Process Identification letter F or M.  
2. New product: identified by Process Identification letter W or G or S.  
Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3)  
Symbol  
ILI  
Parameter  
Test Condition  
Min.  
Max.  
±2.5  
±2.5  
Unit  
µA  
0V V V  
Input Leakage Current  
Output Leakage Current  
IN  
CC  
0V V  
V , Q in Hi-Z  
CC  
ILO  
µA  
OUT  
V
= 5V, S = V , f = 1 MHz, Current  
CC  
IH  
1.5  
2
mA  
mA  
µA  
1
Product  
ICC  
Supply Current  
V
= 5V, S = V , f = 2 MHz, New  
CC  
IH  
2
Product  
V
= 5V, S = V , C = V  
,
SS  
CC  
SS  
50  
1
ORG = V or V , Current Product  
SS  
CC  
ICC1  
Supply Current (Stand-by)  
V
= 5V, S = V , C = V  
,
SS  
CC  
SS  
15  
µA  
2
ORG = V or V , New Product  
SS  
CC  
V
= 5V ± 10%  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
0.45  
0.8  
V
V
V
V
CC  
V
= 5V ± 10%  
V
+ 1  
2
CC  
CC  
V
= 5V, I = 2.1mA  
OL  
VOL  
VOH  
0.4  
CC  
V
= 5V, I  
= 400µA  
2.4  
CC  
OH  
Note: 1. Current product: identified by Process Identification letter F or M.  
2. New product: identified by Process Identification letter W or G or S.  
15/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 17. DC Characteristics (M93Cx6-W, Device Grade 6)  
Symbol  
ILI  
Parameter  
Test Condition  
Min.  
Max.  
±2.5  
±2.5  
Unit  
µA  
0V V V  
Input Leakage Current  
Output Leakage Current  
IN  
CC  
0V V  
V , Q in Hi-Z  
CC  
ILO  
µA  
OUT  
V
= 5V, S = V , f = 1 MHz, Current  
CC  
IH  
1.5  
1
mA  
mA  
mA  
mA  
µA  
1
Product  
V
= 2.5V, S = V , f = 1 MHz, Current  
CC  
IH  
1
Product  
Supply Current (CMOS  
Inputs)  
ICC  
V
= 5V, S = V , f = 2 MHz, New  
CC  
IH  
2
2
Product  
V
= 2.5V, S = V , f = 2 MHz, New  
CC  
IH  
1
2
Product  
V
CC  
= 2.5V, S = V , C = V  
,
SS  
SS  
10  
1
ORG = V or V , Current Product  
SS  
CC  
ICC1  
Supply Current (Stand-by)  
V
CC  
= 2.5V, S = V , C = V  
,
SS  
SS  
5
µA  
2
ORG = V or V , New Product  
SS  
CC  
0.2 V  
VIL  
VIH  
Input Low Voltage (D, C, S)  
Input High Voltage (D, C, S)  
0.45  
V
V
V
V
V
V
CC  
0.7 V  
V
CC  
+ 1  
CC  
V
= 5V, I = 2.1mA  
OL  
0.4  
0.2  
CC  
VOL  
Output Low Voltage (Q)  
Output High Voltage (Q)  
V
CC  
= 2.5V, I = 100µA  
OL  
V
= 5V, I  
= 400µA  
= 100µA  
2.4  
0.2  
CC  
OH  
VOH  
V
= 2.5V, I  
V
CC  
OH  
CC  
Note: 1. Current product: identified by Process Identification letter F or M.  
2. New product: identified by Process Identification letter W or G or S.  
16/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3)  
1
1
Symbol  
ILI  
Parameter  
Test Condition  
Unit  
µA  
Min.  
Max.  
±2.5  
±2.5  
2
0V V V  
Input Leakage Current  
Output Leakage Current  
IN  
CC  
0V V  
V , Q in Hi-Z  
CC  
ILO  
µA  
OUT  
V
= 5V, S = V , f = 2 MHz  
IH  
mA  
mA  
CC  
Supply Current (CMOS  
Inputs)  
ICC  
V
= 2.5V, S = V , f = 2 MHz  
IH  
1
CC  
V
CC  
= 2.5V, S = V , C = V  
,
SS  
SS  
ICC1  
Supply Current (Stand-by)  
5
µA  
ORG = V or V  
SS  
CC  
0.2 V  
VIL  
VIH  
Input Low Voltage (D, C, S)  
Input High Voltage (D, C, S)  
0.45  
V
V
V
V
V
V
CC  
0.7 V  
V
CC  
+ 1  
CC  
V
= 5V, I = 2.1mA  
OL  
0.4  
0.2  
CC  
VOL  
Output Low Voltage (Q)  
Output High Voltage (Q)  
V
CC  
= 2.5V, I = 100µA  
OL  
V
= 5V, I  
= 400µA  
2.4  
0.2  
CC  
OH  
VOH  
V
= 2.5V, I  
= 100µA  
V
CC  
OH  
CC  
Note: 1. New product: identified by Process Identification letter W or G or S.  
Table 19. DC Characteristics (M93Cx6-R)  
1
1
Symbol  
ILI  
Parameter  
Test Condition  
Unit  
µA  
Min.  
Max.  
±2.5  
±2.5  
2
0V V V  
Input Leakage Current  
Output Leakage Current  
IN  
CC  
0V V  
V , Q in Hi-Z  
CC  
ILO  
µA  
OUT  
V
= 5V, S = V , f = 2 MHz  
IH  
mA  
mA  
CC  
Supply Current (CMOS  
Inputs)  
ICC  
V
= 1.8V, S = V , f = 1 MHz  
IH  
1
CC  
V
CC  
= 1.8V, S = V , C = V  
,
SS  
SS  
ICC1  
Supply Current (Stand-by)  
2
µA  
ORG = V or V  
SS  
CC  
0.2 V  
VIL  
VIH  
Input Low Voltage (D, C, S)  
Input High Voltage (D, C, S)  
Output Low Voltage (Q)  
Output High Voltage (Q)  
0.45  
V
V
V
V
CC  
0.8 V  
V
CC  
+ 1  
CC  
V
V
= 1.8V, I = 100µA  
OL  
VOL  
VOH  
0.2  
CC  
= 1.8V, I  
= 100µA  
V
0.2  
CC  
CC  
OH  
Note: 1. This product is under development. For more infomation, please contact your nearest ST sales office.  
17/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3)  
Test conditions specified in Table 12. and Table 9.  
3
3
4
4
Symbol  
Alt.  
Parameter  
Clock Frequency  
Unit  
MHz  
ns  
Min.  
Max.  
Min.  
Max.  
f
C
f
SK  
D.C.  
250  
1
D.C.  
50  
2
t
Chip Select Low to Clock High  
SLCH  
Chip Select Set-up Time  
M93C46, M93C56, M93C66  
50  
50  
50  
ns  
ns  
t
t
CSS  
SHCH  
Chip Select Set-up time  
M93C76, M93C86  
100  
2
t
Chip Select Low to Chip Select High  
Clock High Time  
250  
250  
200  
200  
ns  
ns  
t
CS  
SLSH  
CHCL  
CLCH  
1
1
t
t
t
SKH  
t
Clock Low Time  
250  
100  
100  
100  
0
200  
50  
50  
50  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
SKL  
t
t
Data In Set-up Time  
DVCH  
DIS  
DIH  
SKS  
t
t
Data In Hold Time  
CHDX  
t
t
t
Clock Set-up Time (relative to S)  
Chip Select Hold Time  
Chip Select to Ready/Busy Status  
Chip Select Low to Output Hi-Z  
Delay to Output Low  
CLSH  
t
CLSL  
CSH  
t
t
400  
200  
400  
400  
10  
200  
100  
200  
200  
5
SHQV  
SV  
t
t
SLQZ  
CHQL  
DF  
t
t
t
PD0  
t
Delay to Output Valid  
CHQV  
PD1  
t
t
Erase/Write Cycle time  
W
WP  
Note: 1. t  
+ t  
CLCH  
1 / f .  
C
CHCL  
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.  
3. Current product: identified by Process Identification letter F or M.  
4. New product: identified by Process Identification letter W or G or S.  
18/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 21. AC Characteristics (M93Cx6-W, Device Grade 6)  
Test conditions specified in Table 13. and Table 10.  
3
3
4
4
Symbol  
Alt.  
Parameter  
Clock Frequency  
Unit  
MHz  
ns  
Min.  
Max.  
Min.  
Max.  
f
C
f
SK  
D.C.  
250  
1
D.C.  
50  
2
t
Chip Select Low to Clock High  
Chip Select Set-up Time  
SLCH  
t
t
CSS  
100  
50  
ns  
SHCH  
2
t
Chip Select Low to Chip Select High  
1000  
200  
ns  
t
CS  
SLSH  
1
t
Clock High Time  
350  
200  
ns  
t
SKH  
CHCL  
1
t
Clock Low Time  
250  
100  
100  
100  
0
200  
50  
50  
50  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
t
SKL  
CLCH  
t
t
Data In Set-up Time  
DVCH  
DIS  
DIH  
SKS  
t
t
Data In Hold Time  
CHDX  
t
t
t
Clock Set-up Time (relative to S)  
Chip Select Hold Time  
Chip Select to Ready/Busy Status  
Chip Select Low to Output Hi-Z  
Delay to Output Low  
CLSH  
t
CLSL  
CSH  
t
t
400  
200  
100  
200  
200  
5
SHQV  
SV  
t
t
200  
400  
400  
10  
SLQZ  
DF  
t
t
CHQL  
PD0  
PD1  
t
t
Delay to Output Valid  
CHQV  
t
t
Erase/Write Cycle time  
W
WP  
Note: 1. t  
+ t  
CLCH  
1 / f .  
C
CHCL  
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.  
3. Current product: identified by Process Identification letter F or M.  
4. New product: identified by Process Identification letter W or G or S.  
19/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3)  
Test conditions specified in Table 13. and Table 10.  
3
3
Symbol  
Alt.  
Parameter  
Unit  
MHz  
ns  
Min.  
Max.  
f
f
SK  
Clock Frequency  
D.C.  
50  
2
C
t
Chip Select Low to Clock High  
Chip Select Set-up Time  
SLCH  
t
t
CSS  
50  
ns  
SHCH  
2
t
Chip Select Low to Chip Select High  
200  
ns  
t
CS  
SLSH  
1
t
Clock High Time  
200  
ns  
t
SKH  
CHCL  
1
t
Clock Low Time  
200  
50  
50  
50  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
t
SKL  
CLCH  
t
t
Data In Set-up Time  
DVCH  
DIS  
t
t
Data In Hold Time  
CHDX  
DIH  
t
t
t
Clock Set-up Time (relative to S)  
Chip Select Hold Time  
Chip Select to Ready/Busy Status  
Chip Select Low to Output Hi-Z  
Delay to Output Low  
CLSH  
SKS  
t
CLSL  
CSH  
t
t
200  
100  
200  
200  
5
SHQV  
SV  
t
t
SLQZ  
DF  
t
t
CHQL  
PD0  
PD1  
t
t
Delay to Output Valid  
CHQV  
t
W
t
Erase/Write Cycle time  
WP  
Note: 1. t  
+ t  
CLCH  
1 / f .  
CHCL  
C
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.  
3. New product: identified by Process Identification letter W or G or S.  
20/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Table 23. AC Characteristics (M93Cx6-R)  
Test conditions specified in Table 13. and Table 11.  
3
3
Symbol  
Alt.  
Parameter  
Unit  
MHz  
ns  
Min.  
D.C.  
250  
50  
Max.  
f
f
SK  
Clock Frequency  
1
C
t
Chip Select Low to Clock High  
Chip Select Set-up Time  
SLCH  
t
t
CSS  
ns  
SHCH  
2
t
Chip Select Low to Chip Select High  
250  
250  
ns  
t
CS  
SLSH  
1
t
Clock High Time  
ns  
t
SKH  
CHCL  
1
t
Clock Low Time  
250  
100  
100  
100  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
t
SKL  
CLCH  
t
t
Data In Set-up Time  
DVCH  
DIS  
t
t
Data In Hold Time  
CHDX  
DIH  
t
t
t
Clock Set-up Time (relative to S)  
Chip Select Hold Time  
Chip Select to Ready/Busy Status  
Chip Select Low to Output Hi-Z  
Delay to Output Low  
CLSH  
SKS  
t
CLSL  
CSH  
t
t
400  
200  
400  
400  
10  
SHQV  
SV  
t
t
SLQZ  
DF  
t
t
CHQL  
PD0  
PD1  
t
t
Delay to Output Valid  
CHQV  
t
W
t
Erase/Write Cycle time  
WP  
Note: 1. t  
+ t  
CLCH  
1 / f .  
CHCL  
C
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.  
3. This product is under development. For more infomation, please contact your nearest ST sales office.  
21/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 9. Synchronous Timing (Start and Op-Code Input)  
tCLSH  
tCHCL  
C
tSHCH  
tCLCH  
S
tDVCH  
tCHDX  
D
START  
OP CODE  
OP CODE  
START  
OP CODE INPUT  
AI01428  
Figure 10. Synchronous Timing (Read or Write)  
C
tCLSL  
S
tDVCH  
tCHDX  
tCHQV  
tSLSH  
A0  
D
Q
An  
tSLQZ  
tCHQL  
Hi-Z  
Q15/Q7  
Q0  
ADDRESS INPUT  
DATA OUTPUT  
AI00820C  
Figure 11. Synchronous Timing (Read or Write)  
tSLCH  
C
S
tCLSL  
tDVCH  
tCHDX  
A0/D0  
tSLSH  
D
Q
An  
tSHQV  
BUSY  
tW  
WRITE CYCLE  
tSLQZ  
Hi-Z  
READY  
ADDRESS/DATA INPUT  
AI01429  
22/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
PACKAGE MECHANICAL  
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline  
E
b2  
A2  
A1  
A
L
c
b
e
eA  
eB  
D
8
1
E1  
PDIP-B  
Note: Drawing is not to scale.  
Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data  
mm  
inches  
Min.  
Symb.  
Typ.  
Min.  
Max.  
Typ.  
Max.  
A
A1  
A2  
b
5.33  
0.210  
0.38  
2.92  
0.36  
1.14  
0.20  
9.02  
7.62  
6.10  
0.015  
0.115  
0.014  
0.045  
0.008  
0.355  
0.300  
0.240  
3.30  
0.46  
1.52  
0.25  
9.27  
7.87  
6.35  
2.54  
7.62  
4.95  
0.56  
1.78  
0.36  
10.16  
8.26  
7.11  
0.130  
0.018  
0.060  
0.010  
0.365  
0.310  
0.250  
0.100  
0.300  
0.195  
0.022  
0.070  
0.014  
0.400  
0.325  
0.280  
b2  
c
D
E
E1  
e
eA  
eB  
L
10.92  
3.81  
0.430  
0.150  
3.30  
2.92  
0.130  
0.115  
23/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 13. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline  
h x 45˚  
A
C
B
CP  
e
D
N
E
H
1
A1  
α
L
SO-a  
Note: Drawing is not to scale.  
Table 25. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data  
mm  
Min.  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
inches  
Min.  
0.053  
0.004  
0.013  
0.007  
0.189  
0.150  
Symb.  
Typ.  
Max.  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
Typ.  
Max.  
0.069  
0.010  
0.020  
0.010  
0.197  
0.157  
A
A1  
B
C
D
E
e
1.27  
0.050  
H
h
5.80  
0.25  
0.40  
0°  
6.20  
0.50  
0.90  
8°  
0.228  
0.010  
0.016  
0°  
0.244  
0.020  
0.035  
8°  
L
α
N
CP  
8
8
0.10  
0.004  
24/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline  
e
b
D
L1  
L3  
E
E2  
L
A
D2  
ddd  
A1  
UFDFPN-01  
Note: 1. Drawing is not to scale.  
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V . It must not be allowed to be connected to  
SS  
any other voltage or signal line on the PCB, for example during the soldering process.  
Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data  
mm  
Min.  
0.50  
0.00  
0.20  
inches  
Min.  
Symbol  
Typ.  
Max.  
0.60  
0.05  
0.30  
Typ.  
Max.  
0.024  
0.002  
0.012  
A
A1  
b
0.55  
0.022  
0.020  
0.000  
0.008  
0.25  
2.00  
0.010  
0.079  
D
D2  
ddd  
E
1.55  
1.65  
0.05  
0.061  
0.065  
0.002  
3.00  
0.118  
E2  
e
0.15  
0.25  
0.006  
0.010  
0.50  
0.45  
0.020  
0.018  
L
0.40  
0.50  
0.15  
0.016  
0.020  
0.006  
L1  
L3  
N
0.30  
0.012  
8
8
25/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline  
D
8
1
5
4
c
E1  
E
α
A1  
L
A
A2  
L1  
CP  
b
e
TSSOP8BM  
Note: Drawing is not to scale.  
Table 27. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data  
mm  
inches  
Min.  
Symbol  
Typ.  
Min.  
Max.  
1.100  
0.150  
0.950  
0.400  
0.230  
3.100  
5.150  
3.100  
Typ.  
Max.  
0.0433  
0.0059  
0.0374  
0.0157  
0.0091  
0.1220  
0.2028  
0.1220  
A
A1  
A2  
b
0.050  
0.750  
0.250  
0.130  
2.900  
4.650  
2.900  
0.0020  
0.0295  
0.0098  
0.0051  
0.1142  
0.1831  
0.1142  
0.850  
0.0335  
c
D
3.000  
4.900  
3.000  
0.650  
0.1181  
0.1929  
0.1181  
0.0256  
E
E1  
e
CP  
L
0.100  
0.700  
0.0039  
0.0276  
0.550  
0.950  
0.400  
0.0217  
0.0374  
0.0157  
L1  
α
0°  
6°  
0°  
6°  
26/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Figure 16. TSSOP8 8 lead Thin Shrink Small Outline, Package Outline  
D
8
5
c
E1  
E
1
4
α
A1  
L
A
A2  
L1  
CP  
b
e
TSSOP8AM  
Note: Drawing is not to scale.  
Table 28. TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data  
mm  
inches  
Min.  
Symbol  
Typ.  
Min.  
Max.  
1.200  
0.150  
1.050  
0.300  
0.200  
0.100  
3.100  
Typ.  
Max.  
0.0472  
0.0059  
0.0413  
0.0118  
0.0079  
0.0039  
0.1220  
A
A1  
A2  
b
0.050  
0.800  
0.190  
0.090  
0.0020  
0.0315  
0.0075  
0.0035  
1.000  
0.0394  
c
CP  
D
3.000  
0.650  
6.400  
4.400  
0.600  
1.000  
2.900  
0.1181  
0.0256  
0.2520  
0.1732  
0.0236  
0.0394  
0.1142  
e
E
6.200  
4.300  
0.450  
6.600  
4.500  
0.750  
0.2441  
0.1693  
0.0177  
0.2598  
0.1772  
0.0295  
E1  
L
L1  
α
0°  
8°  
0°  
8°  
27/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
PART NUMBERING  
Table 29. Ordering Information Scheme  
Example:  
M93C86  
W
MN  
6
T
P
Device Type  
M93 = MICROWIRE serial access EEPROM  
Device Function  
86 = 16 Kbit (2048 x 8)  
76 = 8 Kbit (1024 x 8)  
66 = 4 Kbit (512 x 8)  
56 = 2 Kbit (256 x 8)  
46 = 1 Kbit (128 x 8)  
Operating Voltage  
blank = V = 4.5 to 5.5V  
CC  
W = V = 2.5 to 5.5V  
CC  
R = V = 1.8 to 5.5V  
CC  
Package  
BN = PDIP8  
MN = SO8 (150 mil width)  
MB = UDFDFPN8 (MLP8)  
DW = TSSOP8 (169 mil width)  
2
DS = TSSOP8 (3x3mm body size)  
Device Grade  
6 = Industrial temperature range, 40 to 85 °C.  
Device tested with standard test flow  
1
7 = Device tested with High Reliability Certified Flow .  
Automotive temperature range (40 to 105 °C)  
1
3 = Device tested with High Reliability Certified Flow .  
Automotive temperature range (40 to 125 °C)  
Packing  
blank = Standard Packing  
T = Tape and Reel Packing  
Plating Technology  
blank = Standard SnPb plating  
P = Lead-Free and RoHS compliant  
G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free  
2
3
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-  
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.  
2. Available only on new products: identified by the Process Identification letter W or G or S.  
28/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Devices are shipped from the factory with the  
memory content set at all 1s (FFFFh for x16, FFh  
for x8).  
For a list of available options (speed, package,  
etc.) or for further information on any aspect of this  
device, please contact your nearest ST Sales Of-  
fice.  
Table 30. How to Identify Current and New Products by the Process Identification Letter  
1
1
Markings on Current Products  
Markings on New Products  
M93C46W6  
M93C46W6  
AYWWF (or AYWWM)  
AYWWW (or AYWWG or AYWWS)  
Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST  
Sales Office for Process Change Notice PCN MPG/EE/0059 (PCEE0059).  
29/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
REVISION HISTORY  
Table 31. Document Revision History  
Date  
Rev.  
Description of Revision  
Document reformatted, and reworded, using the new template. Temperature range 1 removed.  
TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added,  
with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and  
corresponding parameters adjusted)  
04-Feb-2003  
2.0  
Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges  
26-Mar-2003  
04-Apr-2003  
2.1  
2.2  
V
OUT  
and V separated from V in the Absolute Maximum Ratings table  
IN IO  
Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices  
with Process Identification Letter W  
23-May-2003  
27-May-2003  
2.3 Standby current corrected for -R range  
2.4 Turned-die option re-instated in Ordering Information Scheme  
Table of contents, and Pb-free options added. Temperature range 7 added. V (min) improved  
to 0.45V.  
IL  
25-Nov-2003  
30-Mar-2004  
16-Aug-2004  
3.0  
4.0  
5.0  
MLP package added. Absolute Maximum Ratings for V (min) and V (min) changed.  
IO  
CC  
Soldering temperature information clarified for RoHS compliant devices. Device grade  
information clarified. Process identification letter Ginformation added  
M93C06 removed. Device grade information further clarified. Process identification letter S”  
information added. Turned-die package option removed. Product list summary added.  
30/31  
M93C86, M93C76, M93C66, M93C56, M93C46  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
© 2004 STMicroelectronics - All rights reserved  
STMicroelectronics group of companies  
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -  
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America  
www.st.com  
31/31  

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M93C66-RMB3P/S STMICROELECTRONICS 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 获取价格
M93C66-RMB3P/W STMICROELECTRONICS 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 获取价格
M93C66-RMB3T STMICROELECTRONICS 16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROM 获取价格
M93C66-RMB3TG STMICROELECTRONICS 16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROM 获取价格
M93C66-RMB3TG/S STMICROELECTRONICS 16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide) MICROWIRE㈢ serial access EEPROM 获取价格

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