M93C76-RMN3P/K_技术文档

M93Cx6-A125

Automotive 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit

(8-bit or 16-bit wide) MICROWIRE serial EEPROM

Datasheet - production data

Features

TM

• Industry standard MICROWIRE bus

• Memory array: 1 Kb, 2 Kb, 4 Kb, 8 Kb or 16 Kb

• Dual organization: by word (x16) or byte (x8)

SO8 (MN)

150 mil width

• Write

– Byte within 4 ms

– Word within 4 ms

• READY/BUSY signal during programming

• 2 MHz clock rate

• Sequential read operation

• Single supply voltage: 1.8 V to 5.5 V

TSSOP8 (DW)

169 mil width

• Operating temperature range: -40 °C up to

125 °C

• Enhanced ESD protection

• Write cycle endurance

– 4 million Write cycles at 25 °C

– 1.2 million Write cycles at 85 °C

– 600 k Write cycles at 125 °C

WFDFPN8 (MF)

2 x 3 mm

• Data retention

– 50 years at 125 °C

– more than 100 years at 25 °C

• Packages

– RoHS-compliant and Halogen-free

®

(ECOPACK )

Table 1. Device summary

Reference

Part number

M93C46-A125

M93C56-A125

M93C66-A125

M93C76-A125

M93C86-A125

M93Cx6-A125

December 2013

DocID024752 Rev 2

1/31

This is information on a product in full production.

www.st.com

Contents

M93Cx6-A125

Contents

1

2

3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1

Supply voltage (V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1.1

3.1.2

3.1.3

3.1.4

Operating supply voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4

5

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1

5.2

Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 15

Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6

READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7

8

9

10

11

2/31

DocID024752 Rev 2

M93Cx6-A125

Contents

12

13

14

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DocID024752 Rev 2

3/31

3

List of tables

M93Cx6-A125

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Instruction set for the M93Cx6-A125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Operating conditions (M93Cx6-A125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Cycling performance by byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . 25

TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 26

WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead 2 x 3 mm,

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18.

Table 19.

4/31

DocID024752 Rev 2

M93Cx6-A125

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

M93Cx6-A125 ORG input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

READ, WRITE, WEN, WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. Synchronous timing (Start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. Synchronous timing (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. Synchronous timing (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 25

Figure 14. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15. WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead

2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DocID024752 Rev 2

5/31

5

Description

M93Cx6-A125

1

Description

The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86

(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed

through the MICROWIRE bus protocol. The memory array can be configured either in bytes

(x8b) or in words (x16b).

The M93Cx6-A125 devices operate within a voltage supply range from 1.8 V to 5.5 V

The M93Cx6-A125 devices are guaranteed over the -40 °C/+125 °C temperature range and

are compliant with the Automotive standard AEC-Q100 Grade 1.

Table 2. Memory size versus organization

Device

Number of bits

Number of 8-bit bytes

Number of 16-bit words

M93C86

M93C76

M93C66

M93C56

M93C46

16384

8192

4096

2048

1024

2048

1024

512

1024

512

256

128

64

256

128

Figure 1. Logic diagram

6

##

$

1

#

3

-ꢂꢅ#Xꢆ

/2'

6

33

!)ꢀꢁꢂꢃꢄ

Table 3. Signal names

Function

Signal name

Direction

S

D

Q

C

Chip Select

Input

Output

Input

Serial Data input

Serial Data output

Serial Clock

ORG

V_CC

V_SS

Organization Select

Supply voltage

Ground

6/31

DocID024752 Rev 2

M93Cx6-A125

Description

The M93Cx6-A125 is accessed by a set of instructions, as summarized in Table 4, and in

more detail in Table 5: Instruction set for the M93C46 to Table 7: Instruction set for the

M93C76 and M93C86).

Table 4. Instruction set for the M93Cx6-A125

Instruction

READ

Description

Read Data from Memory

Data

Byte or Word

WRITE

WEN

Write Data to Memory

Write Enable

Byte or Word

-

WDS

Write Disable

-

ERASE

ERAL

WRAL

Erase Byte or Word

Erase All Memory

Byte or Word

-

Write All Memory with same Data

A Read Data from Memory (READ) instruction loads the address of the first byte or word to

be read in an internal address register. The data at this address is then clocked out serially.

The address register is automatically incremented after the data is output and, if Chip Select

Input (S) is held High, the M93Cx6-A125 can output a sequential stream of data bytes or

words. In this way, the memory can be read as a data stream from eight to 16384 bits long

(in the case of the M93C86), or continuously (the address counter automatically rolls over to

00h when the highest address is reached).

Programming is internally self-timed (the external clock signal on Serial Clock (C) may be

stopped or left running after the start of a Write cycle) and does not require an Erase cycle

prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the

byte or word locations of the M93Cx6-A125. After the start of the programming cycle, a

Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is

driven High. An internal Power-on Data Protection mechanism in the M93Cx6-A125 inhibits

the device when the supply is too low.

Figure 2. 8-pin package connections (top view)

-ꢂꢅ#Xꢆ

3

#

$

1

ꢁ

ꢃ

ꢅ

ꢇ

ꢄ

ꢈ

ꢆ

ꢉ

6

##

$5

/2'

6

33

!)ꢀꢁꢂꢃꢂ"

1. See Section 12: Package mechanical data for package dimensions, and how to identify pin-1.

2. DU = Don’t Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is

reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be

connected to V_CCor V_SS

.

DocID024752 Rev 2

7/31

30

Connecting to the serial bus

M93Cx6-A125

2

Connecting to the serial bus

Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.

Only one device is selected at a time, so only one device drives the Serial Data output (Q)

line at a time, the other devices are high impedance.

The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the

bus master leaves the S line in the high impedance state.

In applications where the bus master may be in a state where all inputs/outputs are high

impedance at the same time (for example, if the bus master is reset during the transmission

of an instruction), the clock line (C) must be connected to an external pull-down resistor so

that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is

pulled low): this ensures that C does not become high at the same time as S goes low, and

so, that the t

requirement is met. The typical value of R is 100 kΩ.

SLCH

Figure 3. Bus master and memory devices on the serial bus

6₃₃

6_##

2

3$/

3$)

3#+

"US MASTER

6_##

#

1

$

#

1

$

# 1 $

6₃₃

-ꢂꢅXXX

MEMORY DEVICE

-ꢂꢅXXX

MEMORY DEVICE

-ꢂꢅXXX

MEMORY DEVICE

2

#3ꢅ #3ꢃ #3ꢁ

3

/2'

!)ꢁꢇꢅꢈꢈB

8/31

DocID024752 Rev 2

M93Cx6-A125

Operating features

3

Operating features

3.1

Supply voltage (V_CC)

3.1.1

Operating supply voltage (V

)

CC

Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage

CC

within the specified [V (min), V (max)] range must be applied. In order to secure a stable

CC

DC supply voltage, it is recommended to decouple the V line with a suitable capacitor

CC

(usually of the order of 10 nF to 100 nF) close to the V /V package pins.

CC SS

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (t ).

W

3.1.2

3.1.3

Power-up conditions

When the power supply is turned on, V rises from V to V . During this time, the Chip

Select (S) line is not allowed to float and should be driven to V , it is therefore

recommended to connect the S line to V via a suitable pull-down resistor.

CC

SS

CC

SS

The V rise time must not vary faster than 1 V/µs.

CC

Power-up and device reset

In order to prevent inadvertent Write operations during power-up, a power on reset (POR)

circuit is included. At power-up (continuous rise of V ), the device does not respond to any

CC

instruction until V has reached the power on reset threshold voltage (this threshold is

CC

lower than the minimum V operating voltage defined in Operating conditions, in

CC

Section 11: DC and AC parameters).

When V passes the POR threshold, the device is reset and is in the following state:

CC

•

Standby Power mode

deselected (assuming that there is a pull-down resistor on the S line)

3.1.4

Power-down

At power-down (continuous decrease in V ), as soon as V drops from the normal

CC

operating voltage to below the power on reset threshold voltage, the device stops

responding to any instruction sent to it.

During power-down, the device must be deselected and in the Standby Power mode (that is,

there should be no internal Write cycle in progress).

DocID024752 Rev 2

9/31

30

Memory organization

M93Cx6-A125

4

Memory organization

The M93Cx6-A125 memory is organized either as bytes (x8) or as words (x16). If

Organization Select (ORG) is left unconnected (or connected to V ) the x16 organization is

CC

selected; when Organization Select (ORG) is connected to Ground (V ) the x8

SS

organization is selected. When the M93Cx6-A125 is in Standby mode, Organization Select

(ORG) should be set either to V or V to reach the device minimum power consumption

SS

CC

(as any voltage between V and V applied to ORG input may increase the device

SS

CC

Standby current).

Figure 4. M93Cx6-A125 ORG input connection

9FF

9VV

9FF

9VV

9FF

9VV

1RWꢅ

FRQQHFWHG

25*

[ꢁꢂꢅRUJDQL]DWLRQ

[ꢆꢅRUJDQL]DWLRQ

06Yꢀꢁꢂꢃꢄ9ꢁ

10/31

DocID024752 Rev 2

M93Cx6-A125

Instructions

5

Instructions

The instruction set of the M93Cx6-A125 devices contains seven instructions, as

summarized in Table 5 to Table 7. Each instruction consists of the following parts, as shown

in Figure 5: READ, WRITE, WEN, WDS sequences:

•

Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock

(C) being held low.

A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of

Serial Clock (C).

Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock

(C). (Some instructions also use the first two bits of the address to define the op-code).

The address bits of the byte or word that is to be accessed. For the M93C46, the

address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization

(see Table 5). For the M93C56 and M93C66, the address is made up of 8 bits for the

x16 organization or 9 bits for the x8 organization (see Table 6). For the M93C76 and

M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8

organization (see Table 7).

The M93Cx6-A125 devices are fabricated in CMOS technology and are therefore able to

run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC

characteristics” tables, in Section 11: DC and AC parameters.

Table 5. Instruction set for the M93C46

x8 origination (ORG = 0)

x16 origination (ORG = 1)

Start Op-

Required

clock

Required

Address

Instruction

Description

Address

bit

code

Data

clock

(1)

cycles

Read Data from

Memory

READ

1

10

A6-A0

Q7-Q0

-

A5-A0

Q15-Q0

-

Write Data to

Memory

WRITE

WEN

1

01

00

A6-A0

D7-D0

18

10

A5-A0

D15-D0

25

9

Write Enable

Write Disable

11X XXXX

-

11 XXXX

00 XXXX

-

00X

XXXX

WDS

9

Erase Byte or

Word

ERASE

ERAL

1

11

00

A6-A0

-

10

18

A5-A0

-

9

10X

XXXX

Erase All Memory

10 XXXX

Write All Memory

with same Data

01X

XXXX

WRAL

D7-D0

01 XXXX D15-D0

25

1. X = Don't Care bit.

DocID024752 Rev 2

11/31

30

Instructions

Instruction

M93Cx6-A125

Table 6. Instruction set for the M93C56 and M93C66

x8 origination (ORG = 0)

x16 origination (ORG = 1)

Op-

cod

e

Start

bit

Required

Address

Required

Address

Description

Data

clock

Data

clock

(1) (2)

(1) (3)

cycles

Q7-

Q0

Q15-

Q0

READ

WRITE

WEN

Read Data from Memory

Write Data to Memory

Write Enable

1

10

01

00

A8-A0

-

A7-A0

-

D7-

D0

20

12

A7-A0 D15-D0

27

11

1 1XXX

XXXX

11XX

-

XXXX

0 0XXX

XXXX

00XX

-

WDS

Write Disable

1

00

11

00

-

12

11

XXXX

ERASE

ERAL

Erase Byte or Word

Erase All Memory

A8-A0

A7-A0

-

1 0XXX

XXXX

10XX

XXXX

Write All Memory with

same Data

0 1XXX

XXXX

D7-

D0

01XX

XXXX

WRAL

1

00

20

D15-D0

27

1. X = Don't Care bit.

2. Address bit A8 is not decoded by the M93C56.

3. Address bit A7 is not decoded by the M93C56.

Table 7. Instruction set for the M93C76 and M93C86

x8 Origination (ORG = 0)

x16 Origination (ORG = 1)

Start Op-

bit code

Required

clock

Required

Address

Instruction

Description

Address

Data

clock

(1)(2)

(1) (3)

cycles

Read Data from

Memory

READ

WRITE

WEN

1

10

01

00

A10-A0

Q7-Q0

D7-D0

-

A9-A0 Q15-Q0

A9-A0 D15-D0

-

Write Data to

Memory

22

14

29

13

11X XXXX

XXXX

11 XXXX

-

Write Enable

XXXX

00X XXXX

XXXX

00 XXXX

-

WDS

Write Disable

1

00

11

00

-

14

13

XXXX

ERASE

ERAL

Erase Byte or Word

Erase All Memory

A10-A0

A9-A0

-

10X XXXX

XXXX

10 XXXX

XXXX

Write All Memory

with same Data

01X XXXX

XXXX

01 XXXX

XXXX

WRAL

1

00

D7-D0

22

D15-D0

29

1. X = Don't Care bit.

2. Address bit A10 is not decoded by the M93C76.

3. Address bit A9 is not decoded by the M93C76.

12/31

DocID024752 Rev 2

M93Cx6-A125

Instructions

5.1

Read Data from Memory

The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).

When the instruction is received, the op-code and address are decoded, and the data from

the memory is transferred to an output shift register. A dummy 0 bit is output first, followed

by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are

triggered by the rising edge of Serial Clock (C). The M93Cx6-A125 automatically increments

the internal address register and clocks out the next byte (or word) as long as the Chip

Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or

words) and a continuous stream of data can be read (the address counter automatically rolls

over to 00h when the highest address is reached).

5.2

Erase and Write data

5.2.1

Write Enable and Write Disable

The Write Enable (WEN) instruction enables the future execution of erase or write

instructions, and the Write Disable (WDS) instruction disables it. When power is first

applied, the M93Cx6-A125 initializes itself so that erase and write instructions are disabled.

After a Write Enable (WEN) instruction has been executed, erasing and writing remains

enabled until a Write Disable (WDS) instruction is executed, or until V falls below the

CC

power-on reset threshold voltage. To protect the memory contents from accidental

corruption, it is advisable to issue the Write Disable (WDS) instruction after every write

cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable

(WEN) or Write Disable (WDS) instructions.

5.2.2

Write

For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and

address bits. These form the byte or word that is to be written. As with the other bits, Serial

Data Input (D) is sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the Chip Select Input (S) must be taken low before

the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after

this specific time frame, the self-timed programming cycle will not be started, and the

addressed location will not be programmed. The completion of the cycle can be detected by

monitoring the READY/BUSY line, as described later in this document.

Once the Write cycle has been started, it is internally self-timed (the external clock signal on

Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write

cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an

explicit erase instruction before a Write Data to Memory (WRITE) instruction.

DocID024752 Rev 2

13/31

30

Instructions

M93Cx6-A125

Figure 5. READ, WRITE, WEN, WDS sequences

2EAD

3

$

1

ꢁ ꢁ ꢀ !N

!ꢀ

1N

1ꢀ

!$$2

$!4! /54

/0

#/$%

7RITE

3

$

1

#(%#+

34!453

ꢁ ꢀ ꢁ !N

!ꢀ $N

$ꢀ

!$$2

$!4! ).

7RITE

"539

2%!$9

/0

#/$%

7RITE

%NABLE

3

$

3

$ISABLE

ꢁ ꢀ ꢀ ꢁ ꢁ 8N 8ꢀ

$

ꢁ ꢀ ꢀ ꢀ ꢀ 8N 8ꢀ

/0

#/$%

!)ꢀꢀꢄꢈꢄD

1. For the meanings of An, Xn, Qn and Dn, see Table 5, Table 6 and Table 7.

14/31

DocID024752 Rev 2

M93Cx6-A125

Instructions

5.2.3

Write All

As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with

same Data (WRAL) instruction requires that a dummy address be provided. As with the

Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same

Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.

This value is written to all the addresses of the memory device. The completion of the cycle

can be detected by monitoring the READY/BUSY line, as described next.

Figure 6. WRAL sequence

72)4%

!,,

3

$

1

#(%#+

34!453

ꢁ ꢀ ꢀ ꢀ ꢁ 8N 8ꢀ $N

$ꢀ

!$$2

/0

$!4! ).

"539

2%!$9

#/$%

!)ꢀꢀꢄꢄꢀ#

1. For the meanings of Xn and Dn, please see Table 5, Table 6 and Table 7.

5.2.4

ECC (Error Correction Code) and Write cycling

The devices identified with the Process letter “K” embed an Error Correction Code (ECC)

internal logic function which is transparent for the Microwire communication protocol.

The ECC logic is implemented on each byte.

DocID024752 Rev 2

15/31

30

Instructions

M93Cx6-A125

5.2.5

Erase Byte or Word

The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or

word) to 1. Once the address has been correctly decoded, the falling edge of the Chip

Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be

detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY

status.

Figure 7. ERASE, ERAL sequences

%2!3%

3

$

1

#(%#+

34!453

ꢁ ꢁ ꢁ !N

!ꢀ

!$$2

"539

2%!$9

/0

#/$%

%2!3%

!,,

3

$

1

#(%#+

34!453

ꢁ ꢀ ꢀ ꢁ ꢀ 8N 8ꢀ

!$$2

/0

"539

2%!$9

#/$%

!)ꢀꢀꢄꢈꢂ"

1. For the meanings of An and Xn, please see Table 5, Table 6 and Table 7.

5.2.6

Erase All

The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set

to 1). The format of the instruction requires that a dummy address be provided. The Erase

cycle is conducted in the same way as the Erase instruction (ERASE). The completion of

the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:

READY/BUSY status.

16/31

DocID024752 Rev 2

M93Cx6-A125

READY/BUSY status

6

READY/BUSY status

While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL

instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.

(Please note, though, that there is an initial delay, of t , before this status information

SLSH

becomes available). In this state, the M93Cx6-A125 ignores any data on the bus. When the

Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)

indicates that the M93Cx6-A125 is ready to receive the next instruction. Serial Data Output

(Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is

decoded.

7

8

Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

Common I/O operation

Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a

current limiting resistor, to form a common, single-wire data bus. Some precautions must be

taken when operating the memory in this way, mostly to prevent a short circuit current from

flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output

(Q). Please see the application note AN394 for details.

DocID024752 Rev 2

17/31

30

Clock pulse counter

M93Cx6-A125

9

Clock pulse counter

In a noisy environment, the number of pulses received on Serial Clock (C) may be greater

than the number delivered by the master (the microcontroller). This can lead to a

misalignment of the instruction of one or more bits (as shown in Figure 8) and may lead to

the writing of erroneous data at an erroneous address.

To avoid this problem, the M93Cx6-A125 has an on-chip counter that counts the clock

pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of

clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL

instruction is aborted, and the contents of the memory are not modified.

The number of clock cycles expected for each instruction, and for each member of the

M93Cx6-A125 family, are summarized in Table 5: Instruction set for the M93C46 to Table 7:

Instruction set for the M93C76 and M93C86. For example, a Write Data to Memory (WRITE)

instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization)

from the start bit to the falling edge of Chip Select Input (S). That is:

1 Start bit

+ 2 Op-code bits

+ 9 Address bits

+ 8 Data bits

Figure 8. Write sequence with one clock glitch

3

#

$

!N

!Nꢊꢁ

'LITCH

!Nꢊꢃ

34!24

ꢋꢀꢋ

ꢋꢁꢋ

$ꢀ

!$$2%33 !.$ $!4!

!2% 3()&4%$ "9 /.% ")4

72)4%

!)ꢀꢁꢅꢂꢉ

18/31

DocID024752 Rev 2

M93Cx6-A125

Maximum ratings

10

Maximum ratings

Stressing the device outside the ratings listed in the Absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only, and operation of the

device at these, or any other conditions outside those indicated in the operating sections of

this specification, is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 8. Absolute maximum ratings

Symbol

Parameter

Min.

Max.

Unit

Ambient operating temperature

Storage temperature

–40

–65

130

150

°C

V

T_STG

T_LEADLead temperature during soldering

See note ⁽¹⁾

V_OUT

V_IN

Output range (Q = V_OHor Hi-Z)

Input range

–0.50

-

V_CC+0.5

V_CC+1

6.5

V

V_CC

V_ESD

Supply voltage

V

Electrostatic discharge voltage (human body model)⁽²⁾

4000

V

1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb assembly), the ST ECOPACK®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS

directive 2011/65/EU of July 2011).

2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with JEDEC

Std JESD22-A114, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

DocID024752 Rev 2

19/31

30

DC and AC parameters

M93Cx6-A125

11

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device.

Table 9. Operating conditions (M93Cx6-A125)

Symbol

Parameter

Min.

Max.

Unit

V_CC

T_A

Supply voltage

Ambient operating temperature

1.8

5.5

V

–40

125

°C

Table 10. AC measurement conditions

Symbol

Parameter

Min.

Max.

Unit

C_L

Load capacitance

100

pF

ns

V

-

Input rise and fall times

-

50

Input voltage levels

0.2 V_CCto 0.8 V_CC

0.3 V_CCto 0.7 V_CC

Input timing reference voltages

Output timing reference voltages

V

Figure 9. AC testing input output waveforms

-ꢂꢅ#88

ꢄꢇꢆ9

&&

ꢄꢇꢉ9

ꢄꢇꢀ9

&&

)NPUT AND OUTPUT

TIMING REFERENCE LEVELS

)NPUT VOLTAGE LEVELS

ꢄꢇꢈ9

-3ꢁꢂꢈꢄꢄ6ꢅ

Table 11. Input and output capacitance

Symbol

C_OUT

C_IN

Parameter

Test condition⁽¹⁾

Min

Max

Unit

Output capacitance

Input capacitance

V_OUT= 0V

V_IN= 0V

-

8

6

pF

1. Sampled only, not 100% tested, at T_A= 25 °C and a frequency of 1 MHz.

Table 12. Cycling performance by byte

Symbol

Parameter

Test condition

Min.

Max.

Unit

TA ≤ 25 °C, 1.8 V < V_CC< 5.5 V

TA = 85 °C, 1.8 V < V_CC< 5.5 V

TA = 125 °C, 1.8 V < V_CC< 5.5 V

-

4,000,000

1,200,000

600,000

Write cycle

endurance

Write

Ncycle

cycle⁽¹⁾

1. A Write cycle is executed when either a Write, a Write All, an Erase or an Erase All instruction is decoded.

20/31

DocID024752 Rev 2

M93Cx6-A125

DC and AC parameters

Table 13. DC characteristics

Test conditions

(in addition to conditions specified

in Table 9)

Symbol

Parameter

Min.

Max.

Unit

I_LI

Input leakage current

Output leakage current

V_IN= V_SSor V_CC

-

2

µA

I_LO

S = V_CC, V_OUT= V_SSor V_CC

V_CC= 1.8 V, C = 0.1 V_CC/0.9 V_CC

Q = open, f_C= 2 MHz

,

-

1

V_CC= 2.5 V, C = 0.1 V_CC/0.9 V_CC

Q = open, f_C= 2 MHz

I_CC

Supply current (Read)

Supply current (Write)

mA

V_CC= 5.5 V, f_C= 2 MHz

1.5

C = 0.1 V_CC/0.9 V_CC, Q = open

1.8 V ≤ V_CC< 5.5 V during t_W,

S = V_CC

(1)

I_CC0

-

1.5

1

t° = 85 °C, V_CC= 1.8 V,

S = V_CC,V_IN= V_SSor V_CC

t° = 85 °C, V_CC= 2.5 V,

S = V_CC,V_IN= V_SSor V_CC

2

t° = 85 °C, V_CC= 5.5 V,

S = V_CC,V_IN= V_SSor V_CC

3

I_CC1

Supply current (Standby mode)

µA

t° = 125 °C, V_CC= 1.8 V,

S = V_CC,V_IN= V_SSor V_CC

15

t° = 125 °C, V_CC= 2.5 V,

S = V_CC,V_IN= V_SSor V_CC

t° = 125 °C, V_CC= 5.5 V,

S = V_CC,V_IN= V_SSor V_CC

1.8 V ≤ V_CC< 2.5 V

2.5 V ≤ V_CC< 5.5 V

1.8 V ≤ V_CC< 2.5 V

2.5 V ≤ V_CC< 5.5 V

–0.45

0.25 V_CC

0.3 V_CC

V_IL

V_IH

V_OL

Input low voltage (D, C, S)

Input high voltage (D, C, S)

Output low voltage

V

0.75 V_CCV_CC+0.5

0.7 V_CC

V_CC+0.5

V

_CC= 1.8 V, I_OL= 1 mA

V_CC≥ 2.5 V, I_OL= 2.1 mA

_CC= 1.8 V, I_OH= 1 mA

-

0.3

0.4

-

V

0.8 V_CC

0.5

V_OH

Output high voltage

V

V_CC≥ 2.5 V, I_OH= -2.1 mA

-

V_RES

Internal reset threshold voltage

-

1.5

1. Average value during the Write cycle (t_W)

DocID024752 Rev 2

21/31

30

DC and AC parameters

M93Cx6-A125

Table 14. AC characteristics

Test conditions specified in Table 9 and Table 10

Symbol

Alt.

Parameter

Min.

Max.

Unit

f_C

f_SK

Clock frequency

D.C.

50

200

50

0

2

MHz

ns

ms

t_SLCH

t_SHCH

Chip Select low to Clock high

Chip Select set-up time

-

t_CSS

t_CS

-

(1)

t_SLSH

Chip Select low to Chip Select high

Clock high time

-

(2)

t_CHCL

t_SKH

t_SKL

t_DIS

t_DIH

t_SKS

t_CSH

t_SV

-

(2)

t_CLCH

Clock low time

t_DVCH

t_CHDX

t_CLSH

t_CLSL

t_SHQV

Data in set-up time

-

Data in hold time

-

Clock set-up time (relative to S)

Chip Select hold time

-

Chip Select to READY/BUSY status

Chip Select low to output Hi-Z (V_CC>2.5 V)

Chip Select low to output Hi-Z (V_CC<2.5 V)

Delay to output low

-

200

100

200

4

-

(3)

t_SLQZ

t_DF

-

t_CHQL

t_CHQV

t_W

t_PD0

t_PD1

t_WP

-

Delay to output valid

-

Erase or Write cycle time

-

1. Chip Select Input (S) must be brought low for a minimum of t_SLSHbetween consecutive instruction cycles.

2. t_CHCL+ t_CLCH≥ 1 / f_C.

3. Value defined from characterization, not tested in production.

22/31

DocID024752 Rev 2

M93Cx6-A125

DC and AC parameters

Figure 10. Synchronous timing (Start and op-code input)

W&/6+

W&+&/

#

3

$

W6+&+

W&/&+

W'9&+

67$57

W&+';

23ꢅ&2'(

67$57

23ꢅ&2'(ꢅ,1387

AIꢀꢁꢇꢃꢄ

Figure 11. Synchronous timing (Read)

#

3

$

1

T#,3,

T$6#(

T#($8

T#(16

T3,3(

!ꢀ

!N

T3,1:

T#(1,

(Iꢊ:

1ꢁꢉꢌ1ꢈ

1ꢀ

!$$2%33 ).054

$!4! /54054

!)ꢀꢀꢄꢃꢀ#

Figure 12. Synchronous timing (Write)

W6/&+

#

3

$

1

W&/6/

W'9&+

W&+';

$ꢄꢊ'ꢄ

W6/6+

$Q

W6+49

%86<

W6/4=

5($'<

+Lꢋ=

W:

$''5(66ꢊ'$7$ꢅ,1387

:5,7(ꢅ&<&/(

AIꢀꢁꢇꢃꢂ

DocID024752 Rev 2

23/31

30

Package mechanical data

M93Cx6-A125

12

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

24/31

DocID024752 Rev 2

M93Cx6-A125

Package mechanical data

Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width,

package outline

Kꢅ[ꢅꢌꢍ

$ꢈ

$

F

FFF

E

H

ꢄꢇꢈꢍꢅPP

*$8*(ꢅ3/$1(

'

N

ꢆ

(ꢁ

(

/

ꢁ

$ꢁ

/ꢁ

62ꢋ$

1. Drawing is not to scale.

Table 15. SO8 narrow – 8 lead plastic small outline, 150 mils body width,

package data

millimeters

Min

inches⁽¹⁾

Symbol

Typ

Max

Typ

Min

Max

A

A1

A2

b

-

1.75

0.25

-

0.0689

0.0098

-

0.1

1.25

0.28

0.17

-

0.0039

0.0492

0.011

0.0067

-

0.48

0.23

0.1

5

-

0.0189

0.0091

0.0039

0.1969

0.2441

0.1575

-

c

-

ccc

D

-

4.9

6

-

4.8

5.8

3.8

-

0.1929

0.2362

0.1535

0.05

-

0.189

0.2283

0.1496

-

E

6.2

4

E1

e

3.9

1.27

-

h

0.25

0°

0.5

8°

0.0098

0°

0.0197

8°

k

-

L

-

0.4

-

1.27

-

0.0157

-

0.05

L1

1.04

0.0409

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID024752 Rev 2

25/31

30

Package mechanical data

M93Cx6-A125

Figure 14. TSSOP8 – 8 lead thin shrink small outline, package outline

'

ꢆ

ꢁ

ꢍ

ꢌ

F

(ꢁ (

D

$ꢁ

/

$

$ꢈ

/ꢁ

&3

E

H

76623ꢆ$0

1. Drawing is not to scale.

Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

millimeters

Min

inches⁽¹⁾

Symbol

Typ

Max

Typ

Min

Max

A

A1

A2

b

-

1.200

0.150

1.050

0.300

0.200

0.100

3.100

-

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.1220

-

0.050

0.800

0.190

0.090

-

0.0020

0.0315

0.0075

0.0035

-

1.000

-

0.0394

-

c

-

CP

D

-

3.000

0.650

6.400

4.400

0.600

1.000

-

2.900

-

0.1181

0.0256

0.2520

0.1732

0.0236

0.0394

-

0.1142

-

e

E

6.200

4.300

0.450

-

6.600

4.500

0.750

-

0.2441

0.1693

0.0177

-

0.2598

0.1772

0.0295

-

E1

L

L1

α

0°

8°

0°

8°

N

8

1. Values in inches are converted from mm and rounded to four decimal digits.

26/31

DocID024752 Rev 2

M93Cx6-A125

Package mechanical data

Figure 15. WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead

2 x 3 mm, package outline

$ꢃ

$ꢃꢌꢃ

$ATUM !

E

$

%ꢃꢌꢃ

0IN ꢍꢁ )$ MARKING

%ꢃ

3EE

$ETAIL h!v

%

+

ꢃX

AAA

#

.8 B

ꢃX

AAA

#

-

ꢎ.$ꢊꢁꢏ X E

BBB

! "

#

-

DDD

#

4OP VIEW

"OTTOM VIEW

!

CCC

#

$ATUM !

EEE

3EATING PLANE

#

!ꢁ

3IDE VIEW

,

,ꢅ

Eꢌꢃ

E

,ꢁ

4ERMINAL TIP

$ETAIL h!v

-&?-%?6ꢅ

1. Drawing is not to scale.

DocID024752 Rev 2

27/31

30

Package mechanical data

M93Cx6-A125

Table 17. WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead 2 x 3 mm,

mechanical data

millimeters

Min.

inches⁽¹⁾

Symbol

Typ.

Max.

Typ.

Min.

Max.

A

A1

b

0.750

0.045

0.250

2.000

3.000

0.700

0.025

0.200

1.900

2.900

0.500

-

0.800

0.065

0.300

2.100

3.100

0.0295

0.0018

0.0098

0.0787

0.1181

0.0276

0.0010

0.0079

0.0748

0.1142

0.0197

-

0.0315

0.0026

0.0118

0.0827

0.1220

D

E

e

L1

-

0.150

-

0.0059

-

L3

0.300

0.0118

NX⁽²⁾

ND⁽³⁾

aaa

bbb

ccc

ddd

eee⁽⁴⁾

D2

E2

K

8

4

0.150

0.100

0.050

0.080

1.050

0.450

0.300

0.0059

0.0039

0.0020

0.0031

0.0413

0.0177

0.0118

-

1.450

-

0.0571

-

L

0.500

1. Values in inches are converted from mm and rounded to four decimal digits.

2. NX is the number of terminals.

3. ND is the number of terminals on “D” sides.

4. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

measuring.

28/31

DocID024752 Rev 2

M93Cx6-A125

Part numbering

13

Part numbering

Table 18. Ordering information scheme

M93C86

Example:

–

R MN

3

T

P

/K

Device type

M93 = MICROWIRE serial EEPROM

Device function

86 = 16 Kbit (2048 x 8)

76 = 8 Kbit (1024 x 8)

66 = 4 Kbit (512 x 8)

56 = 2 Kbit (256 x 8)

46 = 1 Kbit (128 x 8)

Operating voltage

R = V_CC= 1.8 to 5.5 V

Package⁽¹⁾

MN = SO8 (150 mils width)

DW = TSSOP8 (169 mils width)

MF = WFDFPN8 (2 x 3 mm)

Device grade

3 = Device tested with high reliability certified flow⁽²⁾

Automotive temperature range (–40 to 125 °C)

Packing

blank = standard packing

T = tape and reel packing

Plating technology

P = ECOPACK^®(RoHS compliant)

Process

/K = Manufacturing technology code

1. All packages are ECOPACK2® (RoHS compliant and Halogen-free).

2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your

nearest ST sales office for a copy.

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

DocID024752 Rev 2

29/31

30

Revision history

M93Cx6-A125

14

Revision history

Table 19. Document revision history

Changes

Date

Revision

15-Nov-2013

07-Aug-2013

15

1

Removed Table 14 Cycling performance by byte

Initial release

Document status changed from “Preliminary data” to “Production data”.

Updated:

– Features: “data retention” bullet

– Table 9: Operating conditions (M93Cx6-A125)

– “T_SLQZ” row in Table 14: AC characteristics

– Note ⁽¹⁾under Table 8: Absolute maximum ratings

– Table 13: DC characteristics

02-Dec-2013

2

– Figure 15: WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package

no lead 2 x 3 mm, package outline.

Renamed Figure 11: Synchronous timing (Read) and Figure 12:

Synchronous timing (Write).

30/31

DocID024752 Rev 2

M93Cx6-A125

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE

SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)

AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS

OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT

PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS

EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY

DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE

DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

DocID024752 Rev 2

31/31

31


型号：	M93C76-RMN3P/K
厂家：	ST
描述：	512 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, SOP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总31页 (文件大小：579K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M93C76-RMN3P/K [STMICROELECTRONICS]

相关型号：

M93C76-RMN3P/S

M93C76-RMN3P/W

M93C76-RMN3T

M93C76-RMN3TG

M93C76-RMN3TG/S

M93C76-RMN3TG/W

M93C76-RMN3TP

M93C76-RMN3TP/K

M93C76-RMN3TP/S

M93C76-RMN3TP/W

M93C76-RMN5

M93C76-RMN5T