M93C76M93C76-W [STMICROELECTRONICS]
16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide) MICROWIRE serial access EEPROM; 16千位，8千位，4千位， 2千位和1千位（8位或16位宽） MICROWIRE的串行存取的EEPROM
| 型号： | M93C76M93C76-W |
| 厂家： | 
ST |
| 描述： | 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide) MICROWIRE serial access EEPROM |
| 文件： | 总33页 (文件大小：979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M93C86xx M93C76xx
M93C66xx M93C56xx M93C46xx
16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit
(8-bit or 16-bit wide) MICROWIRE serial access EEPROM
Datasheet - production data
• Self-timed programming cycle with auto-erase:
5 ms
• READY/BUSY signal during programming
• 2 MHz clock rate
• Sequential read operation
PDIP8 (BN)
• Enhanced ESD/latch-up behavior
• More than 1 million write cycles
• More than 40 year data retention
• Packages
– SO8, TSSOP8, UFDFPN8 packages:
RoHS-compliant and Halogen-free
(ECOPACK2®)
SO8 (MN)
150 mil width
– PDIP8 package:
RoHS-compliant (ECOPACK1®)
Table 1. Device summary
TSSOP8 (DW)
169 mil width
Part
number
Memory
size
Supply
voltage
Reference
M93C46
4.5 V to 5.5 V
2.5 V to 5.5 V
4.5 V to 5.5 V
M93C46xx
1 Kbit
M93C46-W
M93C56
UFDFPN8 (MC)
2 x 3 mm
M93C56xx
M93C66xx
M93C56-W
M93C56-R
M93C66
2 Kbit 2.5 V to 5.5 V
1.8 V to 5.5 V
4.5 V to 5.5 V
M93C66-W
M93C66-R
M93C76-W
M93C76-R
M93C86
4 Kbit 2.5 V to 5.5 V
1.8 V to 5.5 V
Features
• Industry standard MICROWIRE bus
2.5 V to 5.5 V
8 Kbit
M93C76xx
M93C86xx
• Single supply voltage:
1.8 V to 5.5 V
– 4.5 V to 5.5 V for M93Cx6
– 2.5 V to 5.5 V for M93Cx6-W
– 1.8 V to 5.5 V for M93Cx6-R
4.5 V to 5.5 V
16 Kbit
M93C86-W
2.5 V to 5.5 V
• Dual organization: by word (x16) or byte (x8)
• Programming instructions that work on: byte,
word or entire memory
April 2013
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This is information on a product in full production.
www.st.com
1
Contents
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1
3.1.2
3.1.3
3.1.4
Operating supply voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
5.2
Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
8
9
10
11
12
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Contents
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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List of tables
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . 20
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics (M93Cx6, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC characteristics (M93Cx6, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . 28
UFDFPN8 8-lead ultra thin fine pitch dual flat package no lead
Table 21.
Table 22.
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 23.
Table 24.
Table 25.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ, WRITE, WEN, WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. UFDFPN8 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30
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Description
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
1
Description
The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed
through the MICROWIRE bus protocol. The memory array can be configured either in bytes
(x8b) or in words (x16b).
The M93Cx6 devices operate within a voltage supply range from 4.5 V to 5.5 V, the
M93Cx6-W devices operate within a voltage supply range from 2.5 V to 5.5 V, and the
M93Cx6-R devices operate within a voltage supply range from 1.8 V to 5.5 V. All these
devices operate with a clock frequency of 2 MHz (or less), over an ambient temperature
range of -40 °C / +85 °C.
Table 2. Memory size versus organization
Device
Number of bits
Number of 8-bit bytes
Number of 16-bit words
M93C86
M93C76
M93C66
M93C56
M93C46
16384
8192
4096
2048
1024
2048
1024
512
1024
512
256
128
64
256
128
Figure 1. Logic diagram
V
CC
D
Q
C
S
M93Cx6
ORG
V
SS
AI01928
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Description
Table 3. Signal names
Function
Signal name
Direction
S
Chip Select
Input
Input
Output
Input
Input
D
Serial Data input
Q
Serial Data output
Serial Clock
C
ORG
VCC
VSS
Organization Select
Supply voltage
Ground
Figure 2. 8-pin package connections (top view)
M93Cx6
S
C
D
Q
1
2
3
4
8
V
CC
DU
7
6
5
ORG
V
SS
AI01929B
1. See Section 11: Package mechanical data for package dimensions, and how to identify pin-1.
2. DU = Don’t Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is
reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be
connected to VCC or VSS
.
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Connecting to the serial bus
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
2
Connecting to the serial bus
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only one device drives the Serial Data output (Q)
line at a time, the other devices are high impedance.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time (for example, if the bus master is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the t
requirement is met. The typical value of R is 100 kΩ.
SLCH
Figure 3. Bus master and memory devices on the serial bus
VSS
VCC
R
SDO
SDI
SCK
Bus master
VCC
VCC
VCC
C
Q
D
C
Q
D
C Q D
VSS
VSS
VSS
M93xxx
memory device
M93xxx
memory device
M93xxx
memory device
R
R
R
CS3 CS2 CS1
S
S
S
ORG
ORG
ORG
AI14377b
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Operating features
3
Operating features
3.1
Supply voltage (VCC)
3.1.1
Operating supply voltage (V
)
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied. In order to secure a stable
CC
CC
DC supply voltage, it is recommended to decouple the V line with a suitable capacitor
CC
(usually of the order of 10 nF to 100 nF) close to the V /V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t ).
W
3.1.2
3.1.3
Power-up conditions
When the power supply is turned on, V rises from V to V . During this time, the Chip
Select (S) line is not allowed to float and should be driven to V , it is therefore
recommended to connect the S line to V via a suitable pull-down resistor.
CC
SS
CC
SS
SS
The V rise time must not vary faster than 1 V/µs.
CC
Power-up and device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of V ), the device does not respond to any
CC
instruction until V has reached the power on reset threshold voltage (this threshold is
CC
lower than the minimum V operating voltage defined in Operating conditions, in
CC
Section 10: DC and AC parameters).
When V passes the POR threshold, the device is reset and is in the following state:
CC
•
•
Standby Power mode
deselected (assuming that there is a pull-down resistor on the S line)
3.1.4
Power-down
At power-down (continuous decrease in V ), as soon as V drops from the normal
CC
CC
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During power-down, the device must be deselected and in the Standby Power mode (that is,
there should be no internal Write cycle in progress).
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Memory organization
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
4
Memory organization
The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization
Select (ORG) is left unconnected (or connected to V ) the x16 organization is selected;
CC
when Organization Select (ORG) is connected to Ground (V ) the x8 organization is
SS
selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set
either to V or V for minimum power consumption. Any voltage between V and V
SS
CC
SS
CC
applied to Organization Select (ORG) may increase the Standby current.
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Instructions
5
Instructions
The instruction set of the M93Cx6 devices contains seven instructions, as summarized in
Table 4 to Table 6. Each instruction consists of the following parts, as shown in Figure 4:
READ, WRITE, WEN, WDS sequences:
•
•
•
•
Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock
(C) being held low.
A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of
Serial Clock (C).
Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock
(C). (Some instructions also use the first two bits of the address to define the op-code).
The address bits of the byte or word that is to be accessed. For the M93C46, the
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 4). For the M93C56 and M93C66, the address is made up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and
M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8
organization (see Table 6).
The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as
slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC
characteristics” tables, in Section 10: DC and AC parameters.
Table 4. Instruction set for the M93C46
x8 origination (ORG = 0)
x16 origination (ORG = 1)
Start Op-
Required
clock
Required
Address
Instruction
Description
Address
bit
code
Data
Data
clock
(1)
(1)
cycles
cycles
Read Data from
Memory
READ
1
10
A6-A0
Q7-Q0
D7-D0
A5-A0
Q15-Q0
D15-D0
Write Data to
Memory
WRITE
WEN
1
1
1
01
00
00
A6-A0
18
10
10
A5-A0
25
9
Write Enable
Write Disable
11X XXXX
11 XXXX
00 XXXX
00X
XXXX
WDS
9
Erase Byte or
Word
ERASE
ERAL
1
1
1
11
00
00
A6-A0
10
10
18
A5-A0
9
9
10X
XXXX
Erase All Memory
10 XXXX
Write All Memory
with same Data
01X
XXXX
WRAL
D7-D0
01 XXXX D15-D0
25
1. X = Don't Care bit.
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Instructions
Instruction
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Table 5. Instruction set for the M93C56 and M93C66
x8 origination (ORG = 0) x16 origination (ORG = 1)
Start Op-
bit code
Description
Address
Required Address
clock cycles
Required
clock cycles
Data
Data
(1) (2)
(1) (3)
Read Data from
Memory
READ
WRITE
WEN
1
1
1
1
1
1
1
10
01
00
00
11
00
00
A8-A0
A8-A0
Q7-Q0
D7-D0
A7-A0 Q15-Q0
A7-A0 D15-D0
Write Data to
Memory
20
12
12
12
12
20
27
11
11
11
11
27
1 1XXX
XXXX
11XX
XXXX
Write Enable
Write Disable
0 0XXX
XXXX
00XX
XXXX
WDS
Erase Byte or
Word
ERASE
ERAL
WRAL
A8-A0
A7-A0
Erase All
Memory
1 0XXX
XXXX
10XX
XXXX
Write All Memory
with same Data
0 1XXX
XXXX
01XX
D7-D0
D15-D0
XXXX
1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.
Table 6. Instruction set for the M93C76 and M93C86
x8 Origination (ORG = 0)
x16 Origination (ORG = 1)
Start Op-
bit code
Required
clock
Required
Address
Instruction
Description
Address(1),
Data
Data
clock
(2)
(1) (3)
cycles
cycles
Read Data from
Memory
READ
WRITE
WEN
1
1
1
10
01
00
A10-A0
A10-A0
Q7-Q0
D7-D0
A9-A0 Q15-Q0
A9-A0 D15-D0
Write Data to
Memory
22
14
29
13
11X XXXX
XXXX
11 XXXX
XXXX
Write Enable
00X XXXX
XXXX
00 XXXX
XXXX
WDS
Write Disable
1
1
1
00
11
00
14
14
14
13
13
13
ERASE
ERAL
Erase Byte or Word
Erase All Memory
A10-A0
A9-A0
10X XXXX
XXXX
10 XXXX
XXXX
Write All Memory
with same Data
01X XXXX
XXXX
01 XXXX
D15-D0
XXXX
WRAL
1
00
D7-D0
22
29
1. X = Don't Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.
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Instructions
5.1
Read Data from Memory
The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).
When the instruction is received, the op-code and address are decoded, and the data from
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the
internal address register and clocks out the next byte (or word) as long as the Chip Select
Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words)
and a continuous stream of data can be read (the address counter automatically rolls over
to 00h when the highest address is reached).
5.2
Erase and Write data
5.2.1
Write Enable and Write Disable
The Write Enable (WEN) instruction enables the future execution of erase or write
instructions, and the Write Disable (WDS) instruction disables it. When power is first
applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After a
Write Enable (WEN) instruction has been executed, erasing and writing remains enabled
until a Write Disable (WDS) instruction is executed, or until V falls below the power-on
CC
reset threshold voltage. To protect the memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read
Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write
Disable (WDS) instructions.
5.2.2
Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write
cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an
explicit erase instruction before a Write Data to Memory (WRITE) instruction.
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Instructions
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Figure 4. READ, WRITE, WEN, WDS sequences
Read
S
D
Q
1 1 0 An
A0
Qn
Q0
ADDR
DATA OUT
OP
CODE
Write
S
D
Q
CHECK
STATUS
1 0 1 An
A0 Dn
D0
ADDR
DATA IN
BUSY
READY
OP
CODE
Write
Enable
S
D
Write
Disable
S
1 0 0 1 1 Xn X0
D
1 0 0 0 0 Xn X0
OP
OP
CODE
CODE
AI00878d
1. For the meanings of An, Xn, Qn and Dn, see Table 4, Table 5 and Table 6.
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Instructions
5.2.3
Write All
As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with
same Data (WRAL) instruction requires that a dummy address be provided. As with the
Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same
Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.
This value is written to all the addresses of the memory device. The completion of the cycle
can be detected by monitoring the READY/BUSY line, as described next.
Figure 5. WRAL sequence
WRITE
ALL
S
D
Q
CHECK
STATUS
1 0 0 0 1 Xn X0 Dn
D0
ADDR
OP
DATA IN
BUSY
READY
CODE
AI00880C
1. For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6.
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Instructions
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
5.2.4
Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.
Figure 6. ERASE, ERAL sequences
ERASE
S
D
Q
CHECK
STATUS
1 1 1 An
A0
ADDR
BUSY
READY
OP
CODE
ERASE
ALL
S
D
Q
CHECK
STATUS
1 0 0 1 0 Xn X0
ADDR
OP
BUSY
READY
CODE
AI00879B
1. For the meanings of An and Xn, please see Table 4, Table 5 and Table 6.
5.2.5
Erase All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:
READY/BUSY status.
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M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
READY/BUSY status
6
READY/BUSY status
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of t
, before this status information
SLSH
becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
7
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
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Clock pulse counter
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
8
Clock pulse counter
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delivered by the master (the microcontroller). This can lead to a
misalignment of the instruction of one or more bits (as shown in Figure 7) and may lead to
the writing of erroneous data at an erroneous address.
To avoid this problem, the M93Cx6 has an on-chip counter that counts the clock pulses from
the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses
received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is
aborted, and the contents of the memory are not modified.
The number of clock cycles expected for each instruction, and for each member of the
M93Cx6 family, are summarized in Table 4: Instruction set for the M93C46 to Table 6:
Instruction set for the M93C76 and M93C86. For example, a Write Data to Memory (WRITE)
instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization)
from the start bit to the falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
Figure 7. Write sequence with one clock glitch
S
C
D
An
An-1
Glitch
An-2
START
"0"
"1"
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
WRITE
AI01395
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Maximum rating
9
Maximum rating
Stressing the device outside the ratings listed in the Absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 7. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
TSTG
PDIP
260(1)
TLEAD Lead temperature during soldering
other packages
See note (2)
°C
V
VOUT
VIN
Output range (Q = VOH or Hi-Z)
Input range
–0.50
–0.50
–0.50
VCC+0.5
VCC+1
6.5
V
VCC
VESD
Supply voltage
V
Electrostatic discharge voltage (human body model)(3)
4000
V
1. TLEAD max must not be applied for more than 10 s.
2. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions of Hazardous
Substances (RoHS) 2011/65/EU.
3. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant
with JEDEC Std JESD22-A114, C1 = 100pF, R1 = 1500Ω, R2 = 500Ω).
DocID4997 Rev 13
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DC and AC parameters
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8. Operating conditions (M93Cx6)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
4.5
5.5
85
V
–40
°C
Table 9. Operating conditions (M93Cx6-W)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
2.5
5.5
85
V
–40
°C
Table 10. Operating conditions (M93Cx6-R)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
1.8
5.5
85
V
–40
°C
Table 11. AC measurement conditions (M93Cx6)
Parameter Min. Max.
Symbol
Unit
CL
Load capacitance
100
pF
ns
V
Input rise and fall times
50
Input voltage levels
0.4 V to 2.4 V
1.0 V and 2.0 V
0.8 V and 2.0 V
Input timing reference voltages
Output timing reference voltages
V
V
Table 12. AC measurement conditions (M93Cx6-W and M93Cx6-R)
Symbol
Parameter
Min.
Max.
Unit
CL
Load capacitance
100
pF
ns
V
Input rise and fall times
50
Input voltage levels
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
0.3 VCC to 0.7 VCC
Input timing reference voltages
Output timing reference voltages
V
V
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DC and AC parameters
Figure 8. AC testing input output waveforms
M93CXX
2.4V
Input voltage levels
2V
1V
2.0V
0.8V
Input and output
timing reference levels
0.4V
Input
Output
M93CXX-W and M93CXX-R
0.8V
CC
0.7V
0.3V
CC
CC
Input and output
timing reference levels
Input voltage levels
0.2V
CC
MS19788V2
Table 13. Capacitance
Test condition(1)
Symbol
COUT
CIN
Parameter
Min
Max
Unit
Output capacitance
Input capacitance
VOUT = 0V
VIN = 0V
5
5
pF
pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 1 MHz.
Table 14. DC characteristics (M93Cx6, device grade 6)
Symbol
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
Output leakage current
0V ≤ VIN ≤ VCC
±2.5
±2.5
µA
µA
ILO
0V ≤ VOUT ≤ VCC, Q in Hi-Z
V
CC = 5 V, S = VIH, f = 2 MHz,
Q = open
ICC
Supply current
2
mA
µA
V
CC = 5 V, S = VSS, C = VSS
,
ICC1
Supply current (Standby)
ORG = VSS or VCC
,
15
pin7 = VCC, VSS or Hi-Z
(1)
VIL
Input low voltage
Input high voltage
Output low voltage
Output high voltage
VCC = 5 V ± 10%
–0.45
2
0.8
VCC + 1
0.4
V
V
V
V
(1)
VIH
VCC = 5 V ± 10%
(1)
VOL
VCC = 5 V, IOL = 2.1 mA
VCC = 5 V, IOH = –400 µA
(1)
VOH
0.8VCC
1. Please note that the input and output levels defined in this table are compatible with TTL logic
levels and are NOT fully compatible with CMOS levels (as defined in Table 15).
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DC and AC parameters
Symbol
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Table 15. DC characteristics (M93Cx6-W, device grade 6)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
Output leakage current
0V ≤ VIN ≤ VCC
±2.5
±2.5
µA
µA
ILO
0V ≤ VOUT ≤ VCC, Q in Hi-Z
VCC = 5 V, S = VIH, f = 2 MHz,
Q = open
2
1
mA
mA
Supply current (CMOS
inputs)
ICC
VCC = 2.5 V, S = VIH, f = 2 MHz,
Q = open
VCC = 2.5 V, S = VSS, C = VSS
ORG = VSS or VCC
pin7 = VCC, VSS or Hi-Z
,
ICC1
Supply current (Standby)
Input low voltage (D, C, S)
,
5
µA
VIL
VIH
–0.45 0.2 VCC
0.7 VCC VCC + 1
V
V
Input high voltage (D, C,
S)
V
CC = 5 V, IOL = 2.1 mA
0.4
0.2
V
V
V
V
VOL
Output low voltage (Q)
Output high voltage (Q)
VCC = 2.5 V, IOL = 100 µA
VCC = 5 V, IOH = –400 µA
VCC = 2.5 V, IOH = –100 µA
0.8 VCC
VOH
VCC–0.2
Table 16. DC characteristics (M93Cx6-R)
Symbol
Parameter
Test condition
Min.(1) Max. (1) Unit
ILI
Input leakage current
Output leakage current
0V ≤ VIN ≤ VCC
±2.5
±2.5
µA
µA
ILO
0V ≤ VOUT ≤ VCC, Q in Hi-Z
V
CC = 5 V, S = VIH, f = 2 MHz,
Q = open
2
1
mA
mA
Supply current (CMOS
inputs)
ICC
VCC = 1.8 V, S = VIH, f = 1 MHz,
Q = open
V
CC = 1.8 V, S = VSS, C = VSS
,
ICC1
Supply current (Standby)
Input low voltage (D, C, S)
ORG = VSS or VCC
pin7 = VCC, VSS or Hi-Z
,
2
µA
VIL
–0.45
0.2 VCC
V
V
Input high voltage (D, C,
S)
VIH
0.8 VCC VCC + 1
VOL
VOH
Output low voltage (Q)
Output high voltage (Q)
VCC = 1.8 V, IOL = 100 µA
VCC = 1.8 V, IOH = –100 µA
0.2
V
V
VCC–0.2
1. This product is under development. For more information, please contact your nearest ST
sales office.
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DC and AC parameters
Table 17. AC characteristics (M93Cx6, device grade 6)
Test conditions specified in Table 8 and Table 11
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSK
Clock frequency
D.C.
50
2
MHz
ns
tSLCH
Chip Select low to Clock high
Chip Select setup time
M93C46, M93C56, M93C66
50
50
ns
ns
tSHCH
tCSS
Chip Select setup time
M93C76, M93C86
(1)
tSLSH
tCS
tSKH
tSKL
tDIS
tDIH
tSKS
tCSH
tSV
Chip Select low to Chip Select high
Clock high time
200
200
200
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
(2)
tCHCL
(2)
tCLCH
Clock low time
tDVCH
tCHDX
tCLSH
tCLSL
tSHQV
tSLQZ
tCHQL
tCHQV
tW
Data in setup time
Data in hold time
50
Clock setup time (relative to S)
Chip Select hold time
50
0
Chip Select to READY/BUSY status
Chip Select low to output Hi-Z
Delay to output low
200
100
200
200
5
tDF
tPD0
tPD1
tWP
Delay to output valid
Erase or Write cycle time
1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive
instruction cycles.
2. tCHCL + tCLCH ≥ 1 / fC.
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DC and AC parameters
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Table 18. AC characteristics (M93Cx6-W, device grade 6)
Test conditions specified in Table 9 and Table 12
Symbol
Alt.
Parameter
Clock frequency
Min.
Max.
Unit
fC
fSK
D.C.
50
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
Chip Select low to Clock high
Chip Select setup time
Chip Select low to Chip Select high
Clock high time
tCSS
tCS
50
(1)
tSLSH
200
200
200
50
(2)
tCHCL
tSKH
tSKL
tDIS
tDIH
tSKS
tCSH
tSV
(2)
tCLCH
Clock low time
tDVCH
tCHDX
tCLSH
tCLSL
tSHQV
tSLQZ
tCHQL
tCHQV
tW
Data in setup time
Data in hold time
50
Clock setup time (relative to S)
Chip Select hold time
50
0
Chip Select to READY/BUSY status
Chip Select low to output Hi-Z
Delay to output low
200
100
200
200
5
tDF
tPD0
tPD1
tWP
Delay to output valid
Erase or Write cycle time
1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive
instruction cycles.
2. tCHCL + tCLCH ≥ 1 / fC.
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DC and AC parameters
Table 19. AC characteristics (M93Cx6-R)
Test conditions specified in Table 10 and Table 12
Symbol
Alt.
Parameter
Min.(1)
Max.(1)
Unit
fC
fSK
Clock frequency
D.C.
250
50
1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
Chip Select low to Clock high
Chip Select setup time
Chip Select low to Chip Select high
Clock high time
tCSS
tCS
(2)
tSLSH
250
250
250
100
100
100
0
(3)
tCHCL
tSKH
tSKL
tDIS
tDIH
tSKS
tCSH
tSV
(3)
tCLCH
Clock low time
tDVCH
tCHDX
tCLSH
tCLSL
tSHQV
tSLQZ
tCHQL
tCHQV
tW
Data in setup time
Data in hold time
Clock setup time (relative to S)
Chip Select hold time
Chip Select to READY/BUSY status
Chip Select low to output Hi-Z
Delay to output low
400
200
400
400
10
tDF
tPD0
tPD1
tWP
Delay to output valid
Erase or Write cycle time
1. This product is under development. For more information, please contact your nearest ST
sales office.
2. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive
instruction cycles.
3. tCHCL + tCLCH ≥ 1 / fC.
Figure 9. Synchronous timing (start and op-code input)
tCLSH
tCHCL
C
S
D
tSHCH
tCLCH
tDVCH
START
tCHDX
OP CODE
OP CODE
START
OP CODE INPUT
AI01428
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DC and AC parameters
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Figure 10. Synchronous timing (Read or Write)
C
S
tCLSL
tDVCH
tCHDX
tCHQV
tSLSH
A0
D
Q
An
tSLQZ
tCHQL
Hi-Z
Q15/Q7
Q0
ADDRESS INPUT
DATA OUTPUT
AI00820C
Figure 11. Synchronous timing (Read or Write)
tSLCH
C
S
D
Q
tCLSL
tDVCH
tCHDX
A0/D0
tSLSH
An
tSHQV
BUSY
tSLQZ
READY
Hi-Z
tW
ADDRESS/DATA INPUT
WRITE CYCLE
AI01429
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Package mechanical data
11
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark .
Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
1. Drawing is not to scale.
Table 20. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
-
-
5.33
-
-
-
0.2098
-
-
0.38
2.92
0.36
1.14
0.2
9.02
7.62
6.1
-
-
0.015
0.115
0.0142
0.0449
0.0079
0.3551
0.3
3.3
4.95
0.56
1.78
0.36
10.16
8.26
7.11
-
0.1299
0.0181
0.0598
0.0098
0.365
0.3098
0.25
0.1949
0.022
0.0701
0.0142
0.4
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
-
b2
c
D
E
0.3252
0.2799
-
E1
e
0.2402
-
0.1
eA
eB
L
-
-
0.3
-
-
-
10.92
3.81
-
-
0.4299
0.15
3.3
2.92
0.1299
0.115
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 21. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
-
-
1.75
0.25
-
-
-
0.0689
0.0098
-
-
0.1
1.25
0.28
0.17
-
-
0.0039
0.0492
0.011
0.0067
-
-
-
-
0.48
0.23
0.1
5
-
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
-
-
ccc
D
-
4.9
6
-
4.8
5.8
3.8
-
0.1929
0.2362
0.1535
0.05
-
0.189
0.2283
0.1496
-
E
6.2
4
E1
e
3.9
1.27
-
-
h
0.25
0°
0.5
8°
0.0098
0°
0.0197
8°
k
-
-
L
-
0.4
-
1.27
-
-
0.0157
-
0.05
L1
1.04
0.0409
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
Figure 14. UFDFPN8 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline
e
b
D
L1
L3
Pin 1
E2
K
E
L
A
D2
eee
A1
1. Drawing is not to scale.
ZW_MEeV2
2. The central pad (area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed
to be connected to any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 22. UFDFPN8 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.550
0.450
0.000
0.200
1.900
1.200
2.900
1.200
-
0.600
0.050
0.300
2.100
1.600
3.100
1.600
-
0.0217
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0472
-
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
0.0630
-
A1
0.020
0.0008
b
0.250
0.0098
D
2.000
0.0787
D2 (rev MC)
-
-
E
3.000
0.1181
E2 (rev MC)
-
-
e
0.500
0.0197
K (rev MC)
-
-
-
-
-
0.300
0.300
-
-
-
-
-
-
-
0.0118
0.0118
-
-
L
L1
0.500
0.150
-
0.0197
0.0059
-
L3
0.300
0.080
0.0118
0.0031
eee(2)
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle
from measuring.
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Package mechanical data
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 23. TSSOP8 – 8 lead thin shrink small outline, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
-
-
0.05
0.8
0.19
0.09
-
1.2
0.15
1.05
0.3
0.2
0.1
3.1
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.122
-
A1
-
1
-
0.002
0.0315
0.0075
0.0035
-
A2
0.0394
-
b
-
c
-
-
CP
-
-
D
3
2.9
-
0.1181
0.0256
0.252
0.1732
0.0236
0.0394
-
0.1142
-
e
0.65
6.4
4.4
0.6
1
E
6.2
4.3
0.45
-
6.6
4.5
0.75
-
0.2441
0.1693
0.0177
-
0.2598
0.1772
0.0295
-
E1
L
L1
α
-
0°
8°
0°
8°
N (pin number)
8
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
Part numbering
12
Part numbering
Table 24. Ordering information scheme
M93C86
Example:
–
W MN 6
T
P
Device type
M93 = MICROWIRE serial EEPROM
Device function
86 = 16 Kbit (2048 x 8)
76 = 8 Kbit (1024 x 8)
66 = 4 Kbit (512 x 8)
56 = 2 Kbit (256 x 8)
46 = 1 Kbit (128 x 8)
Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
Package
BN = PDIP8
MN = SO8 (150 mils width)
MC = UFDFPN8 2 x 3 mm (MLP8)
DW = TSSOP8 (169 mils width)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Packing
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
DocID4997 Rev 13
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Revision history
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
13
Revision history
Table 25. Document revision history
Changes
Date
Revision
Modified footnote in Table 14 and Table 15 on page 23
Updated Figure 14: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual
flat package no lead 2 x 3 mm, outline and Table 22: UFDFPN8 (MLP8)
8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data
01-Apr-2010
9
Updated Figure 31: Available M93C66-x products (package, voltage
range, temperature grade) UFDFPN option.
29-Apr-2010
10
Updated Table 7: Absolute maximum ratings, MLP8 package data in
Section 12: Package mechanical data and process data in Section 9:
Clock pulse counter.
Deleted Table 29: Available M93C46-x products (package, voltage
range, temperature grade), Table 30: Available M93C56-x products
(package, voltage range, temperature grade), Table 31: Available
M93C66-x products (package, voltage range, temperature grade),
Table 32: Available M93C76-x products (package, voltage range,
temperature grade) and Table 33: Available M93C86-x products
(package, voltage range, temperature grade).
12-Apr-2011
11
Updated Table 1: Device summary and Table 8: Operating conditions
(M93Cx6).
05-Oct-2011
12
Modified footnote 2 in Table 7.
Document reformatted.
Updated:
– Part number names
– Table 1: Device summary and package figure on cover page
– Section 1: Description
– Introductory paragraph in Section 9: Maximum rating
– Note (2) under Table 7: Absolute maximum ratings
– Table 8: Operating conditions (M93Cx6) and Table 9: Operating
conditions (M93Cx6-W)
– Introductory paragraph in Section 11: Package mechanical data
– Figure 14: UFDFPN8 8-lead ultra thin fine pitch dual flat package no
lead 2 x 3 mm, outline and Table 22: UFDFPN8 8-lead ultra thin fine
pitch dual flat package no lead 2 x 3 mm, data
23-Apr-2013
13
– Table 24: Ordering information scheme
Renamed:
– Figure 2: 8-pin package connections (top view)
– Table 17: AC characteristics (M93Cx6, device grade 6)
Deleted:
– Section: Common I/O operation
– Table: DC characteristics (M93Cx6, device grade 3), Table: DC
characteristics (M93Cx6-W, device grade 3), and Table: AC
characteristics (M93Cx6-W, device grade 3)
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DocID4997 Rev 13
M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx
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