M93S66-WDW5 [STMICROELECTRONICS]
IC,SERIAL EEPROM,256X16,CMOS,TSSOP,8PIN,PLASTIC;
| 型号： | M93S66-WDW5 |
| 厂家： | 
ST |
| 描述： | IC,SERIAL EEPROM,256X16,CMOS,TSSOP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总23页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M93S66, M93S56, M93S46
4K/2K/1K (x16) Serial Microwire Bus EEPROM
with Block Protection
INDUSTRY STANDARD MICROWIRE BUS
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SINGLE ORGANIZATION by WORD (x16)
WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
8
8
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
1
1
READY/BUSY SIGNAL DURING
PROGRAMMING
SO8 (MN)
150mil Width
PSDIP8 (BN)
0.25mm Frame
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for M93Sx6 version
– 2.5V to 5.5V for M93Sx6-W version
– 1.8V to 3.6V for M93Sx6-R version
USER DEFINED WRITE PROTECTED AREA
PAGE WRITE MODE (4 words)
8
1
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
TSSOP8 (DW)
169mil Width
ENHANCED ESD and LATCH-UP
PERFORMANCES
Figure 1. Logic Diagram
DESCRIPTION
This M93S46/S56/S66 specification covers a
range of 4K/2K/1K bit serial EEPROM products
respectively. In this text, products are referred to as
M93Sx6. The M93Sx6 is an Electrically Erasable
Programmable Memory (EEPROM) fabricated with
STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology.
V
CC
D
C
Q
Table 1. Signal Names
M93Sx6
S
Chip Select Input
Serial Data Input
Serial Data Output
Serial Clock
S
D
PRE
W
Q
C
PRE
W
Protect Enable
Write Enable
V
SS
AI02020
VCC
VSS
Supply Voltage
Ground
February 1999
1/23
M93S66, M93S56, M93S46
Figure 2A. DIP Pin Connections
Figure 2B. SO and TSSOP Pin Connections
M93Sx6
M93Sx6
S
C
D
Q
1
2
3
4
8
V
CC
PRE
S
C
D
Q
1
2
3
4
8
V
CC
PRE
7
6
7
6
W
W
5
V
5
V
SS
SS
AI02021
AI02022
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
–40 to 125
–65 to 150
°C
TSTG
Storage Temperature
°C
°C
TLEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
VIO
Input or Output Voltages (Q = VOH or Hi-Z)
Supply Voltage
–0.3 to VCC +0.5
–0.3 to 6.5
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
4000
500
V
V
VESD
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d)
Write, Write All and instructions used to set the
memory protection. A Read instruction loads the
address of the first word to be read into an internal
address pointer. The data contained at this address
is then clocked out serially. The address pointer is
automatically incremented after the data is output
and, if the Chip Select input (S) is held High, the
M93Sx6 can output a sequential stream of data
words. In this way, the memory can be read as a
data stream from 16 to 4096 bits (for the M93S66),
or continuously as the address counter automat-
ically rolls over to ’00’ when the highest address is
reached.
The M93Sx6 memory is accessed through a serial
input (D) and output (Q) using the MICROWIRE
bus protocol. The M93Sx6 is specified at 5V ±10%,
the M93Sx6-W specified at 2.5V to 5.5V and the
M93Sx6-R specified at 1.8V to 3.6V.
The M93S66/S56/S46 memory is divided into
256/128/64 x16 bit words respectively. These
memory devices are available in both PSDIP8,
SO8 and TSSOP8 packages.
The M93Sx6 memory is accessed by a set of
instructions which includes Read, Write, Page
2/23
M93S66, M93S56, M93S46
Table 3. AC Measurement Conditions
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages (M93Sxx)
0.4V to 2.4V
0.2VCC to 0.8VCC
1.0V to 2.0V
0.8V to 2.0V
0.3VCC to 0.7VCC
CL = 100pF
Input Pulse Voltages (M93Sxx-W, M93Sxx-R)
Input Timing Reference Voltages (M93Sxx)
Output Timing Reference Voltages (M93Sxx)
Input and Output Timing Reference Voltages (M93Sxx-W, M93Sxx-R)
Output Load
Note that Output Hi-Z is defined as the point where data is no longer driven.
Table 4. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
5
Unit
pF
COUT
VOUT = 0V
5
pF
Note: 1. Sampled only, not 100% tested.
Within the time required by a programming cycle
(tW), up to 4 words may be written with help of the
Page Write instruction. the whole memory may also
be erased, or set to a predetermined pattern, by
using the Write All instruction.
Figure 3. AC Testing Input Output Waveforms
Within the memory, an user defined area may be
protected against further Write instructions. The
size of this area is defined by the content of a
Protect Register, located outside of the memory
array. As a final protection step, data may be per-
manently protected by programming a One Time
Programming bit (OTP bit) which locks the Protect
Register content.
M93SXX
2.4V
2V
1V
2.0V
0.8V
0.4V
INPUT
OUTPUT
M93SXX-W & M93SXX-R
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruc-
tion. The Write instruction writes 16 bits at one time
into one of the 256/128/64 words of the
M93S46/S56/S66 respectively, the Page Write in-
struction writes up to 4 words of 16 bits to sequen-
tial locations, assuming in both cases that all
addresses are outside the Write Protected area.
0.8V
CC
CC
0.7V
0.3V
CC
CC
0.2V
AI02791
After the start of the programming cycle, a
Ready/Busy signal is available on the Data output
(Q) when Chip Select (S) is driven High.
when the Supply is too low. The design of the
M93Sx6 and the High Endurance CMOS technol-
ogy used for its fabrication give an Erase/Write
cycle Endurance of 1,000,000 cycles and a data
retention of 40 years.
An internal feature of the M93Sx6 provides Power-
on Data Protection by inhibiting any operation
3/23
M93S66, M93S56, M93S46
Table 5A. DC Characteristics for M93Sx6
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±2.5
±2.5
1.5
Unit
µA
ILO
0V ≤ VOUT ≤ VCC, Q in Hi-Z
VCC = 5V, S = VIH, f = 1 MHz
µA
ICC
mA
V
CC = 5V, S = VSS, C = VSS,
ICC1
VIL
Supply Current (Standby)
50
µA
V
W = VSS or VCC, PRE = VSS or VCC
Input Low Voltage
(D, C, S, W, PRE)
–0.3
2
0.8
Input High Voltage
(D, C, S, W, PRE)
VIH
V
CC + 1
V
VOL
VOH
Output Low Voltage (Q)
Output High Voltage (Q)
VCC = 5V, IOL = 2.1mA
0.4
V
V
VCC = 5V, IOH = –400µA
2.4
Table 5B. DC Characteristics for M93Sx6
(TA = –40 to 125°C; VCC = 4.5V to 5.5V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±2.5
±2.5
1.5
Unit
µA
ILO
0V ≤ VOUT ≤ VCC, Q in Hi-Z
VCC = 5V, S = VIH, f = 1 MHz
µA
ICC
mA
V
CC = 5V, S = VSS, C = VSS,
ICC1
VIL
Supply Current (Standby)
50
µA
V
W = VSS or VCC, PRE = VSS or VCC
Input Low Voltage
(D, C, S, W, PRE)
–0.3
2
0.8
Input High Voltage
(D, C, S, W, PRE)
VIH
VCC + 1
0.4
V
VOL
VOH
Output Low Voltage (Q)
Output High Voltage (Q)
VCC = 5V, IOL = 2.1mA
V
V
VCC = 5V, IOH = –400µA
2.4
4/23
M93S66, M93S56, M93S46
Table 5C. DC Characteristics for M93Sx6-W
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.5V to 5.5V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±2.5
±2.5
1.5
Unit
µA
ILO
0V ≤ VOUT ≤ VCC, Q in Hi-Z
VCC = 5V, S = VIH, f = 1 MHz
µA
mA
mA
ICC
Supply Current (CMOS Inputs)
Supply Current (Standby)
V
CC = 2.5V, S = VIH, f = 1 MHz
1
V
CC = 2.5V, S = VSS, C = VSS
W = VSS or VCC, PRE = VSS or VCC
,
ICC1
VIL
10
µA
V
Input Low Voltage
(D, C, S, W, PRE)
–0.3
0.2 VCC
VCC + 1
Input High Voltage
(D, C, S, W, PRE)
VIH
0.7 VCC
V
VCC = 5V, IOL = 2.1mA
CC = 2.5V, IOL = 100µA
VCC = 5V, IOH = –400µA
CC = 2.5V, IOH = –100µA
0.4
0.2
V
V
V
V
VOL
Output Low Voltage (Q)
Output High Voltage (Q)
V
2.4
VOH
V
VCC – 0.2
Table 5D. DC Characteristics for M93Sx6-R (1)
(TA = 0 to 70°C or –20 to 85°C; VCC = 1.8V to3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±2.5
±2.5
1.5
Unit
µA
ILO
0V ≤ VOUT ≤ VCC, Q in Hi-Z
VCC = 3.6V, S = VIH, f = 1 MHz
µA
mA
mA
ICC
Supply Current (CMOS Inputs)
Supply Current (Standby)
V
CC = 1.8V, S = VIH, f = 1 MHz
CC = 1.8V, S = VSS, C = VSS
1
V
,
ICC1
VIL
5
µA
V
W = VSS or VCC, PRE = VSS or VCC
Input Low Voltage
(D, C, S, W, PRE)
–0.3
0.2 VCC
Input High Voltage
(D, C, S, W, PRE)
VIH
0.8 VCC
VCC + 1
0.2
V
VOL
VOH
Output Low Voltage (Q)
Output High Voltage (Q)
VCC = 1.8V, IOL = 100µA
VCC = 1.8V, IOH = –100µA
V
V
VCC – 0.2
Note: 1. This is preliminary data.
5/23
M93S66, M93S56, M93S46
Table 6A. AC Characteristics
M93S66/56/46
CC = 4.5V to 5.5V,
V
VCC = 4.5V to 5.5V,
TA = –40 to 125 C
Symbol
Alt
Parameter
Unit
TA = 0 to 70 C,
°
°
TA = –40 to 85 C
°
Min
50
Max
Min
50
Max
tPRVCH
tWVCH
tSHCH
tCLSH
tDVCH
tCHDX
tCHQL
tCHQV
tPRES
tPES
tCSS
tSKS
tDIS
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Chip Select Set-up Time
Clock Set-up Time (relative to S)
Data In Set-up Time
ns
ns
ns
ns
ns
ns
ns
ns
50
50
50
50
100
100
100
100
100
100
tDIH
Data In Hold Time
tPD0
tPD1
Delay to Output Low
400
400
400
400
Delay to Output Valid
Clock Low to Protect Enable
Transition
tCLPRX
tSLWX
tPREH
0
0
ns
ns
Chip Select Low to Write Enable
Transition
tPEH
tCSH
250
250
tCLSL
tSLCH
Chip Select Hold Time
0
0
ns
ns
Chip Select Low to Clock High
Chip Select Low to Chip Select High
Chip Select to Ready/Busy Status
Chip Select Low to Output Hi-Z
Clock High Time
250
250
250
250
(1)
tSLSH
tCS
tSV
ns
tSHQV
tSLQZ
400
200
400
200
ns
tDF
ns
(2)
tCHCL
tSKH
tSKL
tWP
fSK
250
250
250
250
ns
(2)
tCLCH
Clock Low Time
ns
tW
fC
Erase/Write Cycle time
Clock Frequency
10
1
10
1
ms
MHz
0
0
Notes: 1. Chip Select must be brought low for a minimum of tSLSH between consecutive instructions cycles.
2. The Clock frequency specification calls for a minimum clock period of 1/fC, therefore the sum of the timings tCHCL+tCLCH
must be greater or equal to 1/fC.
6/23
M93S66, M93S56, M93S46
Table 6B. AC Characteristics
M93S66/56/46
CC = 2.5V to 5.5V,
CC = 1.8V to 3.6V, (3)
V
V
Symbol
Alt
Parameter
Unit
T = 0 to 70 C, TA = 0 to 70 C
°
°
A
T = –40 to 85 C
A
T = –20 to 85 C
°
A
°
Min
50
Max
Min
50
Max
tPRVCH
tWVCH
tSHCH
tCLSH
tDVCH
tCHDX
tCHQL
tCHQV
tPRES
tPES
tCSS
tSKS
tDIS
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Chip Select Set-up Time
Clock Set-up Time (relative to S)
Data In Set-up Time
ns
ns
ns
ns
ns
ns
ns
ns
50
50
100
100
100
100
200
100
100
200
tDIH
Data In Hold Time
tPD0
tPD1
Delay to Output Low
400
400
700
700
Delay to Output Valid
Clock Low to Protect Enable
Transition
tCLPRX
tSLWX
tPREH
0
0
ns
ns
Chip Select Low to Write Enable
Transition
tPEH
tCSH
250
250
tCLSL
tSLCH
Chip Select Hold Time
0
0
ns
ns
Chip Select Low to Clock High
Chip Select Low to Chip Select High
Chip Select to Ready/Busy Status
Chip Select Low to Output Hi-Z
Clock High Time
250
250
250
1000
(1)
tSLSH
tCS
tSV
ns
tSHQV
tSLQZ
400
200
700
200
ns
tDF
ns
(2)
tCHCL
tSKH
tSKL
tWP
fSK
350
250
800
800
ns
(2)
tCLCH
Clock Low Time
ns
tW
fC
Erase/Write Cycle time
Clock Frequency
10
1
10
ms
MHz
0
0
0.5
Notes: 1. Chip Select must be brought low for a minimum of tSLSH between consecutive instructions cycles.
2. The Clock frequency specification calls for a minimum clock period of 1/fC, therefore the sum of the timings tCHCL+tCLCH
must be greater or equal to 1/fC.
3. This is preliminary data.
7/23
M93S66, M93S56, M93S46
Figure 4. Synchronous Timing, Start and Op-Code Input
PRE
tPRVCH
W
tWVCH
tCHCL
C
tCLSH
tSHCH
tDVCH
tCLCH
S
D
tCHDX
OP CODE
START
OP CODE
OP CODE INPUT
START
AI02025
POWER-ON DATA PROTECTION
– When VCC reaches its functional value, the de-
vice is properly reset (in the Write Disable
mode) and is ready to decode and execute an
incoming instruction.
For the M93Sx6 specified at 5V, the POR threshold
voltage is around 3V.
In order to prevent data corruption and inadvertent
write operations during power-up and power-down,
a Power On Reset (POR) circuit resets all internal
programming circuitry and sets the device in the
Write Disable mode.
– At Power-up and Power-down, the device
must NOT be selected (that is, the S input
must be driven low) until the supply voltage
reaches the operating value Vcc specified in
the AC and DC tables.
For all the other M93Sx6 specified at low VCC (with
-W and -R VCC range options), the POR threshold
voltage is around 1.5V.
8/23
M93S66, M93S56, M93S46
Figure 5. Synchronous Timing, Read or Write
C
S
tCLSL
tSLSH
tDVCH
tCHDX
tCHQV
A0
D
Q
An
tSLQZ
Q0
tCHQL
Hi-Z
Q15
ADDRESS INPUT
DATA OUTPUT
AI002026
PRE
W
tCLPRX
tSLWX
C
tSLCH
tCLSL
S
tSLSH
tDVCH
tCHDX
A0/D0
An
D
Q
tSHQV
BUSY
tW
WRITE CYCLE
tSLQZ
Hi-Z
READY
ADDRESS/DATA INPUT
AI02027
9/23
M93S66, M93S56, M93S46
INSTRUCTIONS
The M93S66/S56/S46 have eleven instructions, as
shown in Table 7. Each instruction is preceded by
the rising edge of the signal applied on the Chip
Select (S) input (assuming that the clock C is low).
After the device is selected, the internal logic waits
for the start bit, which define the begining of the
instruction bit stream. The startbit is the first’1’read
on D input during the rising edge of the clock C.
Following the start bit, the op-codes of the instruc-
tions are made up of the 2 following bits. Notice that
some instructions use only these first two bits,
others use also the first two bits of the address to
define the op-code. The op-code is then followed
by the address of the word to be accessed.
For the M93S46, the address is made up of 6 bits
(See Table 7a). For the M93S56 and M93S66, the
address is made up of 8 bits (See Table 7b).
The M93Sx6 is fabricated in CMOS technology and
is therefore able to run from zero Hz (static input
signals) up to the maximum ratings (specified in
Table 6).
Table 7A. Instruction Set for the M93S46
Start Op-
Req.
Clock
Cycles
Additional
Information
Instr.
Description
W
PRE
Address (1)
Data
Bit Code
Read Data from
Memory
READ
X
’0’
’1’
’1’
10
01
A5-A0
Q15-Q0
Write is executed
if the address is
not inside the
Write Data to
Memory
WRITE
’1’
’0’
A5-A0
D15-D0
25
Protected area
Write is executed
if all the N
addresses are not
inside the
Page Write to
Memory
N x
9 + N
x 16
PAWRITE
WRALL
’1’
’1’
’0’
’0’
’1’
’1’
11
00
A5-A0
D15-D0
Protected area
Write all data if
the Protect
Register is cleared
Write All
Memory
01XXXX
D15-D0
25
WEN
WDS
Write Enable
Write Disable
’1’
X
’0’
’0’
’1’
’1’
00
00
11XXXX
00XXXX
9
9
Data Output =
Protect Register
content + Protect
Flag bit
Protect
Register Read
Q5-Q0
+ Flag
PRREAD
X
’1’
’1’
10
XXXXXX
Data above
specified address
A5-A0 are
Protect
Register Write
PRWRITE
PRCLEAR
’1’
’1’
’1’
’1’
’1’
’1’
01
11
A5-A0
111111
9
9
protected
Protect Flag is
also cleared
(cleared Flag = 1)
Protect
Register Clear
Protect
Register
Enable
PREN
PRDS
’1’
’1’
’1’
’1’
’1’
’1’
00
00
11XXXX
000000
9
9
Protect
Register Disable
OTP bit is set
permanently
Note: 1. X = don’t care bit.
10/23
M93S66, M93S56, M93S46
Table 7B. Instruction Set for the M93S56 and M93S66
Start Op-
Req.
Additional
Information
Instr.
Description
W
PRE
Address (1,2)
Data
Clock
Bit Code
Cycles
Read Data from
Memory
READ
X
’0’
’1’
’1’
10
01
A7-A0
Q15-Q0
D15-D0
Write is executed
if the address is
not inside the
Write Data to
Memory
WRITE
’1’
’0’
A7-A0
27
Protected area
Write is executed
if all the N
addresses are not
inside the
Protected area
Page Write to
Memory
N x
D15-D0
11 + N
x 16
PAWRITE
WRALL
’1’
’1’
’0’
’0’
’1’
’1’
11
00
A7-A0
Write all data if
the Protect
Register is cleared
Write All
Memory
01XXXXXX
D15-D0
27
WEN
WDS
Write Enable
Write Disable
’1’
X
’0’
’0’
’1’
’1’
00
00
11XXXXXX
00XXXXXX
11
11
Data Output =
Protect Register
content + Protect
Flag bit
Protect
Register Read
Q7-Q0
+ Flag
PRREAD
X
’1’
’1’
10
XXXXXXXX
Data above
specified address
A7-A0 are
Protect
Register Write
PRWRITE
PRCLEAR
’1’
’1’
’1’
’1’
’1’
’1’
01
11
A7-A0
11
11
protected
Protect Flag is
also cleared
(cleared Flag = 1)
Protect
Register Clear
11111111
Protect
Register
Enable
PREN
PRDS
’1’
’1’
’1’
’1’
’1’
’1’
00
00
11XXXXXX
00000000
11
11
Protect
Register Disable
OTP bit is set
permanently
Notes: 1. X = don’t care bit.
2. Address bit A7 is not decoded by the M93S56.
11/23
M93S66, M93S56, M93S46
Read
Page Write
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
into an outputshift register. Adummy ’0’bit isoutput
first followed by the 16 bit word with the MSB first.
Output data changes are triggered by the Low to
High transition of the Clock (C). The M93Sx6 will
automatically increment the address and will clock
out the next word as long as the Chip Select input
(S) is held High. In this case the dummy ’0’ bit is
NOT output between words and a continuous
stream of data can be read.
A Page Write instruction (PAWRITE) contains the
first address to be written followed by up to 4 data
words. The Write Enable signal (W) must be held
High during the PAWRITE instruction. Input ad-
dress and data are sampled on the Low to High
transition of the clock. After the receipt of each data
word, bits A1-A0 of the internal address register are
incremented, the high order bits (Ax-A2) remaining
unchanged. Users must take care by software to
ensure that the last word address has the same
upper order address bits as the initial address
transmitted toavoidaddressroll-over. Afterthe LSB
of the last data word, Chip Select (S) must be
brought Low before the next rising edge of the
Clock (C) in order to start the self-timed program-
ming cycle. This is really important as, if S is
brought low before or after this specific frame win-
dow, the addressed locations will not be pro-
grammed. The Page Write operation will not be
performed if any of the 4 words is addressing the
protected area. If the M93Sx6 is still performing the
programming cycle, the Busy signal (Q = 0) will be
returned if the Chip Select input (S) is driven high,
and the M93Sx6 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the M93Sx6 is ready to receive a new instruction.
Write Enable and Write Disable
The Write Enable instruction (WEN) authorizes the
following Write instructions to be executed. The
Write Disable instruction (WDS) disables the exe-
cution of the following Write instructions and the
internal programming cycle cannot run.
When power is first applied, the M93Sx6 is in Write
Disable mode and all Write instructions are inhib-
ited. When the WEN instruction is executed, Write
instructions remain enabled until a Write Disable
instruction (WDS) is executed or VCC falls below
the Power-On Reset threshold Voltage.
To protect the memory contents from accidental
corruption, it is advisable to issue the WDS instruc-
tion after every write cycle. The READ instruction
is not affected by the WEN or WDS instructions.
Write All
The Write All instruction (WRALL) is valid only after
the Protect Register has been cleared by executing
a PRCLEAR (Protect Register Clear) instruction.
The Write All instruction simultaneously writes the
whole memory with the same data word included
in the instruction. The Write Enable signal (W) must
be held High before and during the Write All instruc-
tion. Input address and data are sampled on the
Low to High transition of the clock. If the M93Sx6
is still performing the write cycle, the Busy signal
(Q = 0) will be returned if the Chip Select input (S)
is driven high after the tSLSH delay, and the M93Sx6
will ignore any data on the bus. When the write
cycle is completed, the Ready signal (Q = 1) will
indicate (if S is driven high) that the M93Sx6 is
ready to receive a new instruction.
Write
The Write instruction (WRITE) is composed of the
Start bit plus the Op-Code followed by the address
and the 16 data bits to be written. The Write Enable
signal (W) must be held high during the Write
instruction. Data input (D) is sampled on the Low
to High transition of the clock. After the last data bit
has been sampled, Chip Select (S) must be
brought Low before the next rising edge ofthe clock
(C) in order to start the self-timed programming
cycle. This is really important as, if S is brought low
before or after this specific frame window, the
addressed location will notbe programmed, provid-
ing that the address in NOT in the protected area.
READY/BUSY Status
If the M93Sx6 is still performing the write cycle, the
Busy signal (Q = 0) will be returned if the Chip
Select input (S) is driven high after the tSLSH delay,
and the M93Sx6 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the M93Sx6 is ready to receive a new instruction.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle).
During every programming cycle (after a WRITE,
WRALL or PAWRITE instruction) the Data Output
(Q) indicates the Ready/Busy status of the memory
when the Chip Select is driven High. Once the
M93Sx6 is Ready, the Data Output is set to ’1’ until
a new start bit is decoded or the Chip Select is
brought Low.
12/23
M93S66, M93S56, M93S46
MEMORY WRITE PROTECTION AND PROTECT
REGISTER
(W) input pins must be held High during the instruc-
tion execution.
The M93Sx6 offers a Protect Register containing
the bottom address of the memory area which has
to be protected against write instructions. In addi-
tion to this Protect Register, two flag bits are used
to indicate the Protect Register status: the Protect
Flag enabling/disabling the memory protection
throught the Protect Register and the OTP bit
which, when set, disables access to the Protect
Register and thus prevents any further modifica-
tions of this Protect Register value. The content of
the Protect Register is defined when using the
PRWRITE instruction, it may be read when using
the PRREAD instruction. A specific instruction
PREN (Protect Register Enable) allows the user to
execute the protect instructions PRCLEAR,
PRWRITE and PRDS. this PREN instruction being
used together with the signals applied on the input
pins PRE (Protect Register Enable) and W (Write
Enable).
Protect Register Clear
The Protect Register Clear instruction (PRCLEAR)
clears the address stored in the Protect Register to
all 1’s, and thus enables the execution of WRITE
and WRALL instructions. The Protect Register
Clear execution clears the Protect Flag to ’1’. Both
the Protect Enable (PRE) and Write Enable (W)
input pins must be driven High during the instruc-
tion execution.
Note: A PREN instruction must immediately pre-
cede the PRCLEAR instruction.
Protect Register Write
The Protect Register Write instruction (PRWRITE)
is used to write into the Protect Register the ad-
dress of the first word to be protected. After the
PRWRITE instruction execution, all memory loca-
tions equal to and above the specified address, are
protected from writing. The Protect Flag bit is set to
’0’, it can be read with Protect Register Read
instruction. Both the Protect Enable (PRE) and
Write Enable (W) input pins must be driven High
during the instruction execution.
Accessing the Protect Register is done by execut-
ing the following sequence:
– WEN: execute the Write Enable instruction,
– PREN: execute the PREN instruction,
Note: A PREN instruction must immediately pre-
cede the PRWRITE instruction, but it is not neces-
sary to execute first a PRCLEAR.
– PRWRITE, PRCLEAR or PRDS: the protection
then may be defined, in terms of size of the
protected area (PRWRITE, PRCLEAR) and
may be set permanently (PRDS instruction).
Protect Register Disable
Protect Register Read
The Protect Register Disable instruction sets the
One Time Programmable bit (OTP bit). The Protect
RegisterDisable instruction (PRDS) is a ONE TIME
ONLY instruction which latches the Protect Regis-
ter content, this content is therefore unalterable in
the future. Both the Protect Enable (PRE) and Write
Enable (W) input pins must be driven High during
the instruction execution. The OTP bit cannot be
directly read, it can be checked by reading the
content of the Protect Register (PRREAD instruc-
tion), then by writing this same value into the Pro-
tect Register (PRWRITE instruction): when the
OTP bit is set, the Ready/Busy status cannot ap-
pear on the Data output (Q). When the OTP bit is
not set, the Busy status appear on the Data output
(Q).
The Protect Register Read instruction (PRREAD)
outputs on the Data Output Q the content of the
Protect Register, followed by the Protect Flag bit.
The Protect Register Enable pin (PRE) must be
driven High before and during the instruction.
As in the Read instruction a dummy ’0’ bit is output
first. Since it is not possible to distinguish if the
Protect Register is cleared (all 1’s) or if it is written
with all 1’s, user must check the Protect Flag status
(and not the Protect Register content) to ascertain
the setting of the memory protection.
Protect Register Enable
The Protect Register Enable instruction (PREN) is
used to authorize the use of further PRCLEAR,
PRWRITE and PRDS instructions. The PREN
insruction does not modify the Protect Flag bit
value.
Note: A PREN instruction must immediately pre-
cede the PRDS instruction.
Note: A Write Enable (WEN) instruction must be
executed before the Protect Enable instruction.
Both the Protect Enable (PRE) and Write Enable
13/23
M93S66, M93S56, M93S46
Figure 6. READ, WRITE, WEN, WDS Sequences
READ
PRE
S
D
1 1 0 An
A0
Q
Qn
Q0
ADDR
DATA OUT
OP
CODE
WRITE
PRE
W
S
CHECK
STATUS
D
1 0 1 An
A0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
WRITE
ENABLE
PRE
W
WRITE
DISABLE
PRE
S
S
D
1 0 0 0 0 Xn X0
D
1 0 0 1 1 Xn X0
OP
CODE
OP
CODE
AI00889D
Notes: 1. An - Xn - Qn - Dn: Refer to Table 7a for the M93S46.
2. An - Xn - Qn - Dn: Refer to Table 7b for the M93S56 and M93S66.
14/23
M93S66, M93S56, M93S46
Figure 7. PAWRITE, WRALL Sequences
PAGE
WRITE
PRE
W
S
CHECK
STATUS
D
1 1 1 An
A0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
WRITE
ALL
PRE
W
S
CHECK
STATUS
D
1 0 0 0 1 Xn X0 Dn
D0
Q
ADDR
OP
DATA IN
BUSY
READY
CODE
AI00890C
Notes: 1. An - Xn - Dn: Refer to Table 7a for the M93S46.
2. An - Xn - Dn: Refer to Table 7b for the M93S56 and M93S66.
15/23
M93S66, M93S56, M93S46
Figure 8. PRREAD, PRWRITE, PREN Sequences
Protect
Register
READ
PRE
S
D
1 1 0 Xn
X0
Q
An
A0 F
ADDR
DATA
OUT
F = Protect Flag
OP
CODE
Protect
Register
WRITE
PRE
W
S
CHECK
STATUS
D
1 0 1 An
A0
Q
ADDR
BUSY
READY
OP
CODE
Protect
Register
ENABLE
PRE
W
S
D
1 0 0 1 1 Xn X0
OP
CODE
AI00891D
Notes: 1. An - Xn - Dn: Refer to Table 7a for the M93S46.
2. An - Xn - Dn: Refer to Table 7b for the M93S56 and M93S66.
16/23
M93S66, M93S56, M93S46
Figure 9. PRCLEAR, PRDS Sequences
Protect
Register
CLEAR
PRE
W
S
CHECK
STATUS
D
1 1 1
1 1 1
Q
ADDR
BUSY
READY
OP
CODE
Protect
Register
DISABLE
PRE
W
S
CHECK
STATUS
D
1 0 0
0 0 0
Q
ADDR
BUSY
READY
OP
CODE
AI00892C
Notes: 1. An - Xn - Dn: Refer to Table 7a for the M93S46.
2. An - Xn - Dn: Refer to Table 7b for the M93S56 and M93S66.
17/23
M93S66, M93S56, M93S46
COMMON I/O OPERATION
pulses delivered by the Master (Microcontroller)
driving the M93Sx6. In such a case, a part of the
instruction is delayed by one bit (see Figure 10),
and it may induce an erroneous write of data at a
wrong address. The M93Sx6 has an on-chip
counter which counts the clock pulses from the
Start bit until the falling edge of the Chip Select
signal.
For the WRITE instructions with a M93S56 (or
M93S66), the number of clock pulses incoming to
the counter must be exactly 27 from the Start bit to
the falling edge of Chip Select signal (1 Start bit +
2 Op-code bit + 8 Address bit + 16 Data bit = 27):
if so, the M93S56 (or M93S66) executes the
WRITE instruction. If the number of clock pulses is
not equal to 27, the instruction will not be executed
(and data will not be corrupted).
The Data Output (Q) and Data Input (D) signals can
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memory with this connection, mostly to prevent
a short circuit between the last entered address bit
(A0) and the first data bit output by Q. The reader
should refer to the STMicroelectronics application
note AN394 "MICROWIRE EEPROM Common I/O
Operation".
CLOCK PULSE COUNTER
The M93Sx6 offers a functional security filtering
glitches on the clock input (C), the clock pulse
counter.
The clock pulse counter is active on WRITE,
PAWRITE, WRALL, PRWRITE and PRCLEAR in-
structions. In order to determine the exact number
of clock pulses needed for all the M93Sx6 on
WRITE instructions, refer to Tables 7a and 7b, in
the column: Requested Clock Cycles.
In a normal environment, the M93Sx6 expectes to
receive the exact amount of data on the D input
(start bit, Op-Code, Address, Data), that is the
exact amount of clock pulses on the C input. In a
noisy environment, the number of pulses received
(on the clock input C) may be greater than the clock
Figure 10. Write Sequence with One Clock Glitch
S
C
D
An
An-1
Glitch
An-2
START
"0"
"1"
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
WRITE
AI01395
18/23
M93S66, M93S56, M93S46
ORDERING INFORMATION SCHEME
Example: M93S56 – W MN
6
T
Memory Density
Operating Voltage
Package
BN PSDIP8
Temperature Range
1 (1) 0 to 70 °C
Option
66 4 Kbit
56 2 Kbit
46 1 Kbit
blank 4.5V to 5.5V
T
Tape & Reel
Packing
0.25mm Frame
W
2.5V to 5.5V
5
–20 to 85 °C
MN SO8
R (3) 1.8V to 3.6V
6
–40 to 85 °C
150mil Width
DW TSSOP8
3 (2) –40 to 125 °C
169mil Width
Notes: 1. Temperature range on request only.
2. Produced with High Reliability Certified Flow (HRCF), in VCC range 4.5V to 5.5V at 1MHz only.
3. -R version (1.8V to 3.6V) are only available in temperature ranges 5 or 1.
Devices are shipped from the factory with the memory content set at all "1’s" (FFFFh).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.
19/23
M93S66, M93S56, M93S46
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
Min
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
inches
Min
Symb
Typ
Max
5.90
–
Typ
Max
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
E1
e1
eA
eB
L
7.62
2.54
0.300
0.100
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not to scale
20/23
M93S66, M93S56, M93S46
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Drawing is not to scale
21/23
M93S66, M93S56, M93S46
TSSOP8 - 8 lead Plastic Shrink Small Outline, 169 mils body width
mm
Min
inches
Min
Symb
Typ
Max
1.10
0.15
0.95
0.30
0.20
3.10
6.50
4.50
–
Typ
Max
0.043
0.006
0.037
0.012
0.008
0.122
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
2.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.114
0.246
0.169
–
C
D
E
E1
e
L
0.65
0.026
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
8
8
CP
0.08
0.003
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Drawing is not to scale
22/23
M93S66, M93S56, M93S46
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners
STMicroelectronics GROUP OF COMPANIES
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Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
23/23
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