M95010-WBN6T [STMICROELECTRONICS]
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock; 4k位， 2Kbit和1Kbit的串行SPI总线的EEPROM采用高速时钟
| 型号： | M95010-WBN6T |
| 厂家： | 
ST |
| 描述： | 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 文件： | 总37页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95040
M95020, M95010
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
■
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
Figure 1. Packages
■
Single Supply Voltage:
–
–
–
4.5 to 5.5V for M950x0
2.5 to 5.5V for M950x0-W
1.8 to 5.5V for M950x0-R
■
High Speed
8
–
10MHz Clock Rate, 5ms Write Time
■
■
■
■
■
■
■
Status Register
1
BYTE and PAGE WRITE (up to 16 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
PDIP8 (BN)
8
Table 1. Product List
Reference
1
Part Number
M95040
SO8 (MN)
M95040
M95020
M95010
M95040-W
M95040-R
M95020
150 mil width
M95020-W
M95020-R
M95010
TSSOP8 (DW)
169 mil width
M95010-W
M95010-R
October 2004
1/37
M95040, M95020, M95010
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/37
M95040, M95020, M95010
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Write Status Register (WRSR) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Address Range Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12.Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write to Memory Array (WRITE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13.Byte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Operating Conditions (M950x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating Conditions (M950x0-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Operating Conditions (M950x0-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. DC Characteristics (M950x0, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. DC Characteristics (M950x0, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. DC Characteristics (M950x0-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. DC Characteristics (M950x0-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. DC Characteristics (M950x0-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. AC Characteristics (M950x0, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. AC Characteristics (M950x0, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. AC Characteristics (M950x0-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 21. AC Characteristics (M950x0-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 22. AC Characteristics (M950x0-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 32
3/37
M95040, M95020, M95010
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 32
Figure 20.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 33
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
33
Figure 21.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 34
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 34
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27. How to Identify Present and Previous Products by the Process Identification Letter . . . 35
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4/37
M95040, M95020, M95010
SUMMARY DESCRIPTION
The M95040 is a 4 Kbit (512 x 8) electrically eras-
able programmable memory (EEPROM), access-
ed by a high speed SPI-compatible bus. The other
members of the family (M95020 and M95010) are
identical, though proportionally smaller (2 and 1
Kbit, respectively).
Figure 3. DIP, SO and TSSOP Connections
M95xxx
Each device is accessed by a simple serial inter-
face that is SPI-compatible. The bus signals are C,
D and Q, as shown in Table 2. and Figure 2..
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD). WRITE instruc-
tions are disabled by Write Protect (W).
S
Q
1
2
3
4
8
V
CC
HOLD
7
W
6
5
C
D
V
SS
AI01790D
Figure 2. Logic Diagram
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
V
CC
Table 2. Signal Names
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
D
C
S
Q
D
Q
M95xxx
S
W
W
HOLD
HOLD
V
Supply Voltage
Ground
CC
V
SS
V
SS
AI01789C
5/37
M95040, M95020, M95010
SIGNAL DESCRIPTION
During all operations, V must be held stable and
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by Power mode. Driving Chip Select (S) Low se-
lects the device, placing it in the Active Power
mode.
CC
within the specified valid range: V (min) to
CC
V
(max).
CC
All of the input and output signals can be held High
or Low (according to voltages of V , V , V or
IH
OH
IL
V
, as specified in Table 13. to Table 17.). These
OL
signals are described next.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). This input signal is used to
control whether the memory is write protected.
When Write Protect (W) is held Low, writes to the
memory are disabled, but other operations remain
enabled. Write Protect (W) must either be driven
High or Low, but must not be left floating.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
6/37
M95040, M95020, M95010
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4. shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI03746D
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
7/37
M95040, M95020, M95010
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
–
–
CPOL=0, CPHA=0
CPOL=1, CPHA=1
–
–
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
Figure 5. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
8/37
M95040, M95020, M95010
OPERATING FEATURES
Power-up
When the power supply is turned on, V
Power mode, and the device consumption drops
to I
.
CC1
rises
CC
from V to V
.
Hold Condition
SS
CC
During this time, the Chip Select (S) must be al-
lowed to follow the V voltage. It must not be al-
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
CC
lowed to float, but should be connected to V via
CC
a suitable pull-up resistor.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on V
Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode. The device
.
CC
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
6.).
consumes I , as specified in Table 13. to Table
17..
When Chip Select (S) is High, the device is dese-
lected. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Standby
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 6. also shows what happens if the rising
and falling edges are not timed to coincide with
Serial Clock (C) being Low.
CC
Figure 6. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
AI02029D
9/37
M95040, M95020, M95010
Status Register
Data Protection and Protocol Control
Figure 7. shows the position of the Status Register
in the control logic of the device. This register con-
tains a number of control bits and status bits, as
shown in Table 3..
To help protect the device from data corruption in
noisy or poorly controlled environments, a number
of safety features have been built in to the device.
The main security measures can be summarized
as follows:
Bits b7, b6, b5 and b4 are always read as 1.
–
–
The WEL bit is reset at power-up.
WIP bit. The Write In Progress bit is a volatile
read-only bit that is automatically set and reset by
the internal logic of the device. When set to a 1, it
indicates that the memory is busy with a Write cy-
cle.
Chip Select (S) must rise after the eighth clock
count (or multiple thereof) in order to start a
non-volatile Write cycle (in the memory array
or in the Status Register).
WEL bit. The Write Enable Latch bit is a volatile
read-only bit that is set and reset by specific in-
structions. When reset to 0, no WRITE or WRSR
instructions are accepted by the device.
–
Accesses to the memory array are ignored
during the non-volatile programming cycle,
and the programming cycle continues
unaffected.
BP1, BP0 bits. The Block Protect bits are non-
volatile read-write bits. These bits define the area
of memory that is protected against the execution
of Write cycles, as summarized in Table 4..
–
Invalid Chip Select (S) and Hold (HOLD)
transitions are ignored.
For any instruction to be accepted and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches the last bit of
the instruction, and before the next rising edge of
Serial Clock (C).
For this, “the last bit of the instruction” can be the
eighth bit of the instruction code, or the eighth bit
of a data byte, depending on the instruction (ex-
cept in the case of RDSR and READ instructions).
Moreover, the "next rising edge of CLOCK" might
(or might not) be the next bus transaction for some
other device on the bus.
Table 3. Status Register Format
b7
1
b0
1
1
1
BP1 BP0 WEL WIP
Block Protect Bits
Write Enable Latch Bit
When a Write cycle is in progress, the device pro-
tects it against external interruption by ignoring
any subsequent READ, WRITE or WRSR instruc-
tion until the present cycle is complete.
Write In Progress Bit
Table 4. Write-Protected Block Size
Status Register Bits
Array Addresses Protected
Protected Block
BP1
BP0
M95040
none
M95020
none
M95010
none
0
0
1
1
0
1
0
1
none
Upper quarter
Upper half
180h - 1FFh
100h - 1FFh
000h - 1FFh
C0h - FFh
80h - FFh
00h - FFh
60h - 7Fh
40h - 7Fh
00h - 7Fh
Whole memory
10/37
M95040, M95020, M95010
MEMORY ORGANIZATION
The memory is organized as shown in Figure 7..
Figure 7. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
1 Page
X Decoder
AI01272C
11/37
M95040, M95020, M95010
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 5..
If an invalid instruction is sent (one not contained
in Table 5.), the device automatically deselects it-
self.
Table 5. Instruction Set
Instruc
Instruction
Format
Description
tion
WREN Write Enable
0000 X110
0000 X100
0000 X101
0000 X001
WRDI
RDSR
Write Disable
Read Status Register
WRSR Write Status Register
READ Read from Memory Array
WRITE Write to Memory Array
0000 A 011
8
0000 A 010
8
Note: 1. A8 = 1 for the upper half of the memory array of the
M95040, and 0 for the lower half, and is Don’t Care for
other devices.
2. X = Don’t Care.
12/37
M95040, M95020, M95010
Write Enable (WREN)
As shown in Figure 8., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
Figure 8. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI01441D
Write Disable (WRDI)
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 9., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
–
–
–
–
–
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
Write Protect (W) line being held Low.
Figure 9. Write Disable (WRDI) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03790D
13/37
M95040, M95020, M95010
Read Status Register (RDSR)
One of the major uses of this instruction is to allow
the MCU to poll the state of the Write In Progress
(WIP) bit. This is needed because the device will
not accept further WRITE or WRSR instructions
when the previous Write cycle is not yet finished.
As shown in Figure 10., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte are then shifted in, on
Serial Data Input (D). The current state of the bits
in the Status Register is shifted out, on Serial Data
Out (Q). The Read Cycle is terminated by driving
Chip Select (S) High.
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
The Status Register may be read at any time, even
during a Write cycle (whether it be to the memory
area or to the Status Register). All bits of the Sta-
tus Register remain valid, and can be read using
the RDSR instruction. However, during the current
Write cycle, the values of the non-volatile bits
(BP0, BP1) become frozen at a constant value.
The updated value of these bits becomes avail-
able when a new RDSR instruction is executed, af-
ter completion of the Write cycle. On the other
hand, the two read-only bits (Write Enable Latch
(WEL), Write In Progress (WIP)) are dynamically
updated during the on-going Write cycle.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 4.) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
Figure 10. Read Status Register (RDSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI01444D
14/37
M95040, M95020, M95010
Write Status Register (WRSR)
This instruction has no effect on bits b7, b6, b5, b4,
b1 and b0 of the Status Register.
od t (as specified in Table 18. to Table 22.), at
the end of which the Write in Progress (WIP) bit is
reset to 0.
W
The instruction is not accepted, and is not execut-
ed, under the following conditions:
As shown in Figure 11., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and data byte are then
shifted in on Serial Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High. Chip Select (S) must be driven High
after the rising edge of Serial Clock (C) that latch-
es the eighth bit of the data byte, and before the
the next rising edge of Serial Clock (C). If this con-
dition is not met, the Write Status Register
(WRSR) instruction is not executed. The self-
timed Write Cycle starts, and continues for a peri-
–
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
–
–
if a Write Cycle is already in progress
if the device has not been deselected, by Chip
Select (S) being driven High, after the eighth
bit, b0, of the data byte has been latched in
–
if Write Protect (W) is Low.
Figure 11. Write Status Register (WRSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI01445B
15/37
M95040, M95020, M95010
Read from Memory Array (READ)
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.
As shown in Figure 12., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address byte are
then shifted in, on Serial Data Input (D). For the
M95040, the most significant address bit, A8, is in-
corporated as bit b3 of the instruction byte, as
shown in Table 5.. The address is loaded into an
internal address register, and the byte of data at
that address is shifted out, on Serial Data Output
(Q).
If Chip Select (S) continues to be driven Low, an
internal bit-pointer is automatically incremented at
each clock cycle, and the corresponding data bit is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
Table 6. Address Range Bits
Device
M95040
M95020
M95010
Address Bits
A8-A0
A7-A0
A6-A0
Figure 12. Read from Memory Array (READ) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
C
Instruction
A8
Byte Address
A7 A6 A5 A4 A3 A2 A1 A0
D
Q
Data Out
High Impedance
2
1
7
6
5
4
3
0
AI01440E
Note: Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
16/37
M95040, M95020, M95010
Write to Memory Array (WRITE)
given address to the end of the same page can be
programmed in a single instruction.
If Chip Select (S) still continues to be driven Low,
the next byte of input data is shifted in, and is used
to overwrite the byte at the start of the current
page.
As shown in Figure 13., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High after the rising edge of Serial Clock
(C) that latches the last data bit, and before the
next rising edge of Serial Clock (C) occurs any-
where on the bus. In the case of Figure 13., this
occurs after the eighth bit of the data byte has
been latched in, indicating that the instruction is
being used to write a single byte. The self-timed
The instruction is not accepted, and is not execut-
ed, under the following conditions:
–
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
–
–
if a Write cycle is already in progress
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the rising edge of Serial Clock
(C) that latches the last data bit, and before
the next rising edge of Serial Clock (C) occurs
anywhere on the bus)
Write cycle starts, and continues for a period t
WC
(as specified in Table 18. to Table 22.), at the end
of which the Write in Progress (WIP) bit is reset to
0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 14., the next byte of input
data is shifted in. In this way, all the bytes from the
–
if Write Protect (W) is Low or if the addressed
page is in the region protected by the Block
Protect (BP1 and BP0) bits.
Figure 13. Byte Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction
A8
Byte Address
Data Byte
1
A7 A6 A5 A4 A3 A2 A1 A0
7
6
5
4
3
2
0
D
Q
High Impedance
AI01442D
Note: Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
17/37
M95040, M95020, M95010
Figure 14. Page Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
D
S
C
D
Instruction
A8
Byte Address
Data Byte 1
1
A7 A6 A5 A4 A3 A2 A1 A0
7
6
5
4
3
2
0
7
24 25 26 27 28 29 30 31
Data Byte 2
Data Byte N
Data Byte 16
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
0
7
6
5
4
3
2
1
0
AI01443D
Note: Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
18/37
M95040, M95020, M95010
POWER-UP AND DELIVERY STATE
Power-up State
Initial Delivery State
After Power-up, the device is in the following state:
The device is delivered with the memory array set
at all 1s (FFh). The Block Protect (BP1 and BP0)
bits are initialized to 0.
–
–
low power Standby Power mode
deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be started).
–
–
–
not in the Hold Condition
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
The BP1 and BP0 bits of the Status Register are
unchanged from the previous power-down (they
are non-volatile bits).
19/37
M95040, M95020, M95010
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 7. may cause permanent damage to the de-
vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 7. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
°C
°C
V
T
Storage Temperature
–65
150
STG
1
1
TLEAD
VO
Lead Temperature during Soldering
Output Voltage
See note
V
CC+0.6
6.5
–0.50
–0.50
–0.50
VI
Input Voltage
V
V
Supply Voltage
6.5
V
CC
2
VESD
–4000
4000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
20/37
M95040, M95020, M95010
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 8. Operating Conditions (M950x0)
Symbol
Parameter
Min.
4.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
°C
°C
TA
125
Table 9. Operating Conditions (M950x0-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
°C
°C
TA
125
Table 10. Operating Conditions (M950x0-R)
Symbol
Parameter
Min.
1.8
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
Table 11. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
50
0.2V to 0.8V
Input Pulse Voltages
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Voltages
V
CC
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 15. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
CC
0.7V
CC
0.3V
CC
0.2V
AI00825B
21/37
M95040, M95020, M95010
Table 12. Capacitance
Symbol
COUT
Parameter
Test Condition
= 0V
Min.
Max.
Unit
pF
Output Capacitance (Q)
Input Capacitance (D)
Input Capacitance (other pins)
V
8
8
6
OUT
CIN
V
= 0V
= 0V
pF
IN
IN
V
pF
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 5MHz.
A
Table 13. DC Characteristics (M950x0, Device Grade 6)
Symbol
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
Unit
ILI
Input Leakage Current
Output Leakage Current
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
± 2
C = 0.1VCC/0.9VCC at 5MHz,
5
5
mA
mA
µA
2
3
VCC = 5 V, Q = open, Previous Product
ICC
Supply Current
C = 0.1VCC/0.9VCC at 10MHz,
VCC = 5 V, Q = open, Present Product
S = VCC , VCC = 5 V,
10
2
2
V
IN = VSS or VCC, Previous Product
Supply Current
(Standby Power mode)
ICC1
S = VCC , VCC = 5 V,
µA
3
VIN = VSS or VCC, Present Product
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.45
0.3 VCC
VCC+1
0.4
V
V
V
0.7 VCC
1
IOL = 2 mA, VCC = 5 V
IOH = –2 mA, VCC = 5 V
VOL
1
Output High Voltage
0.8 VCC
V
VOH
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Previous product: identified by Process Identification letter K.
3. Present product: identified by Process Identification letter W or G.
22/37
M95040, M95020, M95010
Table 14. DC Characteristics (M950x0, Device Grade 3)
Symbol
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
Unit
µA
ILI
Input Leakage Current
Output Leakage Current
ILO
S = VCC, VOUT = VSS or VCC
± 2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
5
3
mA
mA
µA
2
V
CC = 5 V, Q = open, Previous Product
ICC
Supply Current
C = 0.1VCC/0.9VCC at 5 MHz,
3
V
CC = 5 V, Q = open, Present Product
S = VCC , VCC = 5 V,
10
5
2
VIN = VSS or VCC, Previous Product
Supply Current
(Standby Power mode)
ICC1
S = VCC , VCC = 5 V,
µA
3
V
IN = VSS or VCC, Present Product
VIL
VIH
0.3 VCC
VCC+1
0.4
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.45
V
V
V
0.7 VCC
1
IOL = 2 mA, VCC = 5 V
IOH = –2 mA, VCC = 5 V
VOL
1
Output High Voltage
0.8 VCC
V
VOH
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Previous product: identified by Process Identification letter K.
3. Present product: identified by Process Identification letter W or G.
Table 15. DC Characteristics (M950x0-W, Device Grade 6)
Symbol
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
Unit
µA
ILI
Input Leakage Current
Output Leakage Current
ILO
S = VCC, VOUT = VSS or VCC
± 2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
2
2
2
1
mA
mA
µA
1
VCC = 2.5 V, Q = open, Previous Product
ICC
Supply Current
C = 0.1VCC/0.9VCC at 5 MHz,
2
VCC = 2.5 V, Q = open, Present Product
S = VCC , VCC = 2.5 V,
1
V
IN = VSS or VCC, Previous Product
Supply Current
(Standby Power mode)
ICC1
S = VCC , VCC = 2.5 V
µA
2
V
IN = VSS or VCC, Present Product
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.3 VCC
VCC+1
0.4
V
V
V
V
0.7 VCC
VOL
VOH
I
OL = 1.5 mA, VCC = 2.5 V
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
Note: 1. Previous product: identified by Process Identification letter K.
2. Present product: identified by Process Identification letter W or G.
23/37
M95040, M95020, M95010
Table 16. DC Characteristics (M950x0-W, Device Grade 3)
Symbol
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
Unit
µA
ILI
Input Leakage Current
Output Leakage Current
ILO
S = VCC, VOUT = VSS or VCC
± 2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
2
mA
1
V
CC = 2.5 V, Q = open, Previous Product
ICC
Supply Current
C = 0.1VCC/0.9VCC at 5 MHz,
2
2
mA
µA
2
V
CC = 2.5 V, Q = open, Present Product
Supply Current
(Standby Power mode)
ICC1
S = VCC , VCC = 2.5 V, VIN = VSS or VCC
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.3 VCC
VCC+1
0.4
V
V
V
V
0.7 VCC
VOL
VOH
IOL = 1.5 mA, VCC = 2.5 V
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
Note: 1. Previous product: identified by Process Identification letter K.
2. Present product: identified by Process Identification letter W or G.
Table 17. DC Characteristics (M950x0-R)
1
1
Symbol
ILI
Parameter
Test Condition
VIN = VSS or VCC
Unit
µA
Min.
Max.
Input Leakage Current
Output Leakage Current
± 2
± 2
ILO
S = VCC, VOUT = VSS or VCC
µA
C = 0.1 VCC/0.9. VCC at 1 MHz,
VCC = 1.8 V, Q = open
ICC
Supply Current
1
mA
µA
Supply Current
(Standby Power mode)
ICC1
S = VCC, VIN = VSS or VCC , VCC = 1.8 V
0.5
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.25 VCC
VCC+1
0.3
V
V
V
V
0.7 VCC
VOL
VOH
I
OL = 0.15 mA, VCC = 1.8 V
I
OH = –0.1 mA, VCC = 1.8 V
0.8 VCC
Note: 1. Preliminary data: Product under development. Please contact your nearest ST sales office for information.
24/37
M95040, M95020, M95010
Table 18. AC Characteristics (M950x0, Device Grade 6)
Test conditions specified in Table 11. and Table 8.
3
3
4
4
Symbol
Alt.
Parameter
Unit
MHz
ns
Min.
Max.
Min.
Max.
f
C
f
Clock Frequency
D.C.
90
5
D.C.
15
10
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
15
ns
SHCH
t
t
100
90
40
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
25
ns
CHSH
t
90
15
ns
CHSL
1
t
90
40
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
90
40
ns
µs
t
CLL
CL
2
t
1
1
1
1
t
RC
CLCH
2
t
Clock Fall Time
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
FC
CHCL
t
t
DSU
Data In Setup Time
20
30
70
40
15
15
15
20
30
30
DVCH
t
t
Data In Hold Time
CHDX
DH
t
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
Clock High Set-up Time before HOLD not Active
Output Disable Time
HHCH
t
HLCH
t
t
CHHL
CH
t
t
CHHH
CH
2
t
100
60
25
35
t
t
DIS
SHQZ
t
t
Clock Low to Output Valid
Output Hold Time
CLQV
V
t
t
HO
0
0
CLQX
2
t
Output Rise Time
50
50
20
20
25
35
5
RO
QLQH
2
t
Output Fall Time
ns
ns
ns
ms
t
FO
QHQL
t
t
LZ
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
50
HHQV
2
t
100
10
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t must never be less than the shortest possible clock period, 1 / f (max)
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Previous product: identified by Process Identification letter K.
4. Present product: identified by Process Identification letter W or G.
25/37
M95040, M95020, M95010
Table 19. AC Characteristics (M950x0, Device Grade 3)
Test conditions specified in Table 11. and Table 8.
3
3
4
4
Symbol
Alt.
Parameter
Unit
MHz
ns
Min.
Max.
Min.
Max.
f
C
f
Clock Frequency
D.C.
200
200
200
200
200
200
2
D.C.
90
5
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
1
t
90
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
200
90
ns
µs
t
CLL
CL
2
t
1
1
1
1
t
RC
CLCH
2
t
Clock Fall Time
µs
ns
ns
ns
ns
ns
t
FC
CHCL
t
t
DSU
Data In Setup Time
40
50
20
30
70
40
60
DVCH
t
t
Data In Hold Time
CHDX
DH
t
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
140
90
HHCH
t
HLCH
t
t
CHHL
CH
Clock High Set-up Time before HOLD not
Active
t
t
60
ns
CHHH
CH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
250
150
100
60
ns
ns
ns
t
DIS
SHQZ
t
t
CLQV
V
t
t
HO
0
0
CLQX
2
t
Output Rise Time
100
100
100
250
10
50
50
50
100
5
ns
ns
ns
ns
ms
t
RO
QLQH
2
t
Output Fall Time
t
FO
QHQL
t
t
LZ
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
2
t
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t must never be less than the shortest possible clock period, 1 / f (max)
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Previous product: identified by Process Identification letter K.
4. Present product: identified by Process Identification letter W or G.
26/37
M95040, M95020, M95010
Table 20. AC Characteristics (M950x0-W, Device Grade 6)
Test conditions specified in Table 11. and Table 9.
3
3
4
4
Symbol
Alt.
Parameter
Unit
MHz
ns
Min.
Max.
Min.
Max.
f
C
f
Clock Frequency
D.C.
200
200
200
200
200
200
2
D.C.
90
5
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
1
t
90
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
200
90
ns
µs
t
CLL
CL
2
t
1
1
1
1
t
RC
CLCH
2
t
Clock Fall Time
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
FC
CHCL
t
t
DSU
Data In Setup Time
40
50
20
30
70
40
60
60
DVCH
t
t
Data In Hold Time
CHDX
DH
t
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
Clock High Set-up Time before HOLD not Active
Output Disable Time
140
90
HHCH
t
HLCH
t
t
CHHL
CH
t
t
CHHH
CH
2
t
250
150
100
60
t
t
DIS
SHQZ
t
t
Clock Low to Output Valid
Output Hold Time
CLQV
V
t
t
HO
0
0
CLQX
2
t
Output Rise Time
100
100
100
250
10
50
50
50
100
5
RO
QLQH
2
t
Output Fall Time
ns
ns
ns
ms
t
FO
QHQL
t
t
LZ
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
2
t
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t must never be less than the shortest possible clock period, 1 / f (max)
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Previous product: identified by Process Identification letter K.
4. Present product: identified by Process Identification letter W or G.
27/37
M95040, M95020, M95010
Table 21. AC Characteristics (M950x0-W, Device Grade 3)
Test conditions specified in Table 11. and Table 9.
3
3
4
4
Symbol
Alt.
Parameter
Unit
MHz
ns
Min.
Max.
Min.
Max.
f
C
f
Clock Frequency
D.C.
200
200
200
200
200
200
2
D.C.
90
5
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
1
t
90
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
200
90
ns
µs
t
CLL
CL
2
t
1
1
1
1
t
RC
CLCH
2
t
Clock Fall Time
µs
ns
ns
ns
ns
ns
t
FC
CHCL
t
t
DSU
Data In Setup Time
40
50
20
30
70
40
60
DVCH
t
t
Data In Hold Time
CHDX
DH
t
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
140
90
HHCH
t
HLCH
t
t
CHHL
CH
Clock High Set-up Time before HOLD not
Active
t
t
60
ns
CHHH
CH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
250
150
100
60
ns
ns
ns
t
DIS
SHQZ
t
t
CLQV
V
t
t
HO
0
0
CLQX
2
t
Output Rise Time
100
100
100
250
10
50
50
50
100
5
ns
ns
ns
ns
ms
t
RO
QLQH
2
t
Output Fall Time
t
FO
QHQL
t
t
LZ
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
2
t
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t must never be less than the shortest possible clock period, 1 / f (max)
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Previous product: identified by Process Identification letter K.
4. Present product: identified by Process Identification letter W or G.
28/37
M95040, M95020, M95010
Table 22. AC Characteristics (M950x0-R)
Test conditions specified in Table 11. and Table 10.
Symbol
Alt.
Parameter
Min.
D.C.
200
200
200
200
200
Max.
Unit
MHz
ns
f
f
Clock Frequency
2
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
ns
SHCH
t
t
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
ns
CHSL
1
t
200
200
ns
ns
µs
µs
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
Clock Fall Time
t
CL
CLL
2
2
t
1
1
t
t
RC
CLCH
t
FC
CHCL
t
t
DSU
Data In Setup Time
40
50
ns
ns
ns
ns
ns
ns
DVCH
CHDX
t
t
t
DH
Data In Hold Time
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
Clock High Set-up Time before HOLD not Active
140
90
HHCH
t
HLCH
CHHL
t
t
120
120
CHHH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
250
180
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
0
CLQX
HO
RO
2
t
Output Rise Time
100
100
100
250
10
t
t
QLQH
2
t
Output Fall Time
ns
ns
ns
ms
FO
QHQL
t
t
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
LZ
2
t
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t must never be less than the shortest possible clock period, 1 / f (max)
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data: Product under development. Please contact your nearest ST sales office for information.
29/37
M95040, M95020, M95010
Figure 16. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 17. Hold Timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQV
Q
D
HOLD
AI02032B
30/37
M95040, M95020, M95010
Figure 18. Output Timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449D
31/37
M95040, M95020, M95010
PACKAGE MECHANICAL
Figure 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Note: Drawing is not to scale.
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
32/37
M95040, M95020, M95010
Figure 20. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
33/37
M95040, M95020, M95010
Figure 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
34/37
M95040, M95020, M95010
PART NUMBERING
Table 26. Ordering Information Scheme
Example:
M95040
–
W MN
6
T
P
/W
Device Type
M95 = SPI serial access EEPROM
Device Function
040 = 4 Kbit (512 x 8)
020 = 2 Kbit (256 x 8)
010 = 1 Kbit (128 x 8)
Operating Voltage
blank = V = 4.5 to 5.5V
CC
W = V = 2.5 to 5.5V
CC
R = V = 1.8 to 5.5V
CC
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
1
3 = Device tested with High Reliability Certified Flow .
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free
2
3
2
Process
blank = F6SP20%
/W = F6SP36%
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. Used only for Device Grade 3
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
Table 27. How to Identify Present and Previous Products by the Process Identification Letter
1
1
Markings on Present Products
Markings on Previous Products
95040W6
95040W6
AYWWW (or AYWWG)
AYWWK
35/37
M95040, M95020, M95010
REVISION HISTORY
Table 28. Document Revision History
Date
Version
Description of Revision
10-May-2000
2.2
s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation
Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & Tab
9. Wording changes, according to the standard glossary
16-Mar-2001
2.3
Illustrations and Package Mechanical data updated
19-Jul-2001
11-Oct-2001
26-Feb-2002
2.4
3.0
3.1
Temperature range ‘3’ added to the -W supply voltage range in DC and AC characteristics
Document reformatted using the new template
Description of chip deselect after 8th clock pulse made more explicit
Position of A8 in Read Instruction Sequence Figure corrected. Load Capacitance C
changed
L
27-Sep-2002
3.2
24-Oct-2002
24-Feb-2003
28-May-2003
3.3
3.4
3.5
Minimum values for tCHHL and tCHHH changed.
Description of Read from Memory Array (READ) instruction corrected, and clarified
New products, identified by the process letter W, added
Correction to current products, identified by the process letter K not L.
I
changed in DC characteristics, and t
, t
substituted in AC characteristics
CC
CHHL CHHH
25-Jun-2003
3.6
Voltage range -S upgraded by removing it, and adding the -R voltage range in its place
Temperature range 5 removed.
Table of contents, and Pb-free options added. V (min) improved to -0.45V
21-Nov-2003
02-Feb-2004
4.0
4.1
IL
V (max) and t
(max) changed
CLQV
IL
Absolute Maximum Ratings for V (min) and V (min) improved. Soldering temperature
IO
CC
information clarified for RoHS compliant devices. New 5V and 2.5V devices, with process
letter W, promoted from preliminary data to full data. Device Grade 3 clarified, with reference
to HRCF and automotive environments
01-Mar-2004
05-Oct-2004
5.0
6.0
Product List summary table added. Process identification letter “G” information added. Order
information for Tape and Reel changed to T. AEC-Q100-002 compliance. Device Grade
informaton clarified. tHHQX corrected to tHHQV. Signal Description updated.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified
36/37
M95040, M95020, M95010
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
37/37
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
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