M95020-WBN5 [STMICROELECTRONICS]
256X8 SPI BUS SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8;
| 型号： | M95020-WBN5 |
| 厂家： | 
ST |
| 描述： | 256X8 SPI BUS SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总33页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95040
M95020, M95010
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
■ Compatible with SPI Bus Serial Interface
Figure 1. Packages
(Positive Clock SPI Modes)
■ Single Supply Voltage:
– 4.5V to 5.5V for M950x0
– 2.5V to 5.5V for M950x0-W
– 1.8V to 3.6V for M950x0-S
8
■ 5 MHz Clock Rate (maximum)
■ Status Register
1
■ BYTE and PAGE WRITE (up to 16 Bytes)
■ Self-Timed Programming Cycle
■ Adjustable Size Read-Only EEPROM Area
■ Enhanced ESD Protection
PDIP8 (BN)
■ More than 1,000,000 Erase/Write Cycles
■ More than 40 Year Data Retention
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
July 2003
1/33
M95040, M95020, M95010
SUMMARY DESCRIPTION
The M95040 is a 4 Kbit (512 x 8) electrically eras-
able programmable memory (EEPROM), access-
ed by a high speed SPI-compatible bus. The other
members of the family (M95020, M95010) are
identical, though proportionally smaller (2 and 1
Kbit, respectively).
Figure 3. DIP, SO and TSSOP Connections
M95xxx
Each device is accessed by a simple serial
interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD). WRITE instruc-
tions are disabled by Write Protect (W).
S
Q
1
2
3
4
8
V
CC
HOLD
7
W
6
5
C
D
V
SS
AI01790D
Figure 2. Logic Diagram
Note: 1. See page 28 (onwards) for package dimensions, and how
to identify pin-1.
V
CC
Table 1. Signal Names
D
C
S
Q
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
D
M95xxx
Q
W
S
W
HOLD
HOLD
V
Supply Voltage
Ground
CC
V
SS
V
SS
AI01789C
2/33
M95040, M95020, M95010
SIGNAL DESCRIPTION
V
V
must be held within the specified range:
Chip Select (S)
CC
CC
(min) to V (max).
CC
When this input signal is High, the device is dese-
lected, and the Serial Data Output (Q) is high im-
pedance.
All of the input and output signals can be held High
or Low (according to voltages of V , V , V or
IH
OH
IL
V
, as specified in Tables 12 to 16). These sig-
OL
Hold (HOLD)
nals are described next.
This input signal is used to pause temporarily any
serial communications with the device, without los-
ing bits that have already been passed on the se-
rial bus.
Serial Data Output (Q)
This output signal is used to transfer data serially
out of the device. Data bytes are shifted out on the
falling edge of the Serial Clock (C).
Write Protect (W)
Serial Data Input (D)
This input signal is used to control whether the
memory is write protected. When W is held Low,
writes to the memory are disabled, but other oper-
ations remain enabled. No action on this signal, or
on the Write Enable Latch (WEL) bit, can interrupt
a Write cycle that has already started.
This input signal is used to transfer data serially
into the device. Instructions, addresses, and input
data bytes are shifted in on the rising edge of the
Serial Clock (C).
Serial Clock (C)
This input signal provides the timing for the serial
interface.
3/33
M95040, M95020, M95010
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4 shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI03746D
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
4/33
M95040, M95020, M95010
Figure 5. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
5/33
M95040, M95020, M95010
OPERATING FEATURES
Power mode, and the device consumption drops
to I
Power-up
.
CC1
When the power supply is turned on, V
rises
CC
from V to V
During this time, the Chip Select (S) must be al-
lowed to follow the V voltage. It must not be al-
lowed to float, but should be connected to V via
a suitable pull-up resistor.
.
SS
CC
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
CC
CC
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
6).
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on V
.
CC
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 6 also shows what happens if the rising and
falling edges are not timed to coincide with Serial
Clock (C) being Low.
Active Power and Stand-by Power Modes
When Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode. The device
consumes I , as specified in Tables 12 to 16.
CC
When Chip Select (S) is High, the device is dis-
abled. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Stand-by
Figure 6. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
AI02029D
6/33
M95040, M95020, M95010
Status Register
of memory that is protected against the execution
of Write cycles, as summarized in Table 3.
Figure 7 shows the position of the Status Register
in the control logic of the device. This register con-
tains a number of control bits and status bits, as
shown in Table 2.
Table 2. Status Register Format
Bits b7, b6, b5 and b4 are always read as 1.
b7
1
b0
WIP bit. The Write In Progress bit is a volatile
read-only bit that is automatically set and reset by
the internal logic of the device. When set to a 1, it
indicates that the memory is busy with a Write cy-
cle.
1
1
1
BP1 BP0 WEL WIP
Block Protect Bits
WEL bit. The Write Enable Latch bit is a volatile
read-only bit that is set and reset by specific in-
structions. When reset to 0, no WRITE or WRSR
instructions are accepted by the device.
Write Enable Latch Bit
Write In Progress Bit
BP1, BP0 bits. The Block Protect bits are non-
volatile read-write bits. These bits define the area
7/33
M95040, M95020, M95010
For any instruction to be accepted and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches the last bit of
the instruction, and before the next rising edge of
Serial Clock (C).
For this, “the last bit of the instruction” can be the
eighth bit of the instruction code, or the eighth bit
of a data byte, depending on the instruction (ex-
cept in the case of RDSR and READ instructions).
Moreover, the "next rising edge of CLOCK" might
(or might not) be the next bus transaction for some
other device on the bus.
Data Protection and Protocol Control
To help protect the device from data corruption in
noisy or poorly controlled environments, a number
of safety features have been built in to the device.
The main security measures can be summarized
as follows:
– The WEL bit is reset at power-up.
– Chip Select (S) must rise after the eighth clock
count (or multiple thereof) in order to start a non-
volatile Write cycle (in the memory array or in
the Status Register).
When a Write cycle is in progress, the device pro-
tects it against external interruption by ignoring
any subsequent READ, WRITE or WRSR instruc-
tion until the present cycle is complete.
– Accesses to the memory array are ignored dur-
ing the non-volatile programming cycle, and the
programming cycle continues unaffected.
– Invalid Chip Select (S) and Hold (HOLD) transi-
tions are ignored.
Table 3. Write-Protected Block Size
Status Register Bits
Protected Block
Array Addresses Protected
BP1
BP0
M95040
none
M95020
none
M95010
none
0
0
1
1
0
1
0
1
none
Upper quarter
Upper half
180h - 1FFh
100h - 1FFh
000h - 1FFh
C0h - FFh
80h - FFh
00h - FFh
060h - 7Fh
040h - 7Fh
000h - 7Fh
Whole memory
8/33
M95040, M95020, M95010
MEMORY ORGANIZATION
The memory is organized as shown in Figure 7.
Figure 7. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
1 Page
X Decoder
AI01272C
9/33
M95040, M95020, M95010
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 4.
If an invalid instruction is sent (one not contained
in Table 4), the device automatically deselects it-
self.
Table 4. Instruction Set
Instruc
Instruction
Format
Description
tion
WREN Write Enable
0000 X110
0000 X100
0000 X101
0000 X001
WRDI
RDSR
Write Disable
Read Status Register
WRSR Write Status Register
READ Read from Memory Array
WRITE Write to Memory Array
0000 A 011
8
0000 A 010
8
Note: 1. A8 = 1 for the upper half of the memory array of the
M95040, and 0 for the lower half, and is Don’t Care for
other devices.
2. X = Don’t Care.
Figure 8. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI01441D
As shown in Figure 8, to send this instruction to the
device, Chip Select (S) is driven Low, and the bits
of the instruction byte are shifted in, on Serial Data
Input (D). The device then enters a wait state. It
waits for a the device to be deselected, by Chip
Select (S) being driven High.
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
10/33
M95040, M95020, M95010
Figure 9. Write Disable (WRDI) Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03790D
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
As shown in Figure 9, to send this instruction to the
device, Chip Select (S) is driven Low, and the bits
of the instruction byte are shifted in, on Serial Data
Input (D).
– Power-up
– WRDI instruction execution
– WRSR instruction completion
– WRITE instruction completion
– Write Protect (W) line being held Low.
11/33
M95040, M95020, M95010
Figure 10. Read Status Register (RDSR) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI01444D
Read Status Register (RDSR)
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 3) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
One of the major uses of this instruction is to allow
the MCU to poll the state of the Write In Progress
(WIP) bit. This is needed because the device will
not accept further WRITE or WRSR instructions
when the previous Write cycle is not yet finished.
As shown in Figure 10, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte are then shifted in, on
Serial Data Input (D). The current state of the bits
in the Status Register is shifted out, on Serial Data
Out (Q). The Read Cycle is terminated by driving
Chip Select (S) High.
The Status Register may be read at any time, even
during a Write cycle (whether it be to the memory
area or to the Status Register). All bits of the Sta-
tus Register remain valid, and can be read using
the RDSR instruction. However, during the current
Write cycle, the values of the non-volatile bits
(BP0, BP1) become frozen at a constant value.
The updated value of these bits becomes avail-
able when a new RDSR instruction is executed, af-
ter completion of the Write cycle. On the other
hand, the two read-only bits (Write Enable Latch
(WEL), Write In Progress (WIP)) are dynamically
updated during the on-going Write cycle.
12/33
M95040, M95020, M95010
Figure 11. Write Status Register (WRSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI01445B
timed Write Cycle starts, and continues for a peri-
Write Status Register (WRSR)
od t (as specified in Tables 17 to 20), at the end
W
of which the Write in Progress (WIP) bit is reset to
0.
This instruction has no effect on bits b7, b6, b5, b4,
b1 and b0 of the Status Register.
The instruction is not accepted, and is not execut-
ed, under the following conditions:
– if the Write Enable Latch (WEL) bit has not been
set to 1 (by executing a Write Enable instruction
just before)
As shown in Figure 11, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and data byte are then
shifted in on Serial Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High. Chip Select (S) must be driven High
after the rising edge of Serial Clock (C) that latch-
es the eighth bit of the data byte, and before the
the next rising edge of Serial Clock (C). If this con-
dition is not met, the Write Status Register
(WRSR) instruction is not executed. The self-
– if a Write Cycle is already in progress
– if the device has not been deselected, by Chip
Select (S) being driven High, after the eighth bit,
b0, of the data byte has been latched in
– if Write Protect (W) is Low.
13/33
M95040, M95020, M95010
Figure 12. Read from Memory Array (READ) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
C
Instruction
A8
Byte Address
A7 A6 A5 A4 A3 A2 A1 A0
D
Q
Data Out
High Impedance
2
1
7
6
5
4
3
0
AI01440E
Note: Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
can, therefore, be read with a single READ instruc-
tion.
Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address byte are
then shifted in, on Serial Data Input (D). For the
M95040, the most significant address bit, A8, is in-
corporated as bit b3 of the instruction byte, as
shown in Table 4. The address is loaded into an in-
ternal address register, and the byte of data at that
address is shifted out, on Serial Data Output (Q).
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.
If Chip Select (S) continues to be driven Low, an
internal bit-pointer is automatically incremented at
each clock cycle, and the corresponding data bit is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
Table 5. Address Range Bits
Device
M95040
M95020
M95010
Address Bits
A8-A0
A7-A0
A6-A0
14/33
M95040, M95020, M95010
Figure 13. Byte Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction
A8
Byte Address
Data Byte
1
A7 A6 A5 A4 A3 A2 A1 A0
7
6
5
4
3
2
0
D
Q
High Impedance
AI01442D
Note: Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
given address to the end of the same page can be
programmed in a single instruction.
Write to Memory Array (WRITE)
If Chip Select (S) still continues to be driven Low,
the next byte of input data is shifted in, and is used
to overwrite the byte at the start of the current
page.
The instruction is not accepted, and is not execut-
ed, under the following conditions:
As shown in Figure 13, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High after the rising edge of Serial Clock
(C) that latches the last data bit, and before the
next rising edge of Serial Clock (C) occurs any-
where on the bus. In the case of Figure 13, this oc-
curs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being
used to write a single byte. The self-timed Write
– if the Write Enable Latch (WEL) bit has not been
set to 1 (by executing a Write Enable instruction
just before)
– if a Write cycle is already in progress
– if the device has not been deselected, by Chip
Select (S) being driven High, at a byte boundary
(after the rising edge of Serial Clock (C) that
latches the last data bit, and before the next ris-
ing edge of Serial Clock (C) occurs anywhere on
the bus)
cycle starts, and continues for a period t
(as
WC
specified in Tables 17 to 20), at the end of which
the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 14, the next byte of input
data is shifted in. In this way, all the bytes from the
– if Write Protect (W) is Low or if the addressed
page is in the region protected by the Block Pro-
tect (BP1 and BP0) bits.
15/33
M95040, M95020, M95010
Figure 14. Page Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
D
S
C
D
Instruction
A8
Byte Address
Data Byte 1
1
A7 A6 A5 A4 A3 A2 A1 A0
7
6
5
4
3
2
0
7
24 25 26 27 28 29 30 31
Data Byte 2
Data Byte N
Data Byte 16
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
0
7
6
5
4
3
2
1
0
AI01443D
Note: Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
16/33
M95040, M95020, M95010
POWER-UP AND DELIVERY STATE
– Write In Progress (WIP) is reset to 0
Power-up State
After Power-up, the device is in the following state:
– low power Stand-by mode
the BP1 and BP0 bits of the Status Register are
unchanged from the previous power-down (they
are non-volatile bits).
– deselected (after Power-up, a falling edge is re-
quired on Chip Select (S) before any instruc-
tions can be started).
– not in the Hold Condition
– the Write Enable Latch (WEL) is reset to 0
Initial Delivery State
The device is delivered with the memory array set
at all 1s (FFh). The Block Protect (BP1 and BP0)
bits are initialized to 0.
17/33
M95040, M95020, M95010
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
T
STG
Storage Temperature
–65
150
°C
PDIP: 10 seconds
SO: 20 seconds (max)
260
235
235
Lead Temperature during
Soldering
1
TLEAD
°C
1
TSSOP: 20 seconds (max)
VO
VI
Output Voltage
Input Voltage
Supply Voltage
–0.3
–0.3
VCC+0.6
6.5
V
V
V
V
V
–0.3
6.5
CC
2
VESD
–4000
4000
Electrostatic Discharge Voltage (Human Body model)
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
18/33
M95040, M95020, M95010
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 7. Operating Conditions (M950x0)
Symbol
Parameter
Min.
4.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (range 6)
–40
–40
85
°C
°C
TA
Ambient Operating Temperature (range 3)
125
Table 8. Operating Conditions (M950x0-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (range 6)
Ambient Operating Temperature (range 3)
–40
–40
85
°C
°C
TA
125
Table 9. Operating Conditions (M950x0-S)
Symbol
Parameter
Min.
1.8
Max.
3.6
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
–20
85
°C
Table 10. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
50
0.2V to 0.8V
Input Pulse Voltages
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Voltages
V
CC
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 15. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
0.2V
CC
CC
0.7V
CC
0.3V
CC
AI00825B
19/33
M95040, M95020, M95010
Table 11. Capacitance
Symbol
COUT
Parameter
Test Condition
= 0V
Min.
Max.
Unit
pF
Output Capacitance (Q)
Input Capacitance (D)
Input Capacitance (other pins)
V
8
8
6
OUT
CIN
V
IN
= 0V
= 0V
pF
V
IN
pF
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 5 MHz.
A
Table 12. DC Characteristics (M950x0, temperature range 6)
Symbol
ILI
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
Unit
Input Leakage Current
Output Leakage Current
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
± 2
C = 0.1 VCC/0.9. VCC at 5 MHz,
VCC = 5 V, Q = open
ICC
Supply Current
5
mA
ICC1
VIL
Supply Current (Stand-by)
Input Low Voltage
S = VCC, VIN = VSS or VCC , VCC = 5 V
10
µA
V
– 0.3
0.3 VCC
VCC+1
VIH
0.7 VCC
Input High Voltage
V
1
IOL = 2 mA, VCC = 5 V
Output Low Voltage
0.4
V
VOL
1
I
OH = –2 mA, VCC = 5 V
0.8 VCC
Output High Voltage
V
VOH
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 13. DC Characteristics (M950x0, temperature range 3)
Symbol
ILI
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
Unit
µA
Input Leakage Current
Output Leakage Current
ILO
S = VCC, VOUT = VSS or VCC
± 2
µA
C = 0.1 VCC/0.9. VCC at 5 MHz,
VCC = 5 V, Q = open
ICC
Supply Current
5
mA
ICC1
VIL
Supply Current (Stand-by)
Input Low Voltage
S = VCC, VIN = VSS or VCC , VCC = 5 V
10
0.3 VCC
VCC+1
0.4
µA
V
– 0.3
VIH
Input High Voltage
0.7 VCC
V
1
Output Low Voltage
IOL = 2 mA, VCC = 5 V
IOH = –2 mA, VCC = 5 V
V
VOL
1
Output High Voltage
0.8 VCC
V
VOH
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
20/33
M95040, M95020, M95010
Table 14. DC Characteristics (M950x0-W, temperature range 6)
Symbol
ILI
Parameter
Test Condition
IN = VSS or VCC
Min.
Max.
± 2
Unit
µA
V
Input Leakage Current
Output Leakage Current
ILO
S = VCC, VOUT = VSS or VCC
± 2
µA
C = 0.1 VCC/0.9. VCC at 2 MHz,
VCC = 2.5 V, Q = open
ICC
Supply Current
2
mA
ICC1
VIL
S = VCC, VIN = VSS or VCC , VCC = 2.5 V
Supply Current (Stand-by)
Input Low Voltage
2
µA
V
– 0.3
0.3 VCC
VCC+1
0.4
VIH
VOL
VOH
Input High Voltage
0.7 VCC
V
Output Low Voltage
Output High Voltage
IOL = 1.5 mA, VCC = 2.5 V
OH = –0.4 mA, VCC = 2.5 V
V
I
0.8 VCC
V
Table 15. DC Characteristics (M950x0-W, temperature range 3)
Symbol
ILI
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
Unit
µA
Input Leakage Current
Output Leakage Current
ILO
S = VCC, VOUT = VSS or VCC
± 2
µA
C = 0.1 VCC/0.9. VCC at 2 MHz,
VCC = 2.5 V, Q = open
ICC
Supply Current
2
mA
ICC1
VIL
Supply Current (Stand-by)
Input Low Voltage
S = VCC, VIN = VSS or VCC , VCC = 2.5 V
5
µA
V
– 0.3
0.3 VCC
VCC+1
0.4
VIH
VOL
VOH
Input High Voltage
0.7 VCC
V
I
OL = 1.5 mA, VCC = 2.5 V
Output Low Voltage
Output High Voltage
V
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
V
Table 16. DC Characteristics (M950x0-S)
1
1
Symbol
ILI
Parameter
Test Condition
Unit
µA
Min.
Max.
Input Leakage Current
Output Leakage Current
VIN = VSS or VCC
± 2
± 2
ILO
S = VCC, VOUT = VSS or VCC
µA
C = 0.1 VCC/0.9. VCC at 1 MHz,
VCC = 1.8 V, Q = open
ICC
Supply Current
2
mA
ICC1
VIL
Supply Current (Stand-by)
Input Low Voltage
S = VCC, VIN = VSS or VCC , VCC = 1.8 V
2
µA
V
– 0.3
0.3 VCC
VCC+1
0.3
VIH
VOL
VOH
Input High Voltage
0.7 VCC
V
I
OL = 0.15 mA, VCC = 1.8 V
Output Low Voltage
Output High Voltage
V
IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
V
Note: 1. Preliminary data, for the 1.8V to 3.6 supply voltage range devices.
21/33
M95040, M95020, M95010
Table 17. AC Characteristics (M950x0, temperature range 6)
Test conditions specified in Table 10 and Table 7
Symbol
Alt.
Parameter
Min.
D.C.
90
Max.
Unit
MHz
ns
f
f
Clock Frequency
5
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
1
t
90
90
ns
ns
µs
µs
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
Clock Fall Time
t
CLL
CL
2
2
t
1
t
RC
CLCH
t
FC
1
t
CHCL
t
t
DSU
Data In Setup Time
20
30
70
40
60
60
ns
ns
ns
ns
ns
ns
DVCH
CHDX
t
t
t
DH
Data In Hold Time
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
Clock High Set-up Time before HOLD not Active
HHCH
t
HLCH
CHHL
t
t
CHHH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
100
60
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
0
CLQX
HO
RO
2
t
Output Rise Time
50
50
50
t
t
QLQH
QHQL
HHQX
2
2
2
t
Output Fall Time
ns
ns
FO
t
HOLD High to Output Low-Z
t
LZ
t
HOLD Low to Output High-Z
Write Time
100
10
ns
t
HZ
HLQZ
t
W
t
WC
ms
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
22/33
M95040, M95020, M95010
Table 18. AC Characteristics (M950x0, temperature range 3)
Test conditions specified in Table 10 and Table 7
Symbol
Alt.
Parameter
Min.
D.C.
100
100
200
100
200
Max.
Unit
MHz
ns
f
f
Clock Frequency
2
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
ns
SHCH
t
t
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
ns
CHSL
1
t
200
200
ns
ns
µs
µs
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
Clock Fall Time
t
CLL
CL
2
2
t
1
t
RC
CLCH
t
FC
1
t
CHCL
t
t
DSU
Data In Setup Time
40
50
ns
ns
ns
ns
ns
ns
DVCH
CHDX
t
t
t
DH
Data In Hold Time
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
Clock High Set-up Time before HOLD not Active
100
90
HHCH
t
HLCH
CHHL
t
t
120
120
CHHH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
150
150
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
0
CLQX
HO
RO
2
t
Output Rise Time
100
100
100
t
t
QLQH
QHQL
HHQX
2
2
2
t
Output Fall Time
ns
ns
FO
t
HOLD High to Output Low-Z
t
LZ
t
HOLD Low to Output High-Z
Write Time
150
10
ns
t
HZ
HLQZ
t
W
t
WC
ms
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
23/33
M95040, M95020, M95010
Table 19. AC Characteristics (M950x0-W, temperature ranges 6 and 3)
Test conditions specified in Table 10 and Table 8
Symbol
Alt.
Parameter
Min.
D.C.
200
200
200
200
200
Max.
Unit
MHz
ns
f
f
Clock Frequency
2
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
ns
SHCH
t
t
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
ns
CHSL
1
t
200
200
ns
ns
µs
µs
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
Clock Fall Time
t
CLL
CL
2
2
t
1
t
RC
CLCH
t
FC
1
t
CHCL
t
t
DSU
Data In Setup Time
40
50
ns
ns
ns
ns
ns
ns
DVCH
CHDX
t
t
t
DH
Data In Hold Time
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
Clock High Set-up Time before HOLD not Active
140
90
HHCH
t
HLCH
CHHL
t
t
120
120
CHHH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
250
150
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
0
CLQX
HO
RO
2
t
Output Rise Time
100
100
100
t
t
QLQH
QHQL
HHQX
2
2
2
t
Output Fall Time
ns
ns
FO
t
HOLD High to Output Low-Z
t
LZ
t
HOLD Low to Output High-Z
Write Time
250
10
ns
t
HZ
HLQZ
t
W
t
WC
ms
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
24/33
M95040, M95020, M95010
Table 20. AC Characteristics (M950x0-S)
Test conditions specified in Table 10 and Table 9
Symbol
Alt.
Parameter
Min.
D.C.
400
400
300
400
400
Max.
Unit
MHz
ns
f
f
Clock Frequency
1
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
ns
SHCH
t
t
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
ns
CHSL
1
t
400
400
ns
ns
µs
µs
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
Clock Fall Time
t
CLL
CL
2
2
t
1
t
RC
CLCH
t
FC
1
t
CHCL
t
t
DSU
Data In Setup Time
60
ns
ns
ns
ns
ns
ns
DVCH
CHDX
t
t
t
DH
Data In Hold Time
100
350
200
250
250
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
Clock High Set-up Time before HOLD not Active
HHCH
t
HLCH
CHHL
t
t
CHHH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
500
380
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
0
CLQX
HO
RO
2
t
Output Rise Time
200
200
250
t
t
QLQH
QHQL
HHQX
2
2
2
t
Output Fall Time
ns
ns
FO
t
HOLD High to Output Low-Z
t
LZ
t
HOLD Low to Output High-Z
Write Time
500
10
ns
t
HZ
HLQZ
t
W
t
WC
ms
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
25/33
M95040, M95020, M95010
Figure 16. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 17. Hold Timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQX
Q
D
HOLD
AI02032
26/33
M95040, M95020, M95010
Figure 18. Output Timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449D
27/33
M95040, M95020, M95010
PACKAGE MECHANICAL
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Notes: 1. Drawing is not to scale.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
28/33
M95040, M95020, M95010
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: Drawing is not to scale.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
29/33
M95040, M95020, M95010
TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Notes: 1. Drawing is not to scale.
TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
30/33
M95040, M95020, M95010
PART NUMBERING
Table 21. Ordering Information Scheme
Example:
M95040
–
W
MN
6
TR
Device Type
M95 = SPI serial access EEPROM
3
Device Function
040 = 4 Kbit (512 x 8)
020 = 2 Kbit (256 x 8)
010 = 1 Kbit (128 x 8)
Operating Voltage
blank = V = 4.5 to 5.5V
CC
W = V = 2.5 to 5.5V
CC
2
S = V = 1.8 to 3.6V
CC
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
Temperature Range
6 = –40 to 85 °C
1
3 = –40 to 125 °C
5 = –20 to 85 °C
Option
TR = Tape & Reel Packing
Note: 1. Temperature range available only on request.
2. The -S version (V range 1.8 V to 3.6 V) only available in temperature range 5.
CC
3. All devices use a positive clock strobe: Serial Data In (D) is strobed on the rising edge of Serial Clock (C) and Serial Data Out (Q)
is synchronized from the falling edge of Serial Clock (C).
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
31/33
M95040, M95020, M95010
REVISION HISTORY
Table 22. Document Revision History
Date
Rev.
Description of Revision
10-May-2000
2.2 s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation
Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & Tab 9.
2.3 Wording changes, according to the standard glossary
16-Mar-2001
Illustrations and Package Mechanical data updated
19-Jul-2001
11-Oct-2001
26-Feb-2002
27-Sep-2002
24-Oct-2002
24-Feb-2003
2.4 Temperature range ‘3’ added to the -W supply voltage range in DC and AC characteristics
3.0 Document reformatted using the new template
3.1 Description of chip deselect after 8th clock pulse made more explicit
Position of A8 in Read Instruction Sequence Figure corrected. Load Capacitance C changed
3.2
L
3.3 Minimum values for tCHHL and tCHHH changed.
3.4 Description of Read from Memory Array (READ) instruction corrected, and clarified
32/33
M95040, M95020, M95010
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2003 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
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33/33
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