M95080-DFDW6TG/S [STMICROELECTRONICS]
SPI BUS SERIAL EEPROM;
| 型号： | M95080-DFDW6TG/S |
| 厂家： | 
ST |
| 描述： | SPI BUS SERIAL EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总44页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95080-W M95080-R M95080-DF
8-Kbit serial SPI bus EEPROM with high-speed clock
Datasheet - production data
Features
• Compatible with the Serial Peripheral Interface
(SPI) bus
• Memory array
– 8 Kb (1 Kbyte) of EEPROM
SO8 (MN)
150 mil width
– Page size: 32 bytes
– Additional Write lockable Page
(Identification page)
• Write
– Byte Write within 5 ms
– Page Write within 5 ms
• Write Protect: quarter, half or whole memory
TSSOP8 (DW)
169 mil width
array
• High-speed clock: 20 MHz
• Single supply voltage:
– 2.5 V to 5.5 V for M95080-W
– 1.8 V to 5.5 V for M95080-R
– 1.7 V to 5.5 V for M95080-DF
UFDFPN8 (MC)
• Operating temperature range: from -40°C up to
2 x 3 mm
+85°C
• Enhanced ESD protection
• More than 4 million Write cycles
• More than 200-year data retention
• Packages
– RoHS compliant and halogen-free
®
(ECOPACK )
March 2014
DocID022540 Rev 3
1/44
This is information on a product in full production.
www.st.com
Contents
M95080-W M95080-R M95080-DF
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
CC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
4
5
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1
5.1.2
5.1.3
5.1.4
Operating supply voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
5.3
5.4
5.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . 14
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Contents
6.3.2
6.3.3
6.3.4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4
6.5
6.6
6.7
6.8
6.9
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Identification Page (available only in M95080-D devices) . . . . . . . 26
Write Identification Page (available only in M95080-D devices) . . . . . . . 27
Read Lock Status (available only in M95080-D devices) . . . . . . . . . . . . . 28
6.10 Lock ID (available only in M95080-D devices) . . . . . . . . . . . . . . . . . . . . . 29
7
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
7.2
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9
10
11
12
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3
List of tables
M95080-W M95080-R M95080-DF
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating conditions (M95080-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Operating conditions (M95080-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Operating conditions (M95080-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC characteristics (M95080-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC characteristics (M95080-R or M95080-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . 35
AC characteristics (M95080-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics (M95080-R or M95080-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . 37
SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 39
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 40
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22.
Table 23.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Write identification page sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Read Lock Status sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. Serial output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 39
Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 41
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Description
M95080-W M95080-R M95080-DF
1
Description
The M95080 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 1024 x 8 bits, accessed through the SPI bus.
The M95080-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95080-R can
operate with a supply voltage from 1.8 V to 5.5 V, and the M95080-DF can operate with a
supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
The M95080-D offers an additional page, named the Identification Page (32 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
6
##
$
#
3
1
-ꢄꢅXXX
7
(/,$
6
33
!)ꢀꢁꢂꢃꢄ#
The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.
Table 1. Signal names
Signal name
Function
Direction
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Input
Input
Output
Input
Input
Input
-
D
Q
S
W
HOLD
VCC
VSS
Supply voltage
Ground
-
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Description
Figure 2. 8-pin package connections (top view)
-ꢄꢅXXX
3
1
ꢁ
ꢆ
ꢇ
ꢈ
ꢃ
ꢂ
ꢉ
ꢅ
6
##
(/,$
7
#
$
6
33
!)ꢀꢁꢂꢄꢀ$
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
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Memory organization
M95080-W M95080-R M95080-DF
2
Memory organization
The memory is organized as shown in the following figure.
Figure 3. Block diagram
(/,$
7
(IGH VOLTAGE
GENERATOR
#ONTROL LOGIC
3
#
$
1
)ꢊ/ SHIFT REGISTER
$ATA
REGISTER
!DDRESS REGISTER
AND COUNTER
3TATUS
REGISTER
ꢁꢊꢈ
ꢁꢊꢆ
3IZE OF THE
2EAD ONLY
%%02/-
AREA
ꢁ PAGE
)DENTIFICATION PAGE
8 DECODER
-3ꢁꢄꢂꢇꢇ6ꢁ
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Signal description
3
Signal description
During all operations, V must be held stable and within the specified valid range:
CC
V
(min) to V (max).
CC
CC
All of the input and output signals must be held high or low (according to voltages of V ,
IH
V
, V or V , as specified in Section 9: DC and AC parameters). These signals are
OH
IL OL
described next.
3.1
3.2
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3
3.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Signal description
M95080-W M95080-R M95080-DF
3.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7
3.8
VCC supply voltage
V
is the supply voltage.
CC
VSS ground
V
is the reference for all signals, including the V supply voltage.
SS
CC
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Connecting to the SPI bus
4
Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4. Bus master and memory devices on the SPI bus
633
6##
2
3$/
30) )NTERFACE WITH
ꢋ#0/,ꢌ #0(!ꢍ ꢎ
ꢋꢀꢌ ꢀꢍ OR ꢋꢁꢌ ꢁꢍ
3$)
3#+
6##
6##
6##
#
1
$
#
1
$
# 1 $
633
633
633
30) "US -ASTER
30) -EMORY
$EVICE
30) -EMORY
$EVICE
30) -EMORY
$EVICE
2
2
2
#3ꢇ #3ꢆ #3ꢁ
3
3
3
7
(/,$
7
(/,$
(/,$
7
!)ꢁꢆꢃꢇꢉB
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
t
requirement is met. The typical value of R is 100 kΩ.
SHCH
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Connecting to the SPI bus
M95080-W M95080-R M95080-DF
4.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
•
•
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
•
•
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. SPI modes supported
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M95080-W M95080-R M95080-DF
Operating features
5
Operating features
5.1
Supply voltage (VCC)
5.1.1
Operating supply voltage (V
)
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Operating conditions
CC
CC
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (t ). In order to secure a stable DC supply voltage, it is
W
recommended to decouple the V line with a suitable capacitor (usually of the order of
CC
10 nF to 100 nF) close to the V /V device pins.
CC SS
5.1.2
Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum V operating voltage (see Operating conditions in Section 9: DC
CC
and AC parameters).
At power-up, when V passes over the POR threshold, the device is reset and is in the
CC
following state:
•
•
•
in Standby Power mode,
deselected,
Status Register values:
–
–
–
The Write Enable Latch (WEL) bit is reset to 0.
The Write In Progress (WIP) bit is reset to 0.
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until V reaches a valid and
CC
stable level within the specified [V (min), V (max)] range, as defined under Operating
CC
CC
conditions in Section 9: DC and AC parameters.
5.1.3
Power-up conditions
When the power supply is turned on, V rises continuously from V to V . During this
CC
SS
CC
time, the Chip Select (S) line is not allowed to float but should follow the V voltage. It is
CC
therefore recommended to connect the S line to V via a suitable pull-up resistor (see
CC
Figure 4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
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Operating features
M95080-W M95080-R M95080-DF
5.1.4
Power-down
During power-down (continuous decrease of the V supply voltage below the minimum
CC
V
operating voltage defined under Operating conditions in Section 9: DC and AC
CC
parameters), the device must be:
•
•
deselected (Chip Select S should be allowed to follow the voltage applied on V ),
CC
in Standby Power mode (there should not be any internal write cycle in progress).
5.2
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
.
CC
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
, as specified in DC characteristics (see Section 9: DC and AC parameters).
CC1
5.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial Data
Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
(a) (b)
been in progress.
Figure 6. Hold condition activation
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b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
14/44
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M95080-W M95080-R M95080-DF
Operating features
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 6).
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4
5.5
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
Data protection and protocol control
The device features the following data protection mechanisms:
•
Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
•
•
•
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
•
The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
•
The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
Status Register bits
Protected block
Protected array addresses
BP1
BP0
0
0
1
1
0
1
0
1
none
none
Upper quarter
Upper half
0300h - 03FFh
0200h - 03FFh
0000h - 03FFh
Whole memory
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Instructions
M95080-W M95080-R M95080-DF
6
Instructions
Each command is composed of bytes (MSBit transmitted first), initiated with the instruction
byte, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically enters
a Wait state until deselected.
Table 3. Instruction set
Instruction
Instruction
WREN
Description
format
Write Enable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1000 0011
1000 0010
1000 0011
1000 0010
WRDI
Write Disable
RDSR
WRSR
READ
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
Read Identification Page
Write Identification Page
WRITE
RDID(1)
WRID(1)
RDLS(1)
LID(1)
Reads the Identification Page lock status
Locks the Identification page in read-only mode
1. Instruction available only for the M95080-D device.
For read and write commands to memory array and Identification Page, the address is
defined by two bytes as explained in Table 4.
(1)(2)
Table 4. Significant bits within the two address bytes
MSB Address byte
LSB Address byte
Instructions
b15 b14 b13 b12 b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
READ or
WRITE
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
1
A9
0
A8
A7
A6
A5
A4
A3
A2
A1
A0
RDID or
WRID(3)
0
0
0
0
0
0
0
0
A4
0
A3
0
A2
0
A1
0
A0
0
RDLS or
LID(3)
0
1. A: Significant address bit.
2. x: bit is Don’t Care.
3. Instruction available only for the M95080-D device.
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M95080-W M95080-R M95080-DF
Instructions
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 7. Write Enable (WREN) sequence
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Instructions
M95080-W M95080-R M95080-DF
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
•
Power-up
•
•
•
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 8. Write Disable (WRDI) sequence
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M95080-W M95080-R M95080-DF
Instructions
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle is
in progress. When one of these cycles is in progress, it is recommended to check the Write
In Progress (WIP) bit before sending a new instruction to the device. It is also possible to
read the Status Register continuously, as shown in Figure 9.
Figure 9. Read Status Register (RDSR) sequence
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The status and control bits of the Status Register are as follows:
6.3.1
6.3.2
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
•
•
•
•
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Table 2) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
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Instructions
M95080-W M95080-R M95080-DF
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5. Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
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M95080-W M95080-R M95080-DF
Instructions
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 10.
Figure 10. Write Status Register (WRSR) sequence
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Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes t to complete (as specified in AC tables under Section 9: DC
W
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t , and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
W
also reset at the end of the Write cycle t .
W
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
•
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2.
•
The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 6. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t Write cycle.
W
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
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Instructions
M95080-W M95080-R M95080-DF
Table 6. Protection modes
Memory content
W
signal
SRWD
bit
Write protection of the
Status Register
Mode
Protected area(1) Unprotected area(1)
1
0
0
0
Status Register is writable
(if the WREN instruction
has set the WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Software-
protected
(SPM)
Ready to accept
Write-protected
Write instructions
1
1
Status Register is
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
Hardware-
protected
(HPM)
Ready to accept
Write-protected
0
1
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
The protection features of the device are summarized in Table 6.
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
•
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
•
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
•
•
either setting the SRWD bit after driving the Write Protect (W) input pin low,
or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
22/44
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Instructions
6.5
Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
Figure 11. Read from Memory Array (READ) sequence
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1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
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43
Instructions
M95080-W M95080-R M95080-DF
6.6
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period t (as specified in AC characteristics in Section 9: DC and AC parameters), at the
W
end of which the Write in Progress (WIP) bit is reset to 0.
Figure 12. Byte Write (WRITE) sequence
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1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
The instruction is not accepted, and is not executed, under the following conditions:
•
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
•
•
if a Write cycle is already in progress,
if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
•
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
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M95080-W M95080-R M95080-DF
Instructions
Note:
The self-timed write cycle t is internally executed as a sequence of two consecutive
W
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit
is read as “0” and a programmed bit is read as “1”.
Figure 13. Page Write (WRITE) sequence
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1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
DocID022540 Rev 3
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43
Instructions
M95080-W M95080-R M95080-DF
6.7
Read Identification Page (available only in M95080-D
devices)
The Read Identification Page (RDID) instruction is used to read the Identification Page
(additional page of 32 bytes which can be written and later permanently locked in Read-only
mode).
The Chip Select (S) signal is first driven low, the bits of the instruction byte and address
bytes are then shifted in (MSB first) on Serial Data input (D). Address bit A10 must be 0,
other upper address bits are Don't Care (it might be easier to define these bits as 0, as
shown in Table 4). The data byte pointed to by the lower address bits [A4:A0] is shifted out
(MSB first) on Serial Data output (Q).
The first byte addressed can be any byte within the identification page.
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented and the byte of data at the new address is shifted out.
Note that there is no roll over feature in the Identification Page. The address of bytes to read
must not exceed the page boundary.
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time when the data bits are shifted out.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 14. Read Identification Page sequence
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26/44
DocID022540 Rev 3
M95080-W M95080-R M95080-DF
Instructions
6.8
Write Identification Page (available only in M95080-D
devices)
The Write Identification Page (WRID) instruction is used to write the Identification Page
(additional page of 32 bytes which can also be permanently locked in Read-only mode).
The Chip Select signal (S) is first driven low, and then the bits of the instruction byte,
address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D).
Address bit A10 must be 0, other upper address bits are Don't Care (it might be easier to
define these bits as 0, as shown in Table 4). The lower address bits [A4:A0] define the byte
address inside the identification page.
The self-timed Write cycle starts from the rising edge of Chip Select (S), and continues for a
period t (as specified in Section 9: DC and AC parameters).
W
Figure 15. Write identification page sequence
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DocID022540 Rev 3
27/44
43
Instructions
M95080-W M95080-R M95080-DF
6.9
Read Lock Status (available only in M95080-D devices)
The Read Lock Status (RDLS) instruction is used to read the lock status.
To send this instruction to the device, Chip Select (S) first has to be driven low. The bits of
the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input
(D). Address bit A10 must be 1; all other address bits are Don't Care (it might be easier to
define these bits as 0, as shown in Table 4). The Lock bit is the LSB (Least Significant Bit) of
the byte read on Serial Data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the
lock is not active. If Chip Select (S) continues to be driven low, the same data byte is shifted
out.
The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is
shown in Figure 16.
The Read Lock Status instruction is not accepted and not executed if a Write cycle is
currently in progress.
Figure 16. Read Lock Status sequence
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28/44
DocID022540 Rev 3
M95080-W M95080-R M95080-DF
Instructions
6.10
Lock ID (available only in M95080-D devices)
The Lock Identification Page (LID) command is used to permanently lock the Identification
Page in Read-only mode.
The LID instruction is issued by driving Chip Select (S) low, sending (MSB first) the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A10 must be equal to 1. All other address bits are Don't
Care (it might be easier to define these bits as 0, as shown in Table 4). The data byte sent
must be equal to the binary value xxxx xx1x, where x = Don't Care. The LID instruction is
terminated by driving Chip Select (S) high at a data byte boundary, otherwise, the instruction
is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write
cycle which duration is t (specified in Section 9: DC and AC parameters). The instruction
W
sequence is shown in Figure 17.
The instruction is discarded, and is not executed, under the following conditions:
•
If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before).
•
•
If a Write cycle is already in progress.
If the device has not been deselected, by driving high Chip Select (S), at exactly a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in).
Figure 17. Lock ID sequence
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43
Power-up and delivery state
M95080-W M95080-R M95080-DF
7
Power-up and delivery state
7.1
Power-up state
After power-up, the device is in the following state:
•
•
Standby power mode,
deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
•
•
•
not in the Hold condition,
the Write Enable Latch (WEL) is reset to 0,
Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with:
•
•
•
the memory array set to all 1s (each byte = FFh)
Status register: bit SRWD =0, BP1 =0 and BP0 =0
Identification page: byte values are Don’t Care.
30/44
DocID022540 Rev 3
M95080-W M95080-R M95080-DF
Maximum rating
8
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 7. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD
VO
Lead temperature during soldering
Output voltage
See note (1)
–0.50
VCC+0.6
VI
Input voltage
–0.50
6.5
6.5
5
V
VCC
IOL
Supply voltage
–0.50
V
DC output current (Q = 0)
DC output current (Q = 1)
Electrostatic discharge voltage (human body model)(2)
-
-
-
mA
mA
V
IOH
5
VESD
4000
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS)
2011/65/EU.
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
DocID022540 Rev 3
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43
DC and AC parameters
M95080-W M95080-R M95080-DF
9
DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Table 8. Operating conditions (M95080-W, device grade 6)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
2.5
5.5
85
V
–40
°C
Table 9. Operating conditions (M95080-R, device grade 6)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
1.8
5.5
85
V
–40
°C
Table 10. Operating conditions (M95080-DF, device grade 6)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
1.7
5.5
85
V
–40
°C
32/44
DocID022540 Rev 3
M95080-W M95080-R M95080-DF
Symbol
DC and AC parameters
Table 11. AC measurement conditions
Parameter Min.
Max.
Unit
CL
Load capacitance
Input rise and fall times
30
pF
ns
V
-
50
Input pulse voltages
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
Input and output timing reference voltages
V
Figure 18. AC measurement I/O waveform
)NPUT VOLTAGE LEVELS
)NPUT AND OUTPUT
TIMING REFERENCE LEVELS
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Table 12. Cycling performance
Test conditions
TA ≤ 25 °C,
Symbol
Parameter(1)
Min.
Max.
Unit
-
4,000,000
1,200,000
VCC(min) < VCC < VCC(max)
Ncycle
Write cycle endurance
Write cycle
TA = 85 °C,
-
VCC(min) < VCC < VCC(max)
1. Cycling performance for products identified by process letter K.
Table 13. Memory cell data retention
Test conditions
TA = 55 °C
Parameter
Data retention(1)
Min.
Unit
200
Year
1. For products identified by process letter K. The data retention behavior is checked in production, while the
200-year limit is defined from characterization and qualification results.
Table 14. Capacitance
Symbol
Parameter
Test conditions(1)
Min.
Max.
Unit
COUT
Output capacitance (Q)
Input capacitance (D)
VOUT = 0 V
VIN = 0 V
-
-
-
8
8
6
pF
pF
pF
CIN
Input capacitance (other pins)
VIN = 0 V
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
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DC and AC parameters
M95080-W M95080-R M95080-DF
Table 15. DC characteristics (M95080-W, device grade 6)
Test conditions in addition to those
defined in
Symbol
Parameter
Min.
Max.
Unit
Input leakage
current
ILI
V
IN = VSS or VCC
-
-
-
± 2
± 2
2
µA
µA
Output leakage
current
ILO
S = VCC, VOUT = VSS or VCC
V
CC = 2.5 V, fC = 5 MHz,
C = 0.1 VCC/0.9 VCC, Q = open
CC = 2.5 V, fC = 10 MHz,
V
Supply current
(Read)
ICC
-
2 (1)
mA
C = 0.1 VCC/0.9 VCC, Q = open
VCC = 5.5 V, fC = 20 MHz,
-
-
-
-
5 (2)
C = 0.1 VCC/0.9 VCC, Q = open
Supply current
(Write)
(3)
ICC0
During tW, S = VCC, 2.5 V < VCC < 5.5 V
5
3(4)
2(5)
mA
µA
S = VCC, VCC = 5.5 V,
VIN = VSS or VCC
,
Supply current
(Standby)
ICC1
S = VCC, VCC = 2.5 V,
VIN = VSS or VCC
,
VIL
VIH
VOL
Input low voltage
Input high voltage
-
-
–0.45 0.3 VCC
0.7 VCC VCC+1
V
V
V
Output low voltage IOL = 1.5 mA, VCC = 2.5 V
-
0.4
-
V
CC = 2.5 V and IOH = 0.4 mA or
VCC = 5.5 V and IOH = 2 mA
VOH
Output high voltage
0.8 VCC
V
V
Internal reset
threshold voltage
VRES
-
1.0(6)
1.65(7)
(3)
1. 5 mA for the devices identified with process letter G or S.
2. Only for the devices identified by process letter K.
3. Characterized only, not tested in production.
4. 2 µA for the devices identified by process letter G or S.
5. 1 µA for the devices identified by process letter G or S.
6. 0.5 V with the device identified by process letter K.
7. 1.5 V with the device identified by process letter K.
34/44
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M95080-W M95080-R M95080-DF
DC and AC parameters
Table 16. DC characteristics (M95080-R or M95080-DF, device grade 6)
Test conditions in addition to those
defined in in Table 9 or Table 10 and
Table 11(1)
Symbol
Parameter
Min.
Max.
Unit
ILI
Input leakage current
Output leakage current
VIN = VSS or VCC
-
-
± 2
± 2
µA
µA
ILO
S = VCC, voltage applied on Q = VSS or VCC
VCC = 1.8 V or 1.7 V, fC = 5 MHz,
C = 0.1 VCC/0.9 VCC, Q = open
ICC
Supply current (Read)
Supply current (Write)
Supply current (Standby)
-
-
-
2
5
1
mA
mA
µA
(2)
ICC0
VCC = 1.8 V or 1.7 V, during tW, S = VCC
VCC = 1.8 V or 1.7 V, S = VCC, VIN = VSS or
VCC
ICC1
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
VCC < 2.5 V
–0.45
0.75 VCC
-
0.25 VCC
V
V
V
V
VCC < 2.5 V
VCC+1
VOL
VOH
IOL = 0.15 mA, VCC = 1.8 V or 1.7 V
IOH = –0.1 mA, VCC = 1.8 V or 1.7 V
0.3
-
0.8 VCC
Internal reset threshold
voltage
(2)
VRES
-
1.0(3)
1.65(4)
V
1. If the application uses the M95080-R or M95080-DF devices with 2.5 V ≤VCC ≤5.5 V and -40 °C ≤TA ≤+85 °C, please refer to
Table 15: DC characteristics (M95080-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.
3. 0.5 V with the device identified by process letter K.
4. 1.5 V with the device identified by process letter K.
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DC and AC parameters
M95080-W M95080-R M95080-DF
Table 17. AC characteristics (M95080-W, device grade 6)
Test conditions specified in Table 8 and Table 11
(1)
VCC = 2.5 to 5.5 V
Parameter
VCC = 4.5 to 5.5 V
Symbol
Alt.
Unit
Min.
Max.
Min.
Max.
fC
fSCK Clock frequency
D.C.
30
30
40
30
30
40
40
-
10
-
D.C.
15
15
20
15
15
20
20
-
20
-
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
-
-
tCS
S deselect time
-
-
tCSH S active hold time
S not active hold time
tCLH Clock high time
tCLL Clock low time
-
-
-
-
(2)
tCH
-
-
(2)
tCL
-
-
(3)
tCLCH
tRC
tFC
Clock rise time
Clock fall time
2
2
-
2
2
-
(3)
tCHCL
-
-
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
10
10
30
30
0
5
tDH
Data in hold time
-
10
15
15
0
-
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
-
-
-
-
-
-
0
-
0
(3)
tSHQZ
tDIS Output disable time
tV Clock low to output valid
-
40
40
-
-
20
20
-
(4)
tCLQV
-
-
tCLQX
tHO Output hold time
tRO Output rise time
0
0
(3)
tQLQH
-
40
40
40
40
5
-
20
20
20
20
5
(3)
tQHQL
tFO
tLZ
tHZ
Output fall time
-
-
tHHQV
HOLD high to output valid
HOLD low to output high-Z
-
-
(3)
tHLQZ
-
-
tW
tWC Write time
-
-
1. Only for devices identified by process letter K.
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Characterized only, not tested in production.
4. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU
.
36/44
DocID022540 Rev 3
M95080-W M95080-R M95080-DF
DC and AC parameters
Table 18. AC characteristics (M95080-R or M95080-DF, device grade 6)
Test conditions specified in Table 9 or Table 10 and Table 11(1)
Symbol Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock frequency
D.C.
60
60
90
60
60
80
80
-
5
-
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH tCSS1 S active setup time
tSHCH tCSS2 S not active setup time
-
tSHSL
tCHSH
tCHSL
tCS S deselect time
-
tCSH S active hold time
-
S not active hold time
-
(2)
tCH
tCLH Clock high time
-
(2)
tCL
tCLL Clock low time
-
(3)
tCLCH
tRC Clock rise time
2
2
-
(3)
tCHCL
tFC Clock fall time
-
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
tDH Data in hold time
20
20
60
60
0
-
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
tDIS Output disable time
tV Clock low to output valid
tHO Output hold time
-
-
-
0
-
(3)
tSHQZ
tCLQV
tCLQX
-
80
80
-
-
0
(3)
tQLQH
tRO Output rise time
-
80
80
80
80
5
(3)
tQHQL
tHHQV
tFO Output fall time
-
tLZ HOLD high to output valid
tHZ HOLD low to output high-Z
tWC Write time
-
(3)
tHLQZ
tW
-
-
1. If the application uses the M95080-R or M95080-DF devices at 2.5 V ≤VCC ≤5.5 V and -40 °C ≤TA ≤+85 °C,
please refer to Table 15: DC characteristics (M95080-W, device grade 6), rather than to the above table.
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Characterized only, not tested in production.
DocID022540 Rev 3
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43
DC and AC parameters
M95080-W M95080-R M95080-DF
Figure 19. Serial input timing
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38/44
DocID022540 Rev 3
M95080-W M95080-R M95080-DF
Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
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Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
-
-
1.750
0.250
-
-
-
0.0689
0.0098
-
-
0.100
1.250
0.280
0.170
-
-
0.0039
0.0492
0.0110
0.0067
-
-
-
-
0.480
0.230
0.100
5.000
6.200
4.000
-
-
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
-
-
ccc
D
-
-
4.900
6.000
3.900
1.270
-
4.800
5.800
3.800
-
0.1929
0.2362
0.1535
0.0500
-
0.1890
0.2283
0.1496
-
E
E1
e
h
0.250
0°
0.500
8°
0.0098
0°
0.0197
8°
k
-
-
L
-
0.400
-
1.270
-
-
0.0157
-
0.0500
-
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
DocID022540 Rev 3
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43
Package mechanical data
M95080-W M95080-R M95080-DF
Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline
'
ꢊ
ꢄ
ꢇ
ꢈ
F
(ꢄ
(
D
$ꢄ
/
$
$ꢁ
/ꢄ
&3
E
H
76623ꢊ$0
1. Drawing is not to scale.
Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
0.100
3.100
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
-
-
0.050
0.800
0.190
0.090
-
-
0.0020
0.0315
0.0075
0.0035
-
1.000
-
0.0394
-
c
-
-
CP
D
-
-
3.000
0.650
6.400
4.400
0.600
1.000
-
2.900
-
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
-
0.1142
-
e
E
6.200
4.300
0.450
-
6.600
4.500
0.750
-
0.2441
0.1693
0.0177
-
0.2598
0.1772
0.0295
-
E1
L
L1
α
0°
8°
0°
8°
N
8
8
1. Values in inches are converted from mm and rounded to four decimal digits.
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M95080-W M95080-R M95080-DF
Package mechanical data
Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package
outline
Ğ
ď
ꢀ
Dꢄ
>ϭ
>ϯ
WŝŶꢃϭ
ꢁϮ
<
ꢁ
>
ꢂ
ꢀϮ
ĞĞĞ
ꢂϭ
1. Drawing is not to scale.
tͺDꢁĞsϮ
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 21. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.550
0.450
0.000
0.200
1.900
1.200
2.900
1.200
-
0.600
0.050
0.300
2.100
1.600
3.100
1.600
-
0.0217
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0472
-
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
0.0630
-
A1
0.020
0.0008
b
0.250
0.0098
D
2.000
0.0787
D2 (rev MC)
-
-
E
3.000
0.1181
E2 (rev MC)
-
-
e
0.500
0.0197
K (rev MC)
-
-
-
-
-
0.300
0.300
-
-
-
-
-
-
-
0.0118
0.0118
-
-
L
L1
0.500
0.150
-
0.0197
0.0059
-
L3
0.300
0.080
0.0118
0.0031
eee(2)
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
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43
Part numbering
M95080-W M95080-R M95080-DF
11
Part numbering
Table 22. Ordering information scheme
M95080-D
Example:
W MN 6
T
P
\S
Device type
M95 = SPI serial access EEPROM
Device function
080 = 8 Kbit (1024 x 8)
080-D = 8 Kbit (1024 x 8) plus identification page
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package(1)
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (MLP8)
Device grade
6 = Industrial temperature range, –40 to 85 °C
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)
Process(2)
/G, /S or /K = Manufacturing technology code
1. All packages are ECOPACK2® (RoHS compliant and halogen-free).
2. The process letters appear on the device package (marking) and on the shipment box. Please contact your
nearest ST Sales Office for further information.
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M95080-W M95080-R M95080-DF
Revision history
12
Revision history
Table 23. Document revision history
Changes
Date
Revision
22-Mar-2012
1
Initial release.
Replaced “M95080” by “M95080-DF” part number.
Updated:
– Package figure on cover page
– Features: Single supply voltage, high-speed clock frequency, write
cycles and data retention
– Section 1: Description
– Figure 3: Block diagram
– Section 6: Instructions: updated introduction and added Section 6.7 to
Section 6.10
– Section 7.2: Initial delivery state
– Note 1 in Table 7: Absolute maximum ratings
17-Sep-2013
2
– Table 15: DC characteristics (M95080-W, device grade 6), Table 16:
DC characteristics (M95080-R or M95080-DF, device grade 6),
Table 17: AC characteristics (M95080-W, device grade 6) and
Table 18: AC characteristics (M95080-R or M95080-DF, device grade
6).
– Figure 24: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no
lead, package outline and Table 21: UFDFPN8 (MLP8) – 8-lead ultra
thin fine pitch dual flat package no lead 2 x 3 mm, data
– Table 22: Ordering information scheme
Added Table 12: Cycling performance and Table 13: Memory cell data
retention.
Added on front page “Additional Write lockable Page (Identification
page)
05-Mar-2014
3
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43
M95080-W M95080-R M95080-DF
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