M95160-SMN5 [STMICROELECTRONICS]
2KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8;型号: | M95160-SMN5 |
厂家: | ST |
描述: | 2KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
文件: | 总21页 (文件大小:140K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M95160
M95080
16/8 Kbit Serial SPI Bus EEPROM
With High Speed Clock
■ SPI Bus Compatible Serial Interface
■ Supports Positive Clock SPI Modes
■ 5 MHz Clock Rate (maximum)
■ Single Supply Voltage:
8
8
– 4.5V to 5.5V for M95xxx
– 2.5V to 5.5V for M95xxx-W
– 1.8V to 3.6V for M95xxx-S
■ Status Register
1
1
SO8 (MN)
PDIP8 (BN)
150 mil width
■ Hardware and SoftwareProtection of the Status
0.25 mm frame
Register
■ BYTE and PAGE WRITE (up to 32 Bytes)
■ Self-Timed Programming Cycle
■ Adjustable Size Read-Only EEPROM Area
■ Enhanced ESD Protection
TSSOP8 (DW)
169 mil width
TSSOP14 (DL)
169 mil width
■ More than 1,000,000 Erase/Write Cycles
■ More than 40 Year Data Retention
DESCRIPTION
These SPI-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 2K x 8 bits (M95160) and 1K x 8 bits
(M95080), and operate down to 2.5 V (for the -W
version of each device), and down to 1.8 V (for the
-S version of each device).
Figure 1. Logic Diagram
V
CC
Table 1. Signal Names
D
C
Q
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
D
S
W
M95xxx
Q
S
HOLD
W
HOLD
V
SS
V
Supply Voltage
Ground
CC
AI01789C
V
SS
July 2001
1/21
M95160, M95080
Figure 2C. TSSOP14 Connections
Figure 2A. DIP Connections
M95xxx
M95xxx
S
Q
1
2
3
4
5
6
7
14
13
V
CC
HOLD
NC
NC
NC
C
S
Q
1
2
3
4
8
V
CC
HOLD
NC
NC
NC
W
12
7
11
W
6
5
C
D
10
V
SS
9
AI01790C
V
8
D
SS
AI02346B
Note: 1. NC = Not Connected
Figure 2B. SO8 and TSSOP8 Connections
The M95160 and M95080 are available in Plastic
Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages.
Each memory device is accessed by a simple
serial interface that is SPI bus compatible. The bus
signals are C, D and Q, as shown in Table 1 and
Figure 3.
M95xxx
S
Q
1
2
3
4
8
V
CC
HOLD
The device is selected when the chip select input
(S) is held low. Communications with the chip can
be interrupted using the hold input (HOLD).
7
W
6
5
C
D
V
SS
AI01791C
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
TA
Ambient Operating Temperature
–40 to 125
–65 to 150
TSTG
Storage Temperature
°C
PDIP8: 10 seconds
260
235
235
Lead Temperature during
Soldering
2
TLEAD
SO8: 20 seconds (max)
°C
2
TSSOP14:20 seconds (max)
VO
VI
Output Voltage
Input Voltage
Supply Voltage
–0.3 to VCC+0.6
–0.3 to 6.5
–0.3 to 6.5
4000
V
V
V
V
VCC
VESD
3
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
2/21
M95160, M95080
Figure 3. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
HOLD
W
HOLD
W
W
HOLD
AI03746C
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SIGNAL DESCRIPTION
Serial Output (Q)
The output pin is used to transfer data serially out
of the Memory. Data is shifted out on the falling
edge of the serial clock.
(though not to the WIP and WEL bits, which are
set or reset by the device internal logic).
Bit 7 of the status register (as shown in Table 5) is
the Status Register Write Disable bit (SRWD).
When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
bit (Write Enable Latch) has been set by the
WREN instruction (irrespective of the level being
applied to the W input).
Serial Input (D)
The input pin is used to transfer data serially into
the device. Instructions, addresses, and the data
to be written, are each received this way. Input is
latched on the rising edge of the serial clock.
When bit 7 (SRWD) of the status register is set to
1, the ability to write to the status register depends
on the logic level being presented at pin W:
Serial Clock (C)
The serial clock provides the timing for the serial
interface (as shown in Figure 4). Instructions,
addresses, or data are latched, from the input pin,
on the rising edge of the clock input. The output
data on the Q pin changes state after the falling
edge of the clock input.
– If W pin is high, it is possible to write to the
status register, after having set the WEL bit
using the WREN instruction (Write Enable
Latch).
– If W pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EEPROM area, protected by
the BPn bits of the status register, are also
hardware protected against data corruption,
and appear as a Read Only EEPROM area for
the microcontroller. This mode is called the
Hardware Protected Mode (HPM).
Chip Select (S)
When S is high, the memory device is deselected,
and the Q output pin is held in its high impedance
state. Unless an internal write operation is
underway, the memory device is placed in its
stand-by power mode.
After power-on, a high-to-low transition on S is
required prior to the start of any operation.
Write Protect (W)
The protection features of the memory device are
summarized in Table 3.
It is possible to enter the Hardware Protected
Mode (HPM) either by setting the SRWD bit after
pulling low the W pin, or by pulling low the W pin
after setting the SRWD bit.
The only way to abort the Hardware Protected
Mode, once entered, is to pull high the W pin.
The hardware write protection, controlled by the W
pin, restricts write access to the Status Register
3/21
M95160, M95080
Figure 4. Data and Clock Timing
CPOL
CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
If W pin is permanently tied to the high level, the
Hardware Protected Mode is never activated, and
the memory device only allows the user to protect
a part of the memory, using the BPn bits of the
status register, in the Software Protected Mode
(SPM).
is low. To restart communication with the device, it
is necessary both to remove the hold condition (by
taking HOLD high) and to select the memory (by
taking S low).
OPERATIONS
All instructions, addresses and data are shifted
serially in and out of the chip. The most significant
bit is presented first, with the data input (D)
sampled on the first rising edge of the clock (C)
after the chip select (S) goes low.
Every instruction starts with a single-byte code, as
summarised in Table 4. This code is entered via
the data input (D), and latched on the rising edge
of the clock input (C). To enter an instruction code,
the product must have been previously selected (S
held low). If an invalid instruction is sent (one not
contained in Table 4), the chip automatically
deselects itself.
Hold (HOLD)
The HOLD pin is used to pause the serial
communications between the SPI memory and
controller, without losing bits that have already
been decoded in the serial sequence. For a hold
condition to occur, the memory device must
already have been selected (S = 0). The hold
condition starts when the HOLD pin is held low
while the clock pin (C) is also low (as shown in
Figure 14).
During the hold condition, the Q output pin is held
in its high impedance state, and the levels on the
input pins (D and C) are ignored by the memory
device.
Write Enable (WREN) and Write Disable (WRDI)
The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR
operation. The WREN instruction (write enable)
It is possible to deselect the device when it is still
in the hold state, thereby resetting whatever
transfer had been in progress. The memory
remains in the hold state as long as the HOLD pin
Table 3. Write Protection Control on the M95160, M95080
SRWD
Data Bytes
W
Mode
Status Register
Bit
Protected Area
Unprotected Area
0 or 1
0
The data write protection is
defined by the BP1, BP0
bits. The BP1, BP0 bits can instruction has set the WEL
be modified by software
(using WREN and WRSR)
Software
Protected
(SPM)
Writeable (if the WREN
instruction has set the
WEL bit)
Writeable (if the WREN
1
0
1
1
bit)
The data write protection is
defined by the BP1, BP0
bits, which are, themselves,
hardware write protected.
Hardware
Protected
(HPM)
Writeable (if the WREN
instruction has set the WEL
bit)
Hardware write
protected
4/21
M95160, M95080
Figure 5. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
An - 31
An
32 Bytes
0000h
001Fh
X Decoder
AI01792C
Note: 1. The cell An represents the byte at the highest address in the memory
sets this latch, and the WRDI instruction (write
disable) resets it.
The latch becomes reset by any of the following
events:
Read Status Register (RDSR)
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended that the value of the
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 5) can be continuously polled,
before sending a new WRITE instruction. This can
be performed in one of two ways:
■ Repeated RDSR instructions (each one
consisting of Sbeing taken low, C being clocked
8 times for the instruction and 8 times for the
read operation, and S being taken high)
– Power on
– WRDI instruction completion
– WRSR instruction completion
– WRITE instruction completion.
As soon as the WREN or WRDI instruction is
received, the memory device first executes the
instruction, then enters a wait mode until the
device is deselected.
5/21
M95160, M95080
Table 4. Instruction Set
Instruc
reset (and any forthcoming Write instructions will
be ignored).
Instruction
Format
Description
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-
protected. These two bits are non-volatile. They
are set using a WRSR instruction.
tion
WREN Set Write Enable Latch
0000 0110
0000 0100
0000 0101
0000 0001
WRDI
RDSR
Reset Write Enable Latch
Read Status Register
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
(SRWD, BP0, BP1) become frozen at a constant
value. The updated value of these bits becomes
available when a new RDSR instruction is
executed, after completion of the write cycle. On
the other hand, the two read-only bits (WEL, WIP)
are dynamically updated during internal write
cycles. Using this facility, it is possible to poll the
WIP bit to detect the end of the internal write cycle.
WRSR Write Status Register
READ
Read Data from Memory Array 0000 0011
WRITE Write Data to Memory Array
0000 0010
Table 5. Status Register Format
b7
b0
SRWD
X
X
X
BP1 BP0 WEL WIP
Note: 1. SRWD, BP0 and BP1 are Read and write bits.
2. WEL and WIP are Read only bits.
Write Status Register (WRSR)
The format of the WRSR instruction is shown in
Figure 7. After the instruction and the eight bits of
the status register have been latched-in, the
internal Write cycle is triggered by the rising edge
of the S line. This must occur after the falling edge
■ A single, prolonged RDSR instruction
(consisting of S being taken low, C being
clocked 8 times for the instruction and kept
running for repeated read operations), as
shown in Figure 6.
th
of the 16 clock pulse, and before the rising edge
th
of the 17 clock (as indicated in Figure 7),
otherwise the internal write sequence is not
performed.
The Write-In-Process (WIP) bit is read-only, and
indicates whether the memory is busy with a Write
operation. A’1’ indicates that a writeis in progress,
and a ’0’ that no write is in progress.
The WRSR instruction is used for the following:
■ to select the size of memory area that is to be
write-protected
The Write Enable Latch (WEL) bit indicates the
status ofthe write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed in the previous paragraph, or as a result of
executing WREN or WRDI instruction. It cannot be
changed using a WRSR instruction. A ’1’ indicates
that the latch is set (the forthcoming Write
instruction will be executed), and a ’0’ that it is
■ to select between SPM (Software Protected
Mode) and HPM (Hardware Protected Mode).
The size of the write-protection area applies
equally in SPM and HPM. The BP1 and BP0 bits
of the status register have the appropriate value
(see Table 6) written into them after the contents
Figure 6. Read Status Register (RDSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031C
6/21
M95160, M95080
Table 6. Write Protected Block Size
Status Register Bits
Array Addresses Protected
Protected Block
BP1
BP0
M95160
none
M95080
none
0
0
1
1
0
1
0
1
none
Upper quarter
Upper half
0600h - 07FFh
0400h - 07FFh
0000h - 07FFh
0300h - 03FFh
0200h - 03FFh
0000h - 03FFh
Whole memory
of the protected area of the EEPROM have been
written.
Once the device is in the Hardware Protected
Mode, the data bytes in the protected area of the
memory array, and the content of the status
register, are write-protected. The only way to re-
enable writing new values to the status register is
to pull the W pin high. This cause the device to
leave the Hardware Protected Mode, and to revert
to being in the Software Protected Mode. (The
value in the BP1 and BP0 bits will not have been
changed).
The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.
Software Protected Mode (SPM)
The act of writing a non-zero value to the BP1 and
BP0 bits causes the Software Protected Mode
(SPM) to be started. All attempts to write a byte or
page in the protected area are ignored, even if the
Write Enable Latch is set. However, writing is still
allowed in the unprotected area of the memory
array and to the SRWD, BP1 and BP0 bits of the
status register, provided that the WEL bit is first
set.
Further details of the operation of Write Protect
(W) are given earlier, on page 3.
Typical Use of HPM and SPM
Write Protect (W) can be driven by an output port
of a microcontroller. It is important that Write
Protect (W) remains stable (permanently High, or
permanently Low) throughout the duration of the
Write Status Register sequence, shown in Figure
7).
Hardware Protected Mode (HPM)
The Hardware Protected Mode (HPM) offers a
higher level of protection, and can be selected by
setting the SRWD bit after pulling down the W pin
or by pulling down the W pin after setting the
SRWD bit. The SRWD is set by the WSR
instruction, provided that the WEL bit is first set.
The setting of the SRWD bit can be made
independently of, or at the same time as, writing a
new value to the BP1 and BP0 bits.
It is also possible to connect it permanently to V
SS
(by a solder connection, or through a pull-down
resistor). The manufacturer of such a printed
circuit board can take thememory device, still in its
initial delivery state, and can solder it directly on to
the board. After power on, the microcontroller can
Figure 7. Write Status Register (WRSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282C
7/21
M95160, M95080
Figure 8. Read from Memory Array (READ) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
C
Instruction
16 Bit Address
15 14 13
3
2
1
0
D
Q
Data Out
High Impedance
7
6
5
4
3
2
0
1
MSB
AI01793C
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
be instructed to write the protected data into the
appropriate area of the memory. When it has
finished, the appropriate values are written to the
BP1, BP0 and SRWD bits, thereby putting the
device in the hardware protected mode.
Table 7. Address Range Bits
Device
Address Bits
M95160
M95080
A9-A0
A10-A0
Note: 1. Other address bits up to b15 are treated as Don’t Care.
An alternative method is to write the protected
data, and to set the BP1, BP0 and SRWD bits,
before soldering the memory device to the board.
Again, this results in the memory device being
placed in its hardware protected mode.
Read Operation
The chip is first selected by holding S low. The
serial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C).
The data stored in the memory, at the selected
address, is shifted out on the Q output pin. Each
bit is shifted out during the falling edge of the clock
(C) as shown in Figure 8. The internal address
counter is automatically incremented to the next
higher address after each byte of data has been
shifted out. The data stored in the memory, at the
next address, can be read by successive clock
If the W pin has been connected to V by a pull-
SS
down resistor, the memory device can be taken
out of the hardware protected mode by driving the
W pin high, to override the pull-down resistor.
If the W pin has been directly soldered to V
,
SS
there is only one way of taking the memory device
out of the hardware protected mode: the memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Figure 9. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281D
8/21
M95160, M95080
Figure 10. Byte Write to Memory Array (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16 Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795C
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
pulses. When the highest address is reached, the
address counter rolls over to “0000h”, allowing the
read cycle to be continued indefinitely. The read
operation is terminated by deselecting the chip.
The chip can be deselected at any time during
data output. If a read instruction is received during
a write cycle, it is rejected, and the memory device
deselects itself.
Byte Write Operation
Before any write can take place, the WEL bit must
be set, using the WREN instruction. The write
state is entered by selecting the chip, issuing three
Figure 11. Page Write to Memory Array (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
D
Instruction
16 Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796C
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
9/21
M95160, M95080
bytes of instruction and address, and one byte of
data. Chip Select (S) must remain low throughout
the operation, as shown in Figure 10. The product
must be deselected just after the eighth bit of the
data byte has been latched in, as shown in Figure
10, otherwise the write process is cancelled. As
soon as the memory device is deselected, the self-
timed internal write cycle is initiated. While the
write is in progress, the status register may be
read to check the status of the SRWD, BP1, BP0,
WEL and WIP bits. In particular, WIP contains a ‘1’
during the self-timed write cycle, and a ‘0’ when
the cycle is complete, (at which point the write
enable latch is also reset).
– After execution of a WREN, WRDI, or RDSR
instruction, the chip enters a wait state, and
waits to be deselected.
– Invalid S and HOLD transitions are ignored.
POWER ON STATE
After power-on, the memory device is in the
following state:
– low power stand-by state
– deselected (after power-on, a high-to-low
transition is required on the S input before any
operations can be started).
– not in the hold condition
– the WEL bit is reset
Page Write Operation
A maximum of 32 bytes of data can be written
– the SRWD, BP1 and BP0 bits of the status
register are unchanged from the previous
power-down (they are non-volatile bits).
during one Write time, t , provided that they are all
W
to the same page (see Figure 5). The Page Write
operation is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 31 additional bytes can
be shifted in (and then the device is deselected
after the last byte).
Table 8. Initial Status Register Format
b7
0
b0
0
Any address of the memory can be chosen as the
first address to be written. If the address counter
reaches the end of the page (an address of the
form xxxx xxxx xxx1 1111) and the clock
continues, the counter rolls over to the first
address of the same page (xxxx xxxx xxx0 0000)
and over-writes any previously written data.
0
0
0
0
0
0
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all 1s, FFh). The
status register bits are initialized to 00h, as shown
in Table 8.
As before, the Write cycle only starts if the S
transition occurs just after the eighth bit of the last
data byte has been received, as shown in Figure
11.
DATA PROTECTION AND PROTOCOL SAFETY
To protect the data in the memory from inadvertent
corruption, the memory device only responds to
correctly formulated commands. The main
security measures can be summarised as follows:
– The WEL bit is reset at power-up.
– S must rise after the eighth clock count (or
multiple thereof) in order to start a non-volatile
write cycle (in the memory array or in the status
register).
– Accesses to the memory array are ignored
during the non-volatile programming cycle, and
the programming cycle continues unaffected.
1
Table 9. Input Parameters (T = 25 °C, f = 5 MHz)
A
Symbol
COUT
CIN
Parameter
Test Condition
Min.
Max.
Unit
pF
Output Capacitance (Q)
Input Capacitance (other pins)
8
6
pF
Note: 1. Sampled only, not 100% tested.
10/21
M95160, M95080
Table 10. DC Characteristics
(T = –40 to 85 °C or –40 to 125 °C; V = 4.5 to 5.5 V)
A
CC
(T = –40 to 85 °C or –40 to 125 °C; V = 2.5 to 5.5 V)
A
CC
(T = –20 to 85 °C; V = 1.8 to 3.6 V)
A
CC
Voltage Temp.
Range Range
Symbol
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
± 2
4
Unit
µA
Input Leakage
Current
2
ILI
all
all
6
all
all
Output Leakage
Current
2
ILO
All inputs driven to VSS or VCC
C = 0.1VCC/0.9VCC , at 5 MHz,
CC = 5 V, Q = open
C = 0.1VCC/0.9VCC , at 2 MHz,
CC = 5 V, Q = open
C = 0.1VCC/0.9VCC , at 2 MHz,
µA
mA
V
4.5-5.5
2.5-5.5
3
4
mA
V
ICC
Supply Current
6
3
5
2
5
2
mA
mA
mA
V
CC = 2.5 V, Q = open
C = 0.1VCC/0.9VCC , at 2 MHz,
V
CC = 2.5 V, Q = open
C = 0.1VCC/0.9VCC , at 1 MHz,
2
1.8-3.6
V
CC = 1.8 V, Q = open
4.5-5.5
2.5-5.5
S = VCC, VIN = VSS or VCC , VCC = 5 V
S = VCC, VIN = VSS or VCC , VCC = 2.5 V
10
2
µA
µA
µA
Supply Current
(Stand-by)
ICC1
2
S = VCC, VIN = VSS or VCC , VCC = 1.8 V
1
1.8-3.6
Input Low
Voltage
2
VIL
VIH
all
all
– 0.3
0.3 VCC
VCC+1
V
V
all
Input High
Voltage
2
0.7 VCC
all
1
IOL = 2 mA
OL = 1.5 mA
0.4
0.4
0.3
V
V
V
4.5-5.5
Output Low
Voltage
I
2.5-5.5
VOL
2
IOL = 0.15 mA
IOH = –2 mA
1.8-3.6
4.5-5.5
1
0.8 VCC
0.8 VCC
0.8 VCC
V
V
V
Output High
Voltage
2.5-5.5
I
OH = –0.4 mA
VOH
2
IOH = –0.1 mA
1.8-3.6
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Preliminary data, for the 1.8V to 3.6 supply voltage range devices.
11/21
M95160, M95080
Table 11A. AC Characteristics
M95160, M95080
=4.5 to 5.5 V =4.5 to 5.5 V
V
V
CC
CC
Symbol
Alt.
Parameter
Unit
T =–40 to 85°C T =–40 to 125°C
A
A
Min
D.C.
Max
Min
Max
f
f
Clock Frequency
5
D.C.
200
200
200
200
200
200
2
MHz
ns
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
90
90
SLCH
t
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
1
t
90
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
Clock Fall Time
90
200
ns
µs
µs
t
CLL
CL
2
2
t
1
1
1
1
t
RC
CLCH
t
t
FC
CHCL
t
t
DSU
Data In Setup Time
20
30
70
40
0
40
50
140
90
0
ns
ns
ns
ns
ns
ns
DVCH
CHDX
HHCH
t
t
t
Data In Hold Time
DH
t
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
CD
t
HLCH
t
CLHL
t
0
0
CLHH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
100
60
250
150
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
HO
0
0
CLQX
2
t
Output Rise Time
50
50
100
100
t
t
t
RO
QLQH
QHQL
HHQX
2
2
2
t
Output Fall Time
ns
FO
t
HOLD High to Output Low-Z
HOLD Low to Output High-Z
Write Time
50
100
10
100
250
10
ns
ns
LZ
t
t
HZ
HLQZ
t
t
WC
ms
W
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
12/21
M95160, M95080
Table 11B. AC Characteristics
3
M95xxx-W
=2.5 to 5.5 V
T =–40 to 85°C or
T =–40 to 125°C
M95xxx-R
V
CC
V
=1.8 to 3.6 V
T =–20 to 85°C
CC
Symbol
Alt.
Parameter
Unit
A
A
A
Min
D.C.
200
200
200
200
200
Max
Min
D.C.
400
400
300
400
400
Max
f
f
SCK
Clock Frequency
2
1
MHz
ns
C
t
t
CSS1
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
t
CSS2
ns
SHCH
t
t
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
ns
CHSL
1
t
200
200
400
400
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
ns
t
CLL
CL
2
t
1
1
1
1
µs
t
RC
CLCH
2
t
Clock Fall Time
µs
ns
ns
ns
ns
ns
t
FC
CHCL
t
t
t
t
DSU
Data In Setup Time
40
50
140
90
0
60
100
350
200
0
DVCH
CHDX
HHCH
t
Data In Hold Time
DH
t
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
CD
t
HLCH
t
CLHL
Clock Low Set-up Time before HOLD not
Active
t
0
0
ns
CLHH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
250
150
500
380
ns
ns
ns
ns
t
t
DIS
SHQZ
t
t
CLQV
V
t
t
HO
0
0
CLQX
2
t
Output Rise Time
100
100
200
200
RO
QLQH
QHQL
HHQX
2
2
2
t
Output Fall Time
ns
t
t
FO
t
HOLD High to Output Low-Z
HOLD Low to Output High-Z
Write Time
100
250
10
250
500
10
ns
ns
LZ
t
t
HZ
HLQZ
t
t
WC
ms
W
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data, for the 1.8V to 3.6 supply voltage range devices.
13/21
M95160, M95080
Table 12. AC Measurement Conditions
Figure 12. AC Testing Input Output Waveforms
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.8V
CC
0.7V
CC
0.2V to 0.8V
CC
CC
0.3V
CC
Input and Output Timing
Reference Voltages
0.3V to 0.7V
0.2V
CC
CC
CC
AI00825
C = 100 pF
L
Output Load
Note: 1. Output Hi-Z is defined as the point where data is no long-
er driven.
Figure 13. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 14. Hold Timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQX
tHLQZ
Q
D
HOLD
AI01448
14/21
M95160, M95080
Figure 15. Output Timing
S
tCH
C
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
ADDR.LSB IN
D
AI01449C
ORDERING INFORMATION
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
The notation used for the device number is as
shown in Table 13. For a list of available options
Table 13. Ordering Information Scheme
Example:
M95160
–
W
MN
6
T
3
Option
Memory Capacity
160
080
16 Kbit (2K x 8) with positive clock strobe
8 Kbit (1K x 8) with positive clock strobe
T
Tape and Reel Packing
Temperature Range
–20 °C to 85 °C
5
6
–40 °C to 85 °C
1
–40 °C to 125 °C
3
Operating Voltage
Package
blank 4.5 V to 5.5 V
BN PDIP8 (0.25 mm frame)
W
2.5 V to 5.5 V
1.8 V to 3.6 V
MN SO8 (150 mil width)
2
4
TSSOP14 (169 mil width)
TSSOP8 (169 mil width)
S
DL
5
DW
Note: 1. Produced with High Reliability Certified Flow (HRCF).
2. The -S version (V range 1.8 V to 3.6 V) only available in temperature ranges 5.
CC
3. All devices use a positive clock strobe: Data In is strobed on the rising edge of the clock (C) and Data Out is synchronised from the
falling edge of the clock.
4. TSSOP14, 169 mil width, package is available for the M95160 series only.
5. TSSOP8, 169 mil width, package is available for the M95080 series only.
15/21
M95160, M95080
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
E
b2
A2
A
L
A1
c
b
e
eA
eB
D
8
1
E1
PDIP-8
Note: 1. Drawing is not to scale.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
10.16
8.26
7.11
–
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
16/21
M95160, M95080
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
h x 45°
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Symb.
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
17/21
M95160, M95080
TSSOP8 – 8 lead Thin Shrink Small Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8-M
Note: 1. Drawing is not to scale.
TSSOP8 – 8 lead Thin Shrink Small Outline
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
18/21
M95160, M95080
TSSOP14 - 14 lead Thin Shrink Small Outline
D
14
8
c
E1
E
1
7
α
A1
L
A
A2
L1
CP
b
e
TSSOP14-M
Note: 1. Drawing is not to scale.
TSSOP14 - 14 lead Thin Shrink Small Outline
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
5.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.2008
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
5.000
0.650
6.400
4.400
0.600
1.000
4.900
–
0.1969
0.0256
0.2520
0.1732
0.0236
0.0394
0.1929
–
e
E
6.200
4.300
0.500
6.600
4.500
0.750
0.2441
0.1693
0.0197
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
19/21
M95160, M95080
Table 14. Revision History
Date
Rev.
Description of Revision
19-Jul-2001
1.0
Document written from previous M95640/320/160/080 data sheet
20/21
M95160, M95080
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
www.st.com
21/21
相关型号:
M95160-VBN1
2KX8 SPI BUS SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8
STMICROELECTR
M95160-VBN5
2KX8 SPI BUS SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明