M95256-MW5 [STMICROELECTRONICS]
32KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.200 INCH, PLASTIC, SO-8;
| 型号： | M95256-MW5 |
| 厂家： | 
ST |
| 描述： | 32KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.200 INCH, PLASTIC, SO-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总21页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95256
M95128
256/128 Kbit Serial SPI Bus EEPROM
With High Speed Clock
PRELIMINARY DATA
■ SPI Bus Compatible Serial Interface
■ Supports Positive Clock SPI Modes
■ 5 MHz Clock Rate (maximum)
■ Single Supply Voltage:
14
8
– 4.5V to 5.5V for M95xxx
– 2.7V to 3.6V for M95xxx-V
– 2.5V to 5.5V for M95xxx-W
– 1.8V to 3.6V for M95xxx-R
■ Status Register
1
1
PSDIP8 (BN)
0.25 mm frame
TSSOP14 (DL)
169 mil width
■ Hardware and Software Protection of the Status
Register
8
8
■ BYTE and PAGE WRITE (up to 64 Bytes)
■ Self-Timed Programming Cycle
1
1
■ Resizeable Read-Only EEPROM Area
■ Enhanced ESD Protection
SO8 (MN)
SO8 (MW)
150 mil width
200 mil width
■ 100,000 Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)
DESCRIPTION
These SPI-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 32K x 8 bits (M95256) and 16K x 8
bits (M95128), and operate down to 2.7 V (for the
Figure 1. Logic Diagram
V
CC
Table 1. Signal Names
D
C
S
Q
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
D
M95xxx
Q
W
S
HOLD
W
HOLD
V
SS
V
Supply Voltage
Ground
CC
AI01789C
V
SS
March 2000
1/21
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M95256, M95128
Figure 2C. TSSOP Connections
Figure 2A. DIP Connections
M95128
M95xxx
S
Q
1
2
3
4
5
6
7
14
13
V
CC
HOLD
NC
NC
NC
C
S
Q
1
2
3
4
8
V
CC
HOLD
NC
NC
NC
W
12
7
11
W
6
5
C
D
10
V
SS
9
AI01790C
V
8
D
SS
AI02346
Note: 1. NC = Not Connected
Figure 2B. SO Connections
-V version), 2.5 V (for the -W version), and down
to 1.8 V (for the -R version of each device).
The M95256 and M95128 are available in Plastic
Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages.
M95xxx
Each memory device is accessed by a simple
serial interface that is SPI bus compatible. The bus
signals are C, D and Q, as shown in Table 1 and
Figure 3.
The device is selected when the chip select input
(S) is held low. Communications with the chip can
be interrupted using the hold input (HOLD).
S
Q
1
2
3
4
8
V
CC
HOLD
7
W
6
5
C
D
V
SS
AI01791C
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
TA
Ambient Operating Temperature
-40 to 125
-65 to 150
TSTG
Storage Temperature
°C
PSDIP8: 10 sec
SO8: 40 sec
260
215
TLEAD
Lead Temperature during Soldering
°C
TSSOP14: t.b.c.
t.b.c.
VO
VI
-0.3 to VCC+0.6
-0.3 to 6.5
-0.3 to 6.5
4000
Output Voltage Range
Input Voltage Range
Supply Voltage Range
V
V
V
V
VCC
VESD
2
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality
documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
2/21
M95256, M95128
Figure 3. Microcontroller and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')
SDI
SCK
Master
(ST6, ST7, ST9,
ST10, Others)
C
Q
D
C
Q
D
C Q D
M95xxx
M95xxx
M95xxx
CS3 CS2 CS1
S
S
S
AI01958C
SIGNAL DESCRIPTION
Serial Output (Q)
The output pin is used to transfer data serially out
of the Memory. Data is shifted out on the falling
edge of the serial clock.
(though not to the WIP and WEL bits, which are
set or reset by the device internal logic).
Bit 7 of the status register (as shown in Table 5) is
the Status Register Write Disable bit (SRWD).
When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
bit (Write Enable Latch) has been set by the
WREN instruction (irrespective of the level being
applied to the W input).
When bit 7 (SRWD) of the status register is set to
1, the ability to write to the status register depends
on the logic level being presented at pin W:
Serial Input (D)
The input pin is used to transfer data serially into
the device. Instructions, addresses, and the data
to be written, are each received this way. Input is
latched on the rising edge of the serial clock.
Serial Clock (C)
The serial clock provides the timing for the serial
interface (as shown in Figure 4). Instructions,
addresses, or data are latched, from the input pin,
on the rising edge of the clock input. The output
data on the Q pin changes state after the falling
edge of the clock input.
– If W pin is high, it is possible to write to the
status register, after having set the WEL bit
using the WREN instruction (Write Enable
Latch).
– If W pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EEPROM area, protected by
the BPn bits of the status register, are also
hardware protected against data corruption,
and appear as a Read Only EEPROM area for
the microcontroller. This mode is called the
Hardware Protected Mode (HPM).
It is possible to enter the Hardware Protected
Mode (HPM) either by setting the SRWD bit after
pulling low the W pin, or by pulling low the W pin
after setting the SRWD bit.
The only way to abort the Hardware Protected
Mode, once entered, is to pull high the W pin.
Chip Select (S)
When S is high, the memory device is deselected,
and the Q output pin is held in its high impedance
state. Unless an internal write operation is
underway, the memory device is placed in its
stand-by power mode.
After power-on, a high-to-low transition on S is
required prior to the start of any operation.
Write Protect (W)
The protection features of the memory device are
summarized in Table 3.
The hardware write protection, controlled by the W
pin, restricts write access to the Status Register
If W pin is permanently tied to the high level, the
Hardware Protected Mode is never activated, and
3/21
M95256, M95128
Figure 4. Data and Clock Timing
CPOL
CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
the memory device only allows the user to protect
a part of the memory, using the BPn bits of the
status register, in the Software Protected Mode
(SPM).
OPERATIONS
All instructions, addresses and data are shifted
serially in and out of the chip. The most significant
bit is presented first, with the data input (D)
sampled on the first rising edge of the clock (C)
after the chip select (S) goes low.
Every instruction starts with a single-byte code, as
summarized in Table 4. This code is entered via
the data input (D), and latched on the rising edge
of the clock input (C). To enter an instruction code,
the product must have been previously selected (S
held low). If an invalid instruction is sent (one not
contained in Table 4), the chip automatically
deselects itself.
Hold (HOLD)
The HOLD pin is used to pause the serial
communications between the SPI memory and
controller, without losing bits that have already
been decoded in the serial sequence. For a hold
condition to occur, the memory device must
already have been selected (S = 0). The hold
condition starts when the HOLD pin is held low
while the clock pin (C) is also low (as shown in
Figure 5).
During the hold condition, the Q output pin is held
in its high impedance state, and the levels on the
input pins (D and C) are ignored by the memory
device.
It is possible to deselect the device when it is still
in the hold state, thereby resetting whatever
transfer had been in progress. The memory
remains in the hold state as long as the HOLD pin
is low. To restart communication with the device, it
is necessary both to remove the hold condition (by
taking HOLD high) and to select the memory (by
taking S low).
Write Enable (WREN) and Write Disable (WRDI)
The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR
operation. The WREN instruction (write enable)
sets this latch, and the WRDI instruction (write
disable) resets it.
The latch becomes reset by any of the following
events:
– Power on
– WRDI instruction completion
– WRSR instruction completion
– WRITE instruction completion.
Table 3. Write Protection Control on the M95256 and M95128
SRWD
Data Bytes
W
Mode
Status Register
Bit
Protected Area
Unprotected Area
0 or 1
1
0
1
Software
Protected
(SPM)
Writeable (if the WREN
instruction has set the
WEL bit)
Software write protected
by the BPn of the status
register
Writeable (if the WREN
instruction has set the
WEL bit)
Hardware
Protected
(HPM)
Hardware write protected
by the BPn bits of the
status register
Writeable (if the WREN
instruction has set the
WEL bit)
0
1
Hardware write protected
4/21
M95256, M95128
Figure 5. Hold Condition Activation
CLOCK
HOLD PIN
MEMORY
ACTIVE
HOLD
ACTIVE
HOLD
ACTIVE
STATUS
AI02029B
Figure 6. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
area of the
EEPROM
An - 63
An
64 Bytes
0000h
003Fh
X Decoder
AI02030B
Note: 1. The cell An represents the byte at the highest address in the memory
5/21
M95256, M95128
Table 4. Instruction Set
Instruc
Its value can only be changed by one of the events
listed in the previous paragraph, or as a result of
executing WREN or WRDI instruction. It cannot be
changed using a WRSR instruction. A ’1’ indicates
that the latch is set (the forthcoming Write
instruction will be executed), and a ’0’ that it is
reset (and any forthcoming Write instructions will
be ignored).
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-
protected. These two bits are non-volatile. They
are set using a WRSR instruction.
Instruction
Format
Description
tion
WREN Set Write Enable Latch
0000 0110
0000 0100
0000 0101
0000 0001
WRDI
RDSR
Reset Write Enable Latch
Read Status Register
WRSR Write Status Register
READ
Read Data from Memory Array 0000 0011
WRITE Write Data to Memory Array
0000 0010
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
(SRWD, BP0, BP1) become frozen at a constant
value. The updated value of these bits becomes
available when a new RDSR instruction is
executed, after completion of the write cycle. On
the other hand, the two read-only bits (WEL, WIP)
are dynamically updated during internal write
cycles. Using this facility, it is possible to poll the
WIP bit to detect the end of the internal write cycle.
Table 5. Status Register Format
b7
b0
SRWD
X
X
X
BP1 BP0 WEL WIP
Note: 1. SRWD, BP0 and BP1 are Read and write bits.
2. WEL and WIP are Read only bits.
As soon as the WREN or WRDI instruction is
received, the memory device first executes the
instruction, then enters a wait mode until the
device is deselected.
Write Status Register (WRSR)
Read Status Register (RDSR)
The format of the WRSR instruction is shown in
Figure 8. After the instruction and the eight bits of
the status register have been latched-in, the
internal Write cycle is triggered by the rising edge
of the S line. This must occur before the rising
edge of the 17 clock pulse (as indicated in Figure
14), otherwise the internal write sequence is not
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended that the value of the
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 5) can be continuously polled,
before sending a new WRITE instruction, using
the timing shown in Figure 7. The Write-In-
Process (WIP) bit is read-only, and indicates
whether the memory is busy with a Write
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.
th
performed.
The WRSR instruction is used for the following:
■ to select the size of memory area that is to be
write-protected
■ to select between SPM (Software Protected
Mode) and HPM (Hardware Protected Mode).
The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Figure 7. RDSR: Read Status Register Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
D
INSTRUCTION
STATUS REG. OUT
STATUS REG. OUT
HIGH IMPEDANCE
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
MSB
AI02031
6/21
M95256, M95128
Table 6. Write Protected Block Size
Status Register Bits
Array Addresses Protected
Protected Block
BP1
BP0
M95256
none
M95128
none
0
0
1
1
0
1
0
1
none
Upper quarter
Upper half
6000h - 7FFFh
4000h - 7FFFh
0000h - 7FFFh
3000h - 3FFFh
2000h - 3FFFh
0000h - 3FFFh
Whole memory
The size of the write-protection area applies
equally in SPM and HPM. The BP1 and BP0 bits
of the status register have the appropriate value
(see Table 6) written into them after the contents
of the protected area of the EEPROM have been
written.
The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.
Software Protected Mode (SPM)
The act of writing a non-zero value to the BP1 and
BP0 bits causes the Software Protected Mode
(SPM) to be started. All attempts to write a byte or
page in the protected area are ignored, even if the
Write Enable Latch is set. However, writing is still
allowed in the unprotected area of the memory
array and to the SRWD, BP1 and BP0 bits of the
status register, provided that the WEL bit is first
set.
The setting of the SRWD bit can be made
independently of, or at the same time as, writing a
new value to the BP1 and BP0 bits.
Once the device is in the Hardware Protected
Mode, the data bytes in the protected area of the
memory array, and the content of the status
register, are write-protected. The only way to re-
enable writing new values to the status register is
to pull the W pin high. This cause the device to
leave the Hardware Protected Mode, and to revert
to being in the Software Protected Mode. (The
value in the BP1 and BP0 bits will not have been
changed).
Further details of the operation of the Write Protect
pin (W) is given earlier, on page 3.
Typical Use of HPM and SPM
The W pin can be dynamically driven by an output
port of a microcontroller. It is also possible,
Hardware Protected Mode (HPM)
though, to connect it permanently to V
(by a
SS
The Hardware Protected Mode (HPM) offers a
higher level of protection, and can be selected by
setting the SRWD bit after pulling down the W pin
or by pulling down the W pin after setting the
SRWD bit. The SRWD is set by the WSR
instruction, provided that the WEL bit is first set.
solder connection, or through
a
pull-down
resistor). The manufacturer of such a printed
circuit board can take the memory device, still in its
initial delivery state, and can solder it directly on to
the board. After power on, the microcontroller can
be instructed to write the protected data into the
Figure 8. WRSR: Write Status Register Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
STATUS REG.
C
INSTRUCTION
7
6
5
4
3
2
0
1
D
Q
MSB
HIGH IMPEDANCE
AI02282
7/21
M95256, M95128
Figure 9. Read EEPROM Array Operation Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
C
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
D
Q
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
0
1
MSB
AI01793
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
Table 7. Address Range Bits
out of the hardware protected mode by driving the
W pin high, to override the pull-down resistor.
Device
M95256
M95128
If the W pin has been directly soldered to V
,
SS
Address Bits
A14-A0
A13-A0
there is only one way of taking the memory device
out of the hardware protected mode: the memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Note: 1. b15 is Don’t Care on the M95256 series.
b15 and b14 are Don’t Care on the M95128 series.
appropriate area of the memory. When it has
finished, the appropriate values are written to the
BP1, BP0 and SRWD bits, thereby putting the
device in the hardware protected mode.
An alternative method is to write the protected
data, and to set the BP1, BP0 and SRWD bits,
before soldering the memory device to the board.
Again, this results in the memory device being
placed in its hardware protected mode.
Read Operation
The chip is first selected by holding S low. The
serial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C).
The data stored in the memory, at the selected
address, is shifted out on the Q output pin. Each
bit is shifted out during the falling edge of the clock
(C) as shown in Figure 9. The internal address
counter is automatically incremented to the next
higher address after each byte of data has been
shifted out. The data stored in the memory, at the
If the W pin has been connected to V by a pull-
down resistor, the memory device can be taken
SS
Figure 10. Write Enable Latch Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
INSTRUCTION
HIGH IMPEDANCE
AI02281B
8/21
M95256, M95128
Figure 11. Byte Write Operation Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
INSTRUCTION
16 BIT ADDRESS
DATA BYTE
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
HIGH IMPEDANCE
AI01795
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
next address, can be read by successive clock
pulses. When the highest address is reached, the
address counter rolls over to “0000h”, allowing the
read cycle to be continued indefinitely. The read
operation is terminated by deselecting the chip.
The chip can be deselected at any time during
data output. If a read instruction is received during
a write cycle, it is rejected, and the memory device
deselects itself.
Byte Write Operation
Before any write can take place, the WEL bit must
be set, using the WREN instruction. The write
state is entered by selecting the chip, issuing three
Figure 12. Page Write Operation Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
D
INSTRUCTION
16 BIT ADDRESS
DATA BYTE 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
9/21
M95256, M95128
bytes of instruction and address, and one byte of
data. Chip Select (S) must remain low throughout
the operation, as shown in Figure 11. The product
must be deselected just after the eighth bit of the
data byte has been latched in, otherwise the write
process is cancelled. As soon as the memory
device is deselected, the self-timed internal write
cycle is initiated. While the write is in progress, the
status register may be read to check the status of
the SRWD, BP1, BP0, WEL and WIP bits. In
particular, WIP contains a ‘1’ during the self-timed
write cycle, and a ‘0’ when the cycle is complete,
(at which point the write enable latch is also reset).
DATA PROTECTION AND PROTOCOL SAFETY
To protect the data in the memory from inadvertent
corruption, the memory device only responds to
correctly formulated commands. The main
security measures can be summarized as follows:
– The WEL bit is reset at power-up.
– S must rise after the eighth clock count (or
multiple thereof) in order to start a non-volatile
write cycle (in the memory array or in the status
register).
– Accesses to the memory array are ignored
during the non-volatile programming cycle, and
the programming cycle continues unaffected.
Page Write Operation
– After execution of a WREN, WRDI, or RDSR
instruction, the chip enters a wait state, and
waits to be deselected.
A maximum of 64 bytes of data can be written
during one Write time, t , provided that they are all
W
to the same page (see Figure 6). The Page Write
operation is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 63 additional bytes can
be shifted in (and then the device is deselected
after the last byte).
– Invalid S and HOLD transitions are ignored.
POWER ON STATE
After power-on, the memory device is in the
following state:
Any address of the memory can be chosen as the
first address to be written. If the address counter
reaches the end of the page (an address of the
form xxxx xx11 1111) and the clock continues, the
counter rolls over to the first address of the same
page (xxxx xx00 0000) and over-writes any
previously written data.
– low power stand-by state
– deselected (after power-on,
transition is required on the S input before any
operations can be started).
– not in the hold condition
– the WEL bit is reset
a high-to-low
As before, the Write cycle only starts if the S
transition occurs just after the eighth bit of the last
data byte has been received, as shown in Figure
12.
– the SRWD, BP1 and BP0 bits of the status
register are un-changed from the previous
power-down (they are non-volatile bits).
INITIAL DELIVERY STATE
Table 8. Initial Status Register Format
The device is delivered with the memory array in a
fully erased state (all data set at all “1’s” or FFh).
The status register bits are initialized to 00h, as
shown in Table 8.
b7
0
b0
0
0
0
0
0
0
0
Table 9. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.2V to 0.8V
Figure 13. AC Testing Input Output Waveforms
CC
CC
CC
0.8V
CC
Input and Output Timing
Reference Voltages
0.7V
CC
0.3V to 0.7V
CC
0.3V
CC
C = 100 pF
L
Output Load
0.2V
CC
Note: 1. Output Hi-Z is defined as the point where data is no
longer driven.
AI00825
1
Table 10. Input Parameters (T = 25 °C, f = 5 MHz)
A
Symbol
COUT
Parameter
Test Condition
Min.
Max.
Unit
pF
Output Capacitance (Q)
Input Capacitance (other pins)
8
6
CIN
pF
Note: 1. Sampled only, not 100% tested.
10/21
M95256, M95128
Table 11. DC Characteristics
(T = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; V = 4.5 to 5.5 V)
A
CC
(T = 0 to 70 °C or –40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
(T = 0 to 70 °C or –40 to 85 °C; V = 2.5 to 5.5 V)
A
CC
(T = 0 to 70 °C or –20 to 85 °C; V = 1.8 to 3.6 V)
A
CC
Voltage Temp.
Range Range
Symbol
Parameter
Test Condition
Min.
Max.
± 2
± 2
4
Unit
µA
Input Leakage
Current
ILI
all
all
all
all
6
Output Leakage
Current
ILO
µA
C = 0.1 VCC/0.9. VCC at 5 MHz,
VCC = 5 V, Q = open
4.5-5.5
mA
C = 0.1 VCC/0.9. VCC at 2 MHz,
VCC = 5 V, Q = open
4.5-5.5
3
4
mA
ICC
Supply Current
C = 0.1 VCC/0.9. VCC at 5 MHz,
VCC = 2.7 V, Q = open
2.7-3.6
2.5-5.5
1.8-3.6
6
6
5
3
2
2
mA
mA
mA
C = 0.1 VCC/0.9. VCC at 2 MHz,
VCC = 2.5 V, Q = open
C = 0.1 VCC/0.9. VCC at 1 MHz,
VCC = 1.8 V, Q = open
S = VCC, VIN = VSS or VCC , VCC = 5 V
4.5-5.5
4.5-5.5
2.7-3.6
2.5-5.5
1.8-3.6
6
3
6
6
5
10
20
2
µA
µA
µA
µA
µA
S = VCC, VIN = VSS or VCC , VCC = 5 V
S = VCC, VIN = VSS or VCC , VCC = 2.7 V
S = VCC, VIN = VSS or VCC , VCC = 2.5 V
S = VCC, VIN = VSS or VCC , VCC = 1.8 V
Supply Current
(Stand-by)
ICC1
2
1
Input Low
Voltage
VIL
VIH
0.3 VCC
VCC+1
all
all
all
all
– 0.3
V
V
Input High
Voltage
0.7 VCC
4.5-5.5
4.5-5.5
2.7-3.6
2.5-5.5
1.8-3.6
4.5-5.5
4.5-5.5
2.7-3.6
2.5-5.5
1.8-3.6
6
3
6
6
5
6
3
6
6
5
I
OL = 2 mA, VCC = 5 V
OL = 2 mA, VCC = 5 V
0.4
0.4
0.4
0.4
V
V
V
V
V
V
V
V
V
V
I
Output Low
Voltage
1
VOL
I
OL = 1.5 mA, VCC = 2.7 V
OL = 1.5 mA, VCC = 2.5 V
I
IOL = 0.15 mA, VCC = 1.8 V
0.3
I
OH = –2 mA, VCC = 5 V
OH = –2 mA, VCC = 5 V
0.8 VCC
0.8 VCC
I
Output High
Voltage
1
VOH
I
I
I
OH = –0.4 mA, VCC = 2.7 V
OH = –0.4 mA, VCC = 2.5 V
OH = –0.1 mA, VCC = 1.8 V
0.8 VCC
0.8 VCC
0.8 VCC
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
11/21
M95256, M95128
Table 12A. AC Characteristics
M95256 / M95128
=4.5 to 5.5 V
V
CC
V
CC
=4.5 to 5.5 V
Symbol
Alt.
Parameter
T =0 to 70°C or
Unit
A
T =-40 to 125°C
A
-40 to 85°C
Min
D.C.
90
Max
Min
D.C.
200
200
200
200
200
Max
f
f
Clock Frequency
5
2
MHz
ns
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
1
t
90
90
200
200
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
ns
t
CLL
CL
2
t
1
1
µs
t
RC
CLCH
2
t
Clock Fall Time
1
1
µs
ns
ns
µs
t
FC
CHCL
t
t
DSU
Data In Setup Time
Data In Hold Time
Data In Rise Time
20
30
40
50
DVCH
t
t
CHDX
DH
2
t
1
1
1
1
t
RI
DLDH
2
t
Data In Fall Time
µs
ns
ns
ns
ns
ns
t
FI
DHDL
t
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock High Set-up Time before HOLD Active
Clock High Set-up Time before HOLD not Active
Output Disable Time
70
40
60
60
140
90
HHCH
t
HLCH
t
120
120
CHHL
t
CHHH
2
t
100
60
250
150
t
DIS
SHQZ
t
t
Clock Low to Output Valid
Output Hold Time
ns
ns
ns
CLQV
V
t
t
0
0
CLQX
HO
RO
2
t
Output Rise Time
50
50
100
100
100
250
10
t
t
t
QLQH
QHQL
HHQX
2
2
2
t
Output Fall Time
ns
ns
ns
ms
FO
t
HOLD High to Output Low-Z
HOLD Low to Output High-Z
Write Time
50
LZ
t
100
10
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
12/21
M95256, M95128
Table 12B. AC Characteristics
M95256-V /
M95128-V
M95256-W /
M95128-W
M95256-R /
M95128-R
V
CC
=
V
=
V
CC
=
CC
Symbol Alt.
Parameter
2.7 to 3.6 V
T =0 to 70°C
2.5 to 5.5 V
T =0 to 70°C
1.8 to 3.6 V
T =0 to 70°C
Unit
A
A
A
or –40 to 85°C or –40 to 85°C or –20 to 85°C
Min
D.C.
90
Max
Min
D.C.
200
200
200
200
200
Max
Min
D.C.
400
400
300
400
400
Max
f
f
SCK
Clock Frequency
5
2
1
MHz
ns
C
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
CSS1
CSS2
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
ns
CHSH
t
90
ns
CHSL
1
t
Clock High Time
Clock Low Time
Clock Rise Time
90
90
200
200
400
400
ns
ns
µs
t
CLH
CH
1
t
t
CLL
CL
2
2
t
0.05
1
1
t
RC
CLCH
t
Clock Fall Time
0.05
1
1
µs
ns
ns
t
FC
CHCL
t
t
DSU
Data In Setup Time
Data In Hold Time
20
30
40
50
60
DVCH
CHDX
t
t
DH
100
2
t
Data In Rise Time
Data In Fall Time
0.05
0.05
1
1
1
1
µs
µs
t
t
RI
DLDH
DHDL
2
t
FI
Clock Low Hold Time after HOLD not
Active
t
70
40
60
140
90
350
200
250
ns
ns
ns
HHCH
t
Clock Low Hold Time after HOLD Active
HLCH
Clock High Set-up Time before HOLD
Active
t
t
120
CHHL
Clock High Set-up Time before HOLD
not Active
60
120
250
ns
CHHH
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
100
60
250
150
500
380
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
0
0
0
CLQX
HO
RO
2
t
Output Rise Time
50
50
100
100
100
250
10
200
200
250
500
10
t
t
t
QLQH
QHQL
HHQX
2
2
2
t
t
Output Fall Time
ns
ns
ns
ms
FO
t
HOLD High to Output Low-Z
HOLD Low to Output High-Z
Write Time
50
LZ
100
10
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
13/21
M95256, M95128
Figure 14. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
tDLDH
tDHDL
HIGH IMPEDANCE
Q
AI01447
Figure 15. Hold Timing
S
tHLCH
tCHHL
tHLQZ
tHHCH
C
tCHHH
tHHQX
Q
D
HOLD
AI02032
Figure 16. Output Timing
S
tCH
C
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
ADDR.LSB IN
D
AI01449B
14/21
M95256, M95128
Table 13. Ordering Information Scheme
Example:
M95256
–
R
MW
6
T
Memory Capacity
Option
256
128
256 Kbit (32K x 8)
128 Kbit (16K x 8)
T
Tape and Reel Packing
Temperature Range
0 °C to 70 °C
1
1
5
6
–20 °C to 85 °C
–40 °C to 85 °C
–40 °C to 125 °C
Operating Voltage
2
blank 4.5 V to 5.5 V
3
2.7 V to 3.6 V
2.5 V to 5.5 V
1.8 V to 3.6 V
V
W
Package
3
BN PSDIP8 (0.25 mm frame)
R
MW SO8 (200 mil width)
4
SO8 (150 mil width)
MN
5
TSSOP14 (169 mil width)
DL
Note: 1. Temperature range available only on request.
2. Produced with High Reliability Certified Flow (HRCF), in V range 4.5 V to 5.5 V only.
CC
3. The -R version (V range 1.8 V to 3.6 V) only available in temperature ranges 5 or 1.
CC
4. SO8, 150 mil width, package is available for the M95128 series only.
5. TSSOP14, 169 mil width, package is available for the M95128 series only.
ORDERING INFORMATION
The notation used for the device number is as
shown in Table 13. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
15/21
M95256, M95128
Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
inches
Min.
Symb.
Typ.
Min.
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
Max.
5.90
–
Typ.
Max.
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
Figure 17. PSDIP8 (BN)
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Note: 1. Drawing is not to scale.
16/21
M95256, M95128
Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Symb.
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
Figure 18. SO8 narrow (MN)
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: 1. Drawing is not to scale.
17/21
M95256, M95128
Table 16. SO8 - 8 lead Plastic Small Outline, 200 mils body width
mm
inches
Min.
Symb.
Typ.
Min.
Max.
2.03
0.25
1.78
0.45
–
Typ.
Max.
0.080
0.010
0.070
0.018
–
A
A1
A2
B
0.10
0.004
0.35
–
0.014
–
C
0.20
0.008
0.050
D
5.15
5.20
–
5.35
5.40
–
0.203
0.205
–
0.211
0.213
–
E
e
1.27
H
7.70
0.50
0°
8.10
0.80
10°
0.303
0.020
0°
0.319
0.031
10°
L
α
N
8
8
CP
0.10
0.004
Figure 19. SO8 wide (MW)
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: 1. Drawing is not to scale.
18/21
M95256, M95128
Table 17. TSSOP14 - 14 lead Thin Shrink Small Outline
mm
inches
Symb.
Typ.
Min.
Max.
1.10
0.15
0.95
0.30
0.20
5.10
6.50
4.50
–
Typ.
Min.
Max.
0.043
0.006
0.037
0.012
0.008
0.197
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
4.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.193
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
14
14
CP
0.08
0.003
Figure 20. TSSOP14 (DL)
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Note: 1. Drawing is not to scale.
19/21
M95256, M95128
Table 18. Revision History
Date
Description of Revision
New -V voltage range added (including the tables for DC characteristics, AC characteristics, and
ordering information).
17-Nov-1999
07-Feb-2000
New -V voltage range extended to M95256 (including AC characteristics, and ordering
information).
22-Feb-2000
15-Mar-2000
tCLCH and tCHCL, for the M95xxx-V, changed from 1us to 100ns
-V voltage range changed to 2.7-3.6V
20/21
M95256, M95128
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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21/21
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