M95256-WCS6TP/K [STMICROELECTRONICS]
SPI BUS SERIAL EEPROM;
| 型号： | M95256-WCS6TP/K |
| 厂家： | 
ST |
| 描述： | SPI BUS SERIAL EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 内存集成电路 |
| 文件： | 总52页 (文件大小：1542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95256-W M95256-R
M95256-DR M95256-DF
256-Kbit serial SPI bus EEPROM with high-speed clock
Datasheet - production data
Features
• Compatible with the Serial Peripheral Interface
(SPI) bus
• Memory array
SO8 (MN)
– 256 Kb (32 Kbytes) of EEPROM
150 mil width
– Page size: 64 bytes
• Write
– Byte Write within 5 ms
– Page Write within 5 ms
• Additional Write lockable page (Identification
page)
TSSOP8 (DW)
169 mil width
• Write Protect: quarter, half or whole memory
array
• High-speed clock: 20 MHz
• Single supply voltage:
– 2.5 V to 5.5 V for M95256-W
– 1.8 V to 5.5 V for M95256-R and M95256-
DR
UFDFPN8 (MC)
– 1.7 V to 5.5 V for M95256-DF
2 x 3 mm
• Operating temperature range: from -40°C up to
+85°C
• Enhanced ESD protection
WLCSP (CS)
• More than 4 million Write cycles
• More than 200-year data retention
• Packages
– RoHS compliant and halogen-free
®
(ECOPACK )
April 2013
DocID12276 Rev 20
1/52
This is information on a product in full production.
www.st.com
1
Contents
M95256-W M95256-R M95256-DR M95256-DF
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
CC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
4
5
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1
5.1.2
5.1.3
5.1.4
Operating supply voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
5.3
5.4
5.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . 14
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Contents
6.3.2
6.3.3
6.3.4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4
6.5
6.6
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6.1
Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . 25
6.7
6.8
6.9
Read Identification Page (available only in M95256-D devices) . . . . . . . 26
Write Identification Page (available only in M95256-D devices) . . . . . . . 27
Read Lock Status (available only in M95256-D devices) . . . . . . . . . . . . . 28
6.10 Lock ID (available only in M95256-D devices) . . . . . . . . . . . . . . . . . . . . . 29
7
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
7.2
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9
10
11
12
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List of tables
M95256-W M95256-R M95256-DR M95256-DF
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M95256-D instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating conditions (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Operating conditions (M95256-R and M95256-DR, device grade 6) . . . . . . . . . . . . . . . . . 32
Operating conditions (M95256-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC characteristics (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC characteristics (M95256-R, M95256-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 35
DC characteristics (M95256-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC characteristics (M95256-R, M95256-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 38
AC characteristics (M95256-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 41
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 42
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data. 44
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 25.
Table 26.
Table 27.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections (top view, marking side, with bumps on the underside) . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. Read Lock Status sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. Serial output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 41
Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 43
Figure 26. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . 44
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Description
M95256-W M95256-R M95256-DR M95256-DF
1
Description
The M95256 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 32768 x 8 bits, accessed through the SPI bus.
The M95256-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95256-R and
M95256-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M95256-DF can
operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of
-40 °C / +85 °C.
The M95256-Dx offers an additional page, named the Identification Page (64 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
V
CC
D
C
S
Q
M95xxx
W
HOLD
V
SS
AI01789C
The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.
Table 1. Signal names
Signal name
Function
Direction
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Input
Input
Output
Input
Input
Input
-
D
Q
S
W
HOLD
VCC
VSS
Supply voltage
Ground
-
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Description
Figure 2. 8-pin package connections (top view)
M95xxx
S
Q
1
8
V
CC
HOLD
2
3
4
7
W
6
5
C
D
V
SS
AI01790D
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
Figure 3. WLCSP connections (top view, marking side, with bumps on the underside)
(/,$
6##
#
1
3
$
633
7
-3ꢀꢁꢂꢃꢄ6ꢅ
Caution:
As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
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Memory organization
M95256-W M95256-R M95256-DR M95256-DF
2
Memory organization
The memory is organized as shown in the following figure.
Figure 4. Block diagram
HOLD
W
High voltage
generator
Control logic
S
C
D
Q
I/O shift register
Data
Address register
and counter
register
Status
register
1/4
1/2
Size of the
Read only
EEPROM
area
1 page
Identification page
X decoder
MS19733V1
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Signal description
3
Signal description
During all operations, V must be held stable and within the specified valid range:
CC
V
(min) to V (max).
CC
CC
All of the input and output signals must be held high or low (according to voltages of V ,
IH
V
, V or V , as specified in Section 9: DC and AC parameters). These signals are
OH
IL OL
described next.
3.1
3.2
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3
3.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Signal description
M95256-W M95256-R M95256-DR M95256-DF
3.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7
3.8
VCC supply voltage
V
is the supply voltage.
CC
VSS ground
V
is the reference for all signals, including the V supply voltage.
SS
CC
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Connecting to the SPI bus
4
Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 5. Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
VCC
C
Q
D
VCC
C
Q
D
VCC
VSS
VSS
VSS
SPI Bus Master
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
R
R
R
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 5 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
t
requirement is met. The typical value of R is 100 kΩ..
SHCH
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Connecting to the SPI bus
M95256-W M95256-R M95256-DR M95256-DF
4.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
•
•
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 6, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
•
•
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 6. SPI modes supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
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Operating features
5
Operating features
5.1
Supply voltage (VCC)
5.1.1
Operating supply voltage (V )
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Operating conditions
CC
CC
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (t ). In order to secure a stable DC supply voltage, it is
W
recommended to decouple the V line with a suitable capacitor (usually of the order of
CC
10 nF to 100 nF) close to the V /V device pins.
CC SS
5.1.2
Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum V operating voltage (see Operating conditions in Section 9: DC
CC
and AC parameters).
At power-up, when V passes over the POR threshold, the device is reset and is in the
CC
following state:
•
•
•
in Standby Power mode,
deselected,
Status Register values:
–
–
–
The Write Enable Latch (WEL) bit is reset to 0.
The Write In Progress (WIP) bit is reset to 0.
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until V reaches a valid and
CC
stable level within the specified [V (min), V (max)] range, as defined under Operating
CC
CC
conditions in Section 9: DC and AC parameters.
5.1.3
Power-up conditions
When the power supply is turned on, V rises continuously from V to V . During this
CC
SS
CC
time, the Chip Select (S) line is not allowed to float but should follow the V voltage. It is
CC
therefore recommended to connect the S line to V via a suitable pull-up resistor (see
CC
Figure 5).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
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Operating features
M95256-W M95256-R M95256-DR M95256-DF
5.1.4
Power-down
During power-down (continuous decrease of the V supply voltage below the minimum
CC
V
operating voltage defined under Operating conditions in Section 9: DC and AC
CC
parameters), the device must be:
•
•
deselected (Chip Select S should be allowed to follow the voltage applied on V ),
CC
in Standby Power mode (there should not be any internal write cycle in progress).
5.2
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
.
CC
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
, as specified in DC characteristics (see Section 9: DC and AC parameters).
CC1
5.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
(a) (b)
been in progress.
Figure 7. Hold condition activation
c
HOLD
Hold
condition
Hold
condition
ai02029E
a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
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Operating features
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 7).
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 7 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4
5.5
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
Data protection and protocol control
The device features the following data protection mechanisms:
•
Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
•
•
•
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
•
The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
•
The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
Status Register bits
Protected block
Protected array addresses
BP1
BP0
0
0
1
1
0
1
0
1
none
none
Upper quarter
Upper half
6000h - 7FFFh
4000h - 7FFFh
0000h - 7FFFh
Whole memory
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Instructions
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6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
Table 3. Instruction set
Instruction
WREN
Description
Instruction format
Write Enable
Write Disable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
WRDI
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
Table 4. M95256-D instruction set
Description
Instruction
Instruction format
WREN
WRDI
Write Enable
Write Disable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
Read Identification
Page
Reads the page dedicated to identification.
Writes the page dedicated to identification.
1000 0011(1)
1000 0010(1)
Write Identification
Page
Read Lock Status
Lock ID
Reads the lock status of the Identification Page.
Locks the Identification page in read-only mode.
1000 0011(2)
1000 0010(2)
1. Address bit A10 must be 0, all other address bits are Don't Care.
2. Address bit A10 must be 1, all other address bits are Don't Care.
Table 5. Address range bits
Address significant bits
A14-A0(1)
1. Upper MSBs are Don’t Care.
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Instructions
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 8. Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
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6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
•
Power-up
•
•
•
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 9. Write Disable (WRDI) sequence
S
C
D
Q
0
1
2
3
4
5
6
7
Instruction
High Impedance
AI03750D
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Instructions
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 10.
Figure 10. Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
The status and control bits of the Status Register are as follows:
6.3.1
6.3.2
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
•
•
•
•
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Table 2) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
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6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 6. Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
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Instructions
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11.
Figure 11. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes t to complete (as specified in AC tables under Section 9: DC
W
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t , and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
W
also reset at the end of the Write cycle t .
W
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
•
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2.
•
The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 7. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t Write cycle.
W
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
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Table 7. Protection modes
Memory content
W
signal
SRWD
bit
Write protection of the
Status Register
Mode
Protected area(1) Unprotected area(1)
1
0
0
0
Status Register is writable
(if the WREN instruction
has set the WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Software-
protected
(SPM)
Ready to accept
Write-protected
Write instructions
1
1
Status Register is
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
Hardware-
protected
(HPM)
Ready to accept
Write-protected
0
1
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See
Table 2.
The protection features of the device are summarized in Table 7.
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
•
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
•
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
•
•
either setting the SRWD bit after driving the Write Protect (W) input pin low,
or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
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6.5
Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
Figure 12. Read from Memory Array (READ) sequence
S
C
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
6.6
Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period t (as specified in AC characteristics in Section 9: DC and AC parameters), at the
W
end of which the Write in Progress (WIP) bit is reset to 0.
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Figure 13. Byte Write (WRITE) sequence
S
C
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
The instruction is not accepted, and is not executed, under the following conditions:
•
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
•
•
if a Write cycle is already in progress,
if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
•
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note:
The self-timed write cycle t is internally executed as a sequence of two consecutive
W
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit
is read as “0” and a programmed bit is read as “1”.
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Instructions
Figure 14. Page Write (WRITE) sequence
S
C
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
6.6.1
Cycling with Error Correction Code (ECC)
M95256 and M95256-D devices offer an Error Correction Code (ECC) logic. The ECC is an
internal logic function which is transparent for the SPI communication protocol.
(c)
The ECC logic is implemented on each group of four EEPROM bytes . Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
(c)
other bytes located in the same group . As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the four bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 14.
c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
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6.7
Read Identification Page (available only in M95256-D
devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Reading this page is achieved with the Read Identification Page instruction (see Table 4).
The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data Input (D). Address bit A10 must be 0, upper
address bits are Don't Care, and the data byte pointed to by the lower address bits [A5:A0]
is shifted out on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the
internal address register is automatically incremented, and the byte of data at the new
address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the ID page from location 24d, the number of
bytes should be less than or equal to 40d, as the ID page boundary is 64 bytes).
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 15. Read Identification Page sequence
S
C
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-bit address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
7
High impedance
2
7
6
5
4
3
1
0
MSB
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Instructions
6.8
Write Identification Page (available only in M95256-D
devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Writing this page is achieved with the Write Identification Page instruction (see Table 4).
The Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes,
and at least one data byte are then shifted in on Serial Data Input (D). Address bit A10 must
be 0, upper address bits are Don't Care, the lower address bits [A5:A0] address bits define
the byte address inside the identification page. The instruction sequence is shown in
Figure 16.
Figure 16. Write identification page sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
Data byte
D
Q
23 22 21
3
2
1
0
7
6
5
4
3
2
0
1
High impedance
MS30909V1
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Instructions
M95256-W M95256-R M95256-DR M95256-DF
6.9
Read Lock Status (available only in M95256-D devices)
The Read Lock Status instruction (see Table 4) is used to check whether the Identification
Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with
the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are
then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are
Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data
Output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip
Select (S) continues to be driven low, the same data byte is shifted out. The read cycle is
terminated by driving Chip Select (S) high.
The instruction sequence is shown in figure below.
Figure 17. Read Lock Status sequence
S
C
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-bit address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
7
High impedance
2
7
6
5
4
3
1
0
MSB
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M95256-W M95256-R M95256-DR M95256-DF
Instructions
6.10
Lock ID (available only in M95256-D devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed.
The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction
code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data
byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is t (as specified in AC characteristics in Section 9: DC and AC
W
parameters). The instruction sequence is shown in Figure 18.
The instruction is discarded, and is not executed, under the following conditions:
•
•
•
If a Write cycle is already in progress,
If the Block Protect bits (BP1,BP0) = (1,1),
If a rising edge on Chip Select (S) happens outside of a byte boundary.
Figure 18. Lock ID sequence
S
C
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-bit address
Data byte
D
Q
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
High impedance
Ai15967
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Power-up and delivery state
M95256-W M95256-R M95256-DR M95256-DF
7
Power-up and delivery state
7.1
Power-up state
After power-up, the device is in the following state:
•
•
Standby power mode,
deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
•
•
•
not in the Hold condition,
the Write Enable Latch (WEL) is reset to 0,
Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array bits and identification page bits set to all 1s
(each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and
BP0) bits are initialized to 0.
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M95256-W M95256-R M95256-DR M95256-DF
Maximum rating
8
Maximum rating
Stressing the device outside the ratings listed in Table 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 8. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD
VO
Lead temperature during soldering
Output voltage
See note (1)
–0.50
VCC+0.6
VI
Input voltage
–0.50
6.5
6.5
V
VCC
IOL
Supply voltage
–0.50
V
DC output current (Q = 0)
DC output current (Q = 1)
Electrostatic discharge voltage (human body model)(2)
-
-
-
5
mA
mA
V
IOH
5
VESD
4000(3)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions of Hazardous
Substances (RoHS) 2011/65/EU.
2. Positive and negative pulses applied on different combinations of pin connections, according to
AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω,
R2=500 Ω).
3. VESD is 3000 V (max) for the M95256 identified by process letters KA.
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DC and AC parameters
M95256-W M95256-R M95256-DR M95256-DF
9
DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Table 9. Operating conditions (M95256-W, device grade 6)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
2.5
5.5
85
V
–40
°C
Table 10. Operating conditions (M95256-R and M95256-DR, device grade 6)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
1.8
5.5
85
V
–40
°C
Table 11. Operating conditions (M95256-DF, device grade 6)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
1.7
5.5
85
V
–40
°C
Table 12. AC measurement conditions
Parameter Min.
Symbol
Max.
Unit
CL
Load capacitance
30 or 100(1)
- 25
pF
ns
V
Input rise and fall times
Input pulse voltages
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
Input and output timing reference voltages
V
1. 100 pF when the clock frequency fC is less than 10 MHz, 30 pF when the clock frequency fC is
equal to or greater than 10 MHz.
Figure 19. AC measurement I/O waveform
Input voltage levels
Input and output
timing reference levels
0.8 V
CC
0.7 V
CC
0.3 V
CC
0.2 V
CC
AI00825C
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DC and AC parameters
Table 13. Capacitance
Test conditions(1)
Symbol
Parameter
Min.
Max.
Unit
COUT
Output capacitance (Q)
Input capacitance (D)
VOUT = 0 V
VIN = 0 V
-
-
-
8
8
6
pF
pF
pF
CIN
Input capacitance (other pins)
VIN = 0 V
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Table 14. Cycling performance by groups of four bytes
Symbol
Parameter(1)
Test conditions
Min.
Max.
Unit
TA ≤ 25 °C,
VCC(min) < VCC < VCC(max)
-
4,000,000
Ncycle
Write cycle endurance(2)
Write cycle(3)
TA = 85 °C,
-
1,200,000
VCC(min) < VCC < VCC(max)
1. Cycling performance for products identified by process letters KB.
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N,
4*N+1, 4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by
characterization and qualification.
3. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID
instruction is decoded. When using the Byte Write, the Page Write or the WRID instruction,
refer also to Section 6.6.1: Cycling with Error Correction Code (ECC).
Table 15. Memory cell data retention
Parameter
Data retention(1)
Test conditions
TA = 55 °C
Min.
Unit
200
Year
1. For products identified by process letters KB. The data retention behavior is checked in
production. The 200-year limit is defined from characterization and qualification results.
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DC and AC parameters
Symbol
M95256-W M95256-R M95256-DR M95256-DF
Table 16. DC characteristics (M95256-W, device grade 6)
Parameter Test conditions Min.
Max.
Unit
Input leakage
current
ILI
VIN = VSS or VCC
± 2
µA
Output leakage
current
ILO
S = VCC, VOUT = VSS or VCC
± 2
3(1)
2(2)
5(1)
µA
VCC= 2.5 V, C = 0.1 VCC/0.9 VCC
at 5 MHz, Q = open
V
CC= 2.5 V, C = 0.1 VCC/0.9 VCC
at 10 MHz, Q = open
CC= 5.5 V, C = 0.1 VCC/0.9 VCC
Supply current
(Read)
ICC
mA
V
at 5 MHz, Q = open
VCC= 5.5 V, C = 0.1 VCC/0.9 VCC
at 20 MHz, Q = open
5(3)
Supply current
(Write)
During tW, S = VCC,
2.5 V < VCC < 5.5 V
(4)
ICC0
5
3(5)
2(5)
mA
µA
S = VCC, VCC = 5.5 V,
VIN = VSS or VCC
,
Supply current
(Standby)
ICC1
S = VCC, VCC = 2.5 V,
VIN = VSS or VCC
,
VIL
VIH
Input low voltage
Input high voltage
–0.45 0.3 VCC
0.7 VCC VCC+1
V
V
VCC = 2.5 V and IOL = 1.5 mA or
VCC = 5 V and IOL = 2 mA
VOL
VOH
Output low voltage
Output high voltage
0.4
V
V
VCC = 2.5 V and IOH = –0.4 mA or
0.8 VCC
VCC = 5 V and IOH = –2 mA
1. For previous products identified with process letter A.
2. 4 mA at 10 MHz and 3 mA at 5 MHz for M95256 previous devices identified by process letter A.
3. For the M95256 devices identified by process letter K.
4. Characterized only, not tested in production.
5. 5 µA for previous M95256 devices identified by process letter A.
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DC and AC parameters
Table 17. DC characteristics (M95256-R, M95256-DR, device grade 6)
Symbol
Parameter
Test conditions(1)
VIN = VSS or VCC
S = VCC, voltage applied on Q = VSS or VCC
Min.
Max.
Unit
Input leakage
current
ILI
± 2
µA
Output leakage
current
ILO
± 2
µA
VCC = 1.8 V, C = 0.1 VCC or 0.9 VCC
at 2 MHz, Q = open
,
,
1(2)
Supply current
(Read)
ICC
mA
VCC = 1.8 V, C = 0.1 VCC or 0.9 VCC
at 5 MHz, Q = open
2(3)
Supply current
(Write)
(4)
ICC0
V
CC = 1.8 V, during tW, S = VCC
3
mA
µA
Supply current
(Standby)
ICC1
VCC = 1.8 V, S = VCC, VIN = VSS or VCC
1(5)
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
VCC+1
0.3
V
V
V
V
1.8 V ≤ VCC < 2.5 V
0.75 VCC
VOL
VOH
IOL = 0.15 mA, VCC = 1.8 V
Output high voltage IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
1. If the application uses the M95256-R or M95256-DR device at 2.5 V ≤ VCC≤ 5.5 V and -40 °C ≤ TA ≤ +85 °C,
please refer to Table 16: DC characteristics (M95256-W, device grade 6), rather than to the above table.
2. Value tested only for previous M95256 devices identified by process letter A.
3. Only for M95256 devices identified by process letter K.
4. Characterized only, not tested in production.
5. 3 µA for previous M95256 devices identified by process letter A.
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DC and AC parameters
M95256-W M95256-R M95256-DR M95256-DF
Table 18. DC characteristics (M95256-DF, device grade 6)
Symbol
Parameter
Test conditions (1)
VIN = VSS or VCC
S = VCC, voltage applied on Q = VSS or VCC
Min.
Max.
Unit
Input leakage
current
ILI
± 2
µA
Output leakage
current
ILO
± 2
2
µA
mA
mA
µA
VCC = 1.7 V, C = 0.1 VCC or 0.9 VCC
at 5 MHz, Q = open
,
Supply current
(Read)
ICC
Supply current
(Write)
(2)
ICC0
VCC = 1.7 V, during tW, S = VCC
3
Supply current
(Standby)
ICC1
VCC = 1.7 V, S = VCC, VIN = VSS or VCC
1
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
1.7 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
VCC+1
0.3
V
V
V
V
1.7 V ≤ VCC < 2.5 V
0.75 VCC
VOL
VOH
IOL = 0.15 mA, VCC = 1.7 V
Output high voltage IOH = –0.1 mA, VCC = 1.7 V
0.8 VCC
1. If the application uses the M95256-DF devices at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, please
refer to Table 16: DC characteristics (M95256-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.
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DC and AC parameters
Table 19. AC characteristics (M95256-W, device grade 6)
Previous(1)
and new
products
New products(2)
Test conditions specified in
CL = 30 pF
Table 9 and Table 12
Unit
VCC ≥ 2.5V
VCC ≥ 4.5V
CL = 100 pF
Symbol Alt.
Parameter
Min.
D.C.
90
Max.
Min.
D.C.
30
Max.
Min.
D.C.
15
Max.
fC
fSCK Clock frequency
5
10
20
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
90
30
15
tCS
S deselect time
100
90
40
20
tCSH S active hold time
S not active hold time
tCLH Clock high time
tCLL Clock low time
30
15
90
30
15
(3)
tCH
90
40
20
(3)
tCL
90
40
20
(3)
(3)
tCLCH
tCHCL
tDVCH
tCHDX
tRC
tFC
Clock rise time
Clock fall time
1
1
2
2
2
2
tDSU Data in setup time
20
30
10
10
5
tDH
Data in hold time
10
Clock low hold time after
HOLD not active
tHHCH
tHLCH
tCLHL
tCLHH
70
40
0
30
30
0
15
15
0
ns
ns
ns
ns
Clock low hold time after
HOLD active
Clock low setup time
before HOLD active
Clock low setup time
before HOLD not active
0
0
0
(4)
tSHQZ
tCLQV
tCLQX
tQLQH
tQHQL
tDIS Output disable time
100
60
40
40
20
20
ns
ns
ns
ns
ns
tV
Clock low to output valid
Output hold time
Output rise time
tHO
tRO
tFO
0
0
0
(4)
(4)
50
50
20
20
10
10
Output fall time
HOLD high to output
valid
tHHQV
tLZ
50
40
20
ns
HOLD low to output
High-Z
(4)
tHLQZ
tW
tHZ
100
5
40
5
20
5
ns
tWC Write time
ms
1. Previous products are identified by process letters AB.
2. New products are M95256 devices identified by process letter K.
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
4. Characterized only, not tested in production.
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DC and AC parameters
M95256-W M95256-R M95256-DR M95256-DF
Table 20. AC characteristics (M95256-R, M95256-DR, device grade 6)
Test conditions specified in Table 10 and Table 12
New products (2)
VCC ≥ 1.8V VCC ≥ 2.5V VCC ≥ 4.5V Unit
Previous
products (1)
Symbol Alt.
Parameter
Min. Max. Min. Max. Min. Max. Min. Max.
fC
fSCK Clock frequency
2
5
10
20 MHz
tSLCH tCSS1 S active setup time
200
200
200
200
200
200
200
60
60
90
60
60
80
80
30
30
40
30
30
40
40
15
15
20
15
15
20
20
ns
ns
ns
ns
ns
ns
ns
tSHCH tCSS2 S not active setup time
tSHSL
tCHSH
tCHSL
tCS S deselect time
tCSH S active hold time
S not active hold time
tCLH Clock high time
tCLL Clock low time
tRC Clock rise time
tFC Clock fall time
(3)
tCH
(3)
tCL
(4)
tCLCH
1
1
2
2
2
2
2
2
µs
µs
ns
ns
(4)
tCHCL
tDVCH
tCHDX
tDSU Data in setup time
tDH Data in hold time
40
50
20
20
10
10
5
10
Clock low hold time after HOLD
not active
tHHCH
tHLCH
tCLHL
tCLHH
140
90
0
60
60
0
30
30
0
15
15
0
ns
ns
ns
ns
Clock low hold time after HOLD
active
Clock low setup time before
HOLD active
Clock low setup time before
HOLD not active
0
0
0
0
(4)
tSHQZ
tCLQV
tCLQX
tDIS Output disable time
tV Clock low to output valid
tHO Output hold time
250
150
80
80
40
40
20
20
ns
ns
ns
ns
ns
ns
ns
ms
0
0
0
0
(4)
tQLQH
tRO Output rise time
100
100
100
250
5
20
20
80
80
5
20
20
40
40
5
10
10
20
20
5
(4)
tQHQL
tHHQV
tFO Output fall time
tLZ HOLD high to output valid
tHZ HOLD low to output High-Z
tWC Write time
(4)
tHLQZ
tW
1. Previous products are identified by process letters AB.
2. New products are the M95256 devices identified by process letter K.
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
4. Characterized only, not tested in production.
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DC and AC parameters
Table 21. AC characteristics (M95256-DF, device grade 6)
Test conditions specified in Table 11 and Table 12
VCC ≥ 1.7 V VCC ≥ 2.5 V VCC ≥ 4.5 V
Parameter
Unit
Min. Max. Min. Max. Min. Max.
fC
fSCK Clock frequency
5
10
20 MHz
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
tCS S deselect time
60
60
90
60
60
80
80
30
30
40
30
30
40
40
15
15
20
15
15
20
20
ns
ns
ns
ns
ns
ns
ns
tCSH S active hold time
S not active hold time
(1)
tCH
tCLH Clock high time
(2)
tCL
tCLL Clock low time
(2)
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tSHQZ
tCLQV
tCLQX
tQLQH
tQHQL
tHHQV
tHLQZ
tW
tRC Clock rise time
2
2
2
2
2
2
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tFC Clock fall time
tDSU Data in setup time
20
20
60
60
0
10
10
30
30
0
5
10
15
15
0
tDH Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
tDIS Output disable time
0
0
0
80
80
40
40
20
20
tV
Clock low to output valid
tHO Output hold time
tRO Output rise time
0
0
0
20
20
80
80
5
20
20
40
40
5
10
10
20
20
5
tFO Output fall time
tLZ HOLD high to output valid
tHZ HOLD low to output High-Z
tWC Write time
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
2. Characterized only, not tested in production.
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DC and AC parameters
M95256-W M95256-R M95256-DR M95256-DF
Figure 20. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCL
tCLCH
MSB IN
LSB IN
D
Q
High impedance
AI01447d
Figure 21. Hold timing
S
C
Q
tHLCH
tCLHL
tHHCH
tCLHH
tHHQV
tHLQZ
HOLD
AI01448c
Figure 22. Serial output timing
S
C
tCH
tSHSL
tCLQV
tCLQX
tCLCH
tCHCL
tCL
tSHQZ
Q
D
tQLQH
tQHQL
ADDR
LSB IN
AI01449f
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Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
-
-
1.750
0.250
-
-
-
0.0689
0.0098
-
-
0.100
1.250
0.280
0.170
-
-
0.0039
0.0492
0.0110
0.0067
-
-
-
-
0.480
0.230
0.100
5.000
6.200
4.000
-
-
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
-
-
ccc
D
-
-
4.900
6.000
3.900
1.270
-
4.800
5.800
3.800
-
0.1929
0.2362
0.1535
0.0500
-
0.1890
0.2283
0.1496
-
E
E1
e
h
0.250
0°
0.500
8°
0.0098
0°
0.0197
8°
k
-
-
L
-
0.400
-
1.270
-
-
0.0157
-
0.0500
-
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
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Package mechanical data
M95256-W M95256-R M95256-DR M95256-DF
Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 23. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
0.100
3.100
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
-
-
0.050
0.800
0.190
0.090
-
-
0.0020
0.0315
0.0075
0.0035
-
1.000
-
0.0394
-
c
-
-
CP
D
-
-
3.000
0.650
6.400
4.400
0.600
1.000
-
2.900
-
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
-
0.1142
-
e
E
6.200
4.300
0.450
-
6.600
4.500
0.750
-
0.2441
0.1693
0.0177
-
0.2598
0.1772
0.0295
-
E1
L
L1
α
0°
8°
0°
8°
N
8
8
1. Values in inches are converted from mm and rounded to four decimal digits.
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M95256-W M95256-R M95256-DR M95256-DF
Package mechanical data
Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package
outline
e
b
D
L1
L3
Pin 1
E2
K
E
L
A
D2
eee
A1
1. Drawing is not to scale.
ZW_MEeV2
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.550
0.450
0.000
0.200
1.900
1.200
2.900
1.200
-
0.600
0.050
0.300
2.100
1.600
3.100
1.600
-
0.0217
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0472
-
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
0.0630
-
A1
0.020
0.0008
b
0.250
0.0098
D
2.000
0.0787
D2 (rev MC)
-
-
E
3.000
0.1181
E2 (rev MC)
-
-
e
0.500
0.0197
K (rev MC)
-
-
-
-
-
0.300
0.300
-
-
-
-
-
-
-
0.0118
0.0118
-
-
L
L1
0.500
0.150
-
0.0197
0.0059
-
L3
0.300
0.080
0.0118
0.0031
eee(2)
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle
from measuring.
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Package mechanical data
M95256-W M95256-R M95256-DR M95256-DF
Figure 26. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline
bbb
Z
e2
H
D
Y
X
e
F
Detail A
E
e1
F
e3
aaa
A
A2
G
Reference
(4X)
Orientation
Wafer back side
Side view
Bumps side
Bump
A1
eee
Z
Z
b
Seating plane
Øccc M
X Y
Z
Z
Øddd M
Detail A
Rotated 90 °
1Cg_ME_V1
1. Drawing is not to scale.
Table 25. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package
mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.540
0.190
0.350
0.270
1.271
1.358
0.800
0.693
0.400
0.400
0.333
0.235
0.500
0.580
0.0213
0.0075
0.0138
0.0106
0.0500
0.0535
0.0315
0.0273
0.0157
0.0157
0.0131
0.0093
0.0197
0.0228
A1
A2
b
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D
1.291
0.0508
E
1.378
0.0543
e
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
e3
F
G
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M95256-W M95256-R M95256-DR M95256-DF
Package mechanical data
Table 25. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package
mechanical data (continued)
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
H
0.236
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.0093
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N (number of terminals)
aaa
bbb
ccc
ddd
eee
0.11
0.11
0.11
0.06
0.06
0.0043
0.0043
0.0043
0.0024
0.0024
1. Values in inches are converted from mm and rounded to four decimal digits.
DocID12276 Rev 20
45/52
Part numbering
M95256-W M95256-R M95256-DR M95256-DF
11
Part numbering
Table 26. Ordering information scheme
M95256-D
Example:
W MN 6
T
P /K
Device type
M95 = SPI serial access EEPROM
Device function
256 = 256 Kbit
Device family
Blank = Without Identification page
D = With additional Identification page
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package(1)
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (MLP8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)
Process(2)
/K= Manufacturing technology code
1. All packages are ECOPACK2® (RoHS compliant and halogen-free).
2. The process letters apply to WLCSP devices only. The process letters appear on the device
package (marking) and on the shipment box. Please contact your nearest ST Sales Office for
further information.
46/52
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M95256-W M95256-R M95256-DR M95256-DF
Revision history
12
Revision history
Table 27. Document revision history
Changes
Date
Revision
New -V voltage range added (including the tables for DC characteristics,
AC characteristics, and ordering information).
17-Nov-1999
2.1
New -V voltage range extended to M95256 (including AC characteristics,
and ordering information).
07-Feb-2000
2.2
22-Feb-2000
15-Mar-2000
2.3
2.4
tCLCH and tCHCL, for the M95xxx-V, changed from 1μs to 100ns
-V voltage range changed to 2.7-3.6V
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
29-Jan-2001
12-Jun-2001
2.5
2.6
Illustrations and Package Mechanical data updated
Correction to header of Table 12B
TSSOP14 Illustrations and Package Mechanical data updated
Document promoted from Preliminary Data to Full Data Sheet
Announcement made of planned upgrade to 10 MHz clock for the 5V, –40
to 85°C, range.
08-Feb-2002
09-Aug-2002
2.7
2.8
M95128 split off to its own datasheet. Data added for new and forthcoming
products, including availability of the SO8 narrow package.
24-Feb-2003
26-Jun-2003
2.9
Omission of SO8 narrow package mechanical data remedied
-V voltage range removed
2.10
Table of contents, and Pb-free options added. -S voltage range extended
to -R. VIL(min) improved to –0.45V
21-Nov-2003
17-Mar-2004
3.0
4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) changed.
Soldering temperature information clarified for RoHS compliant devices.
Device grade information clarified
M95128 datasheet merged back in. Product List summary table added.
AEC-Q100-002 compliance. Device Grade information clarified. tHHQX
corrected to tHHQV. 10MHz product becomes standard
21-Oct-2004
5.0
DocID12276 Rev 20
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Revision history
M95256-W M95256-R M95256-DR M95256-DF
Table 27. Document revision history (continued)
Date
Revision
Changes
M95128 part numbers removed from document. PDIP8 package removed.
Delivery state paragraph added.
Section 3.8: Operating supply voltage (VCC) added and information
removed below Section 4: Operating features.
Power up state removed below Section 6: Delivery state.
Figure 18: SPI modes supported modified and Note 2 added.
Note 1 added to Table 8.
ICC1 specified over the whole VCC range and ICC0 added in Table 14,
Table 15 and Table 16. ICC specified over the whole VCC range in
Table 14.
13-Apr-2006
6
Table 17: AC Characteristics (M95256, Device Grade 6) added.
tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively.
Figure 21: Hold timing modified. Process added to Table 25: Ordering
information scheme. Note 1 added to Table 25.
Note 1 removed from Table 20: AC characteristics (M95256-DR, M95256-
R device grade 6).
TA added to Table 7: Absolute maximum ratings.
Order of sections modified.
M95256 with device grade 6 temperature range removed.
Section 3.7: VSS ground added, Section 3.8: Operating supply voltage
(VCC) modified. Small text changes.
Section 5.4: Write Status Register (WRSR), Section 5.5: Read from
Memory Array (READ) and Section 6: Delivery state updated.
Note 2 below Figure 17: Bus master and memory devices on the SPI bus
removed, replaced by explanatory paragraph.
TLEAD added to Table 7: Absolute maximum ratings.
Test conditions modified for ICC0 and ICC1, and VIH min modified in
Table 17: AC characteristics (M95256, device grade 3).
15-Oct-2007
7
tW modified and “preliminary data” note removed in Table 20: AC
characteristics (M95256-DR, M95256-R device grade 6).
Blank option removed below Plating technology, process A modified and
process V removed in Table 25: Ordering information scheme.
Table 26: Available M95256x products (package, voltage range,
temperature grade) added.
SO8N and SO8W package specifications updated (see Section 10:
Package mechanical data). Package mechanical data: inches calculated
from mm and rounded to 3 decimal digits.
Section 3.8: Operating supply voltage (VCC) modified. Small text
changes. Frequency corrected on page 1.
27-Mar-2008
15-Jul-2008
8
9
VIL and VIH modified in Table 16: DC characteristics (M95256-R, M95256-
DR, device grade 6).
AB Process added to Table 25: Ordering information scheme.
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 10: Package
mechanical data).
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Revision history
Table 27. Document revision history (continued)
Date
Revision
Changes
M95080 part number added.
Updated Section 3.8: Operating supply voltage (VCC)
Updated Section 4.3: Data protection and protocol control
Updated Section 5.4: Write Status Register (WRSR)
Added note in Section 5.6: Write to Memory Array (WRITE)
Updated Table 7: Absolute maximum ratings
24-Jun-2010
10
Added Table 20: AC characteristics (M95256-DR, M95256-R device grade
6)
Updated Table 20: AC characteristics (M95256-DR, M95256-R device
grade 6)
Updated Section 1: Description.
Updated Section 5.7: Read Identification Page (available only in M95256-
DR devices).
07-Sep-2010
11
Updated Section 5.8: Write Identification Page.
Updated Section 5.9: Read Lock Status (available only in M95256-DR
devices).
Updated Features.
Updated Section 5.8: Write Identification Page.
Added Figure 25: TSSOP8 – 8 lead thin shrink small outline, package
outline.
Added Table 23: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat
package no lead 2 × 3 mm, package mechanical data.
12-Nov-2010
12
Updated Section 11: Part numbering.
Updated Table 26: Available M95256x products (package, voltage range,
temperature grade).
Updated Figure 25, Figure 26.
Deleted:
– SO8 (MW) picture under Features
– SO8 (MW) mechanical dimensions
Updated:
– UFDFPN8 (MB) with UFDFPN8 (MB, MC) picture under Features
– Section 5.6.1: ECC (error correction code) and Write cycling
– Section 7: Connecting to the SPI bus
22-Mar-2011
13
– Table 7: Absolute maximum ratings
Process letter K substituted with only concerned products (M95256-D and
M95256 in MLP8 package MC).9
(...)
DocID12276 Rev 20
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Revision history
M95256-W M95256-R M95256-DR M95256-DF
Table 27. Document revision history (continued)
Date
Revision
Changes
(...)
– Rephrased “test condition” text in:
Table 14: DC characteristics (M95256, device grade 3)
Table 20: DC characteristics (current M95080-W products)
Table 16: DC characteristics (M95256-W, device grade 3)
Table 23: DC characteristics (current and new M95080-R and M95080-
DR products)
Table 18: AC characteristics (M95256, device grade 3)
Table 31: AC characteristics, M95080-W, device grade 6
Table 20: AC characteristics (M95256-W, device grade 3)
Table 36: AC characteristics (M95080-R, M95080-DR device grade 6)
22-Mar-2011
13
Added:
– Caution under Figure 3: WLCSP connections (top view, marking side,
with balls on the underside)
– MC = UFDFPN8 package in Section 11: Part numbering
Updated:
– UFDFPN8 offered in only one package version
Added:
20-May-2011
19-Jul-2011
14
15
– Table 15: Memory cell characteristics
MC package added (UFDFPN8)
Updated:
– Footnote 3 below Table 7: Absolute maximum ratings
– Footnotes 1, 2, 4, 5 below Table 15: DC characteristics (M95256-W,
device grade 6)
– Footnotes 1, 2, 3, 5 below Table 17: DC characteristics (M95256-R,
M95256-DR, device grade 6)
23-Nov-2011
17-Jan-2012
16
17
– Table 19: AC characteristics, M95256-W, device grade 6 headings,
TQLQH and TQHQL values. One footnote removed and one added
– Table 21: AC characteristics (M95256-DR, M95256-R device grade 6),
new columns for new pairs of products. Footnote 2 edited.
Updated Figure 25: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat
no lead, package outline.
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M95256-W M95256-R M95256-DR M95256-DF
Revision history
Table 27. Document revision history (continued)
Date
Revision
Changes
Datasheet split into:
– M95256-125 datasheet for automotive products (range 3),
– M95256-W, M95256-R, M95256-DR, M95256-DF (this datasheet) for
standard products (range 6).
Added:
– 1.7 V device (M95256-DF)
Updated:
21-Jun-2012
18
– Figure 4: Block diagram
– Table 25: M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale
package mechanical data and Figure 26: M95256-DFCS6TP/K,
WLCSP 8-bump wafer-level chip scale package outline
– Cycling and data retention values (Table 14 and Table 15)
Deleted:
– UFDFPN8 package rev MB
Updated:
– WLCSP package reference from “CT” to “CS”
– Figure 3: WLCSP connections (top view, marking side, with bumps on
the underside)
24-Jul-2012
19
– Figure 26: M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale
package outline
Document reformatted.
Updated:
– Package figure on cover page
– Section 7.2: Initial delivery state
– Note (1) in Table 8: Absolute maximum ratings
09-Apr-2013
20
Deleted note 1 in Table 21: AC characteristics (M95256-DF, device grade
6).
Replaced “ball” by “bump” in the entire document.
DocID12276 Rev 20
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M95256-W M95256-R M95256-DR M95256-DF
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