M95256RCS6TG [STMICROELECTRONICS]
256 Kbit serial SPI bus EEPROM with high-speed clock; 256 Kbit的串行SPI总线的EEPROM与高速时钟
| 型号： | M95256RCS6TG |
| 厂家： | 
ST |
| 描述： | 256 Kbit serial SPI bus EEPROM with high-speed clock |
| 文件： | 总44页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95256
M95256-W M95256-R
256 Kbit serial SPI bus EEPROM
with high-speed clock
Features
■ Compatible with SPI bus serial interface
(positive clock SPI modes)
■ Single supply voltage:
– 4.5 to 5.5 V for M95256
– 2.5 to 5.5 V for M95256-W
– 1.8 to 5.5 V for M95256-R
SO8 (MN)
150 mil width
■ High speed
– 5 MHz clock rate, 5 ms write time
■ Status Register
■ Hardware protection of the Status Register
■ Byte and Page Write (up to 64 bytes)
■ Self-timed programming cycle
■ Adjustable size read-only EEPROM area
■ Enhanced ESD protection
SO8 (MW)
200 mil width
■ More than 1 000 000 write cycles
■ More than 40-year data retention
■ Packages
®
– ECOPACK (RoHS compliant)
TSSOP8 (DW)
169 mil width
WLCSP (CS)
July 2008
Rev 9
1/44
www.st.com
1
Contents
M95256, M95256-W, M95256-R
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8.1
3.8.2
3.8.3
3.8.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
5
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
5.3
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1
5.3.2
5.3.3
5.3.4
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
5.5
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/44
M95256, M95256-W, M95256-R
Contents
5.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.6.1
ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . 23
6
7
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9
10
11
12
3/44
List of tables
M95256, M95256-W, M95256-R
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95256) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95256-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95256-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95256, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95256-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M95256-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC characteristics (M95256, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC characteristics (M95256-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC characteristics (M95256-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SO8N – 8 lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 36
SO8 wide – 8 lead plastic small outline, 200 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 38
M24256-BR WLCSP, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . 39
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Available M95256x products (package, voltage range, temperature grade) . . . . . . . . . . . 41
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
4/44
M95256, M95256-W, M95256-R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 36
Figure 20. SO8 wide – 8 lead plastic small outline, 200 mils body width, package outline . . . . . . . . . 37
Figure 21. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 22. M24256-BR WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5/44
Description
M95256, M95256-W, M95256-R
1
Description
The M95256, M95256-W and M95256-R are electrically erasable programmable memory
(EEPROM) devices. They are accessed by a high speed SPI-compatible bus. Their memory
array is organized as 32768 x 8 bits.
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 1.
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD).
Figure 1.
Logic diagram
V
CC
D
C
S
Q
M95256
W
HOLD
V
SS
AI12361
Figure 2.
SO and TSSOP connections
M95256
S
Q
1
8
7
6
5
V
CC
HOLD
2
3
4
W
C
D
V
SS
AI12362
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
6/44
M95256, M95256-W, M95256-R
Description
Figure 3. WLCSP connections (top view, marking side, with balls on the underside)
VCC
Q
S
HOLD
W
D
C
VSS
ai14707
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
Input
Output
Input
Input
Input
D
Serial Data input
Serial Data output
Chip Select
Write Protect
Hold
Q
S
W
HOLD
VCC
VSS
Supply voltage
Ground
7/44
Memory organization
M95256, M95256-W, M95256-R
2
Memory organization
The memory is organized as shown in Figure 4.
Figure 4.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
1 Page
X Decoder
AI01272C
8/44
M95256, M95256-W, M95256-R
Signal description
3
Signal description
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
3.1
3.2
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3
3.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
9/44
Signal description
M95256, M95256-W, M95256-R
3.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all write instructions.
3.7
VSS ground
V
is the reference for the V supply voltage.
CC
SS
3.8
Supply voltage (VCC)
3.8.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Table 7, Table 8 and
CC
CC
Table 9.). This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a Write instruction, until the completion of the internal write cycle (t ). In
W
order to secure a stable DC supply voltage, it is recommended to decouple the V line with
CC
a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V /V package
CC SS
pins.
3.8.2
Power-up conditions
When the power supply is turned on, V continuously rises from V to V . During this
CC
SS
CC
time, the Chip Select (S) line is not allowed to float but should follow the V voltage, it is
CC
therefore recommended to connect the S line to V via a suitable pull-up resistor (see
CC
Figure 13).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The V rise time must not vary faster than 1 V/µs.
CC
When V passes over the POR threshold, the device is reset and enters the Standby
CC
Power mode. However, the device must not be accessed until V reaches a valid and
CC
stable V voltage within the specified [V (min), V (max)] range.
CC
CC
CC
3.8.3
Device Reset
In order to prevent inadvertent write operations during power-up (continuous rise in V ), a
CC
power on reset (POR) circuit is included. At power-up, the device does not respond to any
instruction until V has reached the power on reset threshold voltage (this threshold is
CC
lower than the minimum V operating voltage defined in Table 7, Table 8 and Table 9).
CC
When V passes over the POR threshold, the device is reset and enters the following
CC
state:
●
Standby Power mode
10/44
M95256, M95256-W, M95256-R
Operating features
●
deselected (at next power-up, a falling edge is required on Chip Select (S) before any
instruction can be started).
●
●
not in the Hold condition
Status register:
–
–
–
the Write Enable Latch (WEL) is reset to 0
the Write In Progress (WIP) is reset to 0
the SRWD, BP1 and BP0 bits of the Status Register are non-volatile bits and
therefore remain unchanged)
Note:
When V passes the power on reset threshold voltage and until it reaches the minimum
CC
V
operating voltage, the memory must not be selected/accessed.
CC
3.8.4
Power-down
During power-down (continuous decrease in V below the minimum V operating
CC
CC
voltage), the device must be:
●
deselected (Chip Select (S) should be allowed to follow the voltage applied on V
)
CC
●
in Standby Power mode (there should not be any internal Write cycle in progress).
4
Operating features
4.1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
11/44
Operating features
Figure 5.
M95256, M95256-W, M95256-R
Hold condition activation
C
HOLD
Hold
Hold
Condition
Condition
AI02029D
12/44
M95256, M95256-W, M95256-R
Operating features
4.2
Status Register
Figure 4 shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 5.3: Read Status Register (RDSR).
4.3
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
●
●
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-protected block size
Status Register bits
Protected array addresse
Protected block
BP1
BP0
M95256, M95256-W, M95256-R
0
0
1
1
0
1
0
1
none
none
Upper quarter
Upper half
6000h - 7FFFh
4000h - 7FFFh
0000h - 7FFFh
Whole memory
13/44
Instructions
M95256, M95256-W, M95256-R
5
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
Table 3.
Instruction set
Instruction
Description
Instruction format
WREN
WRDI
Write Enable
Write Disable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
5.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 6.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
14/44
M95256, M95256-W, M95256-R
Instructions
5.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
●
●
●
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 7.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
15/44
Instructions
M95256, M95256-W, M95256-R
5.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 8.
The status and control bits of the Status Register are as follows:
5.3.1
5.3.2
5.3.3
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
5.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4.
Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
16/44
M95256, M95256-W, M95256-R
Instructions
Figure 8.
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
17/44
Instructions
M95256, M95256-W, M95256-R
5.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed. After the Write Enable (WREN) instruction has been decoded and
executed, the Status Register is updated with the Write Enable Latch bit (WEL) set to 1.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code and the data byte on Serial Data input (D). The instruction is
terminated by driving Chip Select (S) high at a byte boundary of the input data. This event
triggers the self-timed write cycle, and continues for a period t (as specified in Table 16,
W
Table 17, Table 18 and Table 19), at the end of which the Write in Progress (WIP) bit is reset
to 0.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle t , and is 0 when it is completed. When the
W
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in Table 4.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W) signal can be used to put
the device in the Hardware-protected mode (HPM, see Table 5). In this mode, the Write
Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the Write
Status Register (WRSR) instruction, including the t Write cycle.
W
The instruction sequence is shown in Figure 9.
18/44
M95256, M95256-W, M95256-R
Instructions
Table 5.
W signal
Protection modes
Memory content
SRWD
bit
Write protection of the
Status Register
Mode
Protected area(1) Unprotected area(1)
1
0
0
0
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
Software
Protected
(SPM)
Ready to accept Write
Write-protected
instructions
The values in the BP1
and BP0 bits can be
changed
1
1
Status Register is
Hardware write
protected
Hardware
Protected
(HPM)
Ready to accept Write
Write-protected
0
1
instructions
The values in the BP1
and BP0 bits cannot be
changed
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.
The protection features of the device are summarized in Table 2.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●
●
If Write Protect (W) is driven high, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
low
●
or by driving Write Protect (W) low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) high.
If Write Protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
19/44
Instructions
M95256, M95256-W, M95256-R
Figure 9.
Write Status Register (WRSR) sequence
S
C
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
20/44
M95256, M95256-W, M95256-R
Instructions
5.5
Read from Memory Array (READ)
As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 10. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
1. The most significant address bit (b15) is Don’t Care.
21/44
Instructions
M95256, M95256-W, M95256-R
5.6
Write to Memory Array (WRITE)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address bytes, and at least one data byte are then
shifted in, on Serial Data input (D). The instruction is terminated by driving Chip Select (S)
high at a byte boundary of the input data. The self-timed Write cycle, triggered by the rising
edge of Chip Select (S), continues for a period t
(as specified in Table 16, Table 17,
WC
Table 18 and Table 19.), at the end of which the Write in Progress (WIP) bit is reset to 0.
In the case of Figure 11, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S) continues to be driven low, as shown in Figure 12, the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 64 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
●
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 11. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
1. The most significant address bit (b15) is Don’t Care.
22/44
M95256, M95256-W, M95256-R
Figure 12. Page Write (WRITE) sequence
Instructions
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
1. The most significant address bit (b15) is Don’t Care.
5.6.1
ECC (error correction code) and Write cycling
The M95256, M95256-W and M95256-R devices offer an ECC (error correction code) logic
which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if
a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the
ECC detects it and replaces it by the correct value. The read reliability is therefore much
improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by word (4 bytes) in order to
benefit from the larger amount of Write cycles.
The M95256-W6 and M95256-R6 devices are qualified at 1 million (1 000 000) Write cycles,
using a cycling routine that writes to the device by multiples of 4-byte words.
23/44
Delivery state
M95256, M95256-W, M95256-R
6
Delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
7
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 13 shows an example of three memory devices connected to an MCU, on an SPI
bus. Only one memory device is selected at a time, so only one memory device drives the
Serial Data output (Q) line at a time, the other memory devices are high impedance.
Figure 13. Bus master and memory devices on the SPI bus
V
SS
V
CC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
V
V
V
CC
C
Q
D
C
Q
D
C Q D
CC
CC
Bus Master
(ST6, ST7, ST9,
ST10, Others)
V
V
V
SS
SS
SS
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
R
R
R
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI12304b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
The pull-up resistor R (represented in Figure 13) ensures that a device is not selected if the
bus master leaves the S line in the high-impedance state.
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
24/44
M95256, M95256-W, M95256-R
Connecting to the SPI bus
the transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the t
requirement is met. The typical value of R is 100 kΩ.
SHCH
7.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
CPOL=1, CPHA=1
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 14, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
●
Figure 14. SPI modes supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
25/44
Maximum rating
M95256, M95256-W, M95256-R
8
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TA
TSTG
TLEAD
VO
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
Lead temperature during soldering
Output voltage
see note (1)
–0.50 VCC+0.6
V
V
V
V
VI
Input voltage
–0.50
–0.50
–4000
6.5
6.5
VCC
VESD
Supply voltage
Electrostatic discharge voltage (human body model)(2)
4000
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
26/44
M95256, M95256-W, M95256-R
DC and AC parameters
9
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
(1)
Table 7.
Symbol
Operating conditions (M95256)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
4.5
5.5
V
Ambient operating temperature (device grade 3)
–40
125
°C
1. The 5V M95256 part is offered in "V" process (F6DP26%) only.
Table 8.
Symbol
Operating conditions (M95256-W)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
2.5
–40
–40
5.5
85
V
Ambient operating temperature (device grade 6)
Ambient operating temperature (device grade 3)(1)
°C
°C
125
1. This product is under development. For more information, please contact your nearest ST sales office.
Table 9.
Symbol
Operating conditions (M95256-R)
Parameter
Min. (1)
Max. (1)
Unit
VCC
TA
Supply voltage
1.8
5.5
85
V
Ambient operating temperature
–40
°C
1. This product is under development. For more information, please contact your nearest ST sales office.
(1)
Table 10. AC measurement conditions
Symbol
Parameter
Min.
Max.
Unit
CL
Load capacitance
100
pF
ns
V
Input rise and fall times
50
Input pulse voltages
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Input and output timing reference voltages
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 15. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
0.3V
CC
CC
0.2V
CC
AI00825B
27/44
DC and AC parameters
M95256, M95256-W, M95256-R
(1)
Table 11. Capacitance
Symbol
Parameter
Test condition
Min.
Max.
Unit
COUT
Output capacitance (Q)
Input capacitance (D)
VOUT = 0 V
VIN = 0 V
VIN = 0 V
8
8
6
pF
pF
pF
CIN
Input capacitance (other pins)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Table 12. DC characteristics (M95256, device grade 3)
Symbol
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
Output leakage current
VIN = VSS or VCC
2
2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open
ICC
Supply current
4
mA
µA
Supply current
(Standby Power mode)
S = VCC, VCC = 5 V,
VIN = VSS or VCC
ICC1
5
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
–0.45
0.3 VCC
V
V
V
V
0.7 VCC VCC+1
0.4
(1)
VOL
IOL = 2 mA, VCC = 5 V
IOH = –2 mA, VCC = 5 V
(1)
VOH
0.8 VCC
1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 13. DC characteristics (M95256-W, device grade 6)
Symbol
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
Output leakage current
VIN = VSS or VCC
2
2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5 MHz,
3
5
5
mA
mA
mA
µA
V
CC = 2.5 V, Q = open
ICC
Supply current (Read)
Supply current (Write)
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5V, Q = open
During tW, S = VCC
2.5 V < VCC < 5.5 V
,
(1)
ICC0
Supply current
(Standby Power mode)
S = VCC, VIN = VSS or VCC
,
ICC1
5
2.5 V < VCC < 5.5 V
VIL
VIH
Input low voltage
Input high voltage
–0.45
0.3 VCC
V
V
0.7 VCC VCC+1
0.4
VCC = 2.5 V and IOL = 1.5 mA or
VCC = 5 V and IOL = 2 mA
VOL
VOH
Output low voltage
Output high voltage
V
V
VCC = 2.5 V and IOH = –0.4 mA or
0.8 VCC
VCC = 5 V and IOH = –2 mA
1. Characterized value, not tested in production.
28/44
M95256, M95256-W, M95256-R
DC and AC parameters
Table 14. DC characteristics (M95256-W, device grade 3)
Symbol
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
Output leakage current
VIN = VSS or VCC
2
2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
ICC
Supply current (Read)
Supply current (Write)
3
6
mA
mA
µA
During tW, S = VCC
,
(1)
ICC0
2.5 V < VCC < 5.5 V
Supply current
(Standby Power mode)
S = VCC, VIN = VSS or VCC
2.5 V < VCC < 5.5 V,
ICC1
5
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
–0.45
0.3 VCC
V
V
V
V
0.7 VCC VCC+1
0.4
VOL
VOH
IOL = 1.5 mA, VCC = 2.5 V
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
1. Characterized value, not tested in production.
Table 15. DC characteristics (M95256-R)
Symbol
Parameter
Test condition
Min
Max
Unit
ILI
Input leakage current
Output leakage current
VIN = VSS or VCC
2
2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 1.8 V, Q = open
ICC
Supply current (Read)
Supply current (Write)
1 (1)
mA
mA
µA
During tW, S = VCC
,
(2)
ICC0
3
1.8 V < VCC < 2.5 V
Supply current (Standby
Power mode)
S = VCC, VIN = VSS or VCC
,
ICC1
3(1)
1.8 V < VCC < 2.5 V
1.8 V ≤VCC < 2.5 V
2.5 V ≤VCC < 5.5 V
–0.45
–0.45
0.25 VCC
0.3 VCC
VCC+1
VCC+1
0.3
V
V
V
V
V
V
VIL
Input low voltage
Input high voltage
1.8 V ≤VCC < 2.5 V
0.75 VCC
0.7 VCC
VIH
2.5 V ≤VCC < 5.5 V
VOL
VOH
Output low voltage
Output high voltage
IOL = 0.15 mA, VCC = 1.8 V
IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
1. This is preliminary data.
2. Characterized value, not tested in production.
29/44
DC and AC parameters
M95256, M95256-W, M95256-R
Table 16. AC characteristics (M95256, device grade 3)
Test conditions specified in Table 10 and Table 7
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock frequency
D.C.
90
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
tCS S deselect time
90
100
90
tCSH S active hold time
S not active hold time
tCLH Clock high time
tCLL Clock low time
90
(1)
tCH
90
(1)
tCL
90
(2)
tCLCH
tRC
tFC
Clock rise time
Clock fall time
1
1
(2)
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
20
30
70
40
0
tDH
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
0
(2)
tSHQZ
tDIS Output disable time
100
60
tCLQV
tV
Clock low to output valid
Output hold time
tCLQX
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output rise time
50
50
50
100
5
(2)
tQHQL
Output fall time
tHHQV
HOLD high to output valid
HOLD low to output High-Z
(2)
tHLQZ
tHZ
tW
tWC Write time
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
30/44
M95256, M95256-W, M95256-R
DC and AC parameters
Table 17. AC characteristics (M95256-W, device grade 6)
Test conditions specified in Table 10 and Table 8
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock frequency
D.C.
90
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
tCS S deselect time
90
100
90
tCSH S active hold time
S not active hold time
tCLH Clock high time
tCLL Clock low time
90
(1)
tCH
90
(1)
tCL
90
(2)
tCLCH
tRC
tFC
Clock rise time
Clock fall time
1
1
(2)
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
20
30
70
40
0
tDH
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
0
(2)
tSHQZ
tDIS Output disable time
100
60
tCLQV
tV
Clock low to output valid
Output hold time
tCLQX
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output rise time
50
50
50
100
5
(2)
tQHQL
Output fall time
tHHQV
HOLD high to output valid
HOLD low to output High-Z
(2)
tHLQZ
tHZ
tW
tWC Write time
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
31/44
DC and AC parameters
M95256, M95256-W, M95256-R
Table 18. AC characteristics (M95256-W, device grade 3)
Test conditions specified in Table 10 and Table 8
Symbol
Alt.
Parameter
Min. Max. Unit
fC
fSCK
Clock frequency
D.C.
90
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
90
tCS
S deselect time
100
90
tCSH
S active hold time
S not active hold time
Clock high time
90
(1)
tCH
tCLH
tCLL
tRC
90
(1)
tCL
Clock low time
90
(2)
tCLCH
Clock rise time
1
1
(2)
tCHCL
tFC
Clock fall time
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU
tDH
Data in setup time
20
30
70
40
0
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
Output disable time
0
(2)
tSHQZ
tDIS
tV
100
60
tCLQV
Clock low to output valid
Output hold time
tCLQX
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output rise time
50
50
50
100
5
(2)
tQHQL
Output fall time
tHHQV
HOLD high to output valid
HOLD low to output High-Z
Write time
(2)
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
32/44
M95256, M95256-W, M95256-R
DC and AC parameters
Table 19. AC characteristics (M95256-R)
Test conditions specified in Table 10 and Table 9
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK
tCSS1
tCSS2
tCS
Clock frequency
D.C.
200
200
200
200
200
200
200
2
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
S active setup time
S not active setup time
S deselect time
tCSH
S active hold time
S not active hold time
Clock high time
(1)
tCH
tCLH
tCLL
tRC
(1)
tCL
Clock low time
(2)
tCLCH
Clock rise time
1
1
(2)
tCHCL
tFC
Clock fall time
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU
tDH
Data in setup time
40
50
140
90
0
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
Output disable time
0
(2)
tSHQZ
tDIS
tV
250
150
tCLQV
Clock low to output valid
Output hold time
tCLQX
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output rise time
100
100
100
250
5
(2)
tQHQL
Output fall time
tHHQV
HOLD high to output valid
HOLD low to output High-Z
Write time
(2)
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
33/44
DC and AC parameters
Figure 16. Serial input timing
M95256, M95256-W, M95256-R
tSHSL
S
C
tCHSL
tSLCH
tCHSH
tSHCH
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 17. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQV
tHLQZ
Q
D
HOLD
AI01448B
34/44
M95256, M95256-W, M95256-R
DC and AC parameters
Figure 18. Output timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449e
35/44
Package mechanical data
M95256, M95256-W, M95256-R
10
Package mechanical data
®
In order to meet environmental requirements, ST offers the M95256 in ECOPACK
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at www.st.com.
Figure 19. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 20. SO8N – 8 lead plastic small outline, 150 mils body width, package data
millimeters
inches(1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
1.75
0.25
0.0689
0.0098
A1
A2
b
0.1
0.0039
0.0492
0.011
1.25
0.28
0.17
0.48
0.23
0.1
5
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
0.0067
ccc
D
4.9
6
4.8
5.8
3.8
-
0.1929
0.2362
0.1535
0.05
0.189
0.2283
0.1496
-
E
6.2
4
E1
e
3.9
1.27
-
h
0.25
0°
0.5
8°
0.0098
0°
0.0197
8°
k
L
0.4
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
36/44
M95256, M95256-W, M95256-R
Package mechanical data
Figure 20. SO8 wide – 8 lead plastic small outline, 200 mils body width, package
outline
A2
A
c
b
CP
e
D
N
1
E E1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 21. SO8 wide – 8 lead plastic small outline, 200 mils body width, package
mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
2.5
0.25
2
0.0984
0.0098
0.0787
0.0201
0.0138
0.0039
0.2382
0.2449
0.35
0
0
1.51
0.35
0.1
0.0594
0.0138
0.0039
0.4
0.2
0.51
0.35
0.1
0.0157
0.0079
c
CP
D
6.05
6.22
8.89
-
E
5.02
7.62
-
0.1976
E1
e
0.3
1.27
0.05
-
0°
-
k
0°
10°
0.8
10°
L
0.5
8
0.0197
8
0.0315
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
37/44
Package mechanical data
M95256, M95256-W, M95256-R
Figure 21. TSSOP8 – 8 lead thin shrink small outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 22. TSSOP8 – 8 lead thin shrink small outline, package mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8
8°
0°
8
8°
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
38/44
M95256, M95256-W, M95256-R
Package mechanical data
Figure 22. M24256-BR WLCSP, 0.5 mm pitch, package outline
Orientation reference
D
2
3
1
A
B
e2
G
e
C
D
E
B
E
e3
e1
F
A2
A1
A
1. Drawing is not to scale.
Table 23. M24256-BR WLCSP, 0.5 mm pitch, package mechanical data
Millimeters
Min
Inches(1)
Symbol
Typ
0.60
Max
0.65
Typ
0.0236
Min
Max
0.0256
A
0.55
0.0217
A1
A2
B
0.245
0.355
0.22
0.27
0.0096
0.0140
0.0087
0.0130
0.0106
0.0150
0.330
Ø 0.311
1.95
0.380
Ø 0.0122
D
1.97
1.99
0.0776
0.0703
0.0197
0.0341
0.0098
0.0170
0.0217
0.0154
0.0768
0.0695
0.0783
0.0711
E
1.785
0.5
1.765
1.805
e
e1
e2
e3
F
0.866
0.25
0.433
0.552
0.392
0.502
0.342
8
0.602
0.442
0.0198
0.0135
0.0237
0.0174
G
N(2)
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. N is the total number of terminals.
39/44
Part numbering
M95256, M95256-W, M95256-R
11
Part numbering
Table 24. Ordering information scheme
Example:
M95256
–
W MN 6
T
P
/A
Device type
M95 = SPI serial access EEPROM
Device function
256 = 256 Kbit (32768 x 8)
Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
Package
MN = SO8 (150 mils width)
MW = SO8 (200 mils width)
DW = TSSOP8 (169 mils width)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow(1)
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHs compliant)
Process
A or AB = F8L(2)
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
2. Used only for device grade 3 and WLCSP packages.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
The category of second-level interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
40/44
M95256, M95256-W, M95256-R
Part numbering
Table 25. Available M95256x products (package, voltage range, temperature grade)
M95256
(4.5 V to 5.5 V)
M95256-W
(2.5 V to 5.5 V)
M95256-R
(1.8 V to 5.5 V)
Package
SO8N (MN)
SO8W (MW)
TSSOP (DW)
WLCSP
Range 3
Range 6, Range 3
Range 6
Range 6
-
-
-
-
Range 6, Range 3
-
Range 6
Range 6
41/44
Revision history
M95256, M95256-W, M95256-R
12
Revision history
Table 26. Document revision history
Date
Revision
Changes
New -V voltage range added (including the tables for DC characteristics,
AC characteristics, and ordering information).
17-Nov-1999
2.1
New -V voltage range extended to M95256 (including AC characteristics,
and ordering information).
07-Feb-2000
2.2
22-Feb-2000
15-Mar-2000
2.3
2.4
tCLCH and tCHCL, for the M95xxx-V, changed from 1μs to 100ns
-V voltage range changed to 2.7-3.6V
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
29-Jan-2001
12-Jun-2001
2.5
2.6
Illustrations and Package Mechanical data updated
Correction to header of Table 12B
TSSOP14 Illustrations and Package Mechanical data updated
Document promoted from Preliminary Data to Full Data Sheet
Announcement made of planned upgrade to 10 MHz clock for the 5V, –40
to 85°C, range.
08-Feb-2002
09-Aug-2002
2.7
2.8
M95128 split off to its own datasheet. Data added for new and forthcoming
products, including availability of the SO8 narrow package.
24-Feb-2003
26-Jun-2003
2.9
Omission of SO8 narrow package mechanical data remedied
-V voltage range removed
2.10
Table of contents, and Pb-free options added. -S voltage range extended
to -R. VIL(min) improved to –0.45V
21-Nov-2003
17-Mar-2004
3.0
4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering
temperature information clarified for RoHS compliant devices. Device
grade information clarified
M95128 datasheet merged back in. Product List summary table added.
AEC-Q100-002 compliance. Device Grade information clarified. tHHQX
corrected to tHHQV. 10MHz product becomes standard
21-Oct-2004
5.0
M95128 part numbers removed from document. PDIP8 package removed.
ECC (error correction code) and Write cycling paragraph added.
Section 3.8: Supply voltage (VCC) added and information removed below
Section 4: Operating features.
Power up state removed below Section 6: Delivery state.
Figure 14: SPI modes supported modified and Note 2 added.
Note 1 added to Table 7.
ICC1 specified over the whole VCC range and ICC0 added in Table 13,
Table 14 and Table 15. ICC specified over the whole VCC range in Table 13.
Table 17: AC Characteristics (M95256, Device Grade 6) added.
tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively.
Figure 17: Hold timing modified. Process added to Table 24: Ordering
information scheme. Note 1 added to Table 24.
13-Apr-2006
6
Note 1 removed from Table 19: AC characteristics (M95256-R).
TA added to Table 6: Absolute maximum ratings.
Order of sections modified.
42/44
M95256, M95256-W, M95256-R
Table 26. Document revision history (continued)
Revision history
Date
Revision
Changes
M95256 with device grade 6 temperature range removed.
Section 3.7: VSS ground added, Section 3.8: Supply voltage (VCC
)
modified. Small text changes.
Section 5.4: Write Status Register (WRSR), Section 5.5: Read from
Memory Array (READ) and Section 5.6.1: ECC (error correction code) and
Write cycling updated.
Note 2 below Figure 13: Bus master and memory devices on the SPI bus
removed, replaced by explanatory paragraph.
TLEAD added to Table 6: Absolute maximum ratings.
Test conditions modified for ICC0 and ICC1, and VIH min modified in
Table 16: AC characteristics (M95256, device grade 3).
15-Oct-2007
7
tW modified and “preliminary data” note removed in Table 19: AC
characteristics (M95256-R).
Blank option removed below Plating technology, process A modified and
process V removed in Table 24: Ordering information scheme.
Table 25: Available M95256x products (package, voltage range,
temperature grade) added.
SO8N and SO8W package specifications updated (see Section 10:
Package mechanical data). Package mechanical data: inches calculated
from mm and rounded to 3 decimal digits.
Section 3.8: Supply voltage (VCC) modified. Small text changes.
Frequency corrected on page 1.
27-Mar-2008
15-Jul-2008
8
9
VIL and VIH modified in Table 15: DC characteristics (M95256-R).
AB Process added to Table 24: Ordering information scheme.
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 10: Package
mechanical data).
43/44
M95256, M95256-W, M95256-R
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
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