M95320-DR [STMICROELECTRONICS]
32-Kbit serial SPI bus EEPROM with high-speed clock; 32 - Kbit的串行SPI总线的EEPROM与高速时钟
| 型号： | M95320-DR |
| 厂家： | 
ST |
| 描述： | 32-Kbit serial SPI bus EEPROM with high-speed clock |
| 文件： | 总48页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95320-W M95320-R M95320-DR
32-Kbit serial SPI bus EEPROM with high-speed clock
Datasheet −production data
Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
– 32 Kb (4 Kbytes) of EEPROM
– Page size: 32 bytes
SO8 (MN)
150 mil width
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
■ Additional Write lockable page (Identification
page)
TSSOP8 (DW)
169 mil width
■ Write Protect: quarter, half or whole memory
array
■ High-speed clock: 20 MHz
■ Single supply voltage:
– 2.5 V to 5.5 V for M95320-W
– 1.8 V to 5.5 V for M95320-R and M95320-
DR
UFDFPN8 (MB, MC)
2 × 3 mm (MLP)
■ Operating temperature range: from -40°C up to
+85°C
■ Enhanced ESD protection
■ More than 4 million Write cycles
■ More than 200-year data retention
■ Packages
– RoHS compliant and halogen-free
®
(ECOPACK )
May 2012
Doc ID 5711 Rev 14
1/48
This is information on a product in full production.
www.st.com
1
Contents
M95320-W M95320-R M95320-DR
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
CC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
4
5
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1
5.1.2
5.1.3
5.1.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
5.3
5.4
5.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Contents
6.3.2
6.3.3
6.3.4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4
6.5
6.6
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6.1
Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . 25
6.7
6.8
6.9
Read Identification Page (available only in M95320-DR devices) . . . . . . 26
Write Identification Page (available only in M95320-DR devices) . . . . . . 27
Read Lock Status (available only in M95320-DR devices) . . . . . . . . . . . . 28
6.10 Lock ID (available only in M95320-DR devices) . . . . . . . . . . . . . . . . . . . . 29
7
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
7.2
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9
10
11
12
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List of tables
M95320-W M95320-R M95320-DR
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M95320-DR instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating conditions (M95320-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Operating conditions (M95320-R and M95320-DR, device grade 6) . . . . . . . . . . . . . . . . . 32
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC characteristics (M95320-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC characteristics (M95320-R, M95320-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 35
AC characteristics (M95320-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics (M95320-R, M95320-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 37
SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 40
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 42
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21.
Table 22.
Table 23.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Read Lock Status sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 40
Figure 23. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 42
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Description
M95320-W M95320-R M95320-DR
1
Description
The M95320 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 4096 x 8 bits, accessed through the SPI bus.
The M95320 devices can operate with a supply range from 1.8 V up to 5.5 V, and are
guaranteed over the -40 °C/+85 °C temperature range.
The M95320-D offers an additional page, named the Identification Page (32 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1.
Logic diagram
V
CC
D
C
S
Q
M95xxx
W
HOLD
V
SS
AI01789C
The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
Input
Output
Input
Input
Input
D
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Q
S
W
HOLD
VCC
VSS
Supply voltage
Ground
6/48
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M95320-W M95320-R M95320-DR
Figure 2. 8-pin package connections (top view)
M95xxx
Description
S
Q
1
8
V
CC
HOLD
2
3
4
7
W
6
5
C
D
V
SS
AI01790D
1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.
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Memory organization
M95320-W M95320-R M95320-DR
2
Memory organization
The memory is organized as shown in the following figure.
Figure 3. Block diagram
(/,$
(IGH VOLTAGE
GENERATOR
7
3
#ONTROL LOGIC
#
$
1
)ꢄ/ SHIFT REGISTER
$ATA
REGISTER
!DDRESS REGISTER
AND COUNTER
3TATUS
REGISTER
ꢀꢄꢅ
3IZE OF THE
2EAD ONLY
%%02/-
ꢀꢄꢆ
AREA
ꢀ PAGE
)DENTIFICATION PAGE
8 DECODER
-3ꢀꢁꢂꢃꢃ6ꢀ
8/48
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M95320-W M95320-R M95320-DR
Signal description
3
Signal description
During all operations, V must be held stable and within the specified valid range:
CC
V
(min) to V (max).
CC
CC
All of the input and output signals must be held high or low (according to voltages of V ,
IH
V
, V or V , as specified in Section 9: DC and AC parameters). These signals are
OH
IL OL
described next.
3.1
3.2
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3
3.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Signal description
M95320-W M95320-R M95320-DR
3.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7
3.8
VCC supply voltage
V
is the supply voltage.
CC
VSS ground
V
is the reference for all signals, including the V supply voltage.
SS
CC
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Connecting to the SPI bus
4
Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
VCC
VCC
C
Q
D
C
Q
D
C Q D
VSS
VSS
VSS
SPI Bus Master
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
R
R
R
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
t
requirement is met. The typical value of R is 100 kΩ..
SHCH
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Connecting to the SPI bus
M95320-W M95320-R M95320-DR
4.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
●
CPOL=0, CPHA=0
CPOL=1, CPHA=1
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
●
Figure 5.
SPI modes supported
CPOL CPHA
C
0
1
0
1
C
D
MSB
Q
MSB
AI01438B
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Operating features
5
Operating features
5.1
Supply voltage (VCC)
5.1.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Operating conditions
CC
CC
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (t ). In order to secure a stable DC supply voltage, it is
W
recommended to decouple the V line with a suitable capacitor (usually of the order of
CC
10 nF to 100 nF) close to the V /V device pins.
CC SS
5.1.2
Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum V operating voltage (see Operating conditions in Section 9: DC
CC
and AC parameters).
At power-up, when V passes over the POR threshold, the device is reset and is in the
CC
following state:
●
●
●
in Standby Power mode,
deselected,
Status Register values:
–
–
–
The Write Enable Latch (WEL) bit is reset to 0.
The Write In Progress (WIP) bit is reset to 0.
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until V reaches a valid and
CC
stable level within the specified [V (min), V (max)] range, as defined under Operating
CC
CC
conditions in Section 9: DC and AC parameters.
5.1.3
Power-up conditions
When the power supply is turned on, V rises continuously from V to V . During this
CC
SS
CC
time, the Chip Select (S) line is not allowed to float but should follow the V voltage. It is
CC
therefore recommended to connect the S line to V via a suitable pull-up resistor (see
CC
Figure 4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
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Operating features
M95320-W M95320-R M95320-DR
5.1.4
Power-down
During power-down (continuous decrease of the V supply voltage below the minimum
CC
V
operating voltage defined under Operating conditions in Section 9: DC and AC
CC
parameters), the device must be:
●
deselected (Chip Select S should be allowed to follow the voltage applied on V ),
CC
●
in Standby Power mode (there should not be any internal write cycle in progress).
5.2
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
.
CC
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
, as specified in DC characteristics (see Section 9: DC and AC parameters).
CC1
5.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
(a)(b)
been in progress.
Figure 6.
Hold condition activation
C
HOLD
Hold
Hold
Condition
Condition
AI02029D
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 6).
a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
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Operating features
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4
5.5
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
Data protection and protocol control
The device features the following data protection mechanisms:
●
Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
●
●
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
●
The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-protected block size
Status Register bits
Protected block
Protected array addresses
BP1
BP0
0
0
1
1
0
1
0
1
none
none
Upper quarter
Upper half
0C00h - 0FFFh
0800h - 0FFFh
0000h - 0FFFh
Whole memory
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Instructions
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6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
Table 3.
Instruction set
Instruction
Description
Write Enable
Instruction format
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Write Disable
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
Table 4.
M95320-DR instruction set
Instruction
format
Instruction
Description
WREN
WRDI
Write Enable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Write Disable
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
Read Identification
Page
Reads the page dedicated to identification.
Writes the page dedicated to identification.
1000 0011(1)
1000 0010(1)
Write Identification
Page
Read Lock Status Reads the lock status of the Identification Page.
Lock ID Locks the Identification page in read-only mode.
1000 0011(2)
1000 0010(2)
1. Address bit A10 must be 0, all other address bits are Don't Care.
2. Address bit A10 must be 1, all other address bits are Don't Care.
Table 5.
Address range bits
Address significant bits
A11-A0(1)
1. Upper MSBs are Don’t Care.
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Instructions
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 7.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
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Instructions
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6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
●
●
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 8.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
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Instructions
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
Figure 9.
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
The status and control bits of the Status Register are as follows:
6.3.1
6.3.2
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
●
●
●
●
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Table 2) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
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Instructions
M95320-W M95320-R M95320-DR
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 6.
Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 10.
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
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Instructions
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes t to complete (as specified in AC tables under Section 9: DC
W
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t , and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
W
also reset at the end of the Write cycle t .
W
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
●
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2.
●
The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 7. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t Write cycle.
W
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
Table 7.
Protection modes
Memory content
W
signal
SRWD Write protection of the
Mode
bit
Status Register
Protected area(1) Unprotected area(1)
1
0
0
0
Status Register is
writable (if the WREN
Software- instruction has set the
protected WEL bit).
Ready to accept
Write-protected
Write instructions
(SPM)
The values in the BP1
and BP0 bits can be
changed.
1
1
Status Register is
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
Hardware-
protected
(HPM)
Ready to accept
Write-protected
0
1
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
The protection features of the device are summarized in Table 7.
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
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Instructions
M95320-W M95320-R M95320-DR
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
●
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
●
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●
either setting the SRWD bit after driving the Write Protect (W) input pin low,
or driving the Write Protect (W) input pin low after setting the SRWD bit.
●
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
6.5
Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
Figure 11. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
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Instructions
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
6.6
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period t (as specified in AC characteristics in Section 9: DC and AC parameters), at the
W
end of which the Write in Progress (WIP) bit is reset to 0.
Figure 12. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
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Instructions
M95320-W M95320-R M95320-DR
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
●
●
if a Write cycle is already in progress,
if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note:
The self-timed write cycle t is internally executed as a sequence of two consecutive
W
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 13. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
D
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
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Instructions
6.6.1
Cycling with Error Correction Code (ECC)
M95320-D devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic
function which is transparent for the SPI communication protocol.
(c)
The ECC logic is implemented on each group of four EEPROM bytes . Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
(c)
other bytes located in the same group . As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the four bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 13.
c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
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Instructions
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6.7
Read Identification Page (available only in M95320-DR
devices)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Reading this page is achieved with the Read Identification Page instruction (see Table 4).
The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data Input (D). Address bit A10 must be 0, upper
address bits are Don't Care, and the data byte pointed to by the lower address bits [A4:A0]
is shifted out on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the
internal address register is automatically incremented, and the byte of data at the new
address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the ID page from location 10d, the number of
bytes should be less than or equal to 22d, as the ID page boundary is 32 bytes).
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 14. Read Identification Page sequence
3
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Instructions
6.8
Write Identification Page (available only in M95320-DR
devices)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Writing this page is achieved with the Write Identification Page instruction (see Table 4). The
Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and
at least one data byte are then shifted in on Serial Data Input (D). Address bit A10 must be
0, upper address bits are Don't Care, the lower address bits [A4:A0] address bits define the
byte address inside the identification page. The instruction sequence is shown in Figure 15.
Figure 15. Write Identification Page sequence
3
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)NSTRUCTION
ꢀꢈꢋBIT ADDRESS
$ATA BYTE
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Doc ID 5711 Rev 14
27/48
Instructions
M95320-W M95320-R M95320-DR
6.9
Read Lock Status (available only in M95320-DR devices)
The Read Lock Status instruction (see Table 4) is used to check whether the Identification
Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with
the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are
then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are
Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data
Output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip
Select (S) continues to be driven low, the same data byte is shifted out. The read cycle is
terminated by driving Chip Select (S) high.
The instruction sequence is shown in Figure 16.
Figure 16. Read Lock Status sequence
3
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)NSTRUCTION
ꢀꢈꢋBIT ADDRESS
ꢀꢇ ꢀꢅ ꢀꢃ
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$ATA /UT ꢀ
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28/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
Instructions
6.10
Lock ID (available only in M95320-DR devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed.
The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction
code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data
byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is t (as specified in AC characteristics in Section 9: DC and AC
W
parameters). The instruction sequence is shown in Figure 17.
The instruction is discarded, and is not executed, under the following conditions:
●
●
●
If a Write cycle is already in progress,
If the Block Protect bits (BP1,BP0) = (1,1),
If a rising edge on Chip Select (S) happens outside of a byte boundary.
Figure 17. Lock ID sequence
3
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#
)NSTRUCTION
ꢀꢈꢋBIT ADDRESS
$ATA BYTE
$
1
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Doc ID 5711 Rev 14
29/48
Power-up and delivery state
M95320-W M95320-R M95320-DR
7
Power-up and delivery state
7.1
Power-up state
After power-up, the device is in the following state:
●
Standby power mode,
●
deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
●
●
●
not in the Hold condition,
the Write Enable Latch (WEL) is reset to 0,
Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
30/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
Maximum rating
8
Maximum rating
Stressing the device outside the ratings listed in Table 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 8.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD
VO
Lead temperature during soldering
Output voltage
See note (1)
–0.50
–0.50
–0.50
VCC+0.6
VI
Input voltage
6.5
6.5
5
V
VCC
IOL
Supply voltage
V
DC output current (Q = 0)
DC output current (Q = 1)
Electrostatic discharge voltage (human body model)(2)
mA
mA
V
IOH
5
VESD
4000
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
Doc ID 5711 Rev 14
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DC and AC parameters
M95320-W M95320-R M95320-DR
9
DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Table 9.
Symbol
Operating conditions (M95320-W, device grade 6)
Parameter Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
2.5
5.5
85
V
–40
°C
Table 10. Operating conditions (M95320-R and M95320-DR, device grade 6)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
1.8
5.5
85
V
–40
°C
Table 11. AC measurement conditions
Symbol
Parameter
Min.
Max.
Unit
CL
Load capacitance
30
pF
ns
V
Input rise and fall times
25
Input pulse voltages
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
Input and output timing reference voltages
V
Figure 18. AC measurement I/O waveform
)NPUT VOLTAGE LEVELS
)NPUT AND OUTPUT
TIMING REFERENCE LEVELS
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32/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
Table 12. Capacitance
DC and AC parameters
Symbol
Parameter
Test conditions(1)
Min.
Max.
Unit
COUT
Output capacitance (Q)
Input capacitance (D)
VOUT = 0 V
VIN = 0 V
VIN = 0 V
8
8
6
pF
pF
pF
CIN
Input capacitance (other pins)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Table 13. Cycling performance by groups of four bytes
Symbol
Parameter(1)
Test conditions
Min.
Max.
Unit
TA ≤ 25 °C, 1.8 V < VCC < 5.5 V
4,000,000
1,200,000
Write cycle
Write
Ncycle
endurance(2)
cycle(3)
TA = 85 °C, 1.8 V < VCC < 5.5 V
1. Cycling performance for products identified by process letter K.
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1,
4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and
qualification.
3. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID instruction is
decoded. When using the Byte Write, the Page Write or the WRID instruction, refer also to Section 6.6.1:
Cycling with Error Correction Code (ECC).
Table 14. Memory cell data retention
Parameter
Data retention(1)
Test conditions
TA = 55 °C
Min.
Unit
200
Year
1. For products identified by process letter K. The data retention behavior is checked in production. The 200-
year limit is defined from characterization and qualification results.
Doc ID 5711 Rev 14
33/48
DC and AC parameters
M95320-W M95320-R M95320-DR
Table 15. DC characteristics (M95320-W, device grade 6)
Symbol
Parameter
Test conditions
Min.
Max.
Unit
Input leakage
current
ILI
VIN = VSS or VCC
2
µA
Output leakage
current
ILO
S = VCC, VOUT = VSS or VCC
2
3
µA
VCC = 2.5 V, fC = 5 MHz,
C = 0.1 VCC/0.9 VCC, Q = open
V
CC = 2.5 V, fC = 10 MHz,
2(1)
C = 0.1 VCC/0.9 VCC, Q = open
Supply current
(Read)
ICC
mA
VCC = 3.0 V, fC = 10 MHz
4
5(1)
C = 0.1 VCC/0.9 VCC, Q = open
VCC = 5.5 V, fC = 20 MHz,
C = 0.1 VCC/0.9 VCC, Q = open
Supply current
(Write)
(2)
ICC0
During tW, S = VCC, 2.5 V < VCC < 5.5 V
5
3(1)
mA
µA
S = VCC, VCC = 5.5 V
VIN = VSS or VCC
Supply current
(Standby)
S = VCC, VCC = 5.0 V
VIN = VSS or VCC
ICC1
2
S = VCC, VCC = 2.5 V
VIN = VSS or VCC
1(3)
VIL
VIH
VOL
Input low voltage
Input high voltage
–0.45 0.3 VCC
0.7 VCC VCC+1
0.4
V
V
V
Output low voltage IOL = 1.5 mA, VCC = 2.5 V
VCC = 2.5 V and IOH = 0.4 mA or
Output high voltage
VOH
0.8 VCC
V
V
VCC = 5 V and IOH = 2 mA
Internal reset
threshold voltage
VRES
1.0(4)
1.65(5)
(2)
1. Only for the device identified by process letter K.
2. Characterized only, not tested in production.
3. 2 µA with the device identified by process letter K.
4. 0.7 V with the device identified by process letter K.
5. 1.3 V with the device identified by process letter K.
34/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
DC and AC parameters
Table 16. DC characteristics (M95320-R, M95320-DR, device grade 6)
Symbol
Parameter
Test conditions(1)
Min.
Max.
Unit
Input leakage
current
ILI
VIN = VSS or VCC
2
µA
Output leakage
current
ILO
S = VCC, voltage applied on Q = VSS or VCC
2
2
µA
VCC = 1.8 V, max clock frequency (fC),
C = 0.1VCC/0.9VCC, Q = open
Supply current
(Read)
ICC
mA
VCC = 1.8 V, fC = 5 MHz,
2(2)
C = 0.1VCC/0.9VCC, Q = open
Supply current
(Write)
(3)
ICC0
V
CC = 1.8 V, during tW, S = VCC
5
mA
µA
Supply current
(Standby)
ICC1
VCC = 1.8 V, S = VCC, VIN = VSS or VCC
1
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
1.8 V ≤VCC < 2.5 V
–0.45
0.25 VCC
VCC+1
0.3
V
V
V
V
1.8 V ≤VCC < 2.5 V
0.75 VCC
VOL
VOH
IOL = 0.15 mA, VCC = 1.8 V
Output high voltage IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
1.0(4)
Internal reset
threshold voltage
VRES
1.65(5)
V
(3)
1. If the application uses the M95320-R device at 2.5 V ≤VCC ≤5.5 V and –40 °C ≤TA ≤+85 °C, please refer to Table 15: DC
characteristics (M95320-W, device grade 6), rather than to the above table.
2. For the device identified by process letter K.
3. Characterized only, not tested in production.
4. 0.7 V with the device identified by process letter K.
5. 1.3 V with the device identified by process letter K.
Doc ID 5711 Rev 14
35/48
DC and AC parameters
M95320-W M95320-R M95320-DR
Table 17. AC characteristics (M95320-W, device grade 6)
Test conditions specified in Table 10 and Table 11
Min. Max.
VCC = 2.5 to 5.5 V
Min.
Max.
Symbol
Alt.
Parameter
Unit
New products
V
CC = 4.5 to 5.5 V
fC
fSCK Clock frequency
D.C.
30
30
40
30
30
42
40
10
D.C.
15
15
20
15
15
20
20
20
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
tCS
S deselect time
tCSH S active hold time
S not active hold time
tCLH Clock high time
tCLL Clock low time
(1)
tCH
(1)
tCL
(2)
tCLCH
tRC
tFC
Clock rise time
Clock fall time
2
2
2
2
(2)
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
10
10
30
30
0
5
10
15
15
0
tDH
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
0
0
(2)
tSHQZ
tDIS Output disable time
tV Clock low to output valid
40
40
20
20
(3)
tCLQV
tCLQX
tHO Output hold time
tRO Output rise time
0
0
(2)
tQLQH
40
40
40
40
5
20
20
20
20
5
(2)
tQHQL
tFO
tLZ
tHZ
Output fall time
tHHQV
HOLD high to output valid
HOLD low to output high-Z
(2)
tHLQZ
tW
tWC Write time
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
3. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU
.
36/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
DC and AC parameters
Table 18. AC characteristics (M95320-R, M95320-DR, device grade 6)
Test conditions specified in Table 10 and Table 11(1)
Symbol Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock frequency
D.C.
60
60
90
60
60
90
90
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH tCSS1 S active setup time
tSHCH tCSS2 S not active setup time
tSHSL
tCHSH
tCHSL
tCS S deselect time
tCSH S active hold time
S not active hold time
(2)
tCH
tCLH Clock high time
(2)
tCL
tCLL Clock low time
(3)
tCLCH
tRC Clock rise time
2
2
(3)
tCHCL
tFC Clock fall time
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
tDH Data in hold time
20
20
60
60
0
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
tDIS Output disable time
tV Clock low to output valid
tHO Output hold time
0
(3)
tSHQZ
tCLQV
tCLQX
80
80
0
(3)
tQLQH
tRO Output rise time
80
80
80
80
5
(3)
tQHQL
tFO Output fall time
tHHQV
tLZ HOLD high to output valid
tHZ HOLD low to output high-Z
tWC Write time
(3)
tHLQZ
tW
1. If the application uses the M95320-R at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, please refer t to
Table 17: AC characteristics (M95320-W, device grade 6) rather than to the above table.
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Characterized only, not tested in production.
Doc ID 5711 Rev 14
37/48
DC and AC parameters
Figure 19. Serial input timing
M95320-W M95320-R M95320-DR
tSHSL
S
C
tCHSL
tSLCH
tCH
tCHSH
tSHCH
tDVCH
tCHCL
tCHDX
tCL
tCLCH
MSB IN
LSB IN
D
Q
High impedance
AI01447d
Figure 20. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQV
tHLQZ
Q
HOLD
AI01448c
38/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
DC and AC parameters
Figure 21. Serial output timing
S
tCH
tSHSL
C
tCLQV
tCLQX
tCLCH
tCHCL
tCL
tSHQZ
Q
D
tQLQH
tQHQL
ADDR
LSB IN
AI01449f
Doc ID 5711 Rev 14
39/48
Package mechanical data
M95320-W M95320-R M95320-DR
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
millimeters
inches(1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.750
0.250
0.0689
0.0098
0.100
1.250
0.280
0.170
0.0039
0.0492
0.0110
0.0067
0.480
0.230
0.100
5.000
6.200
4.000
-
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
ccc
D
4.900
6.000
3.900
1.270
4.800
5.800
3.800
-
0.1929
0.2362
0.1535
0.0500
0.1890
0.2283
0.1496
-
E
E1
e
h
0.250
0°
0.500
8°
0.0098
0°
0.0197
8°
k
L
0.400
1.270
0.0157
0.0500
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
40/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
Package mechanical data
Figure 23. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
-"
-#
E
B
E
B
$
,ꢀ
,ꢀ
,ꢃ
,ꢃ
0IN ꢀ
%ꢆ
+
%
%ꢆ
+
,
,
!
$ꢆ
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!ꢀ
1. Drawing is not to scale.
:7?-%E
2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 20. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.550
0.020
0.250
2.000
1.600
0.450
0.000
0.200
1.900
1.500
1.200
2.900
0.100
1.200
0.600
0.050
0.300
2.100
1.700
1.600
3.100
0.300
1.600
0.0217
0.0008
0.0098
0.0787
0.0630
0.0177
0.0000
0.0079
0.0748
0.0591
0.0472
0.1142
0.0039
0.0472
0.0236
0.0020
0.0118
0.0827
0.0669
0.0630
0.1220
0.0118
0.0630
A1
b
D
D2 (rev MB)
D2 (rev MC)
E
3.000
0.200
0.1181
0.0079
E2 (rev MB)
E2 (rev MC)
e
0.500
0.0197
K (rev MB)
K (rev MC)
L
0.800
0.300
0.300
0.0315
0.0118
0.0118
0.500
0.150
0.0197
0.0059
L1
L3
0.300
0.080
0.0118
0.0031
eee(2)
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
Doc ID 5711 Rev 14
41/48
Package mechanical data
M95320-W M95320-R M95320-DR
Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 21. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
0.100
3.100
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
-
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
-
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
-
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8
8°
0°
8
8°
N
1. Values in inches are converted from mm and rounded to four decimal digits.
42/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
Part numbering
11
Part numbering
Table 22. Ordering information scheme
Example:
M95320
W MN 6
T
P /P
Device type
M95 = SPI serial access EEPROM
Device function
320 = 32 Kbit (4096 x 8)
320-D = 32 Kbit plus Identification page
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB or MC = MLP8 (2 x 3 mm)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)
Process(1)
/P or /K= Manufacturing technology code
1. The process letters appear on the device package (marking) and on the shipment box. Please contact your
nearest ST Sales Office.
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Revision history
M95320-W M95320-R M95320-DR
12
Revision history
Table 23. Document revision history
Date
Revision
Changes
Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp
1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2,
Ordering Info, Mechanical Data
13-Jul-2000
1.2
Test condition added ILI and ILO, and specification of tDLDH and tDHDL
removed.
tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range.
“-V” Voltage range changed to “2.7V to 3.6V” throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
16-Mar-2001
1.3
“Bus Master and Memory Devices on the SPI bus” illustration updated.
Package Mechanical data updated
19-Jul-2001
06-Dec-2001
18-Dec-2001
1.4
1.5
2.0
M95160 and M95080 devices removed to their own data sheet
Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated
Document reformatted using the new template. No parameters changed.
Announcement made of planned upgrade to 10MHz clock for the 5V, –40
to 85°C, range.
08-Feb-2002
18-Dec-2002
2.1
2.2
Endurance set to 100K write/erase cycles
10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write
cycles distinguished on front page, and in the DC and AC Characteristics
tables
Process identification letter corrected in footnote to AC Characteristics
table for temp. range 3
26-Mar-2003
26-Jun-2003
2.3
2.4
-S voltage range upgraded by removing it and inserting -R voltage range
in its place
15-Oct-2003
21-Nov-2003
28-Jan-2004
3.0
3.1
4.0
Table of contents, and Pb-free options added. VIL(min) improved to -0.45V
VI(min) and VO(min) corrected (improved) to -0.45V
TSSOP8 connections added to DIP and SO connections
M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and
related characteristics added.
20MHz Clock rate added.TSSOP14 package removed and MLP8 package
added.
Description of Power On Reset: VCC Lock-Out Write Protect updated.
Product List summary table added. Absolute Maximum Ratings for
VIO(min) and VCC(min) improved. Soldering temperature information
clarified for RoHS compliant devices. Device Grade 3 clarified, with
reference to HRCF and automotive environments. AEC-Q100-002
compliance. tCHHL(min) and tCHHH(min) is tCH for products under “S”
24-May-2005
5.0
process. tHHQX corrected to tHHQV
.
Figure 20: Hold timing updated.
44/48
Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
Revision history
Table 23. Document revision history (continued)
Date Revision Changes
Document converted to new ST template.
Packages are ECOPACK® compliant. PDIP package removed.
SO8N package specifications updated (see Table 23 and Figure 22).
M95640-S and M95320-S part numbers removed (DC and AC parameters
updated accordingly).
How to identify previous, current and new products by the Process
identification letter Table removed.
Figure 9: SPI modes supported updated and Note 2 added. First three
paragraphs of Section 4: Operating features replaced by Section 4.1:
Supply voltage (VCC).
07-Jul-2006
6
TA added to Table 8: Absolute maximum ratings. ICC and ICC1 updated in
Table 13, Table 16, Table 16 and Table 19. VOL and VOH updated in
Table 16. ICC updated in Table 17. Data in Table 19 is no longer
preliminary.
tCH updated in Table 32. Table 21: AC characteristics (M95640-R) added.
Timing line of tSHQZ modified in Figure 21: Serial output timing.
Process letter added to Table 45: Ordering information scheme, Note 2
removed. Note 2 removed from Figure 2.
JEDEC standard revision updated to D in Note 1 below Table 8: Absolute
maximum ratings.
Note 2 removed below Figure 8 and explanatory paragraph added.
Section 4.1: Supply voltage (VCC) updated. Table 5: Address range bits
corrected.
Products operating at VCC = 4.5 V to 5.5 V are no longer available in the
device grade 6 TA temperature range.
ICC and ICC1 parameters modified in Table 16: DC characteristics
(M95320-W, device grade 6).
Maximum frequency for M95320-W and M95640-W upgraded from 5 MHz
to 10 MHz in the device grade 6 TA temperature range (Table 32: AC
characteristics (M95080-W, device grade 6) modified accordingly).
09-Oct-2007
7
Table 27: Available M95640x products (package, voltage range,
temperature grade): /PB process letter added, /P process letter removed.
Blank option removed below Plating technology in Table 45: Ordering
information scheme.
Table 25 and Table 27 added. Small text changes.
Table 24: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead,
package mechanical data updated.
Package mechanical inch values calculated from mm and rounded to 4
decimal digits in Section 10: Package mechanical data.
Section 3.8: VSS ground added.
Device behavior when VCC passes over the POR threshold updated (see
Section 4.1.2: Device reset and Section 4.1.4: Power-down).
17-Dec-2007
8
VIL and VIH modified in Table 19: DC characteristics (M95640-DF, device
grade 6).
tW, write time, modified in Table 20: AC characteristics (M95320-R) and
Table 21: AC characteristics (M95640-R). Small text changes.
Doc ID 5711 Rev 14
45/48
Revision history
Table 23. Document revision history (continued)
M95320-W M95320-R M95320-DR
Date
Revision
Changes
Section 4.1: Supply voltage (VCC) updated.
10 MHz frequencies added to Table 26: AC characteristics (M95080,
device grade 3) and Table 29: AC characteristics (M95080-W, device
grade 3).
20-Mar-2008
23-Jun-2008
9
Small text changes.
Section 4.1: Supply voltage (VCC) updated.
Table 19: DC characteristics (M95640-DF, device grade 6) modified.
10
Figure 23: Serial input timing, Figure 20: Hold timing and Figure 21: Serial
output timing modified.
Section 4.1: Supply voltage (VCC) and Section 6.4: Write Status Register
(WRSR) updated.
Note added to Section 6.6: Write to Memory Array (WRITE).
Section 7.2: Initial delivery state specified.
Note modified in Table 14: Capacitance. ICC at 10 MHz added to Table 16:
DC characteristics (M95080, device grade 3).
17-Feb-2009
11
VRES parameter added to DC characteristics tables 16, 16, 17 and 19.
Note added to tCLQV in AC characteristics tables 26, 32, 29 and 21.
Note added to Table 20: AC characteristics (M95320-R) and Table 21: AC
characteristics (M95640-R).
Process letter modified in Table 45: Ordering information scheme.
64 Kbit densities removed from datasheet.
ECOPACK status of packages specified in Features and in Table 45:
Ordering information scheme.
07-Dec-2009
12
IOL and IOH added to Table 8: Absolute maximum ratings.
Note 2 added below Figure 27: UFDFPN8 (MLP8) - 8-lead ultra thin fine
pitch dual flat no lead, package outline.
Small text changes.
Added part number M95320-DR and related explanations:
– Table 4: M95320-DR instruction set
– Section 6.7: Read Identification Page
– Section 6.9: Read Lock Status
– Section 6.10: Lock ID
– Figure 16: Read Lock Status sequence
– Figure 17: Lock ID sequence
Updated:
– Features
13-May-2011
13
– Section 1: Description
– Section 6.4: Write Status Register (WRSR)
– Section 6.6: Write to Memory Array (WRITE)
– Table 8: Absolute maximum ratings
– Table 40: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 x 3 mm, data
– All tables in Section 9: DC and AC parameters
– Section 11: Part numbering
– Figure 27: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no
lead, package outline.
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Doc ID 5711 Rev 14
M95320-W M95320-R M95320-DR
Revision history
Table 23. Document revision history (continued)
Date Revision Changes
Datasheet split into:
– M95320-W, M95320-R, M95320-DR (this datasheet) for standard
products (range 6),
29-May-2012
14
– M95320-125 datasheet for automotive products (range 3).
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M95320-W M95320-R M95320-DR
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Doc ID 5711 Rev 14
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