M95320-WMN3TG/B [STMICROELECTRONICS]
32 Kbit and 64 Kbit Serial SPI bus EEPROMs with high speed clock; 32千位和64千位串行SPI总线的EEPROM与高速时钟
| 型号： | M95320-WMN3TG/B |
| 厂家： | 
ST |
| 描述： | 32 Kbit and 64 Kbit Serial SPI bus EEPROMs with high speed clock |
| 文件： | 总44页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95320 M95320-W M95320-R
M95640 M95640-W M95640-R
32 Kbit and 64 Kbit Serial SPI bus EEPROMs
with high speed clock
Feature summary
■ Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
■ Single Supply Voltage:
– 4.5 to 5.5V for M95320 and M95640
– 2.5 to 5.5V for M95320-W and M95320-W
– 1.8 to 5.5V for M95320-R and M95640-R
SO8 (MN)
150 mil width
■ 10MHz, 5MHz or 2MHz clock rates
■ 5ms or 10ms Write Time
■ Status Register
■ Hardware Protection of the Status Register
■ Byte and Page Write (up to 32 Bytes)
■ Self-Timed Programming Cycle
■ Adjustable Size Read-Only EEPROM Area
■ Enhanced ESD Protection
TSSOP8 (DW)
169 mil width
■ More than 1 million Write cycles
■ More than 40-Year Data Retention
MLP8 (MB)
2x3 mm
■ Packages
– ECOPACK® (RoHS compliant)
July 2006
Rev 6
1/44
www.st.com
1
Contents
M95320, M95640, M95320-x, M95640-x
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.1
2.0.2
2.0.3
2.0.4
2.0.5
2.0.6
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.1
4.1.2
4.1.3
4.1.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Internal device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
4.4
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
6.2
6.3
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3.1
6.3.2
6.3.3
6.3.4
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/44
M95320, M95640, M95320-x, M95640-x
Contents
6.4
6.5
6.6
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
7.2
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9
10
11
12
3/44
List of tables
M95320, M95640, M95320-x, M95640-x
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operating conditions (M95320 and M95640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95320-W and M95640-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M95320 and M95640, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC characteristics (M95320 and M95640, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 31
AC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 32
AC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 33
AC characteristics (M95320-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC characteristics (M95640-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . 38
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 39
MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package mechanical data. . . . . . . 40
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
4/44
M95320, M95640, M95320-x, M95640-x
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Serial Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 38
Figure 19. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package outline . . . . . . . . . . . . . . 40
5/44
Summary description
M95320, M95640, M95320-x, M95640-x
1
Summary description
These electrically erasable programmable memory (EEPROM) devices are accessed by a
high speed SPI-compatible bus.
The M95320, M95320-W and M95320-R are 32Kbit devices organized as 4096 x 8 bits. The
M95640, M95640-W and M95640-R are 64Kbit devices organized as 8192 x 8 bits.
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 1.
The device is selected when Chip Select (S) is taken Low. Communications with the device
can be interrupted using Hold (HOLD).
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages.
ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic diagram
V
CC
D
C
S
Q
M95xxx
W
HOLD
V
SS
AI01789C
Figure 2.
8 pin package connections
M95xxx
S
Q
1
8
V
CC
HOLD
2
3
4
7
W
6
5
C
D
V
SS
AI01790D
1. See Package mechanical section for package dimensions and how to identify pin-1.
6/44
M95320, M95640, M95320-x, M95640-x
Summary description
Table 1.
Signal names
C
Serial Clock
Serial data Input
Serial data Output
Chip Select
Write Protect
Hold
D
Q
S
W
HOLD
VCC
VSS
Supply Voltage
Ground
7/44
Signal description
M95320, M95640, M95320-x, M95640-x
2
Signal description
During all operations, V must be held stable and within the specified valid range:
CC
V
(min) to V (max).
CC
CC
All of the input and output signals must be held High or Low (according to voltages of V ,
IH
V
, V or V , as specified in Table 13 to Table 17). These signals are described next.
OH
IL OL
2.0.1
2.0.2
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.0.3
2.0.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.0.5
2.0.6
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and must be stable during all write operations.
8/44
M95320, M95640, M95320-x, M95640-x
Connecting to the SPI bus
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the
others being high impedance.
Figure 3.
Bus master and memory devices on the SPI bus
VSS
VCC
R(2)
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
VCC
VCC
C
Q
D
C
Q
D
C Q D
VSS
VSS
VSS
SPI Bus Master
R(2)
R(2)
R(2)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI12836
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time
(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all
inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become
High at the same time, and so, that the tSHCH requirement is met).
9/44
Connecting to the SPI bus
M95320, M95640, M95320-x, M95640-x
3.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
■
■
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
■
■
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
SPI modes supported
CPOL CPHA
C
C
0
1
0
1
D
Q
MSB
MSB
AI01438B
10/44
M95320, M95640, M95320-x, M95640-x
Operating features
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Table 8.). In order to
CC
CC
secure a stable DC supply voltage, it is recommended to decouple the V line with a
CC
suitable capacitor (usually of the order of 10nF to 100nF) close to the V /V package
CC SS
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t ).
W
4.1.2
Power-up conditions
When the power supply is turned on, V rises from V to V . During this time, the Chip
CC
SS
CC
Select (S) is not allowed to float but must follow the V voltage, therefore the S line should
CC
be connected to V via a suitable pull-up resistor.
CC
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after Power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The V rise time must not be faster than 1V/µs.
CC
4.1.3
Internal device Reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)
circuit is included. At Power-up (continuous rise of V ), the device will not respond to any
CC
instruction until V has reached the Power On Reset threshold voltage (this threshold is
CC
lower than the minimum V operating voltage defined in Tables XX).
CC
When V has passed the POR threshold, the device is reset and in the following state:
CC
■
■
Standby Power mode
deselected (at next Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
■
not in the Hold Condition
Status Register state:
■
■
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status
Register are in the same state as when the power was last removed (they are non-
volatile bits).
11/44
Operating features
M95320, M95640, M95320-x, M95640-x
4.1.4
Power-down
At Power-down (continuous decrease of V ), as soon as V drops from the normal
CC
CC
operating voltage to below the Power On Reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected and in Standby Power mode (that is
there should be no internal Write cycle in progress). Chip Select (S) should be allowed to
follow the voltage applied on V
.
CC
4.2
Active Power and Standby Power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The
device consumes I , as specified in Table 13 to Table 17.
CC
When Chip Select (S) is High, the device is deselected. If an Erase/Write cycle is not
currently in progress, the device then goes in to the Standby Power mode, and the device
consumption drops to I
.
CC1
4.2.1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as
Serial Clock (C) already being Low (as shown in Figure 5).
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as
Serial Clock (C) already being Low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being Low.
Figure 5.
Hold condition activation
C
HOLD
Hold
Hold
Condition
Condition
AI02029D
12/44
M95320, M95640, M95320-x, M95640-x
Operating features
4.3
Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.4
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
■
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
■
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
■
■
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected.
This is the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
■
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
■
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-Protected block size
Status Register Bits
Array Addresses Protected
Protected Block
M95640, M95640-W,
M95640-R, M95640-S
M95320, M95320-W,
M95320-R, M95320-S
BP1
BP0
0
0
1
1
0
1
0
1
none
none
none
Upper quarter
Upper half
1800h - 1FFFh
1000h - 1FFFh
0000h - 1FFFh
0C00h - 0FFFh
0800h - 0FFFh
0000h - 0FFFh
Whole memory
13/44
Memory organization
M95320, M95640, M95320-x, M95640-x
5
Memory organization
The memory is organized as shown in Figure 6.
Figure 6.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
1 Page
X Decoder
AI01272C
14/44
M95320, M95640, M95320-x, M95640-x
Instructions
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in <Blue>Table 3.), the device
automatically deselects itself.
Table 3.
Instruction set
Instruction
Description
Instruction Format
WREN
WRDI
Write Enable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Write Disable
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
High.
Figure 7.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
15/44
Instructions
M95320, M95640, M95320-x, M95640-x
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
■
Power-up
■
■
■
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 8.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
16/44
M95320, M95640, M95320-x, M95640-x
Instructions
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The Status Register format is shown in Table 4 and the status and control bits of the Status
Register are as follows:
6.3.1
6.3.2
6.3.3
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4.
Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
17/44
Instructions
M95320, M95640, M95320-x, M95640-x
Figure 9.
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 10.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is
driven High, the self-timed Write Status Register cycle (whose duration is t ) is initiated.
W
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in Table 4.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to
be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)
instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)
bits are frozen at their current values from just before the start of the execution of Write
Status Register (WRSR) instruction. The new, updated, values take effect at the moment of
completion of the execution of Write Status Register (WRSR) instruction.
18/44
M95320, M95640, M95320-x, M95640-x
Instructions
Table 5.
Protection modes
Memory Content
W
Signal
SRWD
Bit
Write Protection of the
Mode
Unprotected
Status Register
Protected Area(1)
Area(1)
1
0
0
0
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
Software
Protected
(SPM)
Ready to accept
Write instructions
Write Protected
The values in the BP1 and
BP0 bits can be changed
1
1
Status Register is
Hardware write protected
Hardware
Protected
(HPM)
Ready to accept
Write instructions
0
1
Write Protected
The values in the BP1 and
BP0 bits cannot be
changed
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summarized in Table 2.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
■
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
■
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
■
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
■
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
19/44
Instructions
M95320, M95640, M95320-x, M95640-x
(1)
Table 6.
Device
Address Bits
Address range bits
32 Kbit Devices
64 Kbit Devices
A12-A0
A11-A0
1. b15 to b13 are Don’t Care on the 64 Kbit devices.
b15 to b12 are Don’t Care on the 32 Kbit devices.
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
20/44
M95320, M95640, M95320-x, M95640-x
Instructions
6.5
Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
21/44
Instructions
M95320, M95640, M95320-x, M95640-x
6.6
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte, address byte, and at least one data byte are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input
data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts, and continues for a period t
(as specified in Table 18 to Table 22), at
WC
the end of which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
■
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
■
■
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
■
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
22/44
M95320, M95640, M95320-x, M95640-x
Instructions
Figure 13. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
23/44
Power-up and delivery state
M95320, M95640, M95320-x, M95640-x
7
Power-up and delivery state
7.1
Power-up state
After Power-up, the device is in the following state:
■
■
Standby Power mode
deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
■
■
■
not in the Hold Condition
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
24/44
M95320, M95640, M95320-x, M95640-x
Maximum rating
8
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TSTG
TA
Storage Temperature
Ambient operating temperature
Lead Temperature during Soldering
Output Voltage
–65
–40
150
130
°C
°C
°C
V
TLEAD
VO
See note (1)
–0.50
–0.50
–0.50
VCC+0.6
6.5
VI
Input Voltage
V
VCC
Supply Voltage
6.5
V
Electrostatic Discharge Voltage (Human Body
model)(2)
VESD
–4000
4000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
25/44
DC and AC parameters
M95320, M95640, M95320-x, M95640-x
9
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Symbol
Operating conditions (M95320 and M95640)
Parameter
Min.
Max.
Unit
VCC
TA
Supply Voltage
4.5
–40
–40
5.5
85
V
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
°C
°C
125
Table 9.
Symbol
Operating conditions (M95320-W and M95640-W)
Parameter Min.
Max.
Unit
VCC
TA
Supply Voltage
2.5
–40
–40
5.5
85
V
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
°C
°C
125
Table 10. Operating conditions (M95320-R and M95640-R)
Symbol
Parameter
Min.(1)
Max. (1)
Unit
VCC
TA
Supply Voltage
Ambient Operating Temperature
1.8
5.5
85
V
–40
°C
1. This product is under development. For more information, please contact your nearest ST sales office.
(1)
Table 11. AC measurement conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
CL
Load Capacitance
30
pF
ns
V
Input Rise and Fall Times
50
Input Pulse Voltages
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Input and Output Timing Reference Voltages
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 14. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
0.3V
CC
CC
0.2V
CC
AI00825B
26/44
M95320, M95640, M95320-x, M95640-x
DC and AC parameters
(1)
Table 12. Capacitance
Symbol
Parameter
Test Condition
Min.
Max.
Unit
COUT
CIN
Output Capacitance (Q)
Input Capacitance (D)
VOUT = 0V
VIN = 0V
VIN = 0V
8
8
6
pF
pF
pF
Input Capacitance (other pins)
1. Sampled only, not 100% tested, at TA=25°C and a frequency of 5MHz.
Table 13. DC characteristics (M95320 and M95640, device grade 6)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input Leakage Current
VIN = VSS or VCC
± 2
± 2
µA
µA
Output Leakage
Current
ILO
ICC
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 10MHz,
Supply Current
5
2
mA
µA
VCC = 5V, Q = open
Supply Current
(Standby)
S = VCC, VCC = 5V,
VIN = VSS or VCC
ICC1
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45 0.3VCC
0.7VCC VCC+1
0.4
V
V
V
V
(1)
VOL
IOL = 2 mA, VCC = 5V
IOH = –2 mA, VCC = 5V
(1)
VOH
0.8VCC
1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 14. DC characteristics (M95320 and M95640, device grade 3)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS or VCC
± 2
± 2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5MHz,
VCC = 5V, Q = open
ICC
Supply Current
4
5
mA
µA
Supply Current
(Standby)
S = VCC, VCC = 5V,
ICC1
VIN = VSS or VCC
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45 0.3 VCC
0.7 VCC VCC+1
0.4
V
V
V
V
(1)
VOL
IOL = 2mA, VCC = 5V
IOH = –2mA, VCC = 5V
(1)
VOH
0.8 VCC
1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
27/44
DC and AC parameters
M95320, M95640, M95320-x, M95640-x
Table 15. DC characteristics (M95320-W and M95640-W, device grade 6)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS or VCC
± 2
± 2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5MHz,
VCC = 2.5V, Q = open
ICC
Supply Current
3
1
mA
µA
Supply Current
(Standby)
S = VCC, VCC = 2.5V
VIN = VSS or VCC
ICC1
VIL
VIH
Input Low Voltage
Input High Voltage
–0.45 0.3VCC
0.7VCC VCC+1
V
V
IOL = 1.5mA, VCC = 2.5V or
IOL = 2mA, VCC = 5.5V
VOL
VOH
Output Low Voltage
Output High Voltage
0.4
V
V
IOH = –0.4mA, VCC = 2.5V or
IOH = –2mA, VCC = 5.5V
0.8VCC
Table 16. DC characteristics (M95320-W and M95640-W, device grade 3)
Symbol
Parameter
Test Condition
Min.
Max. Unit
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS or VCC
± 2
± 2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5MHz,
VCC = 2.5V, Q = open
ICC
Supply Current
3
2
mA
ICC1
VIL
Supply Current (Standby) S = VCC, VCC = 2.5V, VIN = VSS or VCC
µA
V
Input Low Voltage
Input High Voltage
–0.45 0.3VCC
0.7VCC VCC+1
0.4
VIH
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 1.5mA, VCC = 2.5V
IOH = –0.4mA, VCC = 2.5V
V
0.8VCC
V
28/44
M95320, M95640, M95320-x, M95640-x
DC and AC parameters
Min.(1) Max.(1) Unit
Table 17. DC characteristics (M95320-R and M95640-R)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS or VCC
± 1
± 1
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at max clock
frequency, 1.8V < VCC = 2.5V,
Q = open
ICC
Supply Current
3
1
mA
µA
S = VCC, VIN = VSS or VCC
,
ICC1
Supply Current (Standby)
1.8V < VCC = 2.5V
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45 0.3 VCC
0.7 VCC VCC+1
0.3
V
V
V
V
VOL
VOH
IOL = 0.15 mA, VCC = 1.8 V
IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
1. This product is under qualification. For more information, please contact your nearest ST sales office.
29/44
DC and AC parameters
M95320, M95640, M95320-x, M95640-x
Table 18. AC characteristics (M95320 and M95640, device grade 6)
Test conditions specified in Table 11 and Table 8
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock Frequency
D.C.
15
15
40
25
15
40
40
10
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S Active Setup Time
tCSS2 S Not Active Setup Time
tCS
S Deselect Time
tCSH S Active Hold Time
S Not Active Hold Time
(1)
tCH
tCLH
tCLL
tRC
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
(1)
tCL
(2)
tCLCH
1
1
(2)
tCHCL
tFC
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data In Setup Time
15
15
15
20
0
tDH
Data In Hold Time
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
Output Disable Time
0
(2)
tSHQZ
tDIS
tV
25
25
tCLQV
tCLQX
Clock Low to Output Valid
Output Hold Time
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output Rise Time
20
20
25
25
5
(2)
tQHQL
Output Fall Time
tHHQV
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
(2)
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
30/44
M95320, M95640, M95320-x, M95640-x
DC and AC parameters
Table 19. AC characteristics (M95320 and M95640, device grade 3)
Test conditions specified in Table 11 and Table 8
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock Frequency
D.C.
90
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S Active Setup Time
tCSS2 S Not Active Setup Time
tCS S Deselect Time
90
100
90
tCSH S Active Hold Time
S Not Active Hold Time
tCLH Clock High Time
tCLL Clock Low Time
90
(1)
tCH
90
(1)
tCL
90
(2)
tCLCH
tRC
tFC
Clock Rise Time
Clock Fall Time
1
1
(2)
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data In Setup Time
20
30
70
40
0
tDH
Data In Hold Time
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
0
(2)
tSHQZ
tDIS Output Disable Time
100
60
tCLQV
tCLQX
tV
Clock Low to Output Valid
Output Hold Time
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output Rise Time
50
50
50
100
5
(2)
tQHQL
Output Fall Time
tHHQV
HOLD High to Output Valid
HOLD Low to Output High-Z
(2)
tHLQZ
tHZ
tW
tWC Write Time
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
31/44
DC and AC parameters
M95320, M95640, M95320-x, M95640-x
Table 20. AC characteristics (M95320-W and M95640-W, device grade 6)
Test conditions specified in Table 11 and Table 9
Current
Product
New Product
Version(2)
Version(1)
Parameter
Symbol Alt.
Unit
Min. Max. Min. Max.
fC
fSCK Clock Frequency
D.C.
90
5
D.C.
30
30
40
30
30
42
40
10
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S Active Setup Time
tCSS2 S Not Active Setup Time
tCS S Deselect Time
tCSH S Active Hold Time
S Not Active Hold Time
tCLH Clock High Time
tCLL Clock Low Time
tRC Clock Rise Time
tFC Clock Fall Time
90
100
90
90
(3)
tCH
90
(3)
tCL
90
(4)
tCLCH
1
1
2
2
(4)
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tDSU Data In Setup Time
tDH Data In Hold Time
20
30
10
10
30
30
0
Clock Low Hold Time after HOLD not Active 70
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
40
0
Clock Low Set-up Time before HOLD not
Active
tCLHH
0
0
ns
(4)
tSHQZ
tCLQV
tCLQX
tDIS Output Disable Time
100
60
40
40
ns
ns
ns
ns
ns
ns
ns
ms
tV
Clock Low to Output Valid
tHO Output Hold Time
tRO Output Rise Time
tFO Output Fall Time
0
0
(4)
tQLQH
50
50
50
100
5
40
40
40
40
5
(4)
tQHQL
tHHQV
tLZ HOLD High to Output Valid
tHZ HOLD Low to Output High-Z
tWC Write Time
(4)
tHLQZ
tW
1. Current product version is identified by Process Identification letter ‘V’’.
2. New product version is identified by Process Identification letter ‘P’. Please contact your nearest ST sales
office for details (PCN MPG-NVM/05/1315 and PCN MPG-NVM/05/1191)
3. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
4. Value guaranteed by characterization, not 100% tested in production.
32/44
M95320, M95640, M95320-x, M95640-x
DC and AC parameters
Table 21. AC characteristics (M95320-W and M95640-W, device grade 3)
Test conditions specified in Table 11 and Table 9
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock Frequency
D.C.
90
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S Active Setup Time
tCSS2 S Not Active Setup Time
tCS S Deselect Time
tCSH S Active Hold Time
S Not Active Hold Time
tCLH Clock High Time
tCLL Clock Low Time
90
100
90
90
(1)
tCH
90
(1)
tCL
90
(2)
tCLCH
tRC Clock Rise Time
1
1
(2)
tCHCL
tFC
Clock Fall Time
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data In Setup Time
tDH Data In Hold Time
20
30
70
40
0
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
tDIS Output Disable Time
0
(2)
tSHQZ
100
60
tCLQV
tCLQX
tV
Clock Low to Output Valid
tHO Output Hold Time
tRO Output Rise Time
tFO Output Fall Time
0
(2)
tQLQH
50
50
50
100
5
(2)
tQHQL
tHHQV
tLZ
HOLD High to Output Valid
HOLD Low to Output High-Z
(2)
tHLQZ
tHZ
tW
tWC Write Time
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
33/44
DC and AC parameters
M95320, M95640, M95320-x, M95640-x
Table 22. AC characteristics (M95320-R)
Test conditions specified in Table 11 and Table 10
Symbol
Alt.
Parameter
Min.
D.C.
Max.
Unit
fC
fSCK
tCSS1
tCSS2
tCS
Clock Frequency
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
0
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
S Active Setup Time
60
60
90
60
60
90
90
S Not Active Setup Time
S Deselect Time
tCSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
(1)
tCH
tCLH
tCLL
tRC
(1)
tCL
Clock Low Time
(2)
tCLCH
Clock Rise Time
2
2
(2)
tCHCL
tFC
Clock Fall Time
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tDSU
tDH
Data In Setup Time
20
20
60
60
0
Data In Hold Time
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not
Active
tCLHH
0
0
(2)
tSHQZ
tDIS
tV
Output Disable Time
Clock Low to Output Valid
Output Hold Time
80
80
ns
ns
ns
ns
ns
ns
ns
ms
tCLQV
tCLQX
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output Rise Time
80
80
80
80
10
(2)
tQHQL
Output Fall Time
tHHQV
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
(2)
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
34/44
M95320, M95640, M95320-x, M95640-x
DC and AC parameters
Table 23. AC characteristics (M95640-R)
Test conditions specified in Table 11 and Table 9
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock Frequency
D.C.
150
150
200
150
150
200
200
2
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
0
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S Active Setup Time
tCSS2 S Not Active Setup Time
tCS
S Deselect Time
tCSH S Active Hold Time
S Not Active Hold Time
tCLH Clock High Time
tCLL Clock Low Time
(1)
tCH
(3)
tCL
(2)
tCLCH
tRC
tFC
Clock Rise Time
Clock Fall Time
2
2
(4)
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data In Setup Time
50
50
150
150
0
tDH
Data In Hold Time
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
Output Disable Time
0
0
(4)
tSHQZ
tDIS
tV
200
200
ns
ns
ns
ns
ns
ns
ns
ms
tCLQV
tCLQX
Clock Low to Output Valid
Output Hold Time
tHO
tRO
tFO
tLZ
0
(4)
tQLQH
Output Rise Time
200
200
200
200
10
(4)
tQHQL
Output Fall Time
tHHQV
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
(4)
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
35/44
DC and AC parameters
M95320, M95640, M95320-x, M95640-x
Figure 15. Serial Input timing
tSHSL
S
C
tCHSL
tSLCH
tCHSH
tSHCH
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 16. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQV
tHLQZ
Q
D
HOLD
AI01448B
36/44
M95320, M95640, M95320-x, M95640-x
DC and AC parameters
Figure 17. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
ADDR.
LSB IN
D
AI01449e
37/44
Package mechanical
M95320, M95640, M95320-x, M95640-x
10
Package mechanical
Figure 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 24. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.75
0.25
0.069
0.010
0.10
1.25
0.28
0.17
0.004
0.049
0.011
0.007
0.48
0.23
0.10
5.00
6.20
4.00
–
0.019
0.009
0.004
0.197
0.244
0.157
–
c
ccc
D
4.90
6.00
3.90
1.27
4.80
5.80
3.80
–
0.193
0.236
0.154
0.050
0.189
0.228
0.150
–
E
E1
e
h
0.25
0°
0.50
8°
0.010
0°
0.020
8°
k
L
0.40
1.27
0.016
0.050
L1
1.04
0.041
38/44
M95320, M95640, M95320-x, M95640-x
Package mechanical
Figure 19. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data
millimeters
Min.
inches
Min.
Symbol
Typ.
Max.
Typ.
Max.
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
39/44
Package mechanical
M95320, M95640, M95320-x, M95640-x
Figure 20. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package outline
e
b
D
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
Table 26. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
b
0.55
0.50
0.00
0.20
0.60
0.05
0.30
0.022
0.020
0.000
0.008
0.024
0.002
0.012
0.25
2.00
0.010
0.079
D
D2
ddd
E
1.55
1.65
0.05
0.061
0.065
0.002
3.00
0.118
E2
e
0.15
–
0.25
–
0.006
–
0.010
–
0.50
0.45
0.020
0.018
L
0.40
0.50
0.15
0.016
0.020
0.006
L1
L3
N
0.30
8
0.012
8
40/44
M95320, M95640, M95320-x, M95640-x
Part numbering
11
Part numbering
Table 27. Ordering information scheme
Example:
M95640
–
W MN 6
T
P
/B
Device Type
M95 = SPI serial access EEPROM
Device Function
640 = 64 Kbit (8192 x 8)
320 = 32 Kbit (4096 x 8)
Operating Voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB = MLP8 (2x3 mm)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow(1)Automotive
temperature range (–40 to 125 °C)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = ECOPACK (RoHS compliant)
Process letter(2)
/B = DP26% Rsst
/P = DP26% Chartered
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
2. The Process letter only concerns Grade-3 devices.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
The category of second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
41/44
Revision history
M95320, M95640, M95320-x, M95640-x
12
Revision history
Table 28. Document revision history
Date
Revision
Changes
Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp
1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2,
Ordering Info, Mechanical Data
13-Jul-2000
1.2
Test condition added ILI and ILO, and specification of tDLDH and tDHDL
removed.
tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range.
“-V” Voltage range changed to “2.7V to 3.6V” throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
16-Mar-2001
1.3
“Bus Master and Memory Devices on the SPI bus” illustration updated.
Package Mechanical data updated
19-Jul-2001
06-Dec-2001
18-Dec-2001
1.4
1.5
2.0
M95160 and M95080 devices removed to their own data sheet
Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated
Document reformatted using the new template. No parameters changed.
Announcement made of planned upgrade to 10MHz clock for the 5V, –40
to 85°C, range.
08-Feb-2002
18-Dec-2002
2.1
2.2
Endurance set to 100K write/erase cycles
10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write
cycles distinguished on front page, and in the DC and AC Characteristics
tables
Process indentification letter corrected in footnote to AC Characteristics
table for temp. range 3
26-Mar-2003
26-Jun-2003
2.3
2.4
-S voltage range upgraded by removing it and inserting -R voltage range
in its place
15-Oct-2003
21-Nov-2003
28-Jan-2004
3.0
3.1
4.0
Table of contents, and Pb-free options added. VIL(min) improved to -0.45V
VI(min) and VO(min) corrected (improved) to -0.45V
TSSOP8 connections added to DIP and SO connections
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M95320, M95640, M95320-x, M95640-x
Revision history
Table 28. Document revision history (continued)
Date
Revision
Changes
M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and
related characteristics added.
20MHz Clock rate added.TSSOP14 package removed and MLP8 package
added.
Description of Power On Reset: VCC Lock-Out Write Protect updated.
Product List summary table added. Absolute Maximum Ratings for
VIO(min) and VCC(min) improved. Soldering temperature information
clarified for RoHS compliant devices. Device Grade 3 clarified, with
reference to HRCF and automotive environments. AEC-Q100-002
compliance. tCHHL(min) and tCHHH(min) is tCH for products under “S”
24-May-2005
5.0
process. tHHQX corrected to tHHQV
.
Figure 16: Hold timing updated.
Document converted to new ST template.
Packages are ECOPACK® compliant. PDIP package removed.
SO8N package specifications updated (see Table 24 and Figure 18).
M95640-S and M95320-S part numbers removed (DC and AC parameters
updated accordingly).
How to identify previous, current and new products by the Process
identification letter Table removed.
Figure 4: SPI modes supported updated and Note 2 added. First three
paragraphs of Section 4: Operating features replaced by Section 4.1:
Supply voltage (VCC).
07-Jul-2006
6
TA added to Table 7: Absolute maximum ratings. ICC and ICC1 updated in
Table 13, Table 14, Table 15 and Table 17. VOL and VOH updated in
Table 15. ICC updated in Table 16. Data in Table 17 is no longer
preliminary.
tCH updated in Table 20. Table 23: AC characteristics (M95640-R) added.
Timing line of tSHQZ modified in Figure 17: Output timing.
Process letter added to Table 27: Ordering information scheme, Note 2
removed. Note 2 removed from Figure 2.
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M95320, M95640, M95320-x, M95640-x
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