M95512-WDW6T [STMICROELECTRONICS]
64KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.169 INCH, TSSOP-8;
| 型号： | M95512-WDW6T |
| 厂家： | 
ST |
| 描述： | 64KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.169 INCH, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总31页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95512-W
M95512-R
512Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
■
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
Figure 1. Packages
■
Single Supply Voltage:
–
–
2.5 to 5.5V for M95512-W
1.8 to 5.5V for M95512-R
■
High Speed
–
–
10MHz Clock Rate
5ms Write Time
8
■
■
■
■
■
■
■
■
Status Register
Hardware Protection of the Status Register
BYTE and PAGE WRITE (up to 128 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
1
SO8 (MN)
150 mil width
More than 100,000 Erase/Write Cycles
More than 40-Year Data Retention
TSSOP8 (DW)
169 mil width
Table 1. Product List
Reference
Part Number
M95512-W
M95512-R
M95512
June 2005
1/31
M95512-W, M95512-R
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/31
M95512-W, M95512-R
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Write Status Register (WRSR) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write to Memory Array (WRITE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13.Byte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14.Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Operating Conditions (M95512-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating Conditions (M95512-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. DC Characteristics (M95512-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. DC Characteristics (M95512-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. AC Characteristics (M95512-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. AC Characteristics (M95512-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 19.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 27
Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 28
Table 17. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 28
3/31
M95512-W, M95512-R
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. Ordering Information Scheme(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/31
M95512-W, M95512-R
SUMMARY DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 65536 x 8 bit.
Figure 3. SO and TSSOP Connections
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 2. and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
M95xxx
S
Q
1
8
V
CC
HOLD
2
3
4
7
W
6
5
C
D
V
SS
AI01790D
Figure 2. Logic Diagram
V
CC
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
D
C
S
Q
Table 2. Signal Names
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
M95xxx
D
Q
W
S
HOLD
W
HOLD
V
SS
V
Supply Voltage
Ground
CC
AI01789C
V
SS
5/31
M95512-W, M95512-R
SIGNAL DESCRIPTION
During all operations, VCC must be held stable and
within the specified valid range: VCC(min) to
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by Power mode. Driving Chip Select (S) Low se-
lects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
VCC(max).
All of the input and output signals must be held
High or Low (according to voltages of VIH, VOH, VIL
or VOL, as specified in Table 13.). These signals
are described next.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write instructions.
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
6/31
M95512-W, M95512-R
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4. shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
Figure 4. Bus Master and Memory Devices on the SPI Bus
V
CC
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
V
V
V
CC
C
Q
D
C
Q
D
C Q D
CC
CC
Bus Master
(ST6, ST7, ST9,
ST10, Others)
(2)
(2)
(2)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
R
R
R
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI03746e
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
7/31
M95512-W, M95512-R
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
–
–
CPOL=0, CPHA=0
CPOL=1, CPHA=1
–
–
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
Figure 5. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
8/31
M95512-W, M95512-R
OPERATING FEATURES
Power-up
Active Power and Standby Power Modes
When the power supply is turned on, VCC rises
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode. The device
consumes ICC, as specified in Table 13.
from VSS to VCC
.
During this time, the Chip Select (S) must be al-
lowed to follow the VCC voltage. It must not be al-
lowed to float, but should be connected to VCC via
a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
When Chip Select (S) is High, the device is dese-
lected. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Standby
Power mode, and the device consumption drops
to ICC1
.
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
Power On Reset
In order to prevent inadvertent Write operations
during Power-up, a Power On Reset (POR) circuit
is included. At Power-up, the device will not re-
spond to any instruction until the VCC has reached
the Power On Reset threshold voltage (this thresh-
old is lower than the VCC min operating voltage
defined in Table 8. and Table 9.). In the same way,
as soon as VCC drops from the normal operating
voltage to below the Power On Reset threshold
voltage, the device stops responding to any in-
struction sent to it.
Prior to selecting and issuing instructions to the
memory, a valid and stable VCC voltage must be
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (tW).
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
6.).
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 6. also shows what happens if the rising
and falling edges are not timed to coincide with
Serial Clock (C) being Low.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on VCC
.
Figure 6. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
AI02029D
9/31
M95512-W, M95512-R
Status Register
Figure 7. shows the position of the Status Register
in the control logic of the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
device features the following data protection
mechanisms:
■
Write and Write Status Register instructions
are checked that they consist of a number of
clock pulses that is a multiple of eight, before
they are accepted for execution.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
■
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
–
–
Power-up
Write Disable (WRDI) instruction
completion
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
–
–
Write Status Register (WRSR) instruction
completion
Write (WRITE) instruction completion
■
■
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
Table 3. Status Register Format
For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and before the next rising edge of Serial
Clock (C).
b7
b0
SRWD
0
0
0
BP1 BP0 WEL WIP
Two points need to be noted in the previous sen-
tence:
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
–
The ‘last bit of the instruction’ can be the
eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction
(except for Read Status Register (RDSR) and
Read (READ) instructions).
Data Protection and Protocol Control
–
The ‘next rising edge of Serial Clock (C)’ might
(or might not) be the next bus transaction for
some other device on the SPI bus.
Non-volatile memory devices can be used in envi-
ronments that are particularly noisy, and within ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the
Table 4. Write-Protected Block Size
Status Register Bits
Protected Block
Array Addresses Protected
BP1
BP0
0
0
1
1
0
1
0
1
none
none
Upper quarter
Upper half
C000h - FFFFh
8000h - FFFFh
0000h - FFFFh
Whole memory
10/31
M95512-W, M95512-R
MEMORY ORGANIZATION
The memory is organized as shown in Figure 7.
Figure 7. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
1 Page
X Decoder
AI01272C
11/31
M95512-W, M95512-R
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 5..
If an invalid instruction is sent (one not contained
in Table 5.), the device automatically deselects it-
self.
Table 5. Instruction Set
Instruc
Instruction
Format
Description
tion
WREN Write Enable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
WRDI
RDSR
Write Disable
Read Status Register
WRSR Write Status Register
READ Read from Memory Array
WRITE Write to Memory Array
12/31
M95512-W, M95512-R
Write Enable (WREN)
As shown in Figure 8., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
Figure 8. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
Write Disable (WRDI)
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 9., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
–
–
–
–
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 9. Write Disable (WRDI) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
13/31
M95512-W, M95512-R
Read Status Register (RDSR)
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 3.) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 10..
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
Figure 10. Read Status Register (RDSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
14/31
M95512-W, M95512-R
Write Status Register (WRSR)
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
timed Write Status Register cycle (whose duration
is tW) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Write Status Register cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 11..
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Figure 11. Write Status Register (WRSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
15/31
M95512-W, M95512-R
Table 6. Protection Modes
Memory Content
W
Signal
SRWD
Bit
Write Protection of the
Status Register
Mode
(1)
(1)
Protected Area
Unprotected Area
1
0
0
0
Status Register is Writable
Software (if the WREN instruction
Protected has set the WEL bit)
Ready to accept Write
instructions
Write Protected
(SPM)
The values in the BP1 and
BP0 bits can be changed
1
1
Status Register is
Hardware Hardware write protected
Protected The values in the BP1 and Write Protected
Ready to accept Write
instructions
0
1
(HPM)
BP0 bits cannot be
changed
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6..
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 3..
The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable
(SRWD) and Block Protect (BP1, BP0) bits are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of completion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.
need to be considered, depending on the state of
Write Protect (W):
–
If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction.
–
If Write Protect (W) is driven Low, it is not
possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect
(BP1, BP0) bits of the Status Register, are
also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
–
by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
The protection features of the device are summa-
rized in Table 4..
–
or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
16/31
M95512-W, M95512-R
Read from Memory Array (READ)
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
As shown in Figure 12., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address bytes are
then shifted in, on Serial Data Input (D). The ad-
dress is loaded into an internal address register,
and the byte of data at that address is shifted out,
on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the
internal address register is automatically incre-
mented, and the byte of data at the new address is
shifted out.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.
Figure 12. Read from Memory Array (READ) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
17/31
M95512-W, M95512-R
Write to Memory Array (WRITE)
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the inter-
nal address counter rolls over to the beginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 128 bytes).
As shown in Figure 13., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High at a byte boundary of the input data.
In the case of Figure 13., this occurs after the
eighth bit of the data byte has been latched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period tWC (as specified in Ta-
ble 15.), at the end of which the Write in Progress
(WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 14., the next byte of input
data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.
The instruction is not accepted, and is not execut-
ed, under the following conditions:
–
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
–
–
if a Write cycle is already in progress
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last
data byte that has been latched in)
–
if the addressed page is in the region
protected by the Block Protect (BP1 and BP0)
bits.
Figure 13. Byte Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
18/31
M95512-W, M95512-R
Figure 14. Page Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
D
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
POWER-UP AND DELIVERY STATE
Power-up State
Initial Delivery State
After Power-up, the device is in the following state:
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.
–
–
Standby Power mode
Deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be started).
–
–
–
Not in the Hold Condition
Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
19/31
M95512-W, M95512-R
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 7. may cause permanent damage to the de-
vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 7. Absolute Maximum Ratings
Symbol
Parameter
Ambient Operating Temperature
Min.
–40
–65
Max.
Unit
°C
T
A
125
T
Storage Temperature
150
°C
STG
(1)
TLEAD
VO
Lead Temperature during Soldering
Output Voltage
°C
V
See note
–0.50
–0.50
–0.50
V
CC+0.6
VI
Input Voltage
6.5
V
V
CC
Supply Voltage
6.5
V
2
VESD
–4000
4000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
20/31
M95512-W, M95512-R
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 8. Operating Conditions (M95512-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
Supply Voltage
Ambient Operating Temperature (Device Grade 6)
CC
TA
–40
85
°C
Table 9. Operating Conditions (M95512-R)
1
Symbol
Min.
1.8
Max.
5.5
Unit
V
Parameter
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–40
85
°C
Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
Table 10. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
50
0.2V to 0.8V
Input Pulse Voltages
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Voltages
V
CC
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 15. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
0.2V
CC
CC
0.7V
CC
0.3V
CC
AI00825B
Table 11. Capacitance
Symbol
COUT
Parameter
Test Condition
= 0V
Min.
Max.
Unit
pF
Output Capacitance (Q)
Input Capacitance (D)
V
8
8
6
OUT
CIN
V
= 0V
= 0V
pF
IN
IN
Input Capacitance (other pins)
V
pF
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 5 MHz.
A
21/31
M95512-W, M95512-R
Table 12. DC Characteristics (M95512-W, Device Grade 6)
Test Condition
(1)
(1)
Symbol
Parameter
Unit
Min.
Max.
(in addition to those in Table 8.)
ILI
Input Leakage Current
Output Leakage Current
V
IN = VSS or VCC
± 2
± 2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 10MHz,
10
3
V
CC = 5V, Q = open
C = 0.1VCC/0.9VCC at 5MHz,
ICC
Supply Current
mA
VCC = 2.5V, Q = open
C = 0.1VCC/0.9VCC at 1MHz,
1
VCC = 2.5V, Q = open
S = VCC, VCC = 2.5V, VIN = VSS or VCC
S = VCC, VCC = 5V, VIN = VSS or VCC
5
5
Supply Current
(Standby Power mode)
ICC1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.3 VCC
VCC+1
0.4
V
V
V
V
0.7 VCC
VOL
VOH
IOL = 1.5 mA, VCC = 2.5 V
I
OH = –0.4 mA, VCC = 2.5 V
0.8 VCC
Note: 1. The information contained in Table 12. is subject to change without previous notice.
Table 13. DC Characteristics (M95512-R)
(1)
Test Condition
(1)
(1)
Symbol
Parameter
Unit
Min.
Max.
(in addition to those in Table 9.)
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS or VCC
± 2
± 2
µA
µA
ILO
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 2 MHz,
ICC
Supply Current
1
3
mA
µA
V
CC = 1.8 V, Q = open
Supply Current
(Standby Power mode)
ICC1
S = VCC, VIN = VSS or VCC, VCC = 1.8 V
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.3 VCC
VCC+1
0.3
V
V
V
V
0.7 VCC
VOL
VOH
I
OL = 0.15 mA, VCC = 1.8 V
I
OH = –0.1 mA, VCC = 1.8 V
0.8 VCC
Note: 1. The information contained in Table 13. is subject to change without previous notice.
22/31
M95512-W, M95512-R
Table 14. AC Characteristics (M95512-W, Device Grade 6)
Test conditions specified in Table 10. and Table 8.
V
= 2.5V
V
= 4.5V
CC
(3)
CC
(3)
Symbol
Alt.
Parameter
Unit
(3)
(3)
Min.
D.C.
90
Max.
Min.
D.C.
15
Max.
f
f
Clock Frequency
5
10
MHz
ns
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
15
ns
SHCH
t
t
100
90
40
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
25
ns
CHSH
t
90
15
ns
CHSL
(1)
t
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
90
90
40
40
ns
ns
µs
µs
t
CLH
CH
(1)
t
t
CLL
CL
(2)
(2)
t
1
1
1
1
t
t
RC
CLCH
t
FC
CHCL
t
t
DSU
Data In Setup Time
20
30
70
40
0
15
15
15
20
0
ns
ns
ns
ns
ns
DVCH
t
t
t
DH
Data In Hold Time
CHDX
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
HHCH
t
HLCH
t
CLHL
Clock Low Set-up Time before HOLD not
Active
t
0
0
ns
CLHH
(2)
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
100
60
25
25
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
t
0
0
CLQX
HO
RO
(2)
(2)
Output Rise Time
50
20
t
t
QLQH
t
Output Fall Time
50
50
100
5
20
25
25
5
ns
ns
ns
ms
FO
QHQL
t
t
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
LZ
(2)
t
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t must never be less than the shortest possible clock period, 1 / f (max).
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. The information contained in Table 14. is subject to change without previous notice.
23/31
M95512-W, M95512-R
Table 15. AC Characteristics (M95512-R)
Test conditions specified in Table 10. and Table 9.
(3)
(3)
Symbol
Alt.
Parameter
Unit
MHz
ns
Min.
D.C.
90
Max.
f
C
f
Clock Frequency
5
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
(1)
t
90
90
ns
t
CLH
CH
(1)
t
Clock Low Time
Clock Rise Time
ns
µs
t
CL
CLL
(2)
(2)
t
1
1
t
t
RC
CLCH
t
FC
Clock Fall Time
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
CHCL
t
t
DSU
Data In Setup Time
20
30
70
40
0
DVCH
t
t
t
DH
Data In Hold Time
CHDX
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
Output Disable Time
HHCH
t
HLCH
t
CLHL
t
0
CLHH
(2)
t
100
80
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
CLQV
t
t
t
Output Hold Time
0
CLQX
HO
RO
(2)
(2)
Output Rise Time
50
50
50
100
5
ns
ns
ns
ns
ms
t
t
QLQH
t
Output Fall Time
FO
QHQL
t
t
LZ
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
(2)
t
HZ
t
HLQZ
t
W
t
WC
Note: 1. t + t must never be less than the shortest possible clock period, 1 / f (max).
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. The information contained in Table 15. is subject to change without previous notice.
24/31
M95512-W, M95512-R
Figure 16. Serial Input Timing
tSHSL
tSHCH
tCHCL
S
tCHSL
tSLCH
tCHSH
C
tDVCH
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 17. Hold Timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQV
tHLQZ
Q
D
HOLD
AI01448B
25/31
M95512-W, M95512-R
Figure 18. Output Timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449D
26/31
M95512-W, M95512-R
PACKAGE MECHANICAL
Figure 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data
millimeters
Symbol
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
27/31
M95512-W, M95512-R
Figure 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Note: 1. Drawing is not to scale.
Table 17. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
28/31
M95512-W, M95512-R
PART NUMBERING
Table 18. Ordering Information Scheme(1)
Example:
M95512
–
W MN
6
T
P
Device Type
M95 = SPI serial access EEPROM
Device Function
512 = 512 Kbit (65536 x 8)
Operating Voltage
W = V = 2.5 to 5.5V
CC
R = V = 1.8 to 5.5V
CC
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = Lead-Free and RoHS compliant
Note: 1. Ordering information related to the M95512 identified with the process letter "A".
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
29/31
M95512-W, M95512-R
REVISION HISTORY
Table 19. Document Revision History
Date
Rev.
Description of Revision
Jan-1999
1.0 Document written
Document reformatted using the new template
Voltage range -S added, and -R removed
Instruction Sequence illustrations updated
13-Feb-2002
2.0
Announcement made of planned upgrade to 10 MHz clock for the 5V, –40 to 85°C, range
Table of contents, and Pb-free options added. V (min) improved to -0.45V. Voltage range -R
added, and -S removed
IL
05-Dec-2003
02-Apr-2004
3.0
4.0 Old versions of document completely replaced by one rewritten from M95256
AC and DC characteristics tables updated with the performance data of the new device
identified with the process letter “A”.
Table 1., Product List added. AEC-Q100-002 compliance. Device Grade information clarified.
03-Jan-2005
30-Jun-2005
5.0
t
, t
and t
corrected to t
, t
and t
, respectively.
HHQX CHHL
CHHH
HHQV CLHL
CLHH
M95512 part number with 4.5V to 5.5V operating voltage range removed (related tables
removed). Document status changed to Preliminary Data.
Updated Figure 4., Bus Master and Memory Devices on the SPI Bus and Figure 17., Hold
Timing. Power On Reset information clarified. Protected Array Addresses modified in Table
4., Write-Protected Block Size. Ambient Operating Temperature value added in Table
6.0
7., Absolute Maximum Ratings. Supply Current (I ) value modified for 10 MHz in Table
CC
12., DC Characteristics (M95512-W, Device Grade 6). All values modified in Table 15., AC
Characteristics (M95512-R). Document status changed to Datasheet.
30/31
M95512-W, M95512-R
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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31/31
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