M95640-WBN5 [STMICROELECTRONICS]
8KX8 SPI BUS SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, PLASTIC, DIP-8;
| 型号： | M95640-WBN5 |
| 厂家： | 
ST |
| 描述： | 8KX8 SPI BUS SERIAL EEPROM, PDIP8, 0.25 MM LEAD FRAME, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总19页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95640, M95320
M95160, M95080
64/32/16/8 Kbit Serial SPI Bus EEPROM
With High Speed Clock
PRELIMINARY DATA
■ SPI Bus Compatible Serial Interface
■ Supports Positive Clock SPI Modes
■ 5 MHz Clock Rate (maximum)
■ Single Supply Voltage:
14
8
– 4.5V to 5.5V for M95xxx
– 2.7V to 5.5V for M95xxx-V
– 2.5V to 5.5V for M95xxx-W
– 1.8V to 3.6V for M95xxx-R
■ Status Register
1
1
PSDIP8 (BN)
0.25 mm frame
TSSOP14 (DL)
169 mil width
■ Hardware and Software Protection of the Status
Register
8
■ BYTE and PAGE WRITE (up to 32 Bytes)
■ Self-Timed Programming Cycle
1
■ Adjustable Size Read-Only EEPROM Area
■ Enhanced ESD Protection
SO8 (MN)
150 mil width
■ 100,000 Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)
DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are fabricated with STMi-
croelectronics’
High
Endurance,
Double
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one hundred
Figure 1. Logic Diagram
V
CC
Table 1. Signal Names
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
D
C
S
Q
D
M95xxx
Q
S
W
W
HOLD
HOLD
V
Supply Voltage
Ground
CC
V
SS
AI01789C
V
SS
June 1999
1/19
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M95640, M95320, M95160, M95080
Figure 2A. DIP Connections
Figure 2C. TSSOP Connections
M95128
M95xxx
S
Q
1
2
3
4
5
6
7
14
13
V
CC
HOLD
NC
NC
NC
C
S
Q
1
2
3
4
8
V
CC
HOLD
NC
NC
NC
W
12
7
11
W
6
5
C
D
10
V
SS
9
AI01790C
V
8
D
SS
AI02346
Note: 1. NC = Not Connected
Figure 2B. SO Connections
thousand Erase/Write cycles, with a data retention
of 40 years. The memories are organised as 8K x
8 bits and 4K x 8 bits (M95640, M95320) and 2K x
8 bits and 1K x 8 bits (M95160, M95080), and op-
erate down to 2.5 V (for the -W version of each de-
vice), and down to 1.8 V (for the -R version of each
device).
The M95640, M95320 and M95160, M95080 are
available in Plastic Dual-in-Line, Plastic Small Out-
line and Thin Shrink Small Outline packages.
M95xxx
S
Q
1
2
3
4
8
V
CC
HOLD
7
W
6
5
C
D
V
Each memory device is accessed by a simple se-
rial interface that is SPI bus compatible. The bus
signals are C, D and Q, as shown in Table 1 and
Figure 3.
SS
AI01791C
The device is selected when the chip select input
(S) is held low. Communications with the chip can
be interrupted using the hold input (HOLD).
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
TA
Ambient Operating Temperature
-40 to 125
-65 to 150
TSTG
Storage Temperature
°C
PSDIP8: 10 sec
SO8: 40 sec
260
215
TLEAD
Lead Temperature during Soldering
°C
TSSOP14: t.b.c.
t.b.c.
VO
VI
-0.3 to VCC+0.6
-0.3 to 6.5
-0.3 to 6.5
4000
Output Voltage Range
Input Voltage Range
Supply Voltage Range
V
V
V
V
VCC
VESD
2
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
2/19
M95640, M95320, M95160, M95080
Figure 3. Microcontroller and Memory Devices on the SPI Bus
D
Q
C
SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')
Master
(ST6, ST7, ST9,
ST10, Others)
C
Q
D
C
Q
D
C Q D
M95xxx
M95xxx
M95xxx
CS3 CS2 CS1
S
S
S
AI01958B
SIGNAL DESCRIPTION
Serial Output (Q)
The output pin is used to transfer data serially out
of the Memory. Data is shifted out on the falling
edge of the serial clock.
(though not to the WIP and WEL bits, which are
set or reset by the device internal logic).
Bit 7 of the status register (as shown in Table 5) is
the Status Register Write Disable bit (SRWD).
When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
bit (Write Enable Latch) has been set by the
WREN instruction (irrespective of the level being
applied to the W input).
When bit 7 (SRWD) of the status register is set to
1, the ability to write to the status register depends
on the logic level being presented at pin W:
Serial Input (D)
The input pin is used to transfer data serially into
the device. Instructions, addresses, and the data
to be written, are each received this way. Input is
latched on the rising edge of the serial clock.
Serial Clock (C)
The serial clock provides the timing for the serial
interface (as shown in Figure 4). Instructions, ad-
dresses, or data are latched, from the input pin, on
the rising edge of the clock input. The output data
on the Q pin changes state after the falling edge of
the clock input.
– If W pin is high, it is possible to write to the sta-
tus register, after having set the WEL bit using
the WREN instruction (Write Enable Latch).
– If W pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EEPROM area, protected by
the BPn bits of the status register, are also hard-
ware protected against data corruption, and ap-
pear as a Read Only EEPROM area for the
microcontroller. This mode is called the Hard-
ware Protected Mode (HPM).
Chip Select (S)
When S is high, the memory device is deselected,
and the Q output pin is held in its high impedance
state. Unless an internal write operation is under-
way, the memory device is placed in its stand-by
power mode.
It is possible to enter the Hardware Protected
Mode (HPM) either by setting the SRWD bit after
pulling low the W pin, or by pulling low the W pin
after setting the SRWD bit.
After power-on, a high-to-low transition on S is re-
quired prior to the start of any operation.
Write Protect (W)
The protection features of the memory device are
summarized in Table 3.
The hardware write protection, controlled by the W
pin, restricts write access to the Status Register
The only way to abort the Hardware Protected
Mode, once entered, is to pull high the W pin.
If W pin is permanently tied to the high level, the
Hardware Protected Mode is never activated, and
the memory device only allows the user to protect
3/19
M95640, M95320, M95160, M95080
Figure 4. Data and Clock Timing
CPOL
CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
a part of the memory, using the BPn bits of the sta-
tus register, in the Software Protected Mode
(SPM).
OPERATIONS
All instructions, addresses and data are shifted se-
rially in and out of the chip. The most significant bit
is presented first, with the data input (D) sampled
on the first rising edge of the clock (C) after the
chip select (S) goes low.
Every instruction starts with a single-byte code, as
summarised in Table 4. This code is entered via
the data input (D), and latched on the rising edge
of the clock input (C). To enter an instruction code,
the product must have been previously selected (S
held low). If an invalid instruction is sent (one not
contained in Table 4), the chip automatically dese-
lects itself.
Hold (HOLD)
The HOLD pin is used to pause the serial commu-
nications between the SPI memory and controller,
without losing bits that have already been decoded
in the serial sequence. For a hold condition to oc-
cur, the memory device must already have been
selected (S = 0). The hold condition starts when
the HOLD pin is held low while the clock pin (C) is
also low (as shown in Figure 14).
During the hold condition, the Q output pin is held
in its high impedance state, and the levels on the
input pins (D and C) are ignored by the memory
device.
It is possible to deselect the device when it is still
in the hold state, thereby resetting whatever trans-
fer had been in progress. The memory remains in
the hold state as long as the HOLD pin is low. To
restart communication with the device, it is neces-
sary both to remove the hold condition (by taking
HOLD high) and to select the memory (by taking S
low).
Write Enable (WREN) and Write Disable (WRDI)
The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR oper-
ation. The WREN instruction (write enable) sets
this latch, and the WRDI instruction (write disable)
resets it.
The latch becomes reset by any of the following
events:
– Power on
– WRDI instruction completion
– WRSR instruction completion
– WRITE instruction completion.
Table 3. Write Protection Control on the M95640, M95320, M95160, M95080
Data Bytes
SRWD
Bit
W
Mode
Status Register
Protected Area
Unprotected Area
0 or 1
1
0
1
Software
Protected
(SPM)
Writeable (if the WREN
instruction has set the
WEL bit)
Software write protected
by the BPn of the status
register
Writeable (if the WREN
instruction has set the
WEL bit)
Hardware
Protected
(HPM)
Hardware write protected
by the BPn bits of the
status register
Writeable (if the WREN
instruction has set the
WEL bit)
0
1
Hardware write protected
4/19
M95640, M95320, M95160, M95080
Figure 5. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
An
An - 31
Read only
EEPROM
area
32 Bytes
0000h
001Fh
X Decoder
AI01792C
Note: 1. The cell An represents the byte at the highest address in the memory
As soon as the WREN or WRDI instruction is re-
ceived, the memory device first executes the in-
struction, then enters a wait mode until the device
is deselected.
■ Repeated RDSR instructions (each one
consisting of S being taken low, C being clocked
8 times for the instruction and 8 times for the
read operation, and S being taken high)
Read Status Register (RDSR)
■ A single, prolonged RDSR instruction
(consisting of S being taken low, C being
clocked 8 times for the instruction and kept
running for repeated read operations), as
shown in Figure 6.
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended that the value of the
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 5) can be continuously polled,
before sending a new WRITE instruction. This can
be performed in one of two ways:
The Write-In-Process (WIP) bit is read-only, and
indicates whether the memory is busy with a Write
5/19
M95640, M95320, M95160, M95080
Table 4. Instruction Set
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
(SRWD, BP0, BP1) become frozen at a constant
value. The updated value of these bits becomes
available when a new RDSR instruction is execut-
ed, after completion of the write cycle. On the oth-
er hand, the two read-only bits (WEL, WIP) are
dynamically updated during internal write cycles.
Using this facility, it is possible to poll the WIP bit
to detect the end of the internal write cycle.
Instruc
tion
Instruction
Format
Description
WREN Set Write Enable Latch
0000 0110
0000 0100
0000 0101
0000 0001
WRDI
RDSR
Reset Write Enable Latch
Read Status Register
WRSR Write Status Register
READ
Write Status Register (WRSR)
Read Data from Memory Array 0000 0011
The format of the WRSR instruction is shown in
Figure 7. After the instruction and the eight bits of
the status register have been latched-in, the inter-
nal Write cycle is triggered by the rising edge of
the S line. This must occur after the falling edge of
WRITE Write Data to Memory Array
0000 0010
Table 5. Status Register Format
b7
b0
th
the 16 clock pulse, and before the rising edge of
th
the 17 clock (as indicated in Figure 7), otherwise
SRWD
X
X
X
BP1 BP0 WEL WIP
the internal write sequence is not performed.
The WRSR instruction is used for the following:
■ to select the size of memory area that is to be
write-protected
Note: 1. SRWD, BP0 and BP1 are Read and write bits.
2. WEL and WIP are Read only bits.
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.
■ to select between SPM (Software Protected
Mode) and HPM (Hardware Protected Mode).
The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed in the previous paragraph, or as a result of
executing WREN or WRDI instruction. It cannot be
changed using a WRSR instruction. A ’1’ indicates
that the latch is set (the forthcoming Write instruc-
tion will be executed), and a ’0’ that it is reset (and
any forthcoming Write instructions will be ignored).
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-protect-
ed. These two bits are non-volatile. They are set
using a WRSR instruction.
The size of the write-protection area applies equal-
ly in SPM and HPM. The BP1 and BP0 bits of the
status register have the appropriate value (see Ta-
ble 6) written into them after the contents of the
protected area of the EEPROM have been written.
The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.
Software Protected Mode (SPM)
The act of writing a non-zero value to the BP1 and
BP0 bits causes the Software Protected Mode
(SPM) to be started. All attempts to write a byte or
page in the protected area are ignored, even if the
Write Enable Latch is set. However, writing is still
allowed in the unprotected area of the memory ar-
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
Figure 6. RDSR: Read Status Register Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
D
INSTRUCTION
STATUS REG. OUT
STATUS REG. OUT
HIGH IMPEDANCE
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
MSB
AI02031
6/19
M95640, M95320, M95160, M95080
Table 6. Write Protected Block Size
Status Register Bits
Protected Block
Array Addresses Protected
BP1
BP0
M95640
none
M95320
none
M95160
none
M95080
none
0
0
1
1
0
1
0
1
none
Upper quarter
Upper half
1800h - 1FFFh
1000h - 1FFFh
0000h - 1FFFh
0C00h - 0FFFh
0800h - 0FFFh
0000h - 0FFFh
0600h - 07FFh
0400h - 07FFh
0000h - 07FFh
0300h - 03FFh
0200h - 03FFh
0000h - 03FFh
Whole memory
ray and to the SRWD, BP1 and BP0 bits of the sta-
tus register, provided that the WEL bit is first set.
Hardware Protected Mode (HPM)
Typical Use of HPM and SPM
The W pin can be dynamically driven by an output
port of a microcontroller. It is also possible,
though, to connect it permanently to V (by a sol-
SS
The Hardware Protected Mode (HPM) offers a
higher level of protection, and can be selected by
setting the SRWD bit after pulling down the W pin
or by pulling down the W pin after setting the
SRWD bit. The SRWD is set by the WSR instruc-
tion, provided that the WEL bit is first set. The set-
ting of the SRWD bit can be made independently
of, or at the same time as, writing a new value to
the BP1 and BP0 bits.
Once the device is in the Hardware Protected
Mode, the data bytes in the protected area of the
memory array, and the content of the status regis-
ter, are write-protected. The only way to re-enable
writing new values to the status register is to pull
the W pin high. This cause the device to leave the
Hardware Protected Mode, and to revert to being
in the Software Protected Mode. (The value in the
BP1 and BP0 bits will not have been changed).
der connection, or through a pull-down resistor).
The manufacturer of such a printed circuit board
can take the memory device, still in its initial deliv-
ery state, and can solder it directly on to the board.
After power on, the microcontroller can be instruct-
ed to write the protected data into the appropriate
area of the memory. When it has finished, the ap-
propriate values are written to the BP1, BP0 and
SRWD bits, thereby putting the device in the hard-
ware protected mode.
An alternative method is to write the protected da-
ta, and to set the BP1, BP0 and SRWD bits, before
soldering the memory device to the board. Again,
this results in the memory device being placed in
its hardware protected mode.
If the W pin has been connected to V by a pull-
SS
down resistor, the memory device can be taken
out of the hardware protected mode by driving the
W pin high, to override the pull-down resistor.
Further details of the operation of the Write Protect
pin (W) are given earlier, on page 3.
If the W pin has been directly soldered to V
,
SS
there is only one way of taking the memory device
out of the hardware protected mode: the memory
Figure 7. WRSR: Write Status Register Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
STATUS REG.
C
INSTRUCTION
7
6
5
4
3
2
0
1
D
Q
MSB
HIGH IMPEDANCE
AI02282
7/19
M95640, M95320, M95160, M95080
Figure 8. Read EEPROM Array Operation Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
C
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
D
Q
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
0
1
MSB
AI01793
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
Table 7. Address Range Bits
counter is automatically incremented to the next
higher address after each byte of data has been
shifted out. The data stored in the memory, at the
next address, can be read by successive clock
pulses. When the highest address is reached, the
address counter rolls over to “0000h”, allowing the
read cycle to be continued indefinitely. The read
operation is terminated by deselecting the chip.
The chip can be deselected at any time during
data output. If a read instruction is received during
a write cycle, it is rejected, and the memory device
deselects itself.
Device
M95640 M95320 M95160 M95080
A12-A0 A11-A0 A10-A0 A9-A0
Address Bits
Note: 1. Address bits up to b15 are treated as Don’t Care.
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Read Operation
The chip is first selected by holding S low. The se-
rial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C).
The data stored in the memory, at the selected ad-
dress, is shifted out on the Q output pin. Each bit
is shifted out during the falling edge of the clock
(C) as shown in Figure 8. The internal address
Byte Write Operation
Before any write can take place, the WEL bit must
be set, using the WREN instruction. The write
state is entered by selecting the chip, issuing three
bytes of instruction and address, and one byte of
data. Chip Select (S) must remain low throughout
the operation, as shown in Figure 10. The product
must be deselected just after the eighth bit of the
Figure 9. Write Enable Latch Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
HIGH IMPEDANCE
AI02281
8/19
M95640, M95320, M95160, M95080
Figure 10. Byte Write Operation Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
INSTRUCTION
16 BIT ADDRESS
DATA BYTE
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
HIGH IMPEDANCE
AI01795
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
data byte has been latched in, as shown in Figure
10, otherwise the write process is cancelled. As
soon as the memory device is deselected, the self-
timed internal write cycle is initiated. While the
write is in progress, the status register may be
read to check the status of the SRWD, BP1, BP0,
WEL and WIP bits. In particular, WIP contains a ‘1’
during the self-timed write cycle, and a ‘0’ when
the cycle is complete, (at which point the write en-
able latch is also reset).
Page Write Operation
A maximum of 32 bytes of data can be written dur-
ing one Write time, t , provided that they are all to
W
Figure 11. Page Write Operation Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
D
INSTRUCTION
16 BIT ADDRESS
DATA BYTE 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
9/19
M95640, M95320, M95160, M95080
the same page (see Figure 5). The Page Write op-
eration is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 31 additional bytes can
be shifted in (and then the device is deselected af-
ter the last byte).
Any address of the memory can be chosen as the
first address to be written. If the address counter
reaches the end of the page (an address of the
form xxxx xxxx xxx1 1111) and the clock contin-
ues, the counter rolls over to the first address of
the same page (xxxx xxxx xxx0 0000) and over-
writes any previously written data.
POWER ON STATE
After power-on, the memory device is in the follow-
ing state:
– low power stand-by state
– deselected (after power-on, a high-to-low transi-
tion is required on the S input before any opera-
tions can be started).
– not in the hold condition
– the WEL bit is reset
– the SRWD, BP1 and BP0 bits of the status reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
As before, the Write cycle only starts if the S tran-
sition occurs just after the eighth bit of the last data
byte has been received, as shown in Figure 11.
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all “1’s” or FFh).
The status register bits are initialized to 00h, as
shown in Table 8.
DATA PROTECTION AND PROTOCOL SAFETY
To protect the data in the memory from inadvertent
corruption, the memory device only responds to
correctly formulated commands. The main securi-
ty measures can be summarised as follows:
Table 8. Initial Status Register Format
– The WEL bit is reset at power-up.
b7
0
b0
0
– S must rise after the eighth clock count (or mul-
tiple thereof) in order to start a non-volatile write
cycle (in the memory array or in the status reg-
ister).
0
0
0
0
0
0
– Accesses to the memory array are ignored dur-
ing the non-volatile programming cycle, and the
programming cycle continues unaffected.
– After execution of a WREN, WRDI, or RDSR in-
struction, the chip enters a wait state, and waits
to be deselected.
– Invalid S and HOLD transitions are ignored.
1
Table 9. Input Parameters (T = 25 °C, f = 5 MHz)
A
Symbol
COUT
Parameter
Test Condition
Min.
Max.
Unit
pF
Output Capacitance (Q)
Input Capacitance (other pins)
8
6
CIN
pF
Note: 1. Sampled only, not 100% tested.
10/19
M95640, M95320, M95160, M95080
Table 10. DC Characteristics
(T = 0 to 70 °C, -40 to 85 °C or -40 to 125 °C; V = 4.5 to 5.5 V)
A
CC
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 5.5 V)
A
CC
(T = 0 to 70 °C or -40 to 85 °C; V = 2.5 to 5.5 V)
A
CC
(T = 0 to 70 °C or -20 to 85 °C; V = 1.8 to 3.6 V)
A
CC
Voltage Temp.
Range Range
Symbol
Parameter
Test Condition
Min.
Max.
± 2
± 2
4
Unit
µA
Input Leakage
Current
ILI
all
all
all
all
6
Output Leakage
Current
ILO
µA
C = 0.1 VCC/0.9. VCC at 5 MHz,
VCC = 5 V, Q = open
4.5-5.5
mA
C = 0.1 VCC/0.9. VCC at 2 MHz,
VCC = 5 V, Q = open
4.5-5.5
3
4
mA
ICC
Supply Current
C = 0.1 VCC/0.9. VCC at 5 MHz,
VCC = 2.7 V, Q = open
2.7-5.5
2.5-5.5
1.8-3.6
6
6
5
3
2
2
mA
mA
mA
C = 0.1 VCC/0.9. VCC at 2 MHz,
VCC = 2.5 V, Q = open
C = 0.1 VCC/0.9. VCC at 1 MHz,
VCC = 1.8 V, Q = open
S = VCC, VIN = VSS or VCC , VCC = 5 V
4.5-5.5
4.5-5.5
2.7-5.5
2.5-5.5
1.8-3.6
6
3
6
6
5
10
10
2
µA
µA
µA
µA
µA
S = VCC, VIN = VSS or VCC , VCC = 5 V
S = VCC, VIN = VSS or VCC , VCC = 2.7 V
S = VCC, VIN = VSS or VCC , VCC = 2.5 V
S = VCC, VIN = VSS or VCC , VCC = 1.8 V
Supply Current
(Stand-by)
ICC1
2
1
Input Low
Voltage
VIL
VIH
0.3 VCC
VCC+1
all
all
all
all
– 0.3
V
V
Input High
Voltage
0.7 VCC
4.5-5.5
4.5-5.5
2.7-5.5
2.5-5.5
1.8-3.6
4.5-5.5
4.5-5.5
2.7-5.5
2.5-5.5
1.8-3.6
6
3
6
6
5
6
3
6
6
5
I
OL = 2 mA, VCC = 5 V
OL = 2 mA, VCC = 5 V
0.4
0.4
0.4
0.4
V
V
V
V
V
V
V
V
V
V
I
Output Low
Voltage
1
VOL
I
OL = 1.5 mA, VCC = 2.7 V
OL = 1.5 mA, VCC = 2.5 V
I
IOL = 0.15 mA, VCC = 1.8 V
0.3
I
OH = –2 mA, VCC = 5 V
OH = –2 mA, VCC = 5 V
0.8 VCC
0.8 VCC
I
Output High
Voltage
1
VOH
I
I
I
OH = –0.4 mA, VCC = 2.7 V
OH = –0.4 mA, VCC = 2.5 V
OH = –0.1 mA, VCC = 1.8 V
0.8 VCC
0.8 VCC
0.8 VCC
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
11/19
M95640, M95320, M95160, M95080
Table 11A. AC Characteristics
M95640, M95320, M95160, M95080
=4.5 to 5.5 V
V
CC
V
=4.5 to 5.5 V
CC
Symbol
Alt.
Parameter
T =0 to 70°C or
Unit
A
T =-40 to 125°C
A
-40 to 85°C
Min
D.C.
90
Max
Min
D.C.
200
200
200
200
200
Max
f
f
Clock Frequency
5
2
MHz
ns
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
1
t
90
90
200
200
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
ns
t
CLL
CL
2
t
1
1
µs
t
RC
CLCH
2
t
Clock Fall Time
1
1
µs
ns
ns
µs
t
FC
CHCL
t
t
DSU
Data In Setup Time
Data In Hold Time
Data In Rise Time
20
30
40
50
DVCH
t
t
CHDX
DH
2
t
1
1
1
1
t
RI
DLDH
2
t
Data In Fall Time
µs
ns
ns
ns
ns
ns
t
FI
DHDL
t
t
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
Output Disable Time
70
40
0
140
90
0
HHCH
CD
t
HLCH
t
CLHL
t
0
0
CLHH
2
t
100
60
250
150
t
DIS
SHQZ
t
t
Clock Low to Output Valid
Output Hold Time
ns
ns
ns
CLQV
V
t
t
0
0
CLQX
HO
RO
2
t
Output Rise Time
50
50
100
100
100
250
10
t
t
t
QLQH
QHQL
HHQX
2
2
2
t
Output Fall Time
ns
ns
ns
ms
FO
t
HOLD High to Output Low-Z
HOLD Low to Output High-Z
Write Time
50
LZ
t
100
10
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
12/19
M95640, M95320, M95160, M95080
Table 11B. AC Characteristics
M95xxx-V
=2.7 to 5.5 V
M95xxx-W M95xxx-R
=2.5 to 5.5 V V =1.8 to 3.6 V
CC
V
CC
V
CC
Symbol Alt.
Parameter
T =0 to 70°C or T =0 to 70°C or T =0 to 70°C or Unit
A A A
-40 to 85°C
-40 to 85°C
-20 to 85°C
Min
D.C.
90
Max
Min
D.C.
200
200
200
200
200
Max
Min
D.C.
400
400
300
400
400
Max
f
f
SCK
Clock Frequency
5
2
1
MHz
ns
C
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
CSS1
CSS2
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CHSH
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
t
90
ns
CHSL
1
t
90
90
200
200
400
400
ns
t
CLH
CH
1
t
Clock Low Time
Clock Rise Time
Clock Fall Time
ns
µs
µs
t
CLL
CL
2
2
t
1
1
1
t
RC
CLCH
t
FC
1
1
1
t
CHCL
t
t
DSU
Data In Setup Time
Data In Hold Time
Data In Rise Time
20
30
40
50
60
ns
ns
µs
DVCH
t
t
100
CHDX
DH
2
t
RI
1
1
1
1
1
1
t
t
DLDH
DHDL
t
2
t
FI
Data In Fall Time
µs
ns
Clock Low Hold Time after HOLD
not Active
t
70
40
0
140
90
0
350
200
0
HHCH
CD
Clock Low Hold Time after HOLD
Active
t
ns
ns
ns
HLCH
Clock Low Set-up Time before
HOLD Active
t
CLHL
CLHH
Clock Low Set-up Time before
HOLD not Active
t
0
0
0
2
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
100
60
250
150
500
380
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
CLQV
t
t
0
0
0
CLQX
HO
RO
2
t
Output Rise Time
50
50
100
100
100
250
10
200
200
250
500
10
t
t
QLQH
QHQL
HHQX
2
2
2
t
t
Output Fall Time
ns
ns
ns
ms
FO
t
HOLD High to Output Low-Z
HOLD Low to Output High-Z
Write Time
50
t
LZ
100
10
t
HZ
HLQZ
t
W
t
WC
Note: 1. t + t ≥ 1 / f .
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
13/19
M95640, M95320, M95160, M95080
Table 12. AC Measurement Conditions
Figure 12. AC Testing Input Output Waveforms
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.8V
CC
0.7V
CC
0.2V to 0.8V
CC
CC
0.3V
CC
Input and Output Timing
Reference Voltages
0.3V to 0.7V
0.2V
CC
CC
CC
AI00825
C = 100 pF
L
Output Load
Note: 1. Output Hi-Z is defined as the point where data is no long-
er driven.
Figure 13. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
tDLDH
tDHDL
HIGH IMPEDANCE
AI01447
Figure 14. Hold Timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQX
tHLQZ
Q
D
HOLD
AI01448
14/19
M95640, M95320, M95160, M95080
Figure 15. Output Timing
S
tCH
C
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
ADDR.LSB IN
D
AI01449B
ORDERING INFORMATION
The notation used for the device number is as shown in Table 13. For a list of available options (speed,
package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office
nearest to you.
Table 13. Ordering Information Scheme
Example:
M95640
–
W
MN
6
T
4
Option
Memory Capacity
640
320
160
080
64 Kbit (8K x 8) with positive clock strobe
32 Kbit (4K x 8) with positive clock strobe
16 Kbit (2K x 8) with positive clock strobe
8 Kbit (1K x 8) with positive clock strobe
T
Tape and Reel Packing
Temperature Range
0 °C to 70 °C
1
1
5
6
–20 °C to 85 °C
–40 °C to 85 °C
–40 °C to 125 °C
2
Operating Voltage
3
blank 4.5 V to 5.5 V
V
2.7 V to 5.5 V
2.5 V to 5.5 V
1.8 V to 3.6 V
Package
W
BN PSDIP8 (0.25 mm frame)
3
MN SO8 (150 mil width)
R
5
TSSOP14 (169 mil width)
DL
Note: 1. Temperature range available only on request.
2. Produced with High Reliability Certified Flow (HRCF), in V range 4.5 V to 5.5 V only.
CC
3. The -R version (V range 1.8 V to 3.6 V) only available in temperature ranges 5 or 1.
CC
4. All devices use a positive clock strobe: Data In is strobed on the rising edge of the clock (C) and Data Out is synchronised from the
falling edge of the clock.
5. TSSOP14, 169 mil width, package is available for the M95640 series only.
15/19
M95640, M95320, M95160, M95080
Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
inches
Min.
Symb.
Typ.
Min.
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
Max.
5.90
–
Typ.
Max.
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
Figure 16. PSDIP8 (BN)
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Note: 1. Drawing is not to scale.
16/19
M95640, M95320, M95160, M95080
Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
Figure 17. SO8 narrow (MN)
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: 1. Drawing is not to scale.
17/19
M95640, M95320, M95160, M95080
Table 16. TSSOP14 - 14 lead Thin Shrink Small Outline
mm
inches
Min.
Symb.
Typ.
Min.
Max.
1.10
0.15
0.95
0.30
0.20
5.10
6.50
4.50
–
Typ.
Max.
0.043
0.006
0.037
0.012
0.008
0.197
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
4.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.193
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
14
14
CP
0.08
0.003
Figure 18. TSSOP14 (DL)
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Note: 1. Drawing is not to scale.
18/19
M95640, M95320, M95160, M95080
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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19/19
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