M95640-WMC4TG/K [STMICROELECTRONICS]
8KX8 SPI BUS SERIAL EEPROM, PDSO8, 2 X 3 MM, HALOGEN FREE AND ROHS COMPLIANT, UFDFP-8;
| 型号： | M95640-WMC4TG/K |
| 厂家： | 
ST |
| 描述： | 8KX8 SPI BUS SERIAL EEPROM, PDSO8, 2 X 3 MM, HALOGEN FREE AND ROHS COMPLIANT, UFDFP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总39页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95640-A125
M95640-A145
Automotive 64-Kbit serial SPI bus EEPROMs
with high-speed clock
Datasheet − production data
Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
SO8 (MN)
150 mil width
– 64 Kbits (8 Kbytes) of EEPROM
– Page size: 32 bytes
– Write protection by block: 1/4, 1/2 or whole
memory
– Additional Write lockable Page
(Identification page)
TSSOP8 (DW)
169 mil width
■ Extended temperature and voltage ranges
– Up to 125 °C (V from 1.8 V to 5.5 V)
CC
– Up to 145 °C (V from 2.5 V to 5.5 V)
CC
■ High speed clock frequency
– 20 MHz for V
– 10 MHz for V
4.5 V
2.5 V
CC ≥
CC ≥
– 5 MHz for V
1.8 V
CC ≥
UFDFPN8 (MC)
2 x 3 mm
■ Schmitt trigger inputs for noise filtering
■ Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
■ Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
– 400 k Write cycles at 145 °C
■ Data retention
– 40 years at 55 °C
– 100 years at 25 °C
■ ESD Protection (Human Body Model)
– 4000 V
■ Packages
– RoHS-compliant and halogen-free
®
(ECOPACK2 )
August 2012
Doc ID 022579 Rev 3
1/39
This is information on a product in full production.
www.st.com
1
Contents
M95640-A125M95640-A145
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
3.4
Active power and Standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protocol control and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.1
3.4.2
Protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Status Register and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5
Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Identification Page (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Write Identification Page (WRID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Lock Status (RDLS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.10 Lock Identification Page (LID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Contents
5
Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1
5.1.2
5.1.3
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
5.3
Implementing devices on SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 26
6
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
8
9
10
11
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List of tables
M95640-A125M95640-A145
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device identification bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Cycling performance by groups of 4 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating conditions (voltage range W, temperature range 4). . . . . . . . . . . . . . . . . . . . . . 28
Operating conditions (voltage range R, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . 28
Operating conditions (voltage range R, temperature range 3)
for high speed communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (voltage range W, temperature range 4). . . . . . . . . . . . . . . . . . . . . . . . 29
DC characteristics (voltage range R, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 34
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 35
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19.
Table 20.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Read Lock Status sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
Figure 22. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Description
M95640-A125M95640-A145
1
Description
The M95640-A125 and M95640-A145 are 64-Kbit serial EEPROM Automotive grade
devices operating up to 145°C. They are compliant with the very high level of reliability
defined by the Automotive standard AEC-Q100 grade 0.
The devices are accessed by a simple serial SPI compatible interface running up to 20 MHz.
The memory array is based on advanced true EEPROM technology (Electrically Erasable
PROgrammable Memory). The M95640-A125 and M95640-A145 are byte-alterable
memories (8192 × 8 bits) organized as 256 pages of 32 bytes in which the data integrity is
significantly improved with an embedded Error Correction Code logic.
The M95640-A125 and M95640-A145 offer an additional Identification Page (32 bytes) in
which the ST device identification can be read. This page can also be used to store sensitive
application parameters which can be later permanently locked in read-only mode.
Figure 1.
Logic diagram
(/,$
(IGH VOLTAGE
GENERATOR
7
3
#ONTROL LOGIC
#
$
1
)ꢄ/ SHIFT REGISTER
$ATA
REGISTER
!DDRESS REGISTER
AND COUNTER
3TATUS
REGISTER
ꢀꢄꢅ
ꢀꢄꢆ
3IZE OF THE
2EAD ONLY
%%02/-
AREA
ꢀ PAGE
)DENTIFICATION PAGE
8 DECODER
-3ꢀꢁꢂꢃꢃ6ꢀ
6/39
Doc ID 022579 Rev 3
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Figure 2. 8-pin package connections
Description
M95xxx
S
Q
1
8
V
CC
HOLD
2
3
4
7
W
6
5
C
D
V
SS
AI01790D
1. See Package mechanical data section for package dimensions and how to identify pin-1.
Table 1.
Signal names
Signal name
Description
C
D
Serial Clock
Serial data input
Serial data output
Chip Select
Write Protect
Hold
Q
S
W
HOLD
VCC
VSS
Supply voltage
Ground
Doc ID 022579 Rev 3
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Signal description
M95640-A125M95640-A145
2
Signal description
All input signals must be held high or low (according to voltages of V or V , as specified in
IH
IL
Table 13 and Table 14)). These signals are described below.
2.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device during a Read operation.
Data is shifted out on the falling edge of Serial Clock (C), most significant bit (MSB) first. In
all other cases, the Serial Data output is in high impedance.
2.2
2.3
2.4
2.5
Serial Data input (D)
This input signal is used to transfer data serially into the device. D input receives
instructions, addresses, and the data to be written. Values are latched on the rising edge of
Serial Clock (C), most significant bit (MSB) first.
Serial Clock (C)
This input signal allows to synchronize the timing of the serial interface. Instructions,
addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial
Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
Driving Chip Select (S) low selects the device in order to start communication. Driving Chip
Select (S) high deselects the device and Serial Data output (Q) enters the high impedance
state.
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
2.6
2.7
2.8
Write Protect (W)
This pin is used to write-protect the Status Register.
VSS ground
V
is the reference for all signals, including the V supply voltage.
CC
SS
VCC supply voltage
V
is the supply voltage pin.
CC
Refer to Section 3.1: Active power and Standby power modes and to Section 5.1: Supply
voltage (V ).
CC
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Operating features
3
Operating features
3.1
Active power and Standby power modes
When Chip Select (S) is low, the device is selected and in the Active power mode.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby power mode, and the device consumption
drops to I
, as specified in Table 13 and Table 14.
CC1
3.2
SPI modes
The device can be driven by a microcontroller with its SPI peripheral running in either of the
two following modes:
●
CPOL=0, CPHA=0
CPOL=1, CPHA=1
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 3, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
●
Figure 3.
SPI modes supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
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Operating features
M95640-A125M95640-A145
3.3
Hold mode
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
The Hold mode starts when the Hold (HOLD) signal is driven low and the Serial Clock (C) is
low (as shown in Figure 4). During the Hold mode, the Serial Data output (Q) is high
impedance, and the signals present on Serial Data input (D) and Serial Clock (C) are not
decoded. The Hold mode ends when the Hold (HOLD) signal is driven high and the Serial
Clock (C) is or becomes low.
Figure 4.
Hold mode activation
#
(/,$
(OLD
CONDITION
(OLD
#COONNDDIITTIIOONN
-3ꢀꢁꢂꢂꢇ6ꢀ
Deselecting the device while it is in Hold mode resets the paused communication.
3.4
Protocol control and data protection
3.4.1
Protocol control
The Chip Select (S) input offers a built-in safety feature, as the S input is edge-sensitive as
well as level-sensitive: after power-up, the device is not selected until a falling edge has first
been detected on Chip Select (S). This ensures that Chip Select (S) must have been high
prior to going low, in order to start the first operation.
For Write commands (WRITE, WRSR, WRID, LID) to be accepted and executed:
●
the Write Enable Latch (WEL) bit must be set by a Write Enable (WREN) instruction
●
a falling edge and a low state on Chip Select (S) during the whole command must be
decoded
●
●
●
instruction, address and input data must be sent as multiple of eight bits
the command must include at least one data byte
Chip Select (S) must be driven high exactly after a data byte boundary
Write command can be discarded at any time by a rising edge on Chip Select (S) outside of
a byte boundary.
To execute Read commands (READ, RDSR, RDID, RDLS), the device must decode:
●
a falling edge and a low level on Chip Select (S) during the whole command
instruction and address as multiples of eight bits (bytes)
●
From this step, data bits are shifted out until the rising edge on Chip Select (S).
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Operating features
3.4.2
Status Register and data protection
The Status Register format is shown in Table 2 and the status and control bits of the Status
Register are as follows:
Table 2.
Status Register format
b7
b6
b5
b4
0
b3
b2
b1
b0
SRWD
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
Note:
Bits b6, b5, b4 are always read as 0.
WIP bit
The WIP bit (Write In Progress) is a read-only flag that indicates the Ready/Busy state of the
device. When a Write command (WRITE, WRSR, WRID, LID) has been decoded and a
Write cycle (t ) is in progress, the device is busy and the WIP bit is set to 1. When WIP=0,
W
the device is ready to decode a new command.
During a Write cycle, reading continuously the WIP bit allows to detect when the device
becomes ready (WIP=0) to decode a new command.
WEL bit
The WEL bit (Write Enable Latch) bit is a flag that indicates the status of the internal Write
Enable Latch. When WEL is set to 1, the Write instructions (WRITE, WRSR, WRID, LID) are
executed; when WEL is set to 0, any decoded Write instruction is not executed.
The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the
following events:
●
Write Disable (WRDI) instruction completion
●
Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle
time t
W
●
Power-up
BP1, BP0 bits
The Block Protect bits (BP1, BP0) are non-volatile. BP1,BP0 bits define the size of the
memory block to be protected against write instructions, as defined in Table 2. These bits
are written with the Write Status Register (WRSR) instruction, provided that the Status
Register is not protected (refer to SRWD bit and W input signal).
Doc ID 022579 Rev 3
11/39
Operating features
Table 3.
M95640-A125M95640-A145
Protected array addresses
Write-protected block size
Status Register bits
Protected block
BP1
BP0
0
0
1
1
0
1
0
1
None
None
1800h - 1FFFh
Upper quarter
Upper half
1000h - 1FFFh
Whole memory
0000h - 1FFFh plus Identification page
SRWD bit and W input signal
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect pin (W) signal. When the SRWD bit is written to 0, it is possible to write the Status
Register, regardless of whether the pin Write Protect (W) is driven high or low.
When the SRWD bit is written to 1, two cases have to be considered, depending on the
state of the W input pin:
●
Case 1: if pin W is driven high, it is possible to write the Status Register.
●
Case 2: if pin W is driven low, it is not possible to write the Status Register (WRSR is
discarded) and therefore SRWD,BP1,BP0 bits cannot be changed (the size of the
protected memory block defined by BP1,BP0 bits is frozen).
Case 2 can be entered in either sequence:
●
Writing SRWD bit to 1 after driving pin W low, or
Driving pin W low after writing SRWD bit to 1.
●
The only way to exit Case 2 is to pull pin W high.
Note: if pin W is permanently tied high, the Status Register cannot be write-protected.
The protection features of the device are summarized in Table 4.
Table 4.
Protection modes
W signal
SRWD bit
Status
0
1
1
X
Status Register is writable.
Status Register is write-protected.
1
0
12/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
Operating features
3.5
Identification page
The M95640-A125 and M95640-A145 offer an Identification Page (32 bytes) in addition to
the 64 Kbit memory. This page can be used for several purposes:
●
●
●
Device identification: the three first bytes of the Identification page are programmed by
STMicroelectronics with the Device identification code, as shown in Table 5.
Storage of specific parameters: each byte in the Identification page can be written if the
Identification page is not permanently locked in Read-only mode.
Write protection: once the application specific parameters are written in the
Identification page, the whole Identification page can be permanently locked in read
only mode.
Table 5.
Address in
Identification page
Device identification bytes
Content
Value
00h
01h
02h
ST Manufacturer code
SPI Family code
20h
00h
Memory Density code
0Dh (64 Kbits)
Read, write and lock Identification Page are detailed in Section 4: Instructions.
Doc ID 022579 Rev 3
13/39
Instructions
M95640-A125M95640-A145
4
Instructions
Each command is composed of bytes (MSBit transmitted first), initiated with the instruction
byte, as summarized in Table 6.
If an invalid instruction is sent (one not contained in Table 6), the device automatically enters
a Wait state until deselected.
Table 6.
Instruction set
Instruction
format
Instruction
Description
WREN
WRDI
Write Enable
Write Disable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1000 0011
1000 0010
1000 0011
1000 0010
RDSR
WRSR
READ
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
Read Identification Page
Write Identification Page
WRITE
RDID(1)
WRID(1)
RDLS(1)
LID(1)
Reads the Identification Page lock status.
Locks the Identification page in read-only mode.
1. Instruction available for the M95640-D device only (see Section 10: Part numbering).
For read and write commands to memory array and Identification Page, the address is
defined by two bytes as explained in Table 7.
(1)(2)
Table 7.
Significant bits within the two address bytes
MSB Address byte
LSB Address byte
Instructions
b15 b14 b13 b12 b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
READ or
WRITE
x
0
0
x
0
0
x
0
0
A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RDID or
WRID
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
A4
0
A3
0
A2
0
A1
0
A0
0
RDLS or
LID
1. A: Significant address bit.
2. x: bit is Don’t Care.
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Doc ID 022579 Rev 3
M95640-A125 M95640-A145
Instructions
4.1
Write Enable (WREN)
The WREN instruction must be decoded by the device before a write instruction (WRITE,
WRSR, WRID or LID).
As shown in Figure 5, to send this instruction to the device, Chip Select (S) is driven low, the
bits of the instruction byte are shifted in (MSB first) on Serial Data Input (D) after what the
Chip Select (S) input is driven high and the WEL bit is set (Status Register bit).
Figure 5.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
4.2
Write Disable (WRDI)
One way of resetting the WEL bit (in the Status Register) is to send a Write Disable
instruction to the device.
As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in (MSB first), on Serial Data Input (D), after
what the Chip Select (S) input is driven high and the WEL bit is reset (Status Register bit).
If a Write cycle is currently in progress, the WRDI instruction is decoded and executed and
the WEL bit is reset to 0 with no effect on the ongoing Write cycle.
Figure 6.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
Doc ID 022579 Rev 3
15/39
Instructions
M95640-A125M95640-A145
4.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the content of the Status
Register.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is first driven low.
The bits of the instruction byte are shifted in (MSB first) on Serial Data Input (D), the Status
Register content is then shifted out (MSB first) on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, the Status Register content is continuously
shifted out.
The Status Register can always be read, even if a Write cycle (t ) is in progress. The Status
W
Register functionality is detailed in Section 3.4.2: Status Register and data protection.
Figure 7.
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
4.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
The Write Status Register (WRSR) instruction is entered (MSB first) by driving Chip Select
(S) low, sending the instruction code followed by the data byte on Serial Data input (D), and
driving the Chip Select (S) signal high.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the Write cycle (t ).
W
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0
bits in the Status Register (see Table 2: Status Register format).
The Status Register functionality is detailed in Section 3.4.2: Status Register and data
protection.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
16/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
Figure 8. Write Status Register (WRSR) sequence
Instructions
S
C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
4.5
Read from Memory Array (READ)
The READ instruction is used to read the content of the memory.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven low.
The bits of the instruction byte and address bytes are shifted in (MSB first) on Serial Data
Input (D) and the addressed data byte is then shifted out (MSB first) on Serial Data Output
(Q). The first addressed byte can be any byte within any page.
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the next byte of data is shifted out. The whole memory can therefore be
read with a single READ instruction.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely.
The Read cycle is terminated by driving Chip Select (S) high at any time when the data bits
are shifted out on Serial Data Output (Q).
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Doc ID 022579 Rev 3
17/39
Instructions
M95640-A125M95640-A145
Figure 9.
Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
4.6
Write to Memory Array (WRITE)
The WRITE instruction is used to write new data in the memory.
As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address bytes, and at least one data byte are then
shifted in (MSB first), on Serial Data Input (D). The instruction is terminated by driving Chip
Select (S) high at a data byte boundary. Figure 10 shows a single byte write.
Figure 10. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
1. Depending on the memory size, as shown in Table 8, the most significant address bits are Don’t Care.
A Page write is used to write several bytes inside a page, with a single internal Write cycle.
18/39
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M95640-A125 M95640-A145
Instructions
For a Page write, Chip Select (S) has to remain low, as shown in Figure 11, so that the next
data bytes are shifted in. Each time a new data byte is shifted in, the least significant bits of
the internal address counter are incremented. If the address counter exceeds the page
boundary (the page size is 32 bytes), the internal address pointer rolls over to the beginning
of the same page where next data bytes will be written. If more than 32 bytes are received,
only the last 32 bytes are written.
For both Byte write and Page write, the self-timed Write cycle starts from the rising edge of
Chip Select (S), and continues for a period t (as specified in Table 15).
W
The instruction is discarded, and is not executed, under the following conditions:
●
if a Write cycle is already in progress
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits
●
if one of the conditions defined in Section 3.4.1 is not satisfied
Note:
The self-timed Write cycle t is internally executed as a sequence of two consecutive
W
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 11. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
D
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
Doc ID 022579 Rev 3
19/39
Instructions
M95640-A125M95640-A145
4.7
Read Identification Page (RDID)
The Read Identification Page instruction is used to read the Identification Page (additional
page of 32 bytes which can be written and later permanently locked in Read-only mode).
The Chip Select (S) signal is first driven low, the bits of the instruction byte and address
bytes are then shifted in (MSB first) on Serial Data input (D). Address bit A10 must be 0,
other upper address bits are Don't Care (it might be easier to define these bits as 0, as
shown in Table 7). The data byte pointed to by the lower address bits [A4:A0] is shifted out
(MSB first) on Serial Data output (Q).
The first byte addressed can be any byte within the identification page.
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented and the byte of data at the new address is shifted out.
Note that there is no roll over feature in the Identification Page. The address of bytes to read
must not exceed the page boundary.
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time when the data bits are shifted out.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 12. Read Identification Page sequence
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The first three bytes of the Identification page offer information about the device itself.
Please refer to Section 3.5: Identification page for more information.
20/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
Instructions
4.8
Write Identification Page (WRID)
The Write Identification Page instruction is used to write the Identification Page (additional
page of 32 bytes which can also be permanently locked in Read-only mode).
The Chip Select signal (S) is first driven low, and then the bits of the instruction byte,
address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D).
Address bit A10 must be 0, other upper address bits are Don't Care (it might be easier to
define these bits as 0, as shown in Table 7). The lower address bits [A4:A0] define the byte
address inside the identification page.
The self-timed Write cycle starts from the rising edge of Chip Select (S), and continues for a
period t (as specified in Table 15).
W
Figure 13. Write Identification Page sequence
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Note:
The first three bytes of the Identification page offer the Device Identification code (Please
refer to Section 3.5: Identification page for more information). Using the WRID command on
these first three bytes overwrites the Device Identification code.
The instruction is discarded, and is not executed, under the following conditions:
●
●
●
If a Write cycle is already in progress
If the Block Protect bits (BP1,BP0) = (1,1)
If one of the conditions defined in Section 3.4.1: Protocol control is not satisfied.
4.9
Read Lock Status (RDLS)
The Read Lock Status instruction is used to read the lock status.
To send this instruction to the device, Chip Select (S) first has to be driven low. The bits of
the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input
(D). Address bit A10 must be 1; all other address bits are Don't Care (it might be easier to
define these bits as 0, as shown in Table 7). The Lock bit is the LSB (Least Significant Bit) of
the byte read on Serial Data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the
lock is not active. If Chip Select (S) continues to be driven low, the same data byte is shifted
out.
The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is
shown in Figure 14.
Doc ID 022579 Rev 3
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Instructions
M95640-A125M95640-A145
The Read Lock Status instruction is not accepted and not executed if a Write cycle is
currently in progress.
Figure 14. Read Lock Status sequence
3
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4.10
Lock Identification Page (LID)
The Lock Identification Page (LID) command is used to permanently lock the Identification
Page in Read-only mode.
The LID instruction is issued by driving Chip Select (S) low, sending (MSB first) the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A10 must be equal to 1. All other address bits are Don't
Care (it might be easier to define these bits as 0, as shown in Table 7). The data byte sent
must be equal to the binary value xxxx xx1x, where x = Don't Care. The LID instruction is
terminated by driving Chip Select (S) high at a data byte boundary, otherwise, the instruction
is not executed.
Figure 15. Lock ID sequence
3
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Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write
cycle which duration is t (specified in Table 15). The instruction sequence is shown in
W
Figure 15.
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M95640-A125 M95640-A145
Instructions
The instruction is discarded, and is not executed, under the following conditions:
●
●
●
If a Write cycle is already in progress
If the Block Protect bits (BP1,BP0) = (1,1)
If one of the conditions defined in Section 3.4.1: Protocol control is not satisfied.
Doc ID 022579 Rev 3
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Application design recommendations
M95640-A125M95640-A145
5
Application design recommendations
5.1
Supply voltage (VCC)
5.1.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V
, V
] range must be applied (see Table 10 and Table 11).
CC(min)
CC(max)
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal Write cycle (t ). In order to
W
secure a stable DC supply voltage, it is recommended to decouple the V line with a
CC
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V /V package
CC SS
pins.
5.1.2
Power-up conditions
When the power supply is turned on, V continuously rises from V to V . During this
CC
SS
CC
time, the Chip Select (S) line is not allowed to float but should follow the V voltage. It is
CC
therefore recommended to connect the S line to V via a suitable pull-up resistor (see
CC
Figure 16).
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
defined in Table 13 and Table 14.
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V reaches the internal
CC
threshold voltage (this threshold is defined in the DC characteristics tables 13 and 14 as
VRES).
When V passes over the POR threshold, the device is reset and in the following state:
CC
●
●
●
in the Standby power mode
deselected
Status register values:
–
–
–
Write Enable Latch (WEL) bit is reset to 0.
Write In Progress (WIP) bit is reset to 0.
SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
●
not in the Hold condition
As soon as the V voltage has reached a stable value within [V (min), V (max)] range,
CC
CC
CC
the device is ready for operation.
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M95640-A125 M95640-A145
Application design recommendations
5.1.3
Power-down
During power-down (continuous decrease in the V supply voltage below the minimum
CC
V
●
●
operating voltage defined in Table 13 and Table 14), the device must be:
CC
deselected (Chip Select (S) should be allowed to follow the voltage applied on V ),
CC
in Standby power mode (there should not be any internal Write cycle in progress).
5.2
Implementing devices on SPI bus
Figure 16 shows an example of three devices, connected to the SPI bus master. Only one
device is selected at a time, so that only the selected device drives the Serial Data output
(Q) line. All the other devices outputs are then in high impedance.
Figure 16. Bus master and memory devices on the SPI bus
6##
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1
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6##
#
1
$
6##
#
1
$
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30) BUS MASTER
30) MEMORY
DEVICE
30) MEMORY
DEVICE
30) MEMORY
DEVICE
2
2
2
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1. The Write Protect (W) and Hold (HOLD) signals must be driven high or low as appropriate.
A pull-up resistor connected on each /S input (represented in Figure 16) ensures that each
device is not selected if the bus master leaves the /S line in the high impedance state.
Doc ID 022579 Rev 3
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Application design recommendations
M95640-A125M95640-A145
5.3
Cycling with Error Correction Code (ECC)
The Error Correction Code (ECC) is an internal logic function which is transparent for the
SPI communication protocol.
(a)
The ECC logic is implemented on each group of four EEPROM bytes . Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
(a)
other bytes located in the same group . As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 9: Cycling performance by groups of 4 bytes.
Example1: maximum cycling limit reached with 1 million cycles per byte
Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group
cycling budget is 4 million cycles.
Example2: maximum cycling limit reached with unequal byte cycling
Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times,
byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million
cycles.
a. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
Doc ID 022579 Rev 3
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M95640-A125 M95640-A145
Delivery state
6
Delivery state
The device is delivered with:
●
●
●
the memory array set to all 1s (each byte = FFh),
Status register: bit SRWD =0, BP1 =0 and BP0 =0,
Identification page:
–
–
the first three bytes define the device identification (value defined in Table 5)
the 29 following bytes set to FFh.
7
Absolute maximum ratings
Stressing the device outside the ratings listed in Table 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 8.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TSTG
TAMR
TLEAD
VO
Storage temperature
–65
–40
150
150
°C
°C
°C
V
Ambient operating temperature
Lead temperature during soldering
Voltage on Q pin
See note (1)
–0.50
–0.50
VCC+0.6
VI
Input voltage
6.5
5
V
IOL
DC output current (Q = 0)
DC output current (Q = 1)
Supply voltage
mA
mA
V
IOH
5
VCC
VESD
–0.50
6.5
4000
Electrostatic pulse (Human Body Model)(2)
V
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. Positive and negative pulses applied on pin pairs, in accordance with AEC-Q100-002 (compliant with
JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω)
Doc ID 022579 Rev 3
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DC and AC parameters
M95640-A125M95640-A145
8
DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Table 9.
Symbol
Cycling performance by groups of 4 bytes
Parameter
Test condition
Min.
Max.
Unit
TA ≤ 25 °C, 1.8 V < VCC < 5.5 V
TA = 85 °C, 1.8 V < VCC < 5.5 V
TA = 125 °C, 1.8 V < VCC < 5.5 V
TA = 145 °C(3), 2.5 V < VCC < 5.5 V
4,000,000
1,200,000
600,000
Write
Ncycle
Write cycle endurance(1)
cycle(2)
400,000
1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where
N is an integer, or for the status register byte (refer also to Section 5.3: Cycling with Error Correction Code (ECC)). The
Write cycle endurance is defined by characterization and qualification.
2. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID instruction is decoded. When
using the Byte Write, the Page Write or the WRID, refer also to Section 5.3: Error Correction Code (ECC).
3. For temperature range 4 only.
Table 10. Operating conditions (voltage range W, temperature range 4)
Symbol
Parameter
Supply voltage
Conditions
Min. Max. Unit
VCC
TA
2.5
5.5
V
Ambient operating temperature
Operating clock frequency
–40
145
°C
5.5 V ≥ VCC ≥ 2.5 V,
capacitive load on Q pin ≤100pF
fC
10
MHz
Table 11. Operating conditions (voltage range R, temperature range 3)
Symbol
Parameter
Supply voltage
Conditions
Min. Max. Unit
VCC
TA
1.8
5.5
125
10
5
V
Ambient operating temperature
–40
°C
VCC ≥ 2.5 V, capacitive load on Q pin ≤100pF
VCC ≥ 1.8 V, capacitive load on Q pin ≤100pF
fC
Operating clock frequency
MHz
Table 12. Operating conditions (voltage range R, temperature range 3)
for high speed communications
Symbol
Parameter
Supply voltage
Conditions
Min. Max. Unit
VCC
TA
4.5
5.5
85
20
V
Ambient operating temperature
Operating clock frequency
–40
°C
fC
VCC ≥ 4.5 V, capacitive load on Q pin ≤60 pF
MHz
28/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
DC and AC parameters
Table 13. DC characteristics (voltage range W, temperature range 4)
Specific test conditions
Symbol
Parameter
Min.
Max.
Unit
(in addition to conditions
specified in Table 10)
(2)
COUT
Output capacitance (Q)
Input capacitance
VOUT = 0 V
8
6
2
3
pF
µA
(2)
CIN
VIN = 0 V
ILI
Input leakage current
Output leakage current
VIN = VSS or VCC
S = VCC, VOUT = VSS or VCC
ILO
V
CC = 2.5 V, fC = 10 MHz,
C = 0.1VCC/0.9VCC, Q = open
CC = 5.5 V, fC = 10 MHz,
2
4
ICC
Supply current (Read)
Supply current (Write)
V
mA
C = 0.1VCC/0.9VCC, Q = open
2.5 V < VCC < 5.5 V, during tW,
S = VCC
(1)
ICC0
2(2)
t° = 85 °C, VCC = 2.5 V, S = VCC
VIN = VSS or VCC
2
t° = 85 °C, VCC = 5.5 V, S = VCC
VIN = VSS or VCC
3
t° = 125 °C, VCC = 2.5 V, S = VCC
VIN = VSS or VCC
15
20
25
40
Supply current
(Standby power mode)
ICC1
µA
t° = 125 °C, VCC = 5.5 V, S = VCC
VIN = VSS or VCC
t° = 145 °C, VCC = 2.5 V, S = VCC
VIN = VSS or VCC
t° = 145 °C, VCC = 5.5 V, S = VCC
VIN = VSS or VCC
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
–0.45 0.3VCC
0.7VCC VCC+1
0.4
VOL
VOH
IOL = 2 mA
IOH = -2 mA
V
0.8VCC
Internal reset threshold
voltage
(2)
VRES
0.5
1.3
1. Average value during the Write cycle (tW)
2. Characterized only, not 100% tested
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DC and AC parameters
M95640-A125M95640-A145
Table 14. DC characteristics (voltage range R, temperature range 3)
Test conditions
Symbol
Parameter
Min.
Max.
Unit
(in addition to conditions
specified in Table 11)
(3)
COUT
Output capacitance (Q) VOUT = 0 V
8
6
2
3
pF
µA
(3)
CIN
Input capacitance
VIN = 0 V
ILI
Input leakage current
VIN = VSS or VCC
ILO
Output leakage current S = VCC, VOUT = VSS or VCC
VCC = 1.8 V, C = 0.1VCC/0.9VCC
Q = open, fC = 5 MHz
,
2
2
5
VCC = 2.5 V, C = 0.1VCC/0.9VCC
,
ICC
Supply current (Read)
Supply current (Write)
mA
mA
Q = open, fC = 10 MHz
VCC = 5.5 V, fC = 20 MHz(1)
C = 0.1VCC/0.9VCC, Q = open
1.8 V ≤ VCC < 5.5 V during tW,
S = VCC
ICC0
2(3)
(2)
t° = 85 °C, VCC = 1.8 V, S = VCC,
VIN = VSS or VCC
1
t° = 85 °C, VCC = 2.5 V, S = VCC,
VIN = VSS or VCC
2
t° = 85 °C, VCC = 5.5 V, S = VCC,
VIN = VSS or VCC
3
Supply current
(Standby mode)
ICC1
µA
t° = 125 °C, VCC = 1.8 V, S = VCC,
VIN = VSS or VCC
15
15
20
t° = 125 °C, VCC = 2.5 V, S = VCC,
VIN = VSS or VCC
t° = 125 °C, VCC = 5.5 V, S = VCC,
VIN = VSS or VCC
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC < 5.5 V
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC < 5.5 V
VCC = 1.8 V, IOL = 1 mA
VCC ≥ 2.5 V, IOL = 2 mA
–0.45
–0.45
0.25 VCC
0.3 VCC
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
V
V
V
0.75 VCC VCC+0.5
0.7 VCC
VCC+0.5
0.3
VOL
0.4
VCC = 1.8 V, IOH = 1 mA
0.8 VCC
0.8 VCC
VOH
V
V
VCC ≥ 2.5 V, IOH = -2 mA
Internal reset threshold
voltage
(3)
VRES
0.5
1.3
1. When –40 °C < t° < 85 °C.
2. Average value during the Write cycle (tW)
3. Characterized only, not 100% tested
30/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
DC and AC parameters
Table 15. AC characteristics
Min. Max. Min. Max. Min. Max.
Test
Test
conditions
Test
Symbol
Alt.
Parameter
Unit
conditions specified in conditions
specified in
Table 11
Table 10
and
specified in
Table 12
Table 11
fC
fSCK Clock frequency
5
10
20
MHz
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
tCS S deselect time
tCSH S active hold time
S not active hold time
60
60
90
60
60
80
80
2
30
30
40
30
30
40
40
2
15
15
20
15
15
20
20
2
ns
µs
(1)
tCH
tCLH Clock high time
tCLL Clock low time
(1)
tCL
(2)
tCLCH
tRC Clock rise time
(2)
tCHCL
tFC
Clock fall time
2
2
2
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tDSU Data in setup time
tDH Data in hold time
20
20
60
60
0
10
10
30
30
0
5
10
15
15
0
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not
active
tCLHH
0
0
0
ns
(2)
tSHQZ
tDIS Output disable time
tV Clock low to output valid
80
40
20
(3)
tCLQV
80
40
20
tCLQX
tHO Output hold time
tRO Output rise time
tFO Output fall time
0
0
0
(2)
tQLQH
20
20
80
80
4
20
20
40
40
4
20
20
20
20
4
(2)
tQHQL
tHHQV
tLZ
HOLD high to output valid
(2)
tHLQZ
tHZ HOLD low to output high-Z
tWC Write time
tW
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
3. tCLQV must be compatible with tCL (clock low time): if tSU is the Read setup time of the SPI bus master, tCL must be equal to
(or greater than) tCLQV+tSU
.
Doc ID 022579 Rev 3
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DC and AC parameters
Figure 17. AC measurement I/O waveform
M95640-A125M95640-A145
)NPUT VOLTAGE LEVELS
)NPUT AND OUTPUT
TIMING REFERENCE LEVELS
ꢊꢐꢇ 6
##
ꢊꢐꢂ 6
##
ꢊꢐꢃ 6
##
ꢊꢐꢆ 6
##
!)ꢊꢊꢇꢆꢈ#
Figure 18. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCL
tCLCH
MSB IN
LSB IN
D
Q
High impedance
AI01447d
Figure 19. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQV
tHLQZ
Q
HOLD
AI01448c
32/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
DC and AC parameters
Figure 20. Serial output timing
S
tCH
tSHSL
C
tCLQV
tCLQX
tCLCH
tCHCL
tCL
tSHQZ
Q
D
tQLQH
tQHQL
ADDR
LSB IN
AI01449f
Doc ID 022579 Rev 3
33/39
Package mechanical data
M95640-A125M95640-A145
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 21. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 16. SO8N – 8-lead plastic small outline, 150 mils body width, package
mechanical data
millimeters
inches(1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.75
0.25
0.0689
0.0098
0.10
1.25
0.28
0.17
0.0039
0.0492
0.011
0.48
0.23
0.10
5.00
6.20
4.00
–
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
0.0067
ccc
D
4.90
6.00
3.90
1.27
4.80
5.80
3.80
–
0.1929
0.2362
0.1535
0.05
0.189
0.2283
0.1496
-
E
E1
e
h
0.25
0°
0.50
8°
0.0098
0°
0.0197
8°
k
L
0.40
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
34/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
Package mechanical data
Figure 22. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 17. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 022579 Rev 3
35/39
Package mechanical data
M95640-A125M95640-A145
Figure 23. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
E
B
$
,ꢀ
,ꢃ
0IN ꢀ
%ꢆ
+
%
,
!
$ꢆ
EEE
!ꢀ
1. Drawing is not to scale.
:7?-%E6ꢆ
2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 18. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.550
0.020
0.250
2.000
0.450
0.000
0.200
1.900
1.200
2.900
1.200
0.600
0.050
0.300
2.100
1.600
3.100
1.600
0.0217
0.0008
0.0098
0.0787
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0472
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
0.0630
A1
b
D
D2 (rev MC)
E
3.000
0.500
0.1181
0.0197
E2 (rev MC)
e
K (rev MC)
0.300
0.300
0.0118
0.0118
L
L1
0.500
0.150
0.0197
0.0059
L3
0.300
0.080
0.0118
0.0031
eee(2)
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
36/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
Part numbering
10
Part numbering
Table 19. Ordering information scheme
Example:
M95640-D
W DW 4
T
P /K
Device type
M95 = SPI serial access EEPROM
Device function
640-D = 64 Kbit (8 Kbytes) plus Identification Page
640 = 64 Kbit(8 Kbytes)
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
Package(1)
MN = SO8 (150 mils width)
DW = TSSOP8 (169 mils width)
MC = MLP8 (2 × 3 mm)
Device grade
3 = –40 to 125 °C. Device tested with high reliability certified flow(2)
4 = –40 to 145 °C. Device tested with high reliability certified flow(2)
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK (RoHS compliant)
Process letter
/K = Manufacturing technology code
1. All packages are ECOPACK2® (RoHS compliant and Halogen-free).
2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest
ST sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 022579 Rev 3
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Revision history
M95640-A125M95640-A145
11
Revision history
Table 20. Document revision history
Date
Revision
Changes
16-Dec-2011
1
Initial release.
Updated RDLS and LID in Table 7: Significant bits within the two
address bytes.
Updated condition related to fC in Table 12: Operating conditions
(voltage range R, temperature range 3) for high speed
communications.
Updated Note 2 below Table 9: Cycling performance by groups of 4
bytes.
16-Feb-2012
2
Changed Table 11: Operating conditions (voltage range R,
temperature range 3) and Table 12: Operating conditions (voltage
range R, temperature range 3) for high speed communications titles.
Added Note 1 in Table 14: DC characteristics (voltage range R,
temperature range 3).
Changed datasheet status to Production data.
MLP8 MB version removed in Figure 23: UFDFPN8 (MLP8) - 8-lead
ultra thin fine pitch dual flat no lead, package outline, Table 18:
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no
lead 2 x 3 mm, data, and in Table 19: Ordering information scheme.
02-Aug-2012
3
38/39
Doc ID 022579 Rev 3
M95640-A125 M95640-A145
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Doc ID 022579 Rev 3
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