MK5027PLCC52 [STMICROELECTRONICS]
SS7 SIGNALLING LINK CONTROLLER; SS7信令链路控制器
| 型号： | MK5027PLCC52 |
| 厂家： | 
ST |
| 描述： | SS7 SIGNALLING LINK CONTROLLER |
| 文件： | 总19页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK5027
SS7 SIGNALLING
LINK CONTROLLER
CMOS
FULLY COMPATIBLE WITH BOTH 8 OR 16
BIT SYSTEMS
SYSTEM CLOCK RATE TO 10MHz. DATA
RATE UP TO 2.5Mbps FOR SS7 PROTOCOL
PROCESSING,7Mbps FOR TRANSPARENT
HDLC MODE
DIP48
PLCC52
COMPLETE LEVEL 2 IMPLEMENTATION
COMPATIBLE WITH 1988 CCITT, AT&T,
ANSI, AND BELLCORE SIGNALLING SYS-
TEM NUMBER 7 LINK LEVEL PROTOCOLS
52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN
COMPATIBLE WITH THE SGS-THOMSON
X.25 CHIP (MK5025) AND NEARLY PIN-FOR-
PIN COMPATIBLE WITH THE SGS-THOM-
SON VLANCE CHIP (MK5032)
BUFFER MANAGEMENT INCLUDES:
- Initialization Block
- Separate Receive and Transmit Rings
- Variable Descriptor Ring and Window Sizes.
conductor device which provides a complete link
control function conforming to the 1988 CCITT
version of SS7. This includes frame formatting,
transparency (so called ”bit-stufling”), error recov-
ery by two types of retransmission, error monitor-
ing, sequence number control, link status con-
trol, and FISU generation. One of the outstanding
features of the MK5027 is its buffer management
which includes on-chip DMA. This feature allows
users to handlq multiple packets of receive and
transmit data at a time. (A conventional data link-
control chip plus a separate DMA chip would han-
dle data for only a single block at a time.) The
MK5027 may be used with any of several popular
16 and 8 bit microprocessors, such as 68000,
6800, Z8000, Z80, LSI-11, 8086, 8088, 8080, etc.
ON CHIP DMA CONTROL WITH PROGRAM-
MABLE BURST LENGTH
SELECTABLE BEC OR PCR RETRANSMIS-
SION METHODS, INCLUDING FORCED RE-
TRANSMISSION FOR PCR
HANDLES ALL 7 SS7 TIMERS
HANDLES ALL SS7 FRAME FORMATTING:
- Zero bit insert and delete
Figure 1: Pin Connection.
1
48
VCC (+5V)
VSS-GND
DAL07
2
3
47
46
DAL08
DAL09
DAL06
DAL05
DAL04
4
5
45
44
43
42
DAL10
DAL11
DAL12
DAL13
- FCS generation and detection
- Frame delimiting with flags
DAL03
DAL02
6
7
PROGRAMMABLE MINIMUM SIGNAL UNIT
SPACING (number of flags between SU’s)
HANDLES ALL SEQUENCING AND LINK
CONTROL
SELECTABLE FCS OF 16 OR 32 BITS.
TESTING FACILITIES:
- Internal Loopback
- Silent Loopback
- OptionalInternal Data Clock Generation
- Self Test
ALL INPUTS AND OUTPUTS ARE TTL COM-
PATIBLE
DAL01
DAL00
8
41
40
DAL14
DAL15
M
K
9
10
11
READ
INTR
39
38
A16
A17
A18
A19
5
0
H
2
5
12
13
DALI
37
36
35
34
DALO
A20
A21
DAS
14
15
16
BMO, BYTE, BUSREL
33
A22
BMI, BUSAKO
32
31
A23
RD
HOLD, BUSRQ
ALE, AS
17
18
30
29
DSR, CTS
TD
HLDA
CS
19
20
PROGRAMMABLE FOR FULL OR HALF DU-
PLEX OPERATION
28
27
SYSCLK
RCLK
ADR
21
22
READY
DESCRIPTION
The SGS-THOMSON Signalling System #7 Sig-
nalling Link Controller (MK5027) is a VLSI semi-
26
25
DTR, RTS
TCLK
RESET
23
24
VSS-GND
1/19
August 1989
MK5027
Table 1: Pin Description.
LEGEND:
I
Input only
O
Output only
3-State
IO
OD
Input/Output
3S
Open Drain (no internal pull-up)
Signal Name
Pin(s)
Type
Descriplion
DAL<15:00>
READ
2-9
40-47
IO/3S
The time multiplexed Data Address bus. During the address portion of a
memory transfer, DALe15:00 contains the lower 16 bits of the memory
address.
During the data portion of a memory transfer, DAL<15:00> contains the
read or write data, depending on the type of transfer.
10
IO/3S
READ indicates the type of operation that the bus controller is performing
during a bus transaction. READ is driven by the MK5027 only while it is
the BUS MASTER. READ is valid during the entire bus transaction and is
tristated at all other times.
MK5027 as a Bus Slave:
READ = HIGH - Data is placed on the DAL lines by the chip.
READ = LOW - Data is taken off the DAL lines by the chip.
MK5027 as a Bus Master:
READ = HIGH - Data is taken off the DAL lines by the chip.
READ = LOW - Data is placed on the DAL lines by the chip.
INTR
DALI
11
12
O/OD
O/3S
INTERRUPT is an attention interrupt line that indicates that one or more of
the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT.
INTERRUPT is enabled by CSR0<0.9>, INEA = 1.
DAL IN is an external bus transceiver control line. DALI is driven by the
MK5027 only while it is the BUS MASTER. DALIis asserted by the
MK5027 when | ads from the DAL lines during the data portion of a READ
transfer. DALI is not asserted during a WRITE transfer.
DALO
DAS
13
14
O/3S
DAL OUT is an external bus transceiver control line. DALOis driven by
the MK5027 only while it is the BUS MASTER. DALO is asserted by the
MK5027 when it drives the DAL lines during the address portion of a
READ transfer or for the duration of a WRITE transfer.
IO/3S
DATA STROBE defines the data portio,n of a transaction. By definition,
data is stable and valid at the low to high transition of DAS. This signal is
driven by the MK5027 while it is the BUS MASTER. During the BUS
SLAVE operation, this pin is used as an input. At all other times the signal
is tristated.
BMO
BYTE
BUSREL
15
IO/3S
I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is
set to a one, pin 15 becomes input BUSREL and is used by the host to
signal the MK5027 to terminate a DMA burst after the current bus transfer
has completed. If bit 06 is clear the pin 15 is an output and behaves as
described below for pin 16.
Note: Pin out shown is for 48 pin dip.
2/19
MK5027
Table 1: Pin Description (continued)
Signal Name
Pin(s)
Type
Descriplion
BM1
BUSAKO
16
O/3S
Pins 15 and 16 are programmable though bit 00 of CSR4 (BCON).
If CSR4<00> BCON = 0,
I/O PIN 15 = BMO (O/3S)
I/O PIN 16 = BM1 (O/3S)
BYTE MASK<1:0> indicates the byte(s) on the DAL to be read or written
during this bus transaction. MK5027 drives these lines only as a Bus
Master. MK5027 ignores the BM lines when it is a Bus Slave.
Byte selection is done as outlined in the following table.
BM1
BM0
TYPE OF TRANSFER
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
ENTIRE WORD
UPPER BYTE (DAL<15:08>)
LOWER BYTE (DAL<07:00>)
NONE
If CSR4<00>BCON = 1,
I/O PIN 15 = BYTE (O/3S)
I/O PIN 16 = BUSAKO(O)
Byte selection is done using the BYTE line and DAL<00> latched during
the address portion of the bus transaction. MK5027 drives BYTE only a
Bus Master and ignores it when a Bus Slave. Byte selection is done as
outlined in the following table.
BYTE
DAL<00>
TYPE OF TRANSFER
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
ENTIRE WORD
ILLEGAL CONDITION
LOWER BYTE
UPPER BYTE
BUSAKOis a bus request daisy chain output. If MK5027 is not requesting
the bus and it receives HLDA, BUSAKOwill be driven low. If MK5027 is
requesting the bus when it receives HLDA, BUSAKOwill remain high.
Note: All transfers are entire word unless the MK5027 is configured for 8
bit operation.
HOLD
BUSRQ
17
IO/OD
Pins 17 is configured through bit 0 of CSR4.
If CSR4<00> BCON = 0,
I/O PIN 17 = HOLD
HOLD request is asserted by MK5027 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin.
HOLD is held low for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,
I/O PIN 17 = BUSRQ
BUSRQ is asserted by MK5027 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held
low for the entire ensuing bus transaction.
ALE
AS
18
O/3S
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its
asserted level. This signal is driven by MK5027 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,
I/O PIN 18 = ALE
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define
the address portion of the transfer and remains low during the data portion.
If CSR4<01> ACON = 1,
I/O PIN 18 = AS
As AS, the signal pulses low during the address portion of the bus
transfer. The low to high transition of AScan be used by a slave device to
strobe the address into a register.
AS is effectively the inversion of ALE.
HLDA
19
I
HOLD AKNOWLEDGE is the response to HOLD. When HLDA is low in response
to MK5027’s assertion of HOLD, the MK5027 is the Bus Master. HLDA should be
desasserted ONLY after HOLD has been released by the MK5027.
3/19
MK5027
Table 1: Pin Description (continued)
Signal Name
Pin(s)
Type
Descriplion
CS
20
I
CHIP SELECT indicates, when low, that the MK5027 is the slave device
for the data transfer.CS must be valid througout the enture transaction.
ADR
21
I
ADDRESS selects the Register Address Port or the Register Data Port. It
must be valid throughout the data portion of the transfer and is only used
by the chip when CS is low.
ADR
LOW
HIGH
PORT
REGISTER DATA PORT
REGISTER ADDRESS PORT
READY
22
IO/OD
When the MK5027 is a Bus Master, READY is an asynchronous
acknowledgement from the bus memory that memory will accept data in a
WRITE cycle or that memory has put data on the DAL lines in a READ
cycle.
As a bus Slave, the MK5027 asserts READY when it has put data on the
DAL lines during a READ cycle or is about to take data from the DAL lines
during WRITE cycle. READY is a response to DAS and it will be released
after DAS or CS is negated.
RESET
TCLK
23
25
I
I
RESET is the Bus signal that will cause MK5027 to cease operation, clear
its internal logic and enter an idle state with the Power Off bit of CSR0 set.
TRANSMIT CLOCK. A 1x clock input for transmitter timing. TD changes
on the falling edge of TCLK. The frequency of TCLK may not be greater
than the frequency of SYSCLK.
DTR
RTS
26
IO
DATA TERMINAL READY, REQUEST TO SEND. Modem control pin. Pin
26 is configurable through CSR5. This pin can be programmed to behave
as output RTS or as programmable IO pin DTR. If configured as RTS, the
MK5027 will assert this pin if it has data to send and throughout the
transmission of a signal unit.
RCLK
27
28
I
I
RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on
the rising edge of RCLK. The frequency of RCLK may not be greater than
the frequency of SYSCLK.
SYSCLK
TD
SYSTEM CLOCK. System clock used for internal timing of the MK5027.
SYSCLK should be a square wave, of frequency up to 10MHz.
29
30
O
TRANSMIT DATA. Transmit serial data output.
DSR
CTS
IO
DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is
configurable through CSR5. This pin can be programmed to behave as
input CTS or as programmable IO pin DSR. If configured as CTS, the
MK5027 will transmit all ones while CTS is high.
RD
31
I
RECEIVE DATA. Received serial data input.
A<23:16>
32-39
O/3S
Address bits <23:16> used in conjunction with DAL <15:00> to produce a
24 bit address. MK5027 drives these lines only as a Bus Master.
A23-A20 may be driven continuously as described in the CSR4<7> BAEN
bit.
VSS-GND
VCC
1, 24
48
Ground Pins
Power Supply Pin
+5.0 VDC ± 5%
4/19
MK5027
Figure 2: Possible System Configuration for the MK5027.
5/19
MK5027
Figure 3: MK5027 Simplified Block Diagram.
READY
READ
DAS
FIRMWARE
ROM
CONTROL / STATUS
REGISTERS 0 - 5
MICRO
CONTROLLER
DMA
TIMERS
CONTROLLER
SYSCLK
INTERNAL BUS
RECEIVER
TRANSMITTER
FIFO
FIFO
VCC
VSS - GND
RESET
TCLK
TD
RCLK
RECEIVER
TRANSMITTER
RD
LOOPBACK
TEST
nel DMA: one channel for receive and one chan-
nel for transmit. The MK5027 handles error recov-
ery andlink status signalling.
OPERATIONAL DECRIPTION
The SGS-THOMSON Signalling System #7 Sig-
nalling Link Controller (MK5027) device is a VLSI
product intended for data communication applica-
tions requiring SS7 link level control. The MK5027
will perform all frame formatting, such as: frame
delimiting with flags, FCS generation and detec-
tion. It will also perform all error recovery and link
control. The MK5027 also includes a buffer man-
agement mechanism that allow the user to trans-
mit and/or receive multiple MSU’s. Contained in
the buffer management is an on-chip dual chan-
The MK5027 is intended to be used with any
popular 16 or 8 bit microprocessor. Possible sys-
tem configuration for the MK5027 is shown in Fig-
ure 2. The MK5027 will move multiple blocks of
receive and transmit data directly into and out of
memory through the host’s bus. An I/O accelera-
tion processor in Figure 2 is recommended, but
not required.
6/19
MK5027
MK5027 allows access to its 6 control/status reg-
isters which are used to monitor and control the
chip. These registers are used to control link pro-
cedures, configure interface options, control and
monitor interrupt status. and more. Bus slave
mode also allows both 8 and 16 bit accesses.
All signal pins on the MK5027 are TTL compat-
ible. This has the advantage of making the
MK5027 in- dependent of the physical interface.
As shown in Figure 2. Iine drivers and receivers
are used for electrical- connection to the physical
layer.
BUFFER MANAGEMENT
SERIAL INTERFACE
The basic organization of the buffer management
is a circular queue of tasks in memory called de-
scriptor rings. There are separate rings to de-
scribe the transmit and receive operations. Up to
128 buffers may be queued-up on a descriptor
ring awaiting execution by the MK5027 The de-
scriptor ring has a segment assigned to each
buffer. Each segment holds a pointer for the start-
ing address of the buffer. and holds a value for
the length of the buffer in bytes.
Each segment also contains two control bits
called OWNA and OWNB, which denote whether
the MK5027. the HOST. or the l/O ACCELERA-
TION PROCESSOR (if present) ”owns” the buff-
er. For transmit. when the MK5027 owns the buff-
er. the MK5027 is allowed and commanded to
transmit the buffer When the MK5027 does not
own the buffer, it will not transmit that buffer. For
receive. when the MK5027 owns a buffer. it may
place received data into that buffer. Conversely.
when the MK5027 does not own a receive buff-
er, it will not place received data in that buffer.
The MK5027 provides two separate serial chan-
nels: one for received data and one for transmit-
ted data. These serial channels are completely
separate and may be run at different clock fre-
quencies The receiver is responsible for recogniz-
ing frame boundries. removal of inserted zeroes
(for transparency) and checking the incoming
FCS. Signal units with in correct FCS values are
discarded. The receiver also parallelizes the in-
coming data which is placed into the receive data
buffers within the receive descriptor ring The
transmitter is responsible for framing and serializ-
ing the data frames placed in the transmit de-
scriptor ring. The transmitter calculates the FCS
of the outgoing data and appends it to the data
The transmitter generates flag sequences for in-
ter-signal unit fill, at least two flags are transmit-
ted between adjacent signal units. The FCS cal-
culations for both directions of serial data
optionally follow either the 16 bit CRC CCITT or
the 32-bit CRC 32 algorithms FCS generation and
checking can also be optionally disabled if neces-
sary.
The MK5027 buffer management mechanism will
handly signal units which are longer than the
length of an individual buffer. This is done by a
chaining method which utilizes multiple buffers.
The MK5027 tests the next segment in the de-
scriptor ring in a ”look ahead” manner. If the
packet is too long for one buffer, the next buffer-
will be used after filling the first buffer: that is,
”chained”. The MK5027 will then ”look ahead” to
the next buffer, and chain that buffer if necessary,
and so on The operational parameters for the
buffer management are defined by the user
in the initialization block The parameters defined
include the basic mode of operation. the number
of entries for the transmitter and receiver descrip-
tor rings. etc.
MICROPROCESSOR INTERFACE
The MK5027 contains a dual channel DMA on
chip to handle data transfers to and from the host
mem- ory. All access to the initialization block and
descriptor rings is handled in this way The ad-
dress bus is 24 bits wide and does not use any
segmentation or paging methods. Data transfers
can optionally be 8 and 16 bit operations. this al-
lows easy interfacing with both 8 and 16 bit proc-
essors DMA transfers can be up to 1. 8 or an un-
limited number of words per transfer under
program control During bus slave operation the
7/19
MK5027
Figure 4: MK5027 Buffer Management.
RECEIVE BUFFER
CSR 2, CSR3
BUFFER
0
RECEIVER DESCRIPTOR RINGS
POINTER TO
INITIALIZATI ON BLOCK
DESCRIPTOR 0
BUFFER STATUS
BUFFER ADDRESS
BUFFER SIZE
BUFFER
1
BUFFER MSG COUNT
DESCRIPTOR 1
INITIALIZATI ON BLOCK
MODE
BUFFER
M
FRAME ADDRESS
FIELDS
DESCRIPTOR M
TIMER VALUES
RX DESCRIPTOR
POINTER
TRANSMIT BUFFER
TRANSMIT DESCRIPTOR RINGS
BUFFER
0
TX DESCRIPTOR
POINTER
DESCRIPTOR 0
BUFFER STATUS
XID/TEST TRANSMIT
DESCRIPTOR POINTER
BUFFER ADDRESS
BUFFER SIZE
XID/TEST RECEIVE
DESCRIPTOR POINTER
BUFFER
1
BUFFER MSG COUNT
DESCRIPTOR 1
STATUS
BUFFER ADDRESS
ERROR COUNTERS
STATUS BUFFER
BUFFER
N
XID/TEST
DESCRIPTOR N
RECEIVE BUFFER
XID/TEST
TRANSMIT BUFFER
8/19
MK5027
Name
Definition
Flag Sequence
Forward Sequence Number
Backward Sequences Number
Forward Indicator Bit
Backward Indicator Bit
Lenght Indicator
Programmed As Zeroes
Signalling Information Octet
Service Information Field
Satus Field
SIGNALLING UNIT REPERTOIRE
F
The signal unit repertoire of the MK5027 is shown
in Table 1. This set conforms to the 1988 CCITT
specification for level 2 of Signalling System #7.
The definitions for the symbols for the frame
types are:
FSN
BSN
FIB
BIB
LI
X
SIO
SIF
SF
FCS
Frame Check Sequence
Table 1: MK5027 Signal Unit Repertoire.
9/19
MK5027
MK5027 ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Temperature under Bias
–25°C to +100°C
–65°C to +150°C
–0.5V to VCC +0.5V
0.50W
Storage Temperature
Voltage on Any Pin with Respect to Ground
Power Dissipation
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the above device. This is a stress rating only
and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability.
DC CHARACTERISTICS
TA=0 °C to 70 °C, VCC = +5V ±5 percent unless otherwise specified.
Symbol
VIL
Parameter
Min.
-0.5
Typ.
Max.
+0.8
Units
V
VIH
+2.0
VCC+0.5
+0.5
V
VOL
VOH
IIL
@ IOL = 3.2 mA
@ IOH= -0.4 mA
@ VIN = 0.4 to VCC
@ TSCT = 100 ns
V
+2.4
V
+10
mA
µA
ICC
50
CAPACITANCE
f = 1MHz
Symbol
Parameter
Min.
Typ.
Max.
10
Units
pF
CIN
COUT
CIO
Capacitance on Input pins
Capacitance on Output Pins
Capacitance on I/O pins
10
pF
20
pF
AC TIMING SPECIFICATIONS
TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified.
Test
Condition
No Signal Symbol
Parameter
SYSCLK period
Min.
Typ.
Max. Units
1
2
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
TCLK
TSCT
TSCL
TSCH
TSCR
TSCF
TTCT
TTCL
TTCH
TTCR
TTCF
TTDP
100
45
45
0
20000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYSCLK low time
SYSCLK high time
Rise time of SYSCLK
Fall time of SYSCLK
TCLK period
3
4
8
8
5
0
6
140
63
63
0
7
TCLK
TCLK low time
8
TCLK
TCLK high time
9
TCLK
Rise time of TCLK
Fall time of TCLK
CL = 50 pF
CL = 50 pF
8
8
10
11
TCLK
0
TD
TD data propagation delay after the
falling edge of TCLK
40
12
TD
TTDH
TD data hold time after the falling edge
of TCLK
5
ns
10/19
MK5027
AC TIMING SPECIFICATIONS (Continued)
TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified.
Test
Conditions
No Signal Symbol
Parameter
RCLK period
Min.
Typ.
Max.
Units
13
14
15
16
17
18
19
20
RCLK
RCLK
RCLK
RCLK
RCLK
RD
TRCT
TRCH
TRCL
TRCR
TRCF
TRDR
TRDF
TRDH
140
63
63
0
ns
ns
ns
ns
ns
ns
ns
ns
RCLK high time
RCLK low time
Rise time of RCLK
Fall time of RCLK
RD data rise time
RD data fall time
8
8
8
8
0
0
RD
0
RD
RD hold time after rising edge of
RCLK
5
21
RD
TRDS
TDOFF
TDON
THHA
RD setup time prior to rising edge of
RCLK
30
0
ns
ns
ns
ns
22 A/DAL
23 A/DAL
Bus Master driver disable after rising
edge of HOLD
50
Bus Master driver enable after falling TSCT = 100ns
edge of HLDA
0
200
24
HLDA
Delay to falling edge of HLDA from
falling edge of HOLD (Bus Master)
0
25 RESET
26 A/DAL
TRW
TCYCLE
TXAS
RESET pulse width
30
ns
ns
ns
Read/write, address/data Cycle Time TSCT = 100ns
600
100
27
28
29
30
31
32
33
34
35
36
37
38
A
Address setup time to falling edge
of ALE
A
TXAH
TAS
Address hold time after the rising
edge of DAS
50
75
20
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DAL
DAL
DAL
DAL
DAL
DAL
DAL
DAL
DAL
DAL
Address setup time to falling edge
of ALE
TAH
Address hold time after the falling
edge of ALE
TRDAS
TRDAH
TDDAS
TWDS
TWDH
TSRDH
TSWDH
TSWDS
Data setup time to the falling edge
of DAS (Bus Master read)
Data hold time after the rising edge
of DAS (bus master read)
Data setup time to the falling edge of
DAS (bus master write)
0
Data setup time to the rising edge of
DAS (bus master write)
250
35
0
Data hold time to the rising edge of
DAS (bus slave write)
Data hold time after the rising edge
of DAS (bus slave read)
TSCT = 100ns
35
Data hold time after the rising edge
of DAS (bus slave write)
0
Data setup time to the falling edge of
DAS (bus slave write)
0
39
40
ALE
ALE
TALEW
TDSW
ALE width high
110
70
ns
ns
Delay from rising edge od DAS to
the rising edge of ALE
41
DAS
TDSW
DAS width low
200
ns
11/19
MK5027
AC TIMING SPECIFICATIONS (Continued)
TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified.
Test
Conditions
No Signal Symbol
Parameter
Min.
Typ.
Max.
Units
42
43
DAS
DAS
TADAS
TRIDF
Delay from the falling edge of ALE to
the falling edge of DAS
80
ns
Delay from the rising edge of DALO
to the falling edge of DAS (bus
master read)
35
ns
44
45
DAS
DALI
TRDYS
TROIF
Delay from the falling edge of
READY to the falling edge of DAS
TARYD = 300ns
TSCT = 100ns
120
70
200
ns
ns
Delay from the rising edge of DALO
to the falling edge of DALI (bus
master read)
46
47
48
DALI
DALI
DALI
TRIS
TRIH
DALIsetup time to the rising edge of
DAS (bus master read)
150
0
ns
ns
ns
DALIhold time after the rising edge
of DAS (bus master read)
TRIOF
Delay from the rising edge of DALI
to the falling edge of DALO (bus
master read)
70
49
50
51
DALO
DALO
DALO
TOS
TROH
TWDSI
DALOsetup time to the falling edge
of ALE (bus master read)
110
35
ns
ns
ns
DALOhold time after the falling
edge of ALE (bus master read)
Delay from the rising edge of DAS to
the rising edge of DALO(bus master
write)
50
52
53
54
55
CS
CS
TCSH
TCSS
TSAH
TSAS
CS hold time after the rising edge of
DAS (bus slave)
0
0
0
0
ns
ns
ns
ns
ns
CS setup time to the falling edge of
DAS (bus slave)
ADR
ADR
ADR hold time after the rising edge
of DAS (bus slave)
ADR setup time to the falling edge of
DAS (bus slave)
56 READY
TARYD
Delay from the falling edge of ALE to TSCT = 100ns
the falling edge of READY to Insure
150
a Minimum Bus Cycle Time (600ns)
57 READY
58 READY
59 READY
60 READY
61 READ
62 READY
TSRDS
TRDYH
TSRYH
TRSH
Data setup time to the falling edge of
READY (bus slave read)
75
0
ns
ns
ns
ns
ns
ns
READY hold time after the rising
edge of DAS (bus master)
READY hold time after the rising
edge of DAS (bus slave)
TSCT = 100ns
0
35
READ hold time after rhe rising edge
of DAS (bus slave)
0
TSRS
READ setup time after rhe rising
edge of DAS (bus slave)
0
TRDYD
Delay from falling edge of DAS to
falling edge of READY (bus slave)
TSCT = 100ns
200
12/19
MK5027
Figure 5A: TTL Output Load Diagram.
Figure 5B: Open Drain Output Load Diagram.
TEST
POINT
Vcc
Vcc
R1 = 1.2K
R1 = 1.4K
FROM
FROM
CR1 - CR4 = 1N914 or EQUIV
OUTPUT
UNDER
TEST
OUTPUT
UNDER
TEST
CR
1
CR
2
3
4
0.4 mA
C
L
C
L
CR
CR
CL = 50pF min @ 1 MHz
NOTE: This load is used on open
drain outputs INTR, HOLD, READY.
NOTE: This load is used on all outputs except INTR, HOLD, READY.
Figure 6: MK5027 Serial Link Timing Diagram
13
14
15
RCLK
16
21
17
20
19
RD
18
6
8
7
TCLK
10
9
11
12
TD
TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES,
UNLESS OTHERWISE SPECIFIED:
”1”
”0”
OUTPUT
INPUT
2.0
2.0
V
V
O.8 V
O.8 V
FLOAT
10 %
90 %
13/19
MK5027
Figure 7: MK5027 Bus Master Timing Diagram (read).
Note: The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY.
14/19
MK5027
Figure 8: MK5027 Bus Master Timing Diagram (write).
Note: The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY.
15/19
MK5027
Figure 9: MK5027 Bus Slave Timing Diagram (read)
Figure 10: MK5027 Bus Slave Timing Diagram (write)
16/19
MK5027
DIP48 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.23
15.2
TYP.
0.63
0.45
MAX.
MIN.
0.009
0.598
MAX.
a1
b
0.025
0.018
b1
b2
D
E
0.31
0.012
1.27
0.050
62.74
16.68
2.470
0.657
e
2.54
0.100
2.300
e3
F
58.42
14.1
0.555
I
4.445
3.3
0.175
0.130
L
17/19
MK5027
PLCC52 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
4.20
0.51
2.29
0.33
0.66
MAX.
MIN.
MAX.
A
A1
A3
B
5.08
0.165
0.020
0.090
0.013
0.026
0.20
3.30
0.53
0.81
0.13
0.021
0.032
B1
C
0.25
0.01
0.60
D
19.94
19.05
17.53
20.19
19.20
18.54
0.785
0.750
0.690
0.795
0.756
0.730
D1
D2
D3
E
15.24
19.94
19.05
17.53
20.19
19.20
18.54
0.785
0.750
0.690
0.795
0.756
0.730
E1
E2
E3
e
15.24
1.27
0.60
0.05
L
0.64
1.53
1.07
1.07
0.025
0.060
0.042
0.042
L1
M
1.22
1.42
0.048
0.056
M1
18/19
MK5027
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices orsystems without express
written approval of SGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
19/19
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