NAND01GW3B2BZA6E [STMICROELECTRONICS]
1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory; 1千兆， 2千兆， 2112字节/ 1056字页， 1.8V / 3V ， NAND闪存
| 型号： | NAND01GW3B2BZA6E |
| 厂家： | 
ST |
| 描述： | 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory |
| 文件： | 总62页 (文件大小：713K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND01G-B2B
NAND02G-B2C
1 Gbit, 2 Gbit,
2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
Features
■ High Density NAND Flash memories
–
–
Up to 2 Gbit memory array
Cost effective solutions for mass
storage applications
■ NAND interface
TSOP48 12 x 20mm
–
–
–
x8 or x16 bus width
Multiplexed Address/ Data
Pinout compatibility for all densities
FBGA
■ Supply voltage: 1.8V/3.0V
■ Page size
VFBGA63 9.5 x 12 x 1mm
VFBGA63 9 x 11 x 1mm
–
–
x8 device: (2048 + 64 spare) Bytes
x16 device: (1024 + 32 spare) Words
■ Serial Number option
■ Data protection
■ Block size
–
–
x8 device: (128K + 4K spare) Bytes
x16 device: (64K + 2K spare) Words
–
–
Hardware Block Locking
Hardware Program/Erase locked during
Power transitions
■ Page Read/Program
–
–
–
Random access: 25µs (max)
■ Data integrity
Sequential access: 30ns (min)
Page program time: 200µs (typ)
–
–
100,000 Program/Erase cycles
10 years Data Retention
■ Copy Back Program mode
■ Cache Program and Cache Read modes
■ Fast Block Erase: 2ms (typ)
■ Status Register
®
■ ECOPACK packages
■ Development tools
–
–
Error Correction Code models
Bad Blocks Management and Wear
Leveling algorithms
■ Electronic Signature
■ Chip Enable ‘don’t care’
–
Hardware simulation models
Table 1.
Product List
Reference
Part Number
NAND01GR3B2B, NAND01GW3B2B
NAND01G-B2B
NAND02G-B2C
NAND01GR4B2B, NAND01GW4B2B(1)
NAND02GR3B2C, NAND02GW3B2C
NAND02GR4B2C, NAND02GW4B2C(1)
1. x16 organization only available for MCP Products.
November 2006
Rev 3
1/62
www.st.com
1
Contents
NAND01G-B2B, NAND02G-B2C
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
DD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
4.2
4.3
4.4
4.5
4.6
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
6
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1
6.1.2
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/62
NAND01G-B2B, NAND02G-B2C
Contents
6.2
6.3
Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.1
6.3.2
Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Random Data Input in a page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4
6.5
6.6
6.7
6.8
Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . 31
P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.9
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
8
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1
8.2
8.3
8.4
8.5
8.6
Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Hardware Simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.6.1
8.6.2
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
Program and Erase Times and Endurance cycles . . . . . . . . . . . . . . . . 40
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10
11
DC And AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.1 Ready/Busy Signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54
11.2 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3/62
Contents
12
NAND01G-B2B, NAND02G-B2C
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13
14
4/62
NAND01G-B2B, NAND02G-B2C
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Product List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address Insertion, x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address Definitions, x8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address Definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Copy Back Program x8 Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Copy Back Program x16 Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electronic Signature Byte/Word 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
NAND Flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 40
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DC Characteristics, 1.8V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DC Characteristics, 3V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 57
VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . 58
VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . . 59
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
5/62
List of figures
NAND01G-B2B, NAND02G-B2C
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TSOP48 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VFBGA63 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Cache Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Page Copy Back Program with Random Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14. Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15. Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16. Garbage Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17. Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 18. Equivalent Testing Circuit for AC Characteristics Measurement . . . . . . . . . . . . . . . . . . . . 43
Figure 19. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 20. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 22. Sequential Data Output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 23. Read Status Register AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 24. Read Electronic Signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 25. Page Read operation AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 26. Page Program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 27. Block Erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 28. Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 29. Program/Erase Enable waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 30. Program/Erase Disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 31. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 32. Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 33. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 56
Figure 34. Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 35. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . . . 57
Figure 36. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline. . . . . . . . . . 58
Figure 37. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . . . . 59
6/62
NAND01G-B2B, NAND02G-B2C
Description
1
Description
ST NAND01G-B2B and NAND02G-B2C Flash 2112 Byte/ 1056 Word Page is a family of
non-volatile Flash memories that uses NAND cell technology. The devices range from 1 Gbit
to 2 Gbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either
2112 Bytes (2048 + 64 spare) or 1056 Words (1024 + 32 spare) depending on whether the
device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or
x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of
NAND Flash devices it is strongly recommended to implement an Error Correction Code
(ECC).
The devices feature a Write Protect pin that allows performing hardware protection against
program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the
Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output
allows the Ready/Busy pins from several memories to be connected to a single pull-up
resistor.
A Copy Back Program command is available to optimize the management of defective
blocks. When a Page Program operation fails, the data can be programmed in another page
without having to resend the data to be programmed.
Each device has Cache Program and Cache Read features which improve the program and
read throughputs for large files. During Cache Programming, the device loads the data in a
Cache Register while the previous data is transferred to the Page Buffer and programmed
into the memory array. During Cache Reading, the device loads the data in a Cache
Register while the previous data is transferred to the I/O Buffers to be read.
All devices have the Chip Enable Don’t Care feature, which allows code to be directly
downloaded by a microcontroller, as Chip Enable transitions during the latency time do not
stop the read operation.
All devices have the option of a Unique Identifier (serial number), which allows each device
to be uniquely identified.
The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not
described in the datasheet. For more details of this option contact your nearest ST Sales
office.
The devices are available in the following packages:
■
■
■
TSOP48 (12 x 20mm)
VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for NAND02G-B2C devices.
VFBGA63 (9 x 11 x 1mm, 0.8mm pitch) for NAND01G-B2B devices.
In order to meet environmental requirements, ST offers the NAND01G-B2B and NAND02G-
®
B2C in ECOPACK packages. ECOPACK packages are Lead-free. The category of second
Level Interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark.
7/62
Description
NAND01G-B2B, NAND02G-B2C
For information on how to order these options refer to Table 29: Ordering Information
Scheme. Devices are shipped from the factory with Block 0 always valid and the memory
content bits, in valid blocks, erased to ’1’.
See Table 2: Product Description, for all the devices available in the family.
Table 2.
Product Description
Timings
Bus
Width Size
Page Block Memory Operatin
Random Sequential
Page
Program
time
Reference
Part Number
Density
Package
Block
Erase
(typ)
Size
Array
g Voltage
access
time
access
time
(max)
(min)
(typ)
1.7 to
1.95V
VFBGA63
9x11mm
NAND01GR3B2B
NAND01GW3B2B
NAND01GR4B2B
NAND01GW4B2B
NAND02GR3B2C
NAND02GW3B2C
NAND02GR4B2C
NAND02GW4B2C
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
50ns
30ns
50ns
30ns
50ns
30ns
50ns
30ns
2048+ 128K+
64 4K
Bytes Bytes
x8
x16
x8
2.7 to
3.6V
64
Pages x
1024
TSOP48
(1)
NAND01G
-B2B
1Gbit
2ms
1.7 to
1.95V
Blocks
1024+ 64K+
32
2K
2.7 to
3.6V
Words Words
(1)
200µs
1.7 to
1.95V
VFBGA63
9.5x12mm
2048+ 128K+
64
4K
2.7 to
3.6V
Bytes Bytes
64
Pages x
2048
TSOP48
(1)
NAND02G
-B2C
2Gbit
2ms
1.7 to
1.95V
Blocks
1024+ 64K+
x16
32
2K
2.7 to
3.6V
Words Words
(1)
1. x16 organization only available for MCP
8/62
NAND01G-B2B, NAND02G-B2C
Description
Figure 1.
Logic Block Diagram
Address
Register/Counter
AL
NAND Flash
CL
W
Memory Array
P/E/R Controller,
High Voltage
Generator
Command
Interface
Logic
E
WP
R
Page Buffer
Cache Register
Y Decoder
Command Register
I/O Buffers & Latches
RB
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
AI12799
Figure 2.
Logic Diagram
V
DD
I/O8-I/O15, x16
E
R
I/O0-I/O7, x8/x16
RB
W
NAND01G-B2B
NAND02G-B2C
AL
CL
WP
V
SS
AI13101
1. x16 organization only available for MCP
9/62
Description
NAND01G-B2B, NAND02G-B2C
Table 3.
Signal Names
I/O8-15
Data Input/Outputs for x16 devices
Data Input/Outputs, Address Inputs, or Command Inputs for x8 and
x16 devices
I/O0-7
AL
CL
E
Address Latch Enable
Command Latch Enable
Chip Enable
R
Read Enable
RB
W
Ready/Busy (open-drain output)
Write Enable
WP
VDD
VSS
NC
DU
Write Protect
Supply Voltage
Ground
Not Connected Internally
Do Not Use
10/62
NAND01G-B2B, NAND02G-B2C
Description
Figure 3.
TSOP48 Connections
NC
NC
NC
NC
NC
NC
RB
R
1
48
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
E
NC
NC
NC
NC
V
12 NAND01GW3B2B37
NAND02GW3B2C
36
V
V
DD
DD
SS
V
13
SS
NC
NC
CL
AL
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
W
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
24
25
AI13102
1. Available only for NAND01GW3B2B and NAND02GW3B2C 8-bit devices.
11/62
Description
Figure 4.
NAND01G-B2B, NAND02G-B2C
VFBGA63 Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
DU
DU
DU
A
B
DU
DU
DU
DU
AL
V
SS
C
WP
E
W
RB
D
E
F
NC
NC
NC
NC
R
CL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O3
NC
NC
G
H
J
NC
NC
NC
NC
I/O0
I/O1
I/O2
NC
V
DD
V
I/O5
I/O6
I/O7
DD
V
K
L
I/O4
V
SS
SS
DU
DU
DU
DU
DU
DU
DU
DU
M
AI13103
1. Available only for NAND01GR3B2B and NAND02GR3B2C 8-bit devices.
12/62
NAND01G-B2B, NAND02G-B2C
Memory array organization
2
Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series.
The memory array is organized in blocks where each block contains 64 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store Error correction Codes, software
flags or Bad Block identification.
In x8 devices the pages are split into a 2048 Byte main area and a spare area of 64 Bytes.
In the x16 devices the pages are split into a 1,024 Word main area and a 32 Word spare
area. Refer to Figure 5: Memory Array Organization.
2.1
Bad blocks
The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is
blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional
Bad Blocks may develop during the lifetime of the device.
The Bad Block Information is written prior to shipping (refer to Section 8.1: Bad Block
Management for more details).
Table 4: Valid Blocks shows the minimum number of valid blocks in each device. The values
shown include both the Bad Blocks that are present when the device is shipped and the Bad
Blocks that could develop later on.
These blocks need to be managed using Bad Blocks Management, Block Replacement or
Error Correction Codes (refer to Section 8: Software algorithms).
Table 4.
Valid Blocks
Density of Device
Min
Max
2 Gbits
1 Gbit
2008
1004
2048
1024
13/62
Memory array organization
NAND01G-B2B, NAND02G-B2C
Figure 5.
Memory Array Organization
x8 DEVICES
x16 DEVICES
Block = 64 Pages
Block = 64 Pages
Page = 2112 Bytes (2,048 + 64)
Page = 1056 Words (1024 + 32)
Main Area
Main Area
Block
Page
Block
Page
8 bits
16 bits
2048 Bytes
1024 Words
64
Bytes
32
Words
Page Buffer, 1056 Words
32
Page Buffer, 2112 Bytes
64
1,024 Words
Words
2,048 Bytes
16 bits
Bytes
8 bits
AI09854
14/62
NAND01G-B2B, NAND02G-B2C
Signals description
3
Signals description
See Figure 2: Logic Diagram, and Table 3: Signal Names, for a brief overview of the signals
connected to this device.
3.1
Inputs/Outputs (I/O0-I/O7)
Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read
operation or input a command or data during a Write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
Inputs/Outputs (I/O8-I/O15)
Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a Read operation or input data during a Write operation. Command and Address
Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
3.4
3.5
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the Address inputs in the Command
Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the Command inputs in the Command
Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is low, V , the device is selected. If Chip Enable goes
IL
high, v , while the device is busy, the device remains selected and does not go into standby
IH
mode.
3.6
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during Read operations. Data
is valid t
after the falling edge of R. The falling edge of R also increments the internal
RLQV
column address counter by one.
15/62
Signals description
NAND01G-B2B, NAND02G-B2C
3.7
Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, Input Address and
Data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10µs (min) is required before the
Command Interface is ready to accept a command. It is recommended to keep Write Enable
high during the recovery time.
3.8
3.9
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, V , the device does not accept any
program or erase operations.
IL
It is recommended to keep the Write Protect pin Low, V , during power-up and power-down.
IL
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
Controller is currently active. When Ready/Busy is Low, V , a read, program or erase
OL
operation is in progress. When the operation completes Ready/Busy goes High, V
.
OH
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
Refer to the Section 11.1: Ready/Busy Signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.10
VDD Supply Voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V is below V
(see
LKO
DD
Table 22 and Table 23) to protect the device from any involuntary program/erase during
power-transitions.
Each device in a system should have V decoupled with a 0.1µF capacitor. The PCB track
DD
widths should be sufficient to carry the required program and erase currents.
3.11
VSS Ground
Ground, V
ground.
is the reference for the power supply. It must be connected to the system
SS,
16/62
NAND01G-B2B, NAND02G-B2C
Bus operations
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus Operations, for a summary.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 19 and Table 24 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory addresses. Four bus cycles are
required to input the addresses for 1Gb devices whereas five bus cycles are required for the
2Gb device (refer to Table 6 and Table 7, Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 20 and Table 24 for details of the timings requirements.
4.3
4.4
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 21 and Table 24 and Table 25 for details of the timings requirements.
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status
Register, the lock status, the Electronic Signature and the Unique Identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low. The data is output sequentially using the Read Enable
signal.
See Figure 22 and Table 25 for details of the timings requirements.
17/62
Bus operations
NAND01G-B2B, NAND02G-B2C
4.5
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
Bus Operations
Bus Operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
Command Input
Address Input
Data Input
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIH Rising
VIH Rising
VIH Rising
X(2)
X
Command
Address
X
X
VIH
Data Input
Data Input
Fallin
VIH
g
Data Output
Write Protect
Standby
VIL
X
VIL
X
VIL
X
X
Data Output
Data Output
X
X
X
X
VIL
X
X
X
X
VIL/VD
VIH
X
X
D
1. Only for x16 devices.
2. WP must be VIH when issuing a program or erase command.
Table 6.
Address Insertion, x8 Devices
Bus Cycle(1)
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
2nd
3rd
A7
VIL
A6
VIL
A5
VIL
A4
VIL
A3
A11
A15
A23
VIL
A2
A10
A14
A22
VIL
A1
A9
A0
A8
A19
A27
VIL
A18
A26
VIL
A17
A25
VIL
A16
A24
VIL
A13
A21
VIL
A12
A20
A28
4th
5th(2)
1. Any additional address input cycles will be ignored.
2. The fifth cycle is valid for 2Gb devices. A28 is for 2Gb devices only.
18/62
NAND01G-B2B, NAND02G-B2C
Bus operations
Table 7.
Address Insertion, x16 Devices
I/O8-
Bus
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Cycle(1)
I/O15
1st
2nd
3rd
X
X
X
X
X
A7
VIL
A6
VIL
A5
VIL
A4
VIL
A3
VIL
A2
A10
A13
A21
VIL
A1
A9
A0
A8
A18
A26
VIL
A17
A25
VIL
A16
A24
VIL
A15
A23
VIL
A14
A22
VIL
A12
A20
VIL
A11
A19
A27
4th
5th(2)
1. Any additional address input cycles will be ignored.
2. The fifth cycle is valid for 2Gb devices. A27 is for 2Gb devices only.
Table 8.
Address Definitions, x8
Address
Definition
A0 - A11
A12 - A17
A18 - A27
A18 - A28
Column Address
Page Address
Block Address
Block Address
1Gb device
2Gb device
Table 9.
Address Definitions, x16
Address
Definition
A0 - A10
A11 - A16
A17 - A26
A17 - A27
Column Address
Page Address
Block Address
Block Address
1Gb device
2Gb device
19/62
Command Set
NAND01G-B2B, NAND02G-B2C
5
Command Set
All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is high. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The Commands are summarized in Table 10: Commands.
Table 10. Commands
Bus Write Operations(1)
Commands
accepted
during
Command
1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE
busy
Read
00h
05h
00h
34h
30h
E0h
31h
–
–
–
–
–
–
–
–
–
Random Data Output
Cache Read
Exit Cache Read
Yes(2)
Page Program
80h
10h
–
–
(Sequential Input default)
Random Data Input
Copy Back Program
Cache Program
Block Erase
85h
00h
80h
60h
FFh
90h
70h
–
35h
15h
D0h
–
–
85h
–
–
10h
–
–
–
Reset
–
–
Yes
Yes
Read Electronic Signature
Read Status Register
–
–
–
–
–
–
1. The bus cycles are only shown for issuing the codes. The cycles required to input the
addresses or input/output data are not shown.
2. Only during Cache Read busy.
20/62
NAND01G-B2B, NAND02G-B2C
Device operations
6
Device operations
The following section gives the details of the device operations.
6.1
Read Memory Array
At Power-Up the device defaults to Read mode. To enter Read mode from another mode the
Read command must be issued, see Table 10: Commands.
Once a Read command is issued two types of operations are available: Random Read and
Page Read.
6.1.1
6.1.2
Random Read
Each time the Read command is issued the first read is Random Read.
Page Read
After the first Random Read access, the page data (2112 Bytes or 1056 Words) is
transferred to the Page Buffer in a time of t
(refer to Table 25 for value). Once the
WHBH
transfer is complete the Ready/Busy signal goes High. The data can then be read out
sequentially (from selected column address to last column address) by pulsing the Read
Enable signal.
The device can output random data in a page, instead of the consecutive sequential data, by
issuing a Random Data Output command.
The Random Data Output command can be used to skip some data during a sequential
data output.
The sequential operation can be resumed by changing the column address of the next data
to be output, to the address which follows the Random Data Output command.
The Random Data Output command can be issued as many times as required within a
page.
The Random Data Output command is not accepted during Cache Read operations.
21/62
Device operations
NAND01G-B2B, NAND02G-B2C
Figure 6.
Read Operations
CL
E
W
AL
R
tBLBH1
30h
RB
I/O
Address Input
00h
Data Output (sequentially)
Command
Code
Command
Code
Busy
ai08657b
1. Highest address depends on device density.
22/62
NAND01G-B2B, NAND02G-B2C
Device operations
Figure 7.
Random Data Output During Sequential Data Output
tBLBH1
(Read Busy time)
RB
Busy
R
Address
Address
Inputs
30h
E0h
I/O
00h
05h
Data Output
Data Output
Inputs
Cmd
Cmd
Cmd
Cmd
Code
Code
Code
Code
5 Add cycles
2Add cycles
Row Add 1,2,3 Col Add 1,2
Col Add 1,2
Spare
Area
Spare
Area
Main Area
Main Area
ai08658
23/62
Device operations
NAND01G-B2B, NAND02G-B2C
6.2
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.
An Cache Read operation consists of three steps (see Table 10: Commands):
1. One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)
2. Four or Five (refer to Table 6 and Table 7) bus cycles are then required to input the
Start Address
3. One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.
The Start Address must be at the beginning of a page (Column Address = 00h, see Table 8
and Table 9). This allows the data to be output uninterrupted after the latency time (t
see Figure 8
),
BLBH1
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the Cache Read operation has started, the Status Register can be read using the
Read Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register
is ready to download new data.
To exit the Cache Read operation an Exit Cache Read command must be issued (see
Table 10).
If the Exit Cache Read command is issued while the device is internally reading page n+1,
pages n and n+1 will not be output.
Figure 8.
Cache Read Operation
tBLBH1
tBLBH4
(Read Busy time)
RB
tRHRL2
tRHRL2
R
Busy
Address
Inputs
last page
34h
I/O
31h
00h
1st page
2nd page 3rd page
Block N
Exit
Cache
Read
Code
Read
Setup
Code
Cache
Read
Confirm
Code
Data Output
ai13104
24/62
NAND01G-B2B, NAND02G-B2C
Device operations
6.3
Page Program
The Page Program operation is the standard operation to program data to the memory
array. Generally, the page is programmed sequentially, however the device does support
Random Input within a page. It is recommended to address pages sequentially within a
given block.
The memory array is programmed by page, however partial page programming is allowed
where any number of Bytes (1 to 2112) or Words (1 to 1056) can be programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is four. After exceeding this a Block Erase command must be issued before any further
program operations can take place in that page.
6.3.1
Sequential Input
To input data sequentially the addresses must be sequential and remain in one block.
For Sequential Input each Page Program operation consists of five steps (see Figure 9):
1. one bus cycle is required to setup the Page Program (Sequential Input) command (see
Table 10)
2. four or five bus cycles are then required to input the program address (refer to Table 6
and Table 7)
3. the data is then loaded into the Data Registers
4. one bus cycle is required to issue the Page Program confirm command to start the
P/E/R Controller. The P/E/R will only start if the data has been loaded in step 3.
5. the P/E/R Controller then programs the data into the array.
6.3.2
Random Data Input in a page
During a Sequential Input operation, the next sequential address to be programmed can be
replaced by a random address, by issuing a Random Data Input command. The following
two steps are required to issue the command:
1. one bus cycle is required to setup the Random Data Input command (see Table 10)
2. two bus cycles are then required to input the new column address (refer to Table 6)
Random Data Input can be repeated as often as required in any given page.
Once the program operation has started the Status Register can be read using the Read
Status Register command. During program operations the Status Register will only flag
errors for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands will be
accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in Read Status Register mode until another valid command is written to
the Command Interface.
25/62
Device operations
NAND01G-B2B, NAND02G-B2C
Figure 9.
Page Program Operation
tBLBH2
(Program Busy time)
RB
Busy
I/O
Data Input
10h
Address Inputs
80h
70h
SR0
Confirm
Code
Read Status Register
Page Program
Setup Code
ai08659
Figure 10. Random Data Input During Sequential Data Input
tBLBH2
(Program Busy time)
RB
I/O
Busy
Address
Inputs
Address
Inputs
80h
85h
10h
Data Intput
Data Input
70h
SR0
Cmd
Code
Cmd
Confirm
Code
Read Status Register
Code 2 Add cycles
5 Add cycles
Col Add 1,2
Row Add 1,2,3 Col Add 1,2
Spare
Area
Spare
Area
Main Area
Main Area
ai08664
26/62
NAND01G-B2B, NAND02G-B2C
Device operations
6.4
Copy Back Program
The Copy Back Program operation is used to copy the data stored in one page and
reprogram it in another page.
The Copy Back Program operation does not require external memory and so the operation
is faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the Copy Back Program operation fails an error is signalled in the Status Register.
However as the standard external ECC cannot be used with the Copy Back Program
operation bit error due to charge loss cannot be detected. For this reason it is recommended
to limit the number of Copy Back Program operations on the same data and or to improve
the performance of the ECC.
The Copy Back Program operation requires four steps:
1. The first step reads the source page. The operation copies all 1056 Words/ 2112 Bytes
from the page into the Data Buffer. It requires:
–
–
–
one bus write cycle to setup the command
4 or 5 bus write cycles to input the source page address (see Table 6 and Table 7)
one bus write cycle to issue the confirm command code
2. When the device returns to the ready state (Ready/Busy High), the next bus write cycle
of the command is given with the 4 or 5 bus cycles to input the target page address
(see Table 6 and Table 7). Refer to Table 11 for the addresses that must be the same
for the Source and Target pages.
3. Then the confirm command is issued to start the P/E/R Controller.
To see the Data Input cycle for modifying the source page and an example of the Copy Back
Program operation refer to Figure 11.
A data input cycle to modify a portion or a multiple distant portion of the source page, is
shown in Figure 12.
Table 11. Copy Back Program x8 Addresses
Density
Same Address for Source and Target Pages
1 Gbit
2 Gbit
no constraint
A28
Table 12. Copy Back Program x16 Addresses
Density Same Address for Source and Target Pages
1 Gbit
2 Gbit
no constraint
A27
27/62
Device operations
NAND01G-B2B, NAND02G-B2C
Figure 11. Copy Back Program
Source
Target
Add Inputs
I/O
10h
70h
SR0
35h
85h
00h
Add Inputs
Read
Code
Copy Back
Code
Read Status Register
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai09858b
1. Copy back program is only permitted between odd address pages or even address pages.
Figure 12. Page Copy Back Program with Random Data Input
2 Cycle
Add Inputs
Target
Add Inputs
Source
Add Inputs
I/O
35h
SR0
00h
85h
Data 85h
Data 10h
70h
Read
Code
Copy Back
Code
Unlimited number of repetitions
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai11001
28/62
NAND01G-B2B, NAND02G-B2C
Device operations
6.5
Cache Program
The Cache Program operation is used to improve the programming throughput by
programming data using the Cache Register. The Cache Program operation can only be
used within one block. The Cache Register allows new data to be input while the previous
data that was transferred to the Page Buffer is programmed into the memory array.
The following sequence is required to issue a Cache Program operation (refer to Figure 13):
1. First of all the program setup command is issued: one bus cycle to issue the program
setup command then 4 or 5 bus write cycles to input the address (see Table 6 and
Table 7). The data is then input (up to 2112 Bytes/ 1056 Words) and loaded into the
Cache Register.
2. One bus cycle is required to issue the confirm command to start the P/E/R Controller.
3. The P/E/R Controller then transfers the data to the Page Buffer. During this the device
is busy for a time of t
.
WHBH2
4. Once the data is loaded into the Page Buffer the P/E/R Controller programs the data
into the memory array. As soon as the Cache Registers are empty (after t ) a new
WHBH2
Cache program command can be issued, while the internal programming is still
executing.
Once the program operation has started the Status Register can be read using the Read
Status Register command. During Cache Program operations SR5 can be read to find out
whether the internal programming is ongoing (SR5 = ‘0’) or has completed (SR5 = ‘1’) while
SR6 indicates whether the Cache Register is ready to accept new data. If any errors have
been detected on the previous page (Page N-1), the Cache Program Error Bit SR1 will be set
to ‘1', while if the error has been detected on Page N the Error Bit SR0 will be set to '1’.
When the next page (Page N) of data is input with the Cache Program command, t
is
WHBH2
affected by the pending internal programming. The data will only be transferred from the
Cache Register to the Page Buffer when the pending program cycle is finished and the Page
Buffer is available.
If the system monitors the progress of the operation using only the Ready/Busy signal, the
last page of data must be programmed with the Page Program confirm command (10h).
If the Cache Program confirm command (15h) is used instead, Status Register bit SR5 must
be polled to find out if the last programming is finished before starting any other operations.
Figure 13. Cache Program Operation
tBLBH5
tBLBH5
tCACHEPG
(Cache Busy time)
RB
Busy
Busy
10h
Busy
Address Data
Inputs Inputs
Address Data
Inputs Inputs
Address Data
I/O
80h
15h
80h
15h
80h
70h SR0
Inputs
Inputs
Cache Program
Confirm Code
Page
Program
Confirm Code
Read Status
Register
Page
Program
Code
Cache
Page
Program Program
Code
Code
First Page
Second Page
Last Page
(can be repeated up to 63 times)
ai08672
1. Up to 64 pages can be programmed in one Cache Program operation.
2. tCACHEPG is the program time for the last page + the program time for the (last − 1)th page − (Program command cycle time
+ Last page data loading time).
29/62
Device operations
NAND01G-B2B, NAND02G-B2C
6.6
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to Figure 14):
1. One bus cycle is required to setup the Block Erase command. Only addresses A18-
A28 (x8) or A17-A27 (x16) are used, the other address inputs are ignored.
2. two or three bus cycles are then required to load the address of the block to be erased.
Refer to Table 8 and Table 9 for the block addresses of each device.
3. one bus cycle is required to issue the Block Erase confirm command to start the P/E/R
Controller.
The operation is initiated on the rising edge of write Enable, W, after the confirm command
is issued. The P/E/R Controller handles Block Erase and implements the verify process.
During the Block Erase operation, only the Read Status Register and Reset commands will
be accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Figure 14. Block Erase Operation
tBLBH3
(Erase Busy time)
RB
Busy
Block Address
Inputs
I/O
60h
D0h
70h
SR0
Confirm
Code
Read Status Register
Block Erase
Setup Code
ai07593
6.7
Reset
The Reset command is used to reset the Command Interface and Status Register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for t
after the Reset command is issued. The value
BLBH4
of t
depends on the operation that the device was performing when the command was
BLBH4
issued, refer to Table 25: AC Characteristics for Operations for the values.
30/62
NAND01G-B2B, NAND02G-B2C
Device operations
6.8
Read Status Register
The device contains a Status Register which provides information on the current or previous
Program or Erase operation. The various bits in the Status Register convey information and
errors on the operation.
The Status Register is read by issuing the Read Status Register command. The Status
Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the Status
Register.
After the Read Status Register command has been issued, the device remains in Read
Status Register mode until another command is issued. Therefore if a Read Status Register
command is issued during a Random Read cycle a new Read command must be issued to
continue with a Page Read operation.
The Status Register bits are summarized in Table 13: Status Register Bits,. Refer to
Table 13 in conjunction with the following text descriptions.
6.8.1
6.8.2
Write Protection Bit (SR7)
The Write Protection bit can be used to identify if the device is protected or not. If the Write
Protection bit is set to ‘1’ the device is not protected and program or erase operations are
allowed. If the Write Protection bit is set to ‘0’ the device is protected and program or erase
operations are not allowed.
P/E/R Controller and Cache Ready/Busy Bit (SR6)
Status Register bit SR6 has two different functions depending on the current operation.
During Cache Program operations SR6 acts as a Cache Program Ready/Busy bit, which
indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0',
the Cache Register is busy and when SR6 is set to '1', the Cache Register is ready to
accept new data.
During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the
P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R
Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive
(device is ready).
6.8.3
P/E/R Controller Bit (SR5)
The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or
inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R Controller is inactive (device is ready).
31/62
Device operations
NAND01G-B2B, NAND02G-B2C
6.8.4
Cache Program Error Bit (SR1)
The Cache Program Error bit can be used to identify if the previous page (page N-1) has
been successfully programmed or not in a Cache Program operation. SR1 is set to ’1’ when
the Cache Program operation has failed to program the previous page (page N-1) correctly.
If SR1 is set to ‘0’ the operation has completed successfully.
The Cache Program Error bit is only valid during Cache Program operations, during other
operations it is Don’t Care.
6.8.5
6.8.6
Error Bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The
Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the Error Bit is set to ‘0’ the operation has completed successfully. The Error
Bit SR0, in a Cache Program operation, indicates a failure on Page N.
SR4, SR3 and SR2 are Reserved
Table 13. Status Register Bits
Bit
Name
Logic Level
Definition
'1'
Not Protected
Protected
SR7
Write Protection
'0'
'1'
P/E/R C inactive, device ready
Program/ Erase/ Read
Controller
'0'
P/E/R C active, device busy
SR6
'1'
Cache Register ready (Cache operation only)
Cache Register busy (Cache operation only)
P/E/R C inactive, device ready
Cache Ready/Busy
'0'
'1'
Program/ Erase/ Read
Controller(1)
SR5
SR4, SR3, SR2
SR1
'0'
P/E/R C active, device busy
Reserved
Don’t Care
'1'
'0'
‘1’
‘0’
‘1’
‘0’
Page N-1 failed in Cache Program operation
Page N-1 programmed successfully
Error – operation failed
Cache Program Error(2)
Generic Error
No Error – operation successful
SR0
Page N failed in Cache Program operation
Page N programmed successfully
Cache Program Error
1. Only valid for Cache Program operations, for other operations it is same as SR6.
2. Only valid for Cache operations, for other operations it is Don’t Care.
32/62
NAND01G-B2B, NAND02G-B2C
Device operations
6.9
Read Electronic Signature
The device contains a Manufacturer Code and Device Code. To read these codes three steps
are required:
1. one Bus Write cycle to issue the Read Electronic Signature command (90h)
2. one Bus Write cycle to input the address (00h)
3. four Bus Read Cycles to sequentially output the data (as shown in Table 14: Electronic
Signature).
Table 14. Electronic Signature
Byte/Word 1
Byte/Word 2
Device code
Byte/Word 3
Byte/Word 4
Part Number
Manufacturer
Code
(see Table 15)
(see Table 16)
NAND01GR3B2B
NAND01GW3B2B
NAND01GR4B2B
NAND01GW4B2B
NAND02GR3B2C
NAND02GW3B2C
NAND02GR4B2C
NAND02GW42C
A1h
F1h
B1h
C1h
AAh
DAh
BAh
CAh
15h
1Dh
55h
5Dh
15h
1Dh
55h
5Dh
20h
0020h
20h
80h
0020h
Table 15. Electronic Signature Byte 3
I/O
Definition
Value
Description
0 0
0 1
1 0
1 1
1
2
4
8
I/O1-I/O0
Internal Chip number
0 0
0 1
1 0
1 1
2-level cell
4-level cell
8-level cell
16-level cell
I/O3-I/O2
I/O5-I/O4
Cell Type
0 0
0 1
1 0
1 1
1
2
4
8
Number of simultaneously
programmed pages
0
1
Not supported
Supported
Interleaved Programming
between multiple devices
I/O6
I/O7
0
1
Not supported
Supported
Cache Program
33/62
Device operations
NAND01G-B2B, NAND02G-B2C
Description
Table 16. Electronic Signature Byte/Word 4
I/O
Definition
Value
0 0
0 1
1 0
1 1
1KBytes
2KBytes
Reserved
Reserved
Page Size
I/O1-I/O0
I/O2
(Without Spare Area)
Spare Area Size
(Byte / 512 Byte)
0
1
8
16
0 0
0 1
1 0
1 1
50ns
30ns
Minimum sequential
access time
I/O7, I/O3
25ns
Reserved
0 0
0 1
1 0
1 1
64KBytes
128KBytes
256KBytes
Reserved
Block Size
I/O5-I/O4
I/O6
(Without Spare Area)
0
1
X8
Organization
X16
34/62
NAND01G-B2B, NAND02G-B2C
Data protection
7
Data protection
The device has hardware features to protect against program and erase operations.
It features a Write Protect, WP, pin, which can be used to protect the device against program
and erase operations. It is recommended to keep WP at V during power-up and power-
IL
down.
In addition, to protect the memory from any involuntary program/erase operations during
power-transitions, the device has an internal voltage detector which disables all functions
whenever V is below V
(see Table 22 and Table 23).
DD
LKO
35/62
Software algorithms
NAND01G-B2B, NAND02G-B2C
8
Software algorithms
This section gives information on the software algorithms that ST recommends to implement
to manage the Bad Blocks and extend the lifetime of the NAND device.
NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a
high voltage. Exposing the device to a high voltage for extended periods can cause the
oxide layer to be damaged. For this reason, the number of program and erase cycles is
limited (see Table 18 for value) and it is recommended to implement Garbage Collection, a
Wear-Leveling Algorithm and an Error Correction Code, to extend the number of program
and erase cycles and increase the data retention.
To help integrate a NAND memory into an application ST Microelectronics can provide a File
System OS Native reference software, which supports the basic commands of file
management.
Contact the nearest ST Microelectronics sales office for more details.
8.1
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A Bad Block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad
Block Information is written prior to shipping. Any block, where the 1st and 6th Bytes, or 1st
Word, in the spare area of the 1st page, does not contain FFh, is a Bad Block.
The Bad Block Information must be read before any erase is attempted as the Bad Block
Information may be erased. For the system to be able to recognize the Bad Blocks based on
the original information it is recommended to create a Bad Block table following the
flowchart shown in Figure 15.
8.2
NAND Flash memory failure modes
Over the lifetime of the device additional Bad Blocks may develop.
To implement a highly reliable system, all the possible failure modes must be considered:
■
Program/Erase failure: in this case the block has to be replaced by copying the data
to a valid block. These additional Bad Blocks can be identified as attempts to program
or erase them will give errors in the Status Register.
As the failure of a Page Program operation does not affect the data in other pages in
the same block, the block can be replaced by re-programming the current data and
copying the rest of the replaced block to an available valid block. The Copy Back
Program command can be used to copy the data to a valid block. See Section 6.4:
Copy Back Program for more details.
■
Read failure: in this case, ECC correction must be implemented. To efficiently use the
memory space, it is recommended to recover single-bit error in read by ECC, without
replacing the whole block.
Refer to Table 17 for the procedure to follow if an error occurs during an operation.
36/62
NAND01G-B2B, NAND02G-B2C
Software algorithms
Table 17. NAND Flash failure modes
Operation
Procedure
Erase
Program
Read
Block Replacement
Block Replacement or ECC
ECC
Figure 15. Bad Block Management Flowchart
START
Block Address =
Block 0
Increment
Block Address
Update
Bad Block table
Data
= FFh?
NO
NO
YES
Last
block?
YES
END
AI07588C
Figure 16. Garbage Collection
Old Area
New Area (After GC)
Valid
Page
Invalid
Page
Free
Page
(Erased)
AI07599B
37/62
Software algorithms
NAND01G-B2B, NAND02G-B2C
8.3
Garbage Collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a Garbage Collection algorithm. In a Garbage Collection software the valid
pages are copied into a free area and the block containing the invalid pages is erased (see
Figure 16).
8.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same
rate. Blocks with long-lived data do not endure as many write cycles as the blocks with
frequently-changed data.
The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
■
First Level Wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
■
Second Level Wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The Second Level Wear-leveling is triggered when the difference between the maximum
and the minimum number of write cycles per block reaches a specific threshold.
8.5
Error Correction Code
An Error Correction Code (ECC) can be implemented in the NAND Flash memories to
identify and correct errors in the data.
For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for
line parity plus 6 bits for column parity).
An ECC model is available in VHDL or Verilog. Contact the nearest ST Microelectronics
sales office for more details.
38/62
NAND01G-B2B, NAND02G-B2C
Software algorithms
Figure 17. Error Detection
New ECC generated
during read
XOR previous ECC
with new ECC
NO
NO
>1 bit
= zero?
All results
= zero?
YES
YES
22 bit data = 0
11 bit data = 1
1 bit data = 1
ECC Error
Correctable
Error
No Error
ai08332
8.6
Hardware Simulation models
8.6.1
Behavioral simulation models
Denali Software Corporation models are platform independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND Flash devices, and so allow
software to be developed before hardware.
8.6.2
IBIS simulations models
IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers
and electrical characteristics of Flash devices.
These models provide information such as AC characteristics, rise/fall times and package
mechanical data, all of which are measured or simulated at voltage and temperature ranges
wider than those allowed by target specifications.
IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.
39/62
Program and Erase Times and Endurance cycles
NAND01G-B2B, NAND02G-B2C
9
Program and Erase Times and Endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are
shown in Table 18.
Table 18. Program, Erase Times and Program Erase Endurance Cycles
NAND Flash
Parameters
Unit
Min
Typ
Max
Page Program Time
200
2
700
3
µs
ms
Block Erase Time
Program/Erase Cycles (per block)
Data Retention
100,000
10
cycles
years
40/62
NAND01G-B2B, NAND02G-B2C
Maximum rating
10
Maximum rating
Stressing the device above the ratings listed in Table 19: Absolute Maximum Ratings, may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 19. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
– 50
– 65
125
150
2.7
4.6
2.7
4.6
°C
°C
V
1.8V devices
3 V devices
1.8V devices
3 V devices
– 0.6
– 0.6
– 0.6
– 0.6
(1)
VIO
Input or Output Voltage
Supply Voltage
V
V
VDD
V
1. Minimum Voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2V for less than 20ns during transitions on I/O pins.
41/62
DC And AC parameters
NAND01G-B2B, NAND02G-B2C
11
DC And AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 20: Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 20. Operating and AC Measurement Conditions
NAND Flash
Parameter
Units
Min
Max
1.8V devices
3V devices
1.7
2.7
0
1.95
3.6
70
V
V
Supply Voltage (VDD
)
Grade 1
°C
°C
pF
pF
V
Ambient Temperature (TA)
Grade 6
–40
85
1.8V devices
3V devices (2.7 - 3.6V)
1.8V devices
3V devices
30
50
Load Capacitance (CL)
(1 TTL GATE and CL)
0
VDD
2.4
Input Pulses Voltages
0.4
V
Input and Output Timing Ref. Voltages
Output Circuit Resistor Rref
VDD/2
8.35
5
V
kΩ
ns
Input Rise and Fall Times
(1)
Table 21. Capacitance
Symbol
Parameter
Test Condition
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0V
10
10
pF
Input/Output
CI/O
VIL = 0V
pF
Capacitance(2)
1.
TA = 25°C, f = 1 MHz. CIN and CI/O are not 100% tested
2. Input/output capacitances double in stacked devices
42/62
NAND01G-B2B, NAND02G-B2C
DC And AC parameters
Table 22. DC Characteristics, 1.8V Devices
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
tRLRL minimum
Sequential
Read
IDD1
-
8
15
mA
E=VIL, OUT = 0 mA
I
Operating
Current
IDD2
IDD3
Program
Erase
-
-
-
-
8
8
15
15
mA
mA
E=VDD-0.2,
WP=0/VDD
IDD5
Standby Current (CMOS)(1)
-
10
50
µA
ILI
ILO
Input Leakage Current(1)
Output Leakage Current(1)
Input High Voltage
VIN= 0 to VDDmax
-
-
-
±10
±10
µA
µA
V
VOUT= 0 to VDDmax
-
VIH
-
VDD-0.4
-
VDD+0.3
0.4
VIL
Input Low Voltage
-
-0.3
-
V
VOH
VOL
Output High Voltage Level
Output Low Voltage Level
Output Low Current (RB)
IOH = -100µA
IOL = 100µA
VOL = 0.1V
VDD-0.1
-
-
V
-
-
0.1
V
IOL (RB)
3
4
mA
VDD Supply Voltage (Erase and
Program lockout)
VLKO
-
-
-
1.1
V
1. Leakage current and standby current double in stacked devices
Figure 18. Equivalent Testing Circuit for AC Characteristics Measurement
V
DD
2R
ref
NAND Flash
C
L
2R
ref
GND
GND
Ai11085
43/62
DC And AC parameters
NAND01G-B2B, NAND02G-B2C
Table 23. DC Characteristics, 3V Devices
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
tRLRL minimum
Sequential
Read
IDD1
-
10
20
mA
E=VIL, OUT = 0 mA
I
Operating
Current
IDD2
IDD3
Program
Erase
-
-
-
-
10
10
20
20
1
mA
mA
mA
I
Standby current (TTL)(1)
E=VIH, WP=0/VDD
DD4
E=VDD-0.2,
WP=0/VDD
IDD5
Standby Current (CMOS)(1)
-
10
50
µA
ILI
ILO
Input Leakage Current(1)
Output Leakage Current(1)
Input High Voltage
VIN= 0 to VDDmax
-
-
-
±10
±10
µA
µA
V
VOUT= 0 to VDDmax
-
0.8VDD
-0.3
2.4
-
VIH
-
-
VDD+0.3
0.2VDD
-
VIL
Input Low Voltage
-
-
V
VOH
VOL
Output High Voltage Level
Output Low Voltage Level
Output Low Current (RB)
IOH = -400µA
IOL = 2.1mA
VOL = 0.4V
-
V
-
0.4
V
IOL (RB)
8
10
mA
VDD Supply Voltage (Erase and
Program lockout)
VLKO
-
-
-
1.7
V
1. Leakage current and standby current double in stacked devices
44/62
NAND01G-B2B, NAND02G-B2C
DC And AC parameters
Table 24. AC Characteristics for Command, Address, Data Input
Alt.
1.8V
3V
Symbol
Parameter
Unit
Symbol
Devices Devices
tALLWH
tALHWH
Address Latch Low to Write Enable High
Address Latch High to Write Enable High
tALS
AL Setup time
CL Setup time
Min
Min
25
25
15
15
ns
Command Latch High to Write Enable
High
tCLHWH
tCLLWH
tCLS
ns
Command Latch Low to Write Enable
High
tDVWH
tELWH
tWHALH
tWHALL
tDS
tCS
Data Valid to Write Enable High
Data Setup time Min
20
35
15
20
ns
ns
Chip Enable Low to Write Enable High
E Setup time
Min
Min
Min
Write Enable High to Address Latch High AL Hold time
Write Enable High to Address Latch Low AL Hold time
Write Enable High to Command Latch
tALH
10
5
ns
tWHCLH
tWHCLL
High
tCLH
CL hold time
Min
10
5
ns
Write Enable High to Command Latch
Low
tWHDX
tWHEH
tDH
tCH
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Data Hold time
E Hold time
Min
Min
10
10
5
5
ns
ns
W High Hold
time
tWHWL
tWH
Write Enable High to Write Enable Low
Min
Min
15
10
ns
tWLWH
tWLWL
tWP
tWC
Write Enable Low to Write Enable High
Write Enable Low to Write Enable Low
W Pulse Width
25
45
15
30
ns
ns
Write Cycle time Min
45/62
DC And AC parameters
NAND01G-B2B, NAND02G-B2C
(1)
Table 25. AC Characteristics for Operations
Alt.
1.8V
3V
Symbol
Parameter
Unit
Symbol
Devices Devices
tALLRL1
tALLRL2
tBHRL
Read Electronic Signature
Read cycle
Min
Min
10
10
20
25
700
3
10
10
20
25
700
3
ns
ns
ns
µs
µs
ms
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
Address Latch Low to
Read Enable Low
tAR
tRR
Ready/Busy High to Read Enable Low
Read Busy time
Min
tBLBH1
tBLBH2
tBLBH3
tBLBH4
Max
Max
Max
Max
Typ
tPROG
tBERS
Program Busy time
Erase Busy time
Ready/Busy Low to
Ready/Busy High
Reset Busy time, during ready
5
5
3
3
tBLBH5
tCBSY
Cache Busy time
Max
Max
Max
Max
Min
700
5
700
5
Reset Busy time, during read
Reset Busy time, during program
Reset Busy time, during erase
Write Enable High to
Ready/Busy High
tWHBH1
tRST
10
500
10
0
10
500
10
0
tCLLRL
tDZRL
tEHQZ
tRHQZ
tCLR
tIR
tCHZ
tRHZ
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
Min
Chip Enable High to Output Hi-Z
Read Enable High to Output Hi-z
Max
Max
30
30
30
30
Last Address latched to Data Loading Time during
Program operations
(2)
tWHWH
tADL
Min
Min
100
100
100
100
ns
ns
tVHWH
tVLWH
(3)
tWW
Write Protection time
tRHRL2
tCRRH Read Enable High hold time during Cache Read operation Min
50
45
50
25
ns
ns
tELQV
tCEA
tREH
Chip Enable Low to Output Valid
Max
Min
Read Enable High to
tRHRL
Read Enable High Hold time
15
10
10
10
ns
ns
Read Enable Low
tEHQX
tRHQX
TOH
Chip Enable high or Read Enable high to Output Hold
Min
Read Enable Low to
Read Enable Pulse Width
Read Enable High
tRLRH
tRLRL
tRP
tRC
Min
Min
25
50
15
30
ns
ns
Read Enable Low to
Read Cycle time
Read Enable Low
Read Enable Access time
Read Enable Low to
Read ES Access time(4)
Output Valid
tRLQV
tREA
Max
Max
30
25
20
25
ns
µs
Write Enable High to
Read Busy time
tWHBH
tR
Ready/Busy High
tWHBL
tWHRL
tWB
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
Max
Min
100
60
100
60
ns
ns
tWHR
46/62
NAND01G-B2B, NAND02G-B2C
DC And AC parameters
1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figure 31, Figure 32 and
Figure 33.
2. tWHWH is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
3. During a Program/Erase Enable Operation, tWW is the delay from WP high to W High.
During a Program/Erase Disable Operation, tWW is the delay from WP Low to W High.
4. ES = Electronic Signature.
Figure 19. Command Latch AC waveforms
CL
tCLHWH
tWHCLL
(CL Setup time)
(CL Hold time)
tWHEH
(E Hold time)
tELWH
H(E Setup time)
E
tWLWH
W
tALLWH
tWHALH
(ALSetup time)
(AL Hold time)
AL
I/O
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
Command
ai13105
47/62
DC And AC parameters
NAND01G-B2B, NAND02G-B2C
Figure 20. Address Latch AC waveforms
tCLLWH
(CL Setup time)
CL
tWLWL
tELWH
(E Setup time)
tWLWL
tWLWL
tWLWL
E
tWLWH
tWLWH
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHWL
tWHWL
tWHWL
tWHALL
tALHWH
(AL Setup time)
tWHALL
tWHALL
tWHALL
(AL Hold time)
AL
I/O
tDVWH
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
tWHDX
(Data Hold time)
Adrress
cycle 3
Adrress
cycle 2
Adrress
cycle 4
Adrress
cycle 5
Adrress
cycle 1
ai13106
1. A fifth address cycle is required for 2Gb devices only.
Figure 21. Data Input Latch AC waveforms
tWHCLH
(CL Hold time)
CL
E
tWHEH
(E Hold time)
tALLWH
(ALSetup time)
tWLWL
AL
tWLWH
tWLWH
tWLWH
W
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
(Data Hold time)
Data In
Last
I/O
Data In 0
Data In 1
ai13107
1. Data In Last is 2112 in x8 devices and 1056 in x16 devices.
48/62
NAND01G-B2B, NAND02G-B2C
DC And AC parameters
Figure 22. Sequential Data Output after Read AC waveforms
tRLRL
(Read Cycle time)
E
tRHRL
(R High Holdtime)
tEHQZ
R
tRHQZ
tRHQZ
tRLQV
tRLQV
tRLQV
(R Accesstime)
I/O
RB
Data Out
Data Out
Data Out
tBHRL
ai08031
1. CL = Low, AL = Low, W = High.
Figure 23. Read Status Register AC waveform
tCLLRL
CL
tWHCLL
tWHEH
tCLHWH
E
tELWH
tWLWH
W
R
tELQV
tWHRL
tEHQZ
tDZRL
tWHDX
tDVWH
(Data Setup time)
tRLQV
tRHQZ
(Data Hold time)
Status Register
Output
I/O
70h
ai13108
49/62
DC And AC parameters
NAND01G-B2B, NAND02G-B2C
Figure 24. Read Electronic Signature AC waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
I/O
90h
00h
Byte1
Byte2
Byte3
00h
Byte4
Man.
code
Device
code
Read Electronic 1st Cycle
Signature
Command
see Note.1
Address
ai08667
1. Refer to Table 14 for the values of the Manufacturer and Device Codes, and to Table 15 and Table 16 for the information
contained in Byte 3 and 4.
50/62
NAND01G-B2B, NAND02G-B2C
DC And AC parameters
Figure 25. Page Read operation AC waveform
CL
E
tWLWL
tEHQZ
W
tWHBL
AL
tALLRL2
tWHBH
tRLRL
tRHQZ
(Read Cycle time)
R
tRLRH
tBLBH1
RB
Data
N
Data
N+1
Data
N+2
Data
Last
Add.N Add.N Add.N Add.N
cycle 1 cycle 2 cycle 3 cycle 4
Add.N
cycle 5
I/O
30h
00h
Data Output
from Address N to Last Byte or Word in Page
Command Address N Input
Code
Busy
ai13109b
1. A fifth address cycle is required for 2Gb devices only.
51/62
DC And AC parameters
NAND01G-B2B, NAND02G-B2C
Figure 26. Page Program AC waveform
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHBL
tWHWH
tBLBH2
(Program Busy time)
AL
R
Add.N Add.N
cycle 4 cycle 5
Add.N
Add.N
Add.N
cycle 3
I/O
RB
80h
Last
N
10h
70h
SR0
cycle 1 cycle 2
Confirm
Code
Page Program
Setup Code
Page
Program
Address Input
Data Input
Read Status Register
ai13110b
1. A fifth address cycle is required for 2Gb devices only.
52/62
NAND01G-B2B, NAND02G-B2C
DC And AC parameters
Figure 27. Block Erase AC waveform
CL
E
tWLWL
(Write Cycle time)
W
AL
R
tBLBH3
tWHBL
(Erase Busy time)
Add.
Add.
Add.
I/O
RB
70h
SR0
60h
D0h
cycle 1 cycle 2
cycle 3
Block Erase
Setup Command
Confirm
Code
Block Erase
Read Status Register
Block Address Input
ai08038b
1. Address cycle 3 is required for 2Gb devices only.
Figure 28. Reset AC waveform
W
AL
CL
R
I/O
RB
FFh
tBLBH4
(Reset Busy time)
ai08043
53/62
DC And AC parameters
NAND01G-B2B, NAND02G-B2C
Figure 29. Program/Erase Enable waveform
W
tVHWH
WP
RB
I/O
80h
10h
ai12477
Figure 30. Program/Erase Disable waveform
W
tVLWH
WP
High
RB
I/O
80h
10h
ai12478
11.1
Ready/Busy Signal electrical characteristics
Figure 32, Figure 31 and Figure 33 show the electrical characteristics for the Ready/Busy
signal. The value required for the resistor R can be calculated using the following equation:
P
(
–
)
V
V
DDmax
OLmax
+ I
R min= -------------------------------------------------------------
P
I
L
OL
So,
1.85V
R min(1.8V)= ---------------------------
P
+
3mA
I
L
3.2V
R min(3V)= ---------------------------
P
+
8mA
I
L
where I is the sum of the input currents of all the devices tied to the Ready/Busy signal. R
L
P
max is determined by the maximum value of t .
r
54/62
NAND01G-B2B, NAND02G-B2C
DC And AC parameters
Figure 31. Ready/Busy AC waveform
ready V
DD
V
OH
V
OL
busy
t
t
r
f
AI07564B
Figure 32. Ready/Busy Load Circuit
ibusy
R
P
V
DD
DEVICE
RB
Open Drain Output
V
SS
AI07563B
55/62
DC And AC parameters
NAND01G-B2B, NAND02G-B2C
Figure 33. Resistor value versus waveform timings for Ready/Busy signal
V
= 1.8V, C = 30pF
V = 3.3V, C = 100pF
DD L
DD
L
400
300
200
400
300
200
4
3
2
4
3
2
400
300
2.4
200
1.7
120
1.2
100
0
1
100
0
1
0.85
0.8
100
3.6
90
0.57
0.6
3.6
60
1.7
0.43
1.7
30
1.7
3.6
3.6
1.7
1
2
3
4
1
2
3
4
R
(KΩ)
R (KΩ)
P
P
t
t
r
ibusy
f
ai07565B
1. T = 25°C.
11.2
Data Protection
The ST NAND device is designed to guarantee Data Protection during Power Transitions.
A V detection circuit disables all NAND operations, if V is below the V threshold.
DD
DD
LKO
In the V range from V
to the lower limit of nominal range, the WP pin should be kept
DD
LKO
low (V ) to guarantee hardware protection during power transitions as shown in the below
IL
figure.
Figure 34. Data Protection
Nominal Range
V
DD
V
LKO
Locked
Locked
W
Ai11086
56/62
NAND01G-B2B, NAND02G-B2C
Package mechanical
12
Package mechanical
Figure 35. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 26. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
1.200
0.150
1.050
0.270
0.210
0.080
12.100
20.200
18.500
–
0.0472
0.0059
0.0413
0.0106
0.0083
0.0031
0.4764
0.7953
0.7283
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3°
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3°
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
5°
L1
α
0°
5°
0°
57/62
Package mechanical
NAND01G-B2B, NAND02G-B2C
Figure 36. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D
D2
D1
FD1
SD
FD
e
e
SE
E
E2 E1
ddd
BALL "A1"
FE1
FE
e
b
A
A2
A1
BGA-Z67
1. Drawing is not to scale
Table 27. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.05
0.0413
0.25
0.0098
0.70
0.50
9.60
0.0276
0.0197
0.3780
0.45
9.50
4.00
7.20
0.40
9.40
0.0177
0.3740
0.1575
0.2835
0.0157
0.3701
D
D1
D2
ddd
E
0.10
0.0039
0.4764
12.00
5.60
8.80
0.80
2.75
1.15
3.20
1.60
0.40
0.40
11.90
–
12.10
0.4724
0.2205
0.3465
0.0315
0.1083
0.0453
0.1260
0.0630
0.0157
0.0157
0.4685
E1
E2
e
–
–
–
FD
FD1
FE
FE1
SD
SE
58/62
NAND01G-B2B, NAND02G-B2C
Package mechanical
Figure 37. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D
D2
D1
FD1
FE
e
SE
b
E
E2 E1
ddd
BALL "A1"
FE1
A
A2
e
SD
FD
A1
BGA-Z75
1. Drawing is not to scale
Table 28. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
0.041
A
1.05
A1
A2
b
0.25
0.010
0.70
0.50
9.10
0.028
0.020
0.358
0.45
9.00
4.00
7.20
0.40
8.90
0.018
0.016
0.350
D
0.354
0.157
0.283
D1
D2
ddd
E
0.10
0.004
0.437
11.00
5.60
8.80
0.80
2.50
0.90
2.70
1.10
0.40
0.40
10.90
–
11.10
0.433
0.220
0.346
0.031
0.098
0.035
0.106
0.043
0.016
0.016
0.429
–
E1
E2
e
–
–
FD
FD1
FE
FE1
SD
SE
–
–
–
–
–
–
–
–
59/62
Part numbering
NAND01G-B2B, NAND02G-B2C
13
Part numbering
Table 29. Ordering Information Scheme
Example:
NAND02GR3B2C ZA 6
E
Device Type
NAND Flash Memory
Density
01G = 1Gb
02G = 2Gb
Operating Voltage
R = VDD = 1.7 to 1.95V
W = VDD = 2.7 to 3.6V
Bus Width
3 = x8
4 = x16(1)
Family Identifier
B = 2112 Bytes/ 1056 Word Page
Device Options
2 = Chip Enable Don't Care Enabled
Product Version
B= Second Version (1Gb devices)
C= Third Version (2Gb devices)
Package
N = TSOP48 12 x 20mm
ZA = VFBGA63 9.5 x 12 x 1mm, 0.8mm pitch(2)
ZA= VFBGA63 9 x 11 x 1mm, 0.8mm pitch(3)
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
E = Lead Free Package, Standard Packing
F = Lead Free Package, Tape & Reel Packing
1. x16 organization only available for MCP Products.
2. For NAND02G-B2C devices only.
3. For NAND01G-B2B devices only.
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
’1’. For further information on any aspect of this device, please contact your nearest ST
Sales Office.
60/62
NAND01G-B2B, NAND02G-B2C
Revision history
14
Revision history
Table 30. Document Revision History
Date
Version
Revision Details
18-May-2006
01-Jun-2006
0.1
1
First Issue
Datasheet status changed to Preliminary Data.
VFBGA63 9x11x1mm package added for NAND01G-B2B devices and
VFBGA63 9.5x12x1mm dedicated to NAND02G-B2C devices.
09-Jun-2006
23-Nov-2006
2
3
Note 2 below Commands removed.
Overview of Section 6.1: Read Memory Array updated. Paragraph
concerning Exit Cache Read command updated in Section 6.2: Cache
Read. Block Replacement section replaced by Section 8.2: NAND Flash
memory failure modes.
tWHALL added in Table 24: AC Characteristics for Command, Address,
Data Input.
RB waveform updated in Figure 25: Page Read operation AC waveform,
and CL waveform modified in Figure 26: Page Program AC waveform.
61/62
NAND01G-B2B, NAND02G-B2C
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相关型号：
NAND01GW3B2BZA6T
Flash, 128MX8, 35ns, PBGA63, 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, VFBGA-63
STMICROELECTR
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