PM8903ATR [STMICROELECTRONICS]
3 A step-down monolithic switching regulator;
| 型号： | PM8903ATR |
| 厂家： | 
ST |
| 描述： | 3 A step-down monolithic switching regulator |
| 文件： | 总33页 (文件大小：2532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PM8903A
3 A step-down monolithic switching regulator
Datasheet − production data
Features
■ Integrated 35 mΩ MOSFETs for high efficiency
■ 3 A continuous output current
■ 2.8 V to 6 V input voltage (VIN)
■ 2.9 V to 5.5 V supply voltage (VCC
)
■ Adjustable output voltage down to 0.6 V
■ 1% output voltage accuracy
■ 1.1 MHz switching frequency operation
■ PSKIP mode to optimize light load efficiency
■ Embedded bootstrap diode
VFQFPN16 (3 x 3 mm)
■ Thermally compensated loss-less current
The PM8903A features low-resistance integrated
nMOS and proprietary pulse-skipping mode for
optimum efficiency over all the loading range.
sense across HS and LS MOSFETs
■ OV/UV/OC and overtemperature protection
■ Internal soft-start and soft-stop
The voltage mode control loop allows the widest
range of output filters. Current sense is internally
thermally compensated for optimum precision.
■ Interleaving synchronization (up to 2 ICs)
■ Power Good output
The integrated 0.6 V reference allows the
regulation of output voltages with 1% accuracy
over temperature variations. Switching frequency
is typically set to 1.1 MHz and can be
programmed to 0.8 MHz or 1.0 MHz. Out of phase
synchronization allows the reduction of input RMS
current.
■ Shutdown function (< 15 µA quiescent current)
■ VFQFPN16 3 x 3 mm compact package
Applications
■ Subsystem power supply
■ CPU, DSP and FPGA power supplies
■ Distributed power supply
The PM8903A provides precise dual-threshold
overcurrent protection as well as
over/undervoltage and overtemperature
protection. PGOOD output easily provides real-
time information on the output voltage.
■ General DC-DC converters
Description
The PM8903A is available in VFQFPN16 3 x 3
mm.
The PM8903A is a high efficiency monolithic step-
down switching regulator designed to deliver up to
3 A continuous current. The IC operates from 2.8
V to 6 V input voltage (VIN).
Table 1.
Device summary
Order codes
Package
Packaging
PM8903A
VFQFPN16 (3 x 3 mm)
VFQFPN16 (3 x 3 mm)
Tube
PM8903ATR
Tape and reel
January 2013
Doc ID 024147 Rev 1
1/33
This is information on a product in full production.
www.st.com
33
Contents
PM8903A
Contents
1
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
4.2
4.3
4.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
5.2
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Startup and shutdown management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1
5.2.2
Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Soft-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3
Output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3.1
5.3.2
5.3.3
5.3.4
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Good (PGOOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4
5.5
5.6
5.7
5.8
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pulse-skipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multifunction pin PSKIP/MS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/33
Doc ID 024147 Rev 1
PM8903A
Contents
6.2
6.3
6.4
6.5
Output voltage setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
PM8903A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1
Detailed demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.1
7.1.2
7.1.3
7.1.4
Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Signal input (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Test points and jumper connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 024147 Rev 1
3/33
Typical application circuit and block diagram
PM8903A
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1.
Typical application circuit
1.2
Block diagram
Figure 2.
Block diagram
4/33
Doc ID 024147 Rev 1
PM8903A
Pin description and connection diagrams
2
Pin description and connection diagrams
Figure 3.
Pin connection (top view)
16 15 14 13
EN
SYNCH
PGOOD
BOOT
1
2
3
4
12
11
10
9
VCC
GND
FB
COMP
5
6
7
8
2.1
Pin description
Table 2.
Pin #
Pin description
Name
Function
Enable. Internally pulled up by 5 µA to VCC
.
1
EN
Force low to disable the device, set free or pull up above turn-on threshold to
enable the converter operations.
Synchronization pin.
According to PSKIP status, the IC sends the synchronization signal out of this
pin when master, while accepting a synchronization signal when slave.
Connect to the same SYNCH pin of a similar part when synchronizing ICs.
In case of single IC operation, leave floating.
2
SYNCH
Open drain output set free after SS has finished and pulled low when VOUT is
out of the PGOOD window or any protection is triggered.
Pull up to a voltage lower than VCC, if not used it can be left floating.
3
4
PGOOD
BOOT
Bootstrap pin.
It provides power supply for the floating high-side driver. Connect with 0.1 µF
to PHASE. See Figure 1.
Output inductor connection.
5 to 7
PHASE
The pins are connected to the embedded MOSFETs (high-side source and
low-side drain). Connect directly to output inductor. See Figure 1.
Pulse-skip and master/slave definition.
Connect with a resistor to GND or leave it floating to define:
Pulse-skip feature status;
Master/slave for synchronization;
Switching frequency.
8
PSKIP / MS
See Section 5.8 on page 17.
Doc ID 024147 Rev 1
5/33
Pin description and connection diagrams
PM8903A
Table 2.
Pin #
Pin description (continued)
Name
Function
Error amplifier output.
9
COMP
Connect with an (RF - CF) // CP to FB. See Figure 1
The device cannot be disabled by pulling low this pin.
Error amplifier inverting input.
10
FB
Connect with RFB or RFB // (RS - CS) to VSEN and with an (RF - CF) // CP to
COMP. A resistor ROS to GND sets the output voltage ratio. See Figure 1
All the internal references are referred to this pin. Connect to the PCB Signal
Ground.
11
12
GND
VCC
Device power supply.
Operative voltage is 2.9 V - 5.5 V. Filter with at least 1 µF MLCC vs. GND.
Power input voltage, connected to embedded high-side drain.
13, 14
15, 16
VIN
Supply range is from 2.8 V to 6 V. Bypass VIN pins to PGND pins close to the
IC package with high quality MLCC capacitors (at least 10 µF). See Figure 1.
Power ground connection, connected to embedded low-side MOSFET source.
Connect to PGND PCB plane. See Figure 1.
PGND
Thermal pad connects the silicon substrate and makes good thermal contact
with the PCB. Connect to the PCB PGND plane.
Thermal pad
6/33
Doc ID 024147 Rev 1
PM8903A
Thermal data
3
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
Thermal resistance junction-to-ambient
RthJA
30
°C/W
(Device soldered on standard demonstration board, see
Section 7 for details)
RthJC
TMAX
TSTG
TJ
Thermal resistance junction-to-case
Maximum junction temperature
Storage temperature range
12
°C/W
°C
150
-40 to 150
-25 to 125
°C
Junction temperature range
°C
Doc ID 024147 Rev 1
7/33
Electrical specifications
PM8903A
4
Electrical specifications
4.1
Absolute maximum ratings
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
VIN
to PGND, GND
to PGND, GND
-0.3 to 6
-0.3 to 7
V
V
to PGND, GND
to PHASE
-0.3 to 13
-0.3 to 6
VBOOT
V
V
to PGND, GND
-0.3 to 7
VPHASE
VPGOOD
to PGND, GND, VIN=6 V, t<100 nsec.
-1.7 to 7.5
to PGND, GND
-0.3 to 7
-0.3 to 6
V
V
V
VSYNCH, VEN to PGND, GND
All other pins to GND
-0.3 to 3.6
4.2
Recommended operating conditions
Table 5.
Symbol
Recommended operating conditions
Parameter
Min.
Typ.
Max.
Unit
VIN
Power supply voltage
Signal supply voltage
2.8
2.9
-
-
6
V
V
VCC
5.5
8/33
Doc ID 024147 Rev 1
PM8903A
Electrical specifications
4.3
Electrical characteristics
VIN = VCC = 3.3 V 5%, TJ = 0 °C to 125 °C, typical values at TJ = 25 °C, unless otherwise
specified.
Table 6.
Symbol
Electrical characteristics
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Supply current and undervoltage lockout
IIN
VIN supply current
VCC supply current
Switching, no inductor connected
Switching, no inductor connected
5
1
mA
mA
μA
V
ICC
ISHUTDOWN VCC + VIN supply current Shutdown, EN = 0 V
13
VIN turn-ON
VIN UVLO Hysteresis
Deglitching(1)
VIN rising
2.8
2.9
100
1
mV
μs
Rising and falling edge
VCC rising
VCC turn-ON
V
VCC UVLO Hysteresis
Deglitching(1)
100
1
mV
μs
Rising and falling edge
Oscillator
RPM=0 Ω / 24 kΩ / 180 kΩ / 240 kΩ
or PSKIP/MS pin floating
FSW
Main oscillator accuracy
0.99
0
1.1
1
1.21
100
MHz
ΔVOSC
d
PWM ramp amplitude(1)
Duty cycle(1)
V
%
ns
ns
TON-min
TOFF-min
Minimum on-time(1)
Minimum off-time(1)
80
80
Reference and error amplifier
Output voltage accuracy
DC gain(1)
VOUT = 0.6 V
CCOMP = 20 pF
-1
-
1
%
A0
GBWP
SR
120
dB
Gain-bandwidth product(1)
Slew-rate(1)
14
MHz
V/μs
5
Output power MOSFETS
HS drain-source on-
resistance
HS RDS-on
LS RDS-on
35
35
mΩ
mΩ
LS drain-source on-
resistance
Overcurrent protection
1st level overcurrent
IOC1
HS sourcing
HS sourcing
4.0
4.5
4.6
5.2
5.2
5.9
A
A
threshold
2nd level overcurrent
threshold (1)
IOC2
Doc ID 024147 Rev 1
9/33
Electrical specifications
PM8903A
Table 6.
Symbol
Electrical characteristics (continued)
Parameter Test conditions
Min.
Typ.
Max.
Unit
Over and undervoltage protection
FB rising
0.69
0.45
0.72
0.30
0.48
0.75
0.51
V
V
V
OVP
OVP threshold
UVP threshold
LS turns off, FB falling
FB falling
UVP
IFB
FB disconnection bias
current
Sourced from FB
100
nA
Overtemperature protection
Thermal shutdown
140
40
°C
°C
threshold (1)
OTP
Thermal shutdown
hysteresis (1)
PGOOD
Upper threshold
PGOOD
FB rising
0.69
0.45
0.72
0.48
0.75
0.51
0.4
V
V
V
Lower threshold
FB falling
VPGOODL
PGOOD voltage low
IPGOOD = -4 mA
ENABLE
Input logic high
Input logic low
Hysteresis
EN rising
EN falling
1.5
V
V
0.65
150
EN
mV
μs
Deglitching(1)
Rising and falling edge
3
SS
RPM = 0 Ω / 24 kΩ / 180 kΩ / 240 kΩ
or PSKIP/MS pin floating
TSS
Soft-start time
0.79
ms
1. Guaranteed by design, not subject to test.
10/33
Doc ID 024147 Rev 1
PM8903A
Electrical specifications
4.4
Typical operating characteristics
In the demonstration board, as described in Section 7.1, RPM = 0 Ω, VIN = VCC = 3.3 V,
VOUT=1V5, TJ = 25 °C, unless otherwise specified.
Figure 4.
Efficiency vs. output current -
IN = 3.3 V, RPM = 240 kΩ
Figure 5.
Efficiency vs. output current -
VIN = 5 V, RPM = 240 kΩ
V
Figure 6.
Load regulation - VIN = 3.3 V
Figure 7.
Load regulation - VIN = 5 V
Figure 8.
Line regulation - IOUT = 3 A
Doc ID 024147 Rev 1
11/33
Device description
PM8903A
5
Device description
The PM8903A is a high efficiency synchronous step-down monolithic switching regulator
capable of delivering up to 3 A continuous output current.
The power input voltage (VIN) can range from 2.8 V to 6 V, the signal input voltage (VCC) can
range from 2.9 V to 5.5 V.
Thanks to the 0.6 V internal reference and 0-100% duty cycle capability, the PM8903A can
precisely regulate output voltages ranging from 0.6 V to almost VIN (limited only by minimum
TOFF time). The output voltage accuracy is better than 1% over line, load and temperature.
The PM8903A embeds low RDS(on) (35 mΩ) N-channel MOSFETs for both HS (high-side)
and LS (low-side) and implements the proprietary pulse-skipping technology, therefore, the
PM8903A guarantees high efficiency over all the load range.
The voltage mode control loop with high bandwidth error amplifier and external
compensation enables a wide range of output filter configurations (including all MLCC
solutions) and fast response to load transient. The high-switching frequency (typically 1.1
MHz) and the small VFQFPN16 3x3 mm package allow very compact VR solutions.
The PM8903A features a full set of protections and output voltage monitoring:
●
Precise and accurate dual level overcurrent protection (internally compensated against
temperature variations)
●
●
●
●
Over and undervoltage protection
Overtemperature protection
Undervoltage lockout on both signal and power supply
Power Good open drain output easily provides real-time information about the output
voltage.
By simply connecting two PM8903As through the SYNCH pin, they can synchronize each
other with 180° phase shift switching interleaving, reducing RMS current absorption from the
input filter and preventing ‘beating frequency’ noise, therefore allowing the size and cost of
the input filter to be reduced.
A simple resistor connected from the PSKIP/MS pin to ground enables/disables pulse-
skipping technology and assigns master or slave status to the IC.
The dedicated ENABLE pin (EN) offers easy control on the power sequencing or to reset the
latched protection. Forcing the EN low, the device enters shutdown state and absorbs a total
quiescent current from VCC and VIN less than 15 µA.
5.1
Power section
The PM8903A integrates two low RDS(on) (35 mΩ) N-channel MOSFETs as low-side and
high-side switches, optimized for fast switching transition and high efficiency over all the load
range. The power stage is designed to deliver a continuous output current up to 3 A.
The HS MOSFET drain is connected to the VIN pins (power input), the LS MOSFET source
is connected to the PGND pins (power ground), and HS MOSFET source and LS MOSFET
drain are connected together and to the PHASE pins (see Figure 2). The driving section is
supplied from the VIN pins through an internal voltage regulator (VDRIVE) that assures the
proper driving voltage over all the VIN range.
12/33
Doc ID 024147 Rev 1
PM8903A
Device description
To properly supply the power section the following is advised:
●
Bypass VIN pins to PGND pins as close as possible to the IC package with high quality
MLCC capacitors (at least 10 µF).
●
Connect the bootstrap capacitor (typically a 100 nF ceramic capacitor rated to stand
V
IN voltage) from the BOOT pin to the PHASE pin to supply the HS driver.
Caution:
Do not connect an external bootstrap diode. The IC already integrates an active bootstrap
diode to charge the bootstrap capacitor, saving the cost of this external component.
The PM8903A embodies an anti-shoot-through and adaptive deadtime control to minimize
low-side body diode conduction time and consequently reduce power losses:
●
When the voltage at the PHASE pin drops (to check high-side MOSFET turn-off), the
LS MOSFET is suddenly switched on
●
When the gate driving voltage of LS drops (to check low-side MOSFET turn-off), the
HS MOSFET is suddenly switched on.
If the current flowing in the inductor is negative, voltage on the PHASE pin never drops. A
watchdog controller is implemented to allow the LS MOSFET to turn on even in this case,
allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative (if pulse-skipping is disabled).
5.2
Startup and shutdown management
The PM8903A monitors the supply voltage on both VCC and VIN pins. Once both VCC and
VIN voltages are above the respective UVLO (undervoltage lockout) thresholds and the EN
pin is high, the device waits for 0.5 ms (typ.) and then begins the soft-start.
Figure 9.
PM8903A soft-start sequence
VIN
2.8V
VIN UVLO
t
VCC
2.7V
VCC UVLO
t
EN
1.5V
EN THRESHOLD
t
VREF
0.6V
t
0.5 ms
T
=0.9 ms
SS
Doc ID 024147 Rev 1
13/33
Device description
PM8903A
The PM8903A implements the soft-start by gradually increasing the internal reference from
0 V to 0.6 V in a 1024 switching clock (0.79 ms typ.), linearly charging the output capacitors
to the final regulation voltage in closed loop regulation. The soft-start prevents high inrush
current from power supply rail.
5.2.1
Low-side-less startup
In order to avoid any kind of negative undershoot and dangerous return from the load during
startup, the PM8903A performs a special sequence in enabling the LS driver to switch:
during the soft-start phase, the LS driver results disabled (LS = OFF) until the first PWM
pulse occurs. This avoids the dangerous negative spike on the output voltage that may
happen if starting over a pre-biased output.
As long as the output voltage is biased to a voltage higher than the programmed one, the
control loop does not provide the HS pulse that enables LS. In this case LS is enabled at the
end of the soft-start time and, if the device is allowed to sink (PSKIP disabled), it discharges
the output to the final regulation value.
This particular feature of the device masks the LS turn-on only from the control loop point of
view: protection has higher priority and can turn on the LS MOSFET if an overvoltage event
is detected.
5.2.2
Soft-off
The PM8903A implements the soft-off sequence turning off both HS and LS MOSFETs and
connecting the integrated bleeding resistor (100 Ω) between the PHASE and PGND pin.
When small load currents are applied to the converter, the soft-off sequence allows the
discharging of the output voltage within a maximum time (TSO) that depends only on the
output capacitance value.
TSO = 5 ⋅ 100 ⋅ COUT
The PM8903A begins the soft-off sequence, and remains in a latched state, if one of the
following conditions occurs:
●
●
●
●
●
VCC voltage falls below UVLO threshold
OVP (overvoltage protection)
UVP (undervoltage protection)
OCP (overcurrent protection)
EN pin is pulled low.
Cycle EN or VCC to recover from latched state with a new soft-start sequence.
5.3
Output voltage monitoring and protection
The PM8903A monitors the output voltage status through the FB pin and compares the
voltage on this pin with the internal reference in order to provide over and undervoltage
protection as well as PGOOD signal.
5.3.1
14/33
Overvoltage protection
Overvoltage protection is active as soon as the device is enabled and both VCC and VIN
voltages are above the respective undervoltage lockout levels.
Doc ID 024147 Rev 1
PM8903A
Device description
The protection is triggered when the voltage sensed on the FB pin rises over the OVP
threshold (0.72 V typ.) and the device acts as follows:
●
HS MOSFET is suddenly forced OFF
●
LS MOSFET is turned on (to discharge the output and protect the load) until VFB drops
to 0.3 V, it is then turned off (to avoid negative spikes on the output voltage). If VFB
recrosses OVP rising threshold, LS is turned on again.
This protection state is latched, cycle EN or VCC to recover.
5.3.2
5.3.3
Undervoltage protection
Undervoltage protection is active from the end of soft-start.
If VFB falls below the UVP threshold (0.48 V typ.), undervoltage protection is triggered and
the device starts a soft-off sequence (see Section 5.2.2).
This protection state is latched, cycle EN, VCC or VIN to recover.
Feedback disconnection protection
In order to protect the load even if the FB pin is not connected to the PCB, a 100 nA current
is constantly sourced from the FB pin: if the FB pin is left floating, it is internally pulled high
triggering OVP protection and preventing VOUT from rising out of control.
Figure 10. FB disconnection
VOUT
RFB
FB
720mV
ROS
OVP
COMPARATOR
5.3.4
Power Good (PGOOD)
PGOOD is an open drain output, left floating when VOUT is in regulation at the programmed
voltage, at the end of soft-start.
PGOOD is forced low, to communicate that the output voltage is no longer in regulation, if
one of the following conditions is verified:
●
●
●
●
The voltage of the FB pin exits from the PGOOD window ( 20% of VREF
)
The device is disabled, EN is forced low
VCC voltage is below the UVLO threshold
Any protection is triggered (OVP, UVP, OCP, OTP).
Doc ID 024147 Rev 1
15/33
Device description
PM8903A
5.4
Overcurrent protection
Overcurrent protection is active as soon as the device is enabled and both VCC and VIN
voltages are above the respective UVLO levels.
The overcurrent function protects the converter from a shorted output or overload by
sensing the output current information across the integrated MOSFETs as follows:
●
During normal operation the output current information is monitored reading the current
flowing in the HS MOSFET
●
When the converter is working with an on-time lower than 130 ns (typ.) the current is
monitored reading the current flowing in the LS MOSFET.
If the monitored current information is bigger than the overcurrent thresholds, an overcurrent
event is detected.
For maximum safety and load protection, the PM8903A implements a dual level overcurrent
protection system.
●
First level threshold
During a switching cycle, if the monitored current information exceeds a 4.6 A (typ.)
threshold, first level overcurrent is detected: the HS MOSFET is turned off and the LS
MOSFET is turned on until the next cycle. If four first level OC events are detected in
four consecutive switching cycles, overcurrent protection is triggered.
●
Second level threshold
If the monitored current information exceeds the 5.2 A (typ.) threshold, overcurrent
protection is triggered immediately.
When overcurrent protection is triggered, the device suddenly turns off the HS and keeps
the LS turned on until the output current drops to 600 mA, then the device turns off both LS
and HS MOSFETs in a latched condition; cycle EN or VCC to recover.
5.5
Overtemperature protection
It is recommended that the device never exceeds the maximum allowable junction
temperature. This temperature increase is mainly caused by the total power dissipated from
the integrated power MOSFETs.
To avoid any damage to the device when reaching high temperature, the PM8903A
implements a thermal shutdown feature: when the junction temperature reaches 140 °C the
device turns off both MOSFETs.
When the junction temperature drops to 100 °C, the device restarts with a new soft-start
sequence.
5.6
Synchronization
Synchronization of two PM8903As is enabled simply connecting the SYNCH pins of the two
devices together. No synchronization is implemented if the SYNCH pin is left floating.
When synchronization is enabled, the first device must be configured as a master and the
second device must be configured as a slave. Connect a resistor between the PSKIP/MS
pin and ground, and select the resistor value according to Table 7, to program the IC to be
master or slave.
16/33
Doc ID 024147 Rev 1
PM8903A
Caution:
Device description
Do not connect together the synchronization pin of two master devices in order to avoid any
damage to the ICs.
When two PM8903As are synchronized together they act as follows:
●
Master mode
The SYNCH pin is configured as clock output. The device provides, on the SYNCH pin,
its internal switching clock information with a 180 ° time shifting.
●
Slave mode
The SYNCH pin is configured as clock input. The device uses the clock information
received on the SYNCH pin to synchronize its internal switching clock.
5.7
Pulse-skipping
The PM8903A implements an ST proprietary adaptive pulse-skipping algorithm which
requires no configuration by the user and is independent from application setup and
parasites.
The algorithm allows to strongly increase the overall system efficiency skipping some
switching cycles (so reducing the equivalent switching frequency of the converter) when the
load current is low.
In many applications, MLCCs (multi layer ceramic capacitors) are used as the input or
output filter, or both. MLCCs can produce audible noise if the switching frequency is in the
human hearing range. To avoid audible noise, the PM8903A pulse-skipping algorithm limits
the minimum equivalent switching frequency above the audio band.
Pulse-skipping mode is enabled connecting a resistor between the PSKIP/MS pin and
ground, and selects the resistor value according to Table 7.
5.8
Multifunction pin PSKIP/MS
With this pin it is possible to:
●
●
●
Enable/disable the pulse-skipping management
Assign to the IC master or slave status
Select the switching frequency.
Connect a resistor (RPM) between the PSKIP/MS pin and GND in order to set the IC
functionality according to Table 7.
Table 7.
PSKIP/MS pin configuration
RPM
Pulse-skipping
Synch mode
Switching frequency
0 Ω
Disabled
Enabled
Disabled
Disabled
Enabled
Slave
Slave
1.1 MHz
1.1 MHz
0.8 MHz
1.0 MHz
1.1 MHz
24 kΩ
56 kΩ
110 kΩ
180 kΩ
240 kΩ
Slave
Master
Master
Disabled
Master
1.1 MHz
(or pin floating)
Doc ID 024147 Rev 1
17/33
Application information
PM8903A
6
Application information
6.1
Compensation network
The PM8903A implements a voltage mode control loop (see Figure 11). The output voltage
is regulated to the internal reference (offset resistor between FB node and GND can be
neglected in control loop calculation).
Error amplifier output is compared with the oscillator sawtooth waveform to provide the
PWM signal to the driver section. The PWM signal is then transferred to the switching node
with VIN amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and VOUT. This function has a double pole at frequency FLC depending on the L-C output
filter and a zero at FESR depending on the output capacitor ESR. The DC gain of the
modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage
ΔVOSC
.
Figure 11. PM8903A control loop
Modulator
VIN
DRIVER
HS
ΔVOSC
OSC
L
DCR
VOUT
PHASE
DRIVER
LS
ESR
COUT
Output Filter
VREF
ERROR
AMPLIFIER
RF
CF
RFB
CP
RS
CS
Z
F
ROS
Z
FB
The compensation network closes the loop joining VOUT and EA output with a transfer
function ideally equal to -ZF/ZFB
.
The compensation goal is to close the control loop assuring high DC regulation accuracy,
good dynamic performance, and stability. To achieve this, the overall loop needs high DC
gain, high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to the compensation network transfer
function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for
18/33
Doc ID 024147 Rev 1
PM8903A
Application information
stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain
must cross the 0 dB axis with -20 dB/decade slope.
For example, Figure 12 shows an asymptotic bode plot of a type III compensation.
Figure 12. Example of type III compensation
The open loop converter singularities are:
1
FLC = ---------------------------------
2π L ⋅ COUT
1
FESR = -------------------------------------------
2π ⋅ COUT ⋅ ESR
The compensation network singularity frequencies are:
1
FZ1 = ------------------------------
2π ⋅ RF ⋅ CF
1
FZ2 = ----------------------------------------------------
2π ⋅ (RFB + RS) ⋅ CS
1
FP1 = -------------------------------------------------
CF ⋅ CP
CF + CP
⎛
⎞
--------------------
2π ⋅ RF ⋅
⎝
⎠
1
FP2 = ------------------------------
2π ⋅ RS ⋅ CS
Doc ID 024147 Rev 1
19/33
Application information
PM8903A
The following suggestions may be followed in order to place the poles and zeroes of the
compensation network.
●
Select a value for RFB in the range of some kΩ
●
Select RF in order to obtain the desired closed loop regulator bandwidth according to
the approximate formula:
F0dB ΔVOSC
FLC VIN_MAX
------------ ---------------------
⋅ RFB
RF
=
⋅
●
●
●
Select CF in order to place FZ1 below FLC (typically 0.1*FLC):
1
CF = ---------------------------------------------
2π ⋅ RF ⋅ 0.1 ⋅ FLC
Select CP in order to place FP1 at 0.5*FSW
:
1
CP = ------------------------------
π ⋅ RF ⋅ FSW
Select CS and RS in order to place FZ2 at FLC and FP2 at half of the switching
frequency:
1
CS = ------------------------------------
2π ⋅ RFB ⋅ FLC
1
RS = -------------------------------
π ⋅ CS ⋅ FSW
●
●
●
Check that compensation network gain is lower than open loop EA gain before F0dB
Check phase margin obtained (it should be greater than 45 °)
Repeat the whole procedure if necessary.
6.2
Output voltage setting
The PM8903A integrates a 0.6 V internal reference (VREF), with a total accuracy of 1%
over line, load, and temperature variations (excluding external resistor divider tolerance,
when present).
The output voltage can be easily programmed connecting ROS and RFB resistors as follows
(see also Figure 1 on page 4).
●
Connect pin FB to VOUT through RFB resistor
Connect pin FB to GND through ROS resistor.
●
Usually, the RFB resistor is selected in order to obtain the desired closed loop regulator
bandwidth (see Section 6.1 for details) and it is not changed when setting the output
voltage.
Therefore, the output voltage setting is easily achieved using the following formula to select
the value of the ROS resistor:
VREF
----------------------------------
⋅
ROS = RFB
V
OUT – VREF
20/33
Doc ID 024147 Rev 1
PM8903A
Application information
6.3
Inductor design
The inductance value is defined by a compromise between the dynamic response time, the
efficiency, the cost, and the size. The inductor must be calculated to maintain the ripple
current (ΔIL) between 20% and 30% of the maximum output current (typ.). The inductance
value can be calculated with the following relationship:
V
IN – VOUT VOUT
----------------------------- --------------
L =
⋅
FSW ⋅ ΔIL
VIN
where FSW is the switching frequency, VIN is the input voltage, and VOUT is the output
voltage.
Increasing the value of the inductance reduces the current ripple but, at the same time,
increases the converter response time to a dynamic load change. The response time is the
time required by the inductor to change its current from the initial to the final value. Until the
inductor finishes its charging time, the output current is supplied by the output capacitors.
Minimizing the response time can minimize the output capacitance required. If the
compensation network is well designed, during a load variation the device is able to set a
duty cycle value very different (0% or 100%) from the steady-state one. When this condition
is reached, the response time is limited by the time required to change the inductor current.
6.4
Output capacitors
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
the capacitive value of the output capacitors as follows:
ΔVOUT_ESR = ΔIL ⋅ ESR
1
--------------------------------------
ΔVOUT_C = ΔIL ⋅
8 ⋅ COUT ⋅ FSW
where ΔIL is the inductor current ripple. In particular, the expression that defines ΔVOUT_C
takes into consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
During a load variation, the output capacitor supplies the current to the load or absorbs the
current stored in the inductor until the converter reacts. In fact, even if the controller
immediately recognizes the load transient and sets the duty cycle at 100% or 0%, the
current slope is limited by the inductor value. The output voltage has a drop that, also in this
case, depends on the ESR and capacitive charge/discharge as follows:
ΔVOUT_ESR = ΔIOUT ⋅ ESR
L ⋅ ΔIOUT
2 ⋅ COUT ⋅ ΔVL
-------------------------------------
⋅
ΔVOUT_C = ΔIOUT
where ΔVL is the voltage applied to the inductor during the transient response
( DMAX ⋅ VIN – VOUT for the load appliance or VOUT for the load removal).
MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitance that does not minimize the voltage deviation during dynamic load variations.
Doc ID 024147 Rev 1
21/33
Application information
PM8903A
Electrolytic capacitors have a large capacitance to minimize voltage deviation during load
transients while they do not show the same ESR values as the MLCC, resulting then in
higher ripple voltages.
A mix between an electrolytic and MLCC capacitor can be used to minimize ripple as well as
reducing voltage deviation in dynamic mode.
The high bandwidth error amplifier of the PM8903A and external compensation enables a
wide range of output filter configurations (including all MLCC solutions) and fast transient
response.
6.5
Input capacitors
The input capacitor bank is designed considering, mainly, the input RMS current that
depends on the output deliverable current (IOUT) and the duty-cycle (D) for the regulation as
follows:
Irms = IOUT
⋅ D ⋅ (1 – D)
The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depend on the
input capacitor ESR and, in the worst case, are:
P = ESR ⋅ (IOUT ⁄ 2)2
22/33
Doc ID 024147 Rev 1
PM8903A
PM8903A demonstration board
7
PM8903A demonstration board
The PM8903A demonstration board realizes, in a four-layer PCB, a high efficiency
synchronous step-down monolithic switching converter capable of delivering up to 3 A
continuous output current.
The demonstration board shows the operation of the device in a general purpose
application. Two devices are present on the demonstration board and connected through the
SYNCH pin, also allowing the testing of the synchronization capability of the PM8903A. The
two devices are synchronized to each other with 180° phase shift switching interleaving,
reducing RMS current absorption from the input filter and preventing beating frequency
noise, therefore allowing a reduction in the size and cost of the input filter.
Figure 13. PM8903A demonstration board
The input voltage (VIN) can range from 2.8 V to 6 V and the supply voltage (VCC) can range
from 2.9 V to 5.5 V.
The output voltage is programmed to be 1.5 V but can be easily programmed, changing a
single resistor, from 0.6 V to almost VIN with a total accuracy better than 1% over line, load
and temperature.
A simple resistor connected from the PSKIP / MS pin to ground enables / disables pulse-
skipping technology and assigns, to the IC, master or slave status.
The dedicated dip switch SW1 allows the enabling / disabling of each device and offers easy
control on the power sequencing or to reset latched protection. Forcing EN low, the device
enters a shutdown state and absorbs a total quiescent current from VCC and VIN less than
15 µA.
Doc ID 024147 Rev 1
23/33
PM8903A demonstration board
PM8903A
7.1
Detailed demonstration board description
This section describes:
●
●
●
Demonstration board schematics, see Figure 14
Demonstration board layout, see Figure 15
Demonstration board BOM (bill of materials), see Table 8.
Furthermore, the following sub-sections detail how to configure and use the standard
demonstration board.
24/33
Doc ID 024147 Rev 1
PM8903A
PM8903A demonstration board
Figure 14. PM8903A demonstration board schematic
VIN1
VIN
VCC
JP1
VCC1
R1
VIN2
JP2
C15
C16
C11
R2
C1
VIN1
13, 14
4
VIN
BOOT
D1
R4
C2, C3
C4
R6
C5
PM8903A
15, 16, EP
R3
R5
PGND
EN
VOUT1
L1
EN1
5, 6, 7
PHASE
1
2
3
8
SYNCH
C6, C8, C9
Q1
PGOOD
PSKIP/MS
R8
C10
R10
R7
R9
C7
C12
R11
R13
C13 R12
R14
R15
R18
C14
R16
R17
MARGIN1
EN1 EN2
SW1
ON
VCC2
R19
ON
R20
C17
1
2
VIN2
13, 14
4
VIN
BOOT
D2
C18, C19 C20
R6
C5
PM8903A
15, 16, EP
R22
R21 R23
PGND
EN
VOUT2
L2
EN2
5, 6, 7
PHASE
1
2
3
8
SYNCH
C22, C23, C24
Q2
PGOOD
PSKIP/MS
R26
C26
R28
R25 R27 C25
C27
R29
R31
C28 R30
R32
R33
C29
R34
R35
MARGIN2
Doc ID 024147 Rev 1
25/33
PM8903A demonstration board
Figure 15. PM8903A demonstration board layout
PM8903A
TOP LAYER
INNER-1 LAYER
INNER-2 LAYER
BOTTOM LAYER
Table 8.
PM8903A demonstration board - bill of material
Reference
Alias
Value
Manufacturer P.N.
Package Supplier
Resistors
R1, R7, R9, R19,
R25, R27
NM
0603
R2, R20
R3, R21
R4, R22
R5, R23
R6, R24
R8, R26
R10
10 Ω
10 kΩ
1 kΩ
0603
0603
0603
0603
0603
0603
0603
0603
0603
RPGOOD(1,2)
560 kΩ
0 Ω
RBOOT(1,2)
RSNUBBER(1,2)
RPM(1)
NM
270 kΩ
100 Ω
680 Ω
R11, R29
R12, R30
RS(1,2)
RF(1,2)
R13, R17, R18,
R31, R35
0 Ω
0 Ω
0603
0603
R14, R32
RFB1(1,2)
26/33
Doc ID 024147 Rev 1
PM8903A
Table 8.
PM8903A demonstration board
PM8903A demonstration board - bill of material (continued)
Reference
Alias
Value
Manufacturer P.N.
Package Supplier
R15, R33
R16, R34
R28
RFB2(1,2)
ROS(1,2)
RPM(2)
3.3 kΩ
2.2 kΩ
0 Ω
0603
0603
0603
Capacitors
C1, C17
CVCC(1,2)
CVIN(1,2)
1 µF, X7R
0603
22 µF, X5R, 6.3 V, 10% -
MLCC
C2, C3, C18, C19
GRM21BR60J226ME
0805
MURATA
C4, C20
C5, C21
CVIN(1,2)
100 nF, X7R
100 nF, X7R
0603
0603
CBOOT(1,2)
C6, C8, C9, C22,
C23, C24
COUT(1,2)
10 µF X7R 6.3 V 10% - MLCC GRM21BR70J106KE
0805
MURATA
MURATA
C7, C25
C10, C26
C11
NM
0603
0603
CSNUBBER(1,2)
CVCC
NM
10 µF X7R 6.3 V 10% - MLCC GRM21BR70J106KE
0805
C12, C27
C13, C28
C14, C29
C15a, C16
C15
CS(1,2)
CF(1,2)
CP(1,2)
CIN
4.7 nF, X7R
22 nF, X7R
220 pF, X7R
NM
0603
0603
0603
Case D
T.H.M
CIN)
NM
Inductors
L1, L2
1.0 µH, 10.4 mΩ
SPM5030T-1R0M
TDK
Alternative inductors
L1, L2
1.2 µH, 35 mΩ
1.2 µH, 25 mΩ
H.DI0520-1R2
NEC
TDK
LTF5022T-1R2N4R2-LC
Active components
D1, D2
Q1, Q2
U1, U2
LED
2N7002
PM8903A
STM
STM
Doc ID 024147 Rev 1
27/33
PM8903A demonstration board
PM8903A
7.1.1
Power input (V )
IN
Connect a power supply to connectors J4(VIN) and J5(GND) on the demonstration board to
provide voltage on the power input pins of both devices. Input voltage can range from 2.8 V
to 6 V bus.
If the voltage is between 2.9 V and 5.5 V, it can also supply the signal input pins of both
devices (through the VCC pin). In this case, make sure that resistors R2/R20 are NM (not
mounted) and mount 0 Ω resistors on R1/R19 locations.
7.1.2
7.1.3
Signal input (V )
CC
The controller is usually supplied separately from the power stage through the VCC input
pins.
Connect a power supply to connector J2 (pin one is VC and pin two is GND) on the
demonstration board to provide voltage on the signal input pins of both devices. Supply
voltage can range from 2.9 V to 5.5 V.
Output (V
)
OUT
On the standard demonstration board, the output voltage is programmed to be 1.5 V, but it
can be easily changed mounting one of the values suggested in Table 9.
Select the ROS (R16/R34) resistor value with the following formula in order to program a
custom value for the output voltage of each device.
VREF
----------------------------------
⋅
ROS = RFB
V
OUT – VREF
where:
●
●
●
VOUT is the desiderated output voltage
VREF is the internal voltage reference (0.6 V)
RFB resistor, on the demonstration board, is the sum of two resistors (R14/R15 for
device U1 and R32/R33 for device U2) and has a total value of 3.3 kΩ.
Table 9.
Typical ROS resistors (R16/R34)
Programmed output voltage
Resistor value
0.6 V
0.8 V
1.0 V
1.2 V
1.5 V
1.8 V
2.5 V
NM
10 kΩ
4.9 kΩ
3.3 kΩ
2.2 kΩ
1.65 kΩ
1 kΩ
28/33
Doc ID 024147 Rev 1
PM8903A
PM8903A demonstration board
7.1.4
Test points and jumper connection
Use the following test points in order to measure the most important signals of the
PM8903A.
●
●
●
VCC1 / VCC2: monitor the supply voltages
VIN1 / VIN2: monitor the input voltages
V_OUT_S1 / V_OUT_S2: monitor the output voltages (use these test points to perform
efficiency load-line regulation measurements)
●
●
PGOOD1 / PGOOD2: (active high) monitor the regular functioning of the controllers
SYNCH1 / SYNCH2: these are usually shorted when two devices are synchronized
together.
Unplug jumpers JP1 /JP2 in order to remove the power input voltage from device U1, device
U2, or both. Provide power supply voltage to one device at a time when performing
efficiency tests.
Turn on Dip-Switch SW1 in order to disable device U1, device U2, or both.
Doc ID 024147 Rev 1
29/33
Package mechanical data
PM8903A
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 10. VFQFPN16 3 x 3 x 1.0 mm mechanical data
mm
Dim.
Min.
Typ.
Max.
A
A1
A2
A3
b
0.80
0.90
0.02
0.65
0.20
0.25
3.00
1.50
1.00
0.05
1.00
0.18
2.85
0.30
3.15
D
D1
D2
E
1.60
3.15
2.85
3.00
1.50
E1
E2
e
1.60
0.55
0.50
0.08
0.45
0.30
0.50
0.40
L
ddd
30/33
Doc ID 024147 Rev 1
PM8903A
Package mechanical data
Figure 16. Package dimensions
Doc ID 024147 Rev 1
31/33
Revision history
PM8903A
9
Revision history
Table 11. Document revision history
Date
Revision
Changes
11-Jan-2013
1
First release
32/33
Doc ID 024147 Rev 1
PM8903A
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
Doc ID 024147 Rev 1
33/33
相关型号：
©2020 ICPDF网 联系我们和版权申明