PSD4235F3V-20JI [STMICROELECTRONICS]
Flash In-System-Programmable Peripherals for 16-Bit MCUs; Flash在系统可编程外设的16位MCU型号: | PSD4235F3V-20JI |
厂家: | ST |
描述: | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
文件: | 总93页 (文件大小:498K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSD4135G2
Flash In-System-Programmable Peripherals
for 16-Bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY
■ 5 V±10% Single Supply Voltage:
Figure 1. Packages
■ Up to 4 Mbit of Primary Flash Memory (8
uniform sectors)
■ 256Kbit Secondary Flash Memory (4 uniform
sectors)
■ Up to 64 Kbit SRAM
■ Over 3,000 Gates of PLD: DPLD and CPLD
■ 52 Reconfigurable I/O ports
■ Enhanced JTAG Serial Port
■ Programmable power management
■ High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Erase/Write Cycles of PLD
TQFP80 (U)
January 2002
1/3
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4000 Series
PSD4135G2
Flash In-System-Programmable Peripherals for 16-Bit MCUs
Table of Contents
Introduction ........................................................................................................................................................................................1
In-System Programming (ISP) JTAG .......................................................................................................................................2
In-Application re-Programming (IAP) .......................................................................................................................................2
Key Features......................................................................................................................................................................................3
PSD4000 Family................................................................................................................................................................................3
Block Diagram....................................................................................................................................................................................4
Architectural Overview.......................................................................................................................................................................5
Memory ....................................................................................................................................................................................5
PLDs.........................................................................................................................................................................................5
I/O Ports ...................................................................................................................................................................................5
Microcontroller Bus Interface....................................................................................................................................................5
ISP via JTAG Port ....................................................................................................................................................................6
In-System Programming (ISP) .................................................................................................................................................6
In-Application re-Programming (IAP) .......................................................................................................................................6
Page Register...........................................................................................................................................................................6
Power Management Unit..........................................................................................................................................................6
Development System.........................................................................................................................................................................7
Pin Descriptions.................................................................................................................................................................................8
Register Description and Address Offset.........................................................................................................................................11
Register Bit Definition ......................................................................................................................................................................12
Functional Blocks.............................................................................................................................................................................15
Memory Blocks.......................................................................................................................................................................15
Main Flash and Secondary Flash Memory Description ...................................................................................................15
SRAM...............................................................................................................................................................................26
Memory Select Signals ....................................................................................................................................................26
Page Register ..................................................................................................................................................................29
Memory ID Registers .......................................................................................................................................................30
PLDs.......................................................................................................................................................................................31
Decode PLD (DPLD)........................................................................................................................................................33
General Purpose PLD (GPLD).........................................................................................................................................33
Microcontroller Bus Interface..................................................................................................................................................36
Interface to a Multiplexed Bus..........................................................................................................................................36
Interface to a Non-multiplexed Bus..................................................................................................................................36
Data Byte Enable Reference ...........................................................................................................................................38
Microcontroller Interface Examples..................................................................................................................................39
I/O Ports .................................................................................................................................................................................44
General Port Architecture ................................................................................................................................................44
Port Operating Modes......................................................................................................................................................44
Port Configuration Registers (PCRs)...............................................................................................................................48
Port Data Registers..........................................................................................................................................................49
Ports A, B and C – Functionality and Structure ...............................................................................................................50
Port D – Functionality and Structure................................................................................................................................51
Port E – Functionality and Structure ................................................................................................................................51
Port F – Functionality and Structure ................................................................................................................................52
Port G – Functionality and Structure................................................................................................................................52
i
PSD4000 Series
PSD4135G2
Flash In-System-Programmable Peripherals for 16-Bit MCUs
Table of Contents
Power Management ...............................................................................................................................................................53
Automatic Power Down (APD) Unit and Power Down Mode...........................................................................................53
Other Power Savings Options..........................................................................................................................................57
Reset and Power On Requirement..................................................................................................................................58
Programming In-Circuit using the JTAG-ISP Interface...........................................................................................................59
Standard JTAG Signals ...................................................................................................................................................60
JTAG Extensions .............................................................................................................................................................60
Security and Flash Memories Protection .........................................................................................................................60
Absolute Maximum Ratings .............................................................................................................................................................61
Operating Range..............................................................................................................................................................................61
Recommended Operating Conditions..............................................................................................................................................61
AC/DC Parameters ..........................................................................................................................................................................62
Example of Typical Power Calculation at Vcc = 5..0 V...........................................................................................................63
Example of Typical Power Calculation at Vcc = 5..0 V in Turbo Off Mode.............................................................................64
DC Characteristics (5 V ± 10% versions).........................................................................................................................................65
Microcontroller Interface – AC/DC Parameters (5 V ± 10% versions) .............................................................................................67
DC Characteristics (3.0 V to 3.6 V versions) ...................................................................................................................................71
Microcontroller Interface – AC/DC Parameters (3.0 V to 3.6 V versions).......................................................................................73
Timing Diagrams..............................................................................................................................................................................77
Pin Capacitance...............................................................................................................................................................................81
AC Testing Input/Output Waveforms ...............................................................................................................................................81
AC Testing Load Circuit...................................................................................................................................................................81
Programming ...................................................................................................................................................................................81
Pin Assignments ..............................................................................................................................................................................82
Package Information........................................................................................................................................................................83
Selector Guide .................................................................................................................................................................................85
Part Number Construction ...............................................................................................................................................................86
Ordering Information........................................................................................................................................................................86
Document Revisions........................................................................................................................................................................87
Worldwide Sales, Service and Technical Support ...........................................................................................................................88
ii
PSD4000 Series
PSD4135G2
Configurable Memory System on a Chip
for 16-Bit Microcontrollers
Preliminary Information
The PSD4000 series of Programmable Microcontroller (MCU) Peripherals brings
In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a
simple and flexible solution for embedded designs. PSD4000 devices combine many of the
peripheral functions found in MCU based applications:
1.0
Introduction
• 4 Mbit of Flash memory
• A secondary Flash memory for boot or data
• Over 3,000 gates of Flash programmable logic
• 64 Kbit SRAM
• Reconfigurable I/O ports
• Programmable power management.
1
PSD4000 Series
Preliminary Information
The PSD4135G2 device offers two methods to program PSD Flash memory while the PSD
is soldered to a circuit board.
1.0
Introduction
(Cont.)
❏ In-System Programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG-ISP interface is included on the PSD enabling the
entire device (both flash memories, the PLD, and all configuration) to be rapidly
programmed while soldered to the circuit board. This requires no MCU participation,
which means the PSD can be programmed anytime, even while completely blank.
The innovative JTAG interface to flash memories is an industry first, solving key
problems faced by designers and manufacturing houses, such as:
• First time programming – How do I get firmware into the flash the very first time?
JTAG is the answer, program the PSD while blank with no MCU involvement.
• Inventory build-up of pre-programmed devices – How do I maintain an accurate
count of pre-programmed flash memory and PLD devices based on customer
demand? How many and what version? JTAG is the answer, build your hardware
with blank PSDs soldered directly to the board and then custom program just before
they are shipped to customer. No more labels on chips and no more wasted
inventory.
• Expensive sockets – How do I eliminate the need for expensive and unreliable
sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program
first time and subsequent times with JTAG. No need to handle devices and bend the
fragile leads.
❏ In-Application re-Programming (IAP)
Two independent flash memory arrays are included so the MCU can execute code
from one memory while erasing and programming the other. Robust product firmware
updates in the field are possible over any communication channel (CAN, Ethernet,
UART, J1850, etc) using this unique architecture. Designers are relieved of these
problems:
• Simultaneous read and write to flash memory – How can the MCU program the
same memory from which it is executing code? It cannot. The PSD allows the MCU
to operate the two flash memories concurrently, reading code from one while erasing
and programming the other during IAP.
• Complex memory mapping – How can I map these two memories efficiently?
A Programmable Decode PLD is embedded in the PSD. The concurrent PSD
memories can be mapped anywhere in MCU address space, segment by segment
with extremely high address resolution. As an option, the secondary flash memory
can be swapped out of the system memory map when IAP is complete. A built-in
page register breaks the MCU address limit.
• Separate program and data space – How can I write to flash memory while it
resides in “program” space during field firmware updates, my 80C51XA won’t allow it
The flash PSD provides means to “reclassify” flash memory as “data” space during
IAP, then back to “program” space when complete.
PSDsoft – ST’s software development tool – guides you through the design process step-
by-step making it possible to complete an embedded MCU design
capable of ISP/IAP in just hours. Select your MCU and PSDsoft will take you through
the remainder of the design with point and click entry, covering...PSD selection, pin
definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI C
code generation for your MCU, and merging your MCU firmware with the PSD design.
When complete, two different device programmers are supported directly from PSDsoft –
FlashLINK (JTAG) and PSDpro.
The PSD4135G2 is available in an 80-pin TQFP package.
Please refer to the revision block at the end of this
document for updated information.
2
Preliminary Information
PSD4000 Series
❏ A simple interface to 16-bit microcontrollers that use either multiplexed or
2.0
Key Features
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
• Intel 80196, 80296, 80186, and 80386EX
• Motorola 68HC16, 68HC12, 683XX, and MC2001
• Philips 80C51XA
• Infineon C16X devices
• Hitachi H8
❏ 4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
❏ Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently.
❏ 64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by
connecting an external battery.
❏ General Purpose PLD (GPLD) with 24 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
❏ Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
❏ 52 individually configurable I/O port pins that can be used for the following functions:
• MCU I/Os
• PLD I/Os
• Latched MCU address output
• Special function I/Os.
• I/O ports may be configured as open-drain outputs.
❏ Standby current as low as 50 µA for 5 V devices.
❏ Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
❏ Internal page register that can be used to expand the microcontroller address space
by a factor of 256.
❏ Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD4000 into Power Down Mode.
❏ Erase/Write cycles:
• Flash memory – 100,000 minimum
• PLD – 1,000 minimum
• 15 year data retention
3.0 PSD4000
Series
Table 1. PSD4000 Product Matrix
Part #
Flash
Main
Flash
Boot
Memory
Kbit
Serial ISP Memory
PLD JTAG/ISP Kbit
PSD4000
Series
I/O
PLD
Input
Output
SRAM
Kbit
Supply
Voltage
Device
Pins Inputs Macrocells Macrocells Outputs
Port
8 Sectors (4 Sectors)
PSD4135G2
PSD4235G2*
52
52
66
82
24
24
Yes
Yes
4096
4096
256
256
64
64
5V
5V
PSD4000
24
16
*See PSD4235G2 Data Sheet.
3
ADDRESS/DATA/CONTROL BUS
PLD
INPUT
BUS
4 MBIT MAIN FLASH
MEMORY
PAGE
REGISTER
EMBEDDED
ALGORITHM
8 SECTORS
POWER
MANGMT
UNIT
VSTDBY
CNTL0,
CNTL1,
CNTL2
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
(
)
PE6
SECTOR
SELECTS
PROG.
MCU BUS
INTRF.
FLASH DECODE
PLD DPLD
(
)
66
SECTOR
SELECTS
PROG.
PORT
64 KBIT BATTERY
BACKUP SRAM
PA0 – PA7
PB0 – PB7
PC0 – PC7
PD0 – PD3
PE0 – PE7
SRAM SELECT
CSIOP
PORT
A
AD0 – AD15 *
ADIO
PORT
RUNTIME CONTROL
AND I/O REGISTERS
PROG.
PORT
PORT
B
FLASH ISP PLD
(GPLD)
66
GPLD OUTPUT
GPLD OUTPUT
GPLD OUTPUT
PROG.
PORT
PROG.
PORT
PF0 – PF7
PORT
F
PORT
C
PROG.
PORT
PORT
D
PROG.
PORT
I/O PORT PLD INPUT
PG0 – PG7
PORT
G
PROG.
PORT
PORT
E
GLOBAL
CONFIG. &
SECURITY
JTAG
SERIAL
CHANNEL
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
*Additional address lines can be brought into PSD via Port A, B, C, D, or F.
Preliminary Information
PSD4000 Series
PSD4000 devices contain several major functional blocks. Figure 1 on page 3 shows the
architecture of the PSD4000 device family. The functions of each block are described
briefly in the following sections. Many of the blocks perform multiple functions and are user
configurable.
4.0
PSD4000
Architectural
Overview
4.1 Memory
The PSD4000 contains the following memories:
• 4 Mbit Flash
• A secondary 256 Kbit Flash memory for boot or data
• 64 Kbit SRAM.
Each of the memories is briefly discussed in the following paragraphs. A more detailed
discussion can be found in section 9.
The 4 Mbit Flash is the main memory of the PSD4000. It is divided into eight equally-sized
sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each
sector is individually selectable.
The 64 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the
microcontroller SRAM. If an external battery is connected to the PSD4000’s Vstby pin, data
will be retained in the event of a power failure.
Each block of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
4.2 PLDs
The device contains two PLD blocks, each optimized for a different function, as shown in
Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes
cost/performance, and eases design entry.
The Decode PLD (DPLD) is used to decode addresses and generate chip selects for
the PSD4000 internal memory and registers. The General Purpose PLD (GPLD) can
implement user-defined external chip selects and logic functions. The PLDs receive their
inputs from the PLD Input Bus and are differentiated by their output destinations, number
of Product Terms.
The PLDs consume minimal power by using Zero-Power design techniques. The speed
and power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register
and other bits in the PMMR2 registers. These registers are set by the microcontroller at
runtime. There is a slight penalty to PLD propagation time when invoking the non-Turbo
bit.
4.3 I/O Ports
The PSD4000 has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G).
Each I/O pin can be individually configured for different functions. Ports can be configured
as standard MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using
multiplexed address/data busses.
The JTAG pins can be enabled on Port E for In-System Programming (ISP). Ports F and
G can also be configured as a data port for a non-multiplexed bus.
4.4 Microcontroller Bus Interface
The PSD4000 easily interfaces with most 16-bit microcontrollers that have either
multiplexed or non-multiplexed address/data busses. The device is configured to respond
to the microcontroller’s control signals, which are also used as inputs to the PLDs. Section
9.3.5 contains microcontroller interface examples.
Table 2. PLD I/O Table
Name
Decode PLD
General PLD
Abbreviation
DPLD
Inputs
66
Outputs
14
Product Terms
40
GPLD
66
24
136
5
PSD4000 Series
Preliminary Information
PSD4000
Architectural
Overview
(cont.)
4.5 ISP via JTAG Port
In-System Programming can be performed through the JTAG pins on Port E. This serial
interface allows complete programming of the entire PSD4000 device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on Port E. Table 3 indicates the JTAG signals pin
assignments.
4.6 In-System Programming (ISP)
Using the JTAG signals on Port E, the entire PSD4000 (memory, logic, configuration)
device can be programmed or erased without the use of the microcontroller.
Table 3. JTAG Signals on Port E
Port E Pins
PE0
JTAG Signal
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
TERR
PE5
4.7 In-Application re-Programming (IAP)
The main Flash memory can also be programmed in-system by the microcontroller
executing the programming algorithms out of the secondary Flash memory, or SRAM.
Since this is a sizable separate block, the application can also continue to operate. The
secondary Flash boot memory can be programmed the same way by executing out of the
main Flash memory. Table 4 indicates which programming methods can program different
functional blocks of the PSD4000.
Table 4. Methods of Programming Different Functional Blocks of the PSD4000
Device
Programmer
Functional Block
JTAG-ISP
IAP
Main Flash memory
Flash Boot memory
PLD Array (DPLD and GPLD)
PSD Configuration
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
4.8 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access
external memory and peripherals or internal memory and I/O. The Page Register can also
be used to change the address mapping of blocks of Flash memory into different memory
spaces for IAP.
4.9 Power Management Unit
The Power Management Unit (PMU) in the PSD4000 gives the user control of the
power consumption on selected functional blocks based on system requirements. The
PMU includes an Automatic Power Down unit (APD) that will turn off device functions due
to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce
power consumption.
The PSD4000 also has some bits that are configured at run-time by the MCU to reduce
power consumption of the GPLD. The turbo bit in the PMMR0 register can be turned off
and the GPLD will latch its outputs and go to standby until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the GPLD to reduce power consumption. See section 9.5.
6
Preliminary Information
PSD4000 Series
The PSD4000 series is supported by PSDsoft a Windows-based (95, 98, NT) software
development tool. A PSD design is quickly and easily produced in a point and click
environment. The designer does not need to enter Hardware Definition Language (HDL)
equations (unless desired) to define PSD pin functions and memory map information. The
general design flow is shown in Figure 2 below. PSDsoft is available from our web site
(www.psdst.com) or other distribution channels.
5.0
Development
System
PSDsoft directly supports two low cost device programmers from ST, PSDpro and
FlashLINK (JTAG). Both of these programmers may be purchased through your local
rep/distributor, or directly from our web site using a credit card. The PSD4000 is also
supported by third party device programmers, see web site for current list.
Figure 2. PSDsoft Development Tool
Choose MCU and PSD
Automatically Configures MCU
bus interface and other PSD
attributes.
Define PSD Pin and
C Code Generation
Node functions
Generate C Code
Specific to PSD
Functions
Point and click definition of
PSD pin functions, internal nodes,
and MCU system memory map.
Merge MCU Firmware
with PSD Configuration
User's choice of
Microcontroller
Compiler/Linker
MCU Firmware
A composite object file is created
containing MCU firmware and
PSD configuration.
Hex or S-Record
format
*.OBJ FILE
PSD Programmer
*.OBJ file
available
for 3rd party
programmers
(Conventional or JTAG-ISP)
PSDPro or
FlashLink (JTAG)
7
PSD4000 Series
Preliminary Information
The following table describes the pin names and pin functions of the PSD4000. Pins that
have multiple names and/or functions are defined using PSDsoft.
6.0
Table 5.
PSD4000
Pin
Pin*
(TQFP
Pkg.) Type
Pin Name
Description
Descriptions
ADIO0-7
3-7
10-12
I/O This is the lower Address/Data port. Connect your MCU
address or address/data bus according to the following rules:
1. If your MCU has a multiplexed address/data bus where the
data is multiplexed with the lower address bits, connect
AD[0:7] to this port.
2. If your MCU does not have a multiplexed address/data bus,
connect A[0:7] to this port.
3. If you are using an 80C51XA in burst mode, connect
A4/D0 through A11/D7 to this port.
ALE or AS latches the address. The PSD drives data out only
if the read signal is active and one of the PSD functional blocks
was selected. The addresses on this port are passed to the
PLDs.
ADIO8-15
13-20 I/O This is the upper Address/Data port. Connect your MCU
address or address/data bus according to the following rules:
1. If your MCU has a multiplexed address/data bus where the
data is multiplexed with the upper address bits, connect
AD[8:15] to this port.
2. If your MCU does not have a multiplexed address/data bus,
connect A[8:15] to this port.
3. If you are using an 80C51XA in burst mode, connect
A12/D8 through A19/D15 to this port.
ALE or AS latches the address. The PSD drives data out only
if the read signal is active and one of the PSD functional
blocks was selected. The addresses on this port are passed
to the PLDs.
CNTL0
CNTL1
59
60
I
I
The following control signals can be connected to this port,
based on your MCU:
1. WR — active-low write input.
_
2. R W — active-high read/active low write input.
3. WRL — Write to low byte, active low
This pin is connected to the PLDs. Therefore, these signals can
be used in decode and other logic equations.
The following control signals can be connected to this port,
based on your MCU:
1. RD — active-low read input.
2. E — E clock input.
3. DS — active-low data strobe input.
4. LDS — Strobe for low data byte, active low.
This pin is connected to the PLDs. Therefore, these signals can
be used in decode and other logic equations.
CNTL2
40
I
Read or other Control input pin with multiple configurations.
Depending on the MCU interface selected, this pin can be:
1. PSEN — Program Select enable, active low in code fetch
bus cycle (80C51XA mode)
2. BHE — High byte enable.
3. UDS — Strobe for high data byte, 16-bit data bus mode,
active low.
4. SIZ0 — Byte enable input.
5. LSTRB — Low strobe input.
This pin is also connected to PLD as input.
8
Preliminary Information
PSD4000 Series
Table 5.
PSD4000
Pin
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
Descriptions
(cont.)
Reset
39
I
Active low input. Resets I/O Ports, PLD Micro Cells, some of
the configuration registers and JTAG registers. Must be active
at power up. Reset also aborts the Flash programming/erase
cycle that is in progress.
PA0-PA7 51-58
PB0-PB7 61-68
PC0-PC7 41-48
I/O
Port A, PA0-7. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port
Drain
2. GPLD output.
3. Input to the PLD (can also be PLD input for address A16
and above).
I/O
Port B, PB0-7. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. GPLD output.
3. Input to the PLD (can also be PLD input for address A16
and above).
I/O
Port C, PC0-7. This port is pin configurable and has multiple
CMOS functions:
or Slew 1. MCU I/O — standard output or input port.
Rate
2. External chip select (ECS0-7) output.
3. Input to the PLD (can also be PLD input for address A16
and above).
PD0
PD1
79
80
I/O
Port D pin PD0 can be configured as:
CMOS 1. ALE or AS input — latches addresses on ADIO0-15 pins
or Open 2. AS input — latches addresses on ADIO0-15 pins on the
Drain
rising edge.
3. Input to the PLD (can also be PLD input for address A16
and above).
I/O
Port D pin PD1 can be configured as:
CMOS 1. MCU I/O
or Open 2. Input to the PLD (can also be PLD input for address A16
Drain
and above).
3. CLKIN clock input — clock input to the GPLD
Micro Cells, the APD power down counter and GPLD
AND Array.
PD2
1
I/O
Port D pin PD2 can be configured as:
CMOS 1. MCU I/O
or Open 2. Input to the PLD (can also be PLD input for address A16
Drain
and above).
3. CSI input — chip select input. When low, the CSI enables
the internal PSD memories and I/O. When high, the
internal memories are disabled to conserve power. CSI
trailing edge can get the part out of power-down mode.
PD3
PE0
2
I/O
Port D pin PD3 can be configured as:
CMOS 1. MCU I/O
or Open 2. Input to the PLD (can also be PLD input for address A16
Drain
and above).
3. WRH — for 16-bit data bus, write to high byte, active low.
71
I/O
Port E, PE0. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TMS input for JTAG/ISP interface.
9
PSD4000 Series
Preliminary Information
Table 5.
PSD4000
Pin
Descriptions
(cont.)
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
Port E, PE1. This port is pin configurable and has multiple
PE1
PE2
PE3
PE4
72
73
74
75
I/O
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TCK input for JTAG/ISP interface (Schmidt Trigger).
I/O
Port E, PE2. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TDI input for JTAG/ISP interface.
I/O
Port E, PE3. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TDO output for JTAG/ISP interface.
I/O
Port E, PE4. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TSTAT output for the ISP interface.
4. Rdy/Bsy — for in-circuit Parallel Programming.
PE5
PE6
76
77
I/O
Port E, PE5. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TERR active low output for ISP interface.
I/O
Port E, PE6. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. Vstby — SRAM standby voltage input for battery
backup SRAM
PE7
78
I/O
Port E, PE7. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. Vbaton — battery backup indicator output. Goes high when
power is drawn from an external battery.
PF0-PF7 31-38
I/O
Port F, PF0-7. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Input to the PLD.
3. Latched address outputs.
4. As address A1-3 inputs in 80C51XA mode (PF0 is grounded)
5. As data bus port (D0-7) in non-multiplexed bus configuration
6. MCU reset mode.
PG0-PG7 21-28
I/O
Port G, PG0-7. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain
2. Latched address outputs.
3. As data bus port (D8-15) in non-multiplexed bus configuration.
4. MCU reset mode.
GND
8,30,
49,50,
70
V
9,29,
69
CC
10
Preliminary Information
PSD4000 Series
Table 6 shows the offset addresses to the PSD4000 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD4000 registers. Table 6 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
7.0 PSD4000
Register
Description and
Address Offset
Table 6. Register Address Offset
Register Name
Port A Port B Port C Port D Port E Port F Port G Other*
Description
Reads Port pin as input,
MCU I/O input mode
Data In
00
01
10
11
30
32
40
42
41
43
Selects mode between
MCU I/O or Address Out
Control
Stores data for output
to Port pins, MCU I/O
output mode
Data Out
Direction
04
06
05
07
14
16
15
17
34
36
44
46
45
47
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Drive Select
08
09
18
19
38
48
49
C0
Read only – Flash Sector
Protection
Flash Protection
Read only – PSD Security
and Flash Boot Sector
Protection
Flash Boot
Protection
C2
B0
Power Management
Register 0
PMMR0
Power Management
Register 2
PMMR2
Page
B4
E0
Page Register
Places PSD memory
areas in Program and/or
Data space on an
VM
E2
individual basis.
Read only – Flash and
SRAM size
Memory_ID0
Memory_ID1
F0
F1
Read only – Boot type
and size
11
PSD4000 Series
Preliminary Information
All the registers in the PSD4000 are included here for reference. Detail description of the
registers are found in the Functional Block section of the Data Sheet.
8.0
Register Bit
Definition
Data In Registers – Port A, B, C, D, E, F and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0
Bit definitions:
Read only registers, read Port pin status when Port is in MCU I/O input Mode.
Data Out Registers – Port A, B, C, D, E, F and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0
Bit definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Direction Registers – Port A, B, C, D, E, F and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0
Bit definitions:
Set Register Bit to 0 = configure corresponding Port pin in Input mode (default).
Set Register Bit to 1 = configure corresponding Port pin in Output mode.
Control Registers – Ports E, F and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0
Bit definitions:
Set Register Bit to 0 = configure corresponding Port pin in MCU I/O mode (default).
Set Register Bit to 1 = configure corresponding Port pin in Latched Address Out mode.
Drive Registers – Ports A, B, D, E, and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0
Bit definitions:
Set Register Bit to 0 = configure corresponding Port pin in CMOS output driver (default).
Set Register Bit to 1 = configure corresponding Port pin in Open Drain output driver.
Drive Registers – Ports C and F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7 Port Pin 6 Port Pin 5 Port Pin 4 Port Pin 3 Port Pin 2 Port Pin 1 Port Pin 0
Bit definitions:
Set Register Bit to 0 = configure corresponding Port pin as CMOS output driver (default).
Set Register Bit to 1 = configure corresponding Port pin in Slew Rate mode.
Flash Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit definitions: Read Only Register
Sec<i>_Prot
Sec<i>_Prot
1 = Flash Sector <i> is write protected.
0 = Flash Sector <i> is not write protected.
12
Preliminary Information
PSD4000 Series
Flash Boot Protection Register
8.0
Bit 7
Bit 6
*
Bit 5
*
Bit 4
*
Bit 3
Bit 2
Bit 1
Bit 0
Register Bit
Definition
(cont.)
Security_Bit
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Boot Block Sector <i> is write protected.
0 = Boot Block Sector <i> is not write protected.
Security_Bit
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
Page Register
Bit 7
Pgr7
Bit 6
Bit 5
Pgr5
Bit 4
Pgr4
Bit 3
Pgr3
Bit 2
Pgr2
Bit 1
Pgr1
Bit 0
Pgr0
Pgr6
Bit definitions:
Configure Page input to PLD. Default Pgr[7:0] = 00.
PMMR0 Register
Bit 7
*
Bit 6
*
Bit 5
Bit 4
Bit 3
Bit 2
*
Bit 1
Bit 0
*
PLD
Mcells clk
PLD
array-clk
PLD
Turbo
APD
enable
*Not used bit should be set to zero.
Bit definitions: (default is 0)
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 5 0 = CLKIN input to the PLD Micro Cells is connected.
1 = CLKIN input to the PLD Micro Cells is disconnected, saving power.
PMMR2 Register
Bit 7
*
Bit 6
PLD
Bit 5
PLD
Bit 4
PLD
Bit 3
PLD
Bit 2
PLD
Bit 1
*
Bit 0
*
array WRh array Ale array Cntl2 array Cntl1 array Cntl0
*Not used bit should be set to zero.
Bit definitions (defauld is 0):
Bit 0 0 = Address A[7:0] are connected into the PLD array.
1 = Address A[7:0] are blocked from the PLD array, saving power.
Note: in XA mode, A3-0 come from PF3-0 and A7-4 come from ADIO7-4.
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to the PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to the PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to the PLD AND array is disconnected, saving power.
Bit 5 0 = Ale input to the PLD AND array is connected.
1 = Ale input to the PLD AND array is disconnected, saving power.
Bit 6 0 = WRh/DBE input to the PLD AND array is connected.
1 = WRh/DBE input to the PLD AND array is disconnected, saving power.
13
PSD4000 Series
Preliminary Information
VM Register
8.0
Bit 7
Bit 6
*
Bit 5
*
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Bit
Definition
(cont.)
FL_data
Boot_data FL_code Boot_code SR_code
*
Note: Upon reset, Bit1-Bit4 are loaded to configurations selected by the user in PSDsoft. Bit 0 is always cleared
by reset. Bit 0 to Bit 4 are active only when the device is configured in Philips 80C51XA mode. Not used
bit should be set to zero.
Bit definitions:
Bit 0 0 = PSEN can’t access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Bit 1 0 = PSEN can’t access Boot in 80C51XA modes.
1 = PSEN can access Boot in 80C51XA modes.
Bit 2 0 = PSEN can’t access main Flash in 80C51XA modes.
1 = PSEN can access main Flash in 80C51XA modes.
Bit 3 0 = RD can’t access Boot in 80C51XA modes.
1 = RD can access Boot in 80C51XA modes.
Bit 4 0 = RD can’t access main Flash in 80C51XA modes.
1 = RD can access main Flash in 80C51XA modes.
Memory_ID0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
Bit definitions:
F_size[3:0] = 4h, main Flash size is 2M bit.
F_size[3:0] = 5h, main Flash size is 8M bit.
S_size[3:0] = 0h, SRAM size is 0K bit.
S_size[3:0] = 1h, SRAM size is 16K bit.
S_size[3:0] = 3h, SRAM size is 64K bit.
Memory_ID1 Register
Bit 7
*
Bit 6
*
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
*Not used bit should be set to zero.
Bit definitions:
B_size[3:0] = 0h, Boot block size is 0K bit.
B_size[3:0] = 2h, Boot block size is 256K bit.
B_type[1:0] = 0h, Boot block is Flash memory.
14
Preliminary Information
PSD4000 Series
As shown in Figure 1, the PSD4000 consists of six major types of functional blocks:
9.0
The
❏ Memory Blocks
❏ PLD Blocks
❏ Bus Interface
PSD4000
Functional
Blocks
❏ I/O Ports
❏ Power Management Unit
❏ JTAG-ISP Interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
9.1 Memory Blocks
The PSD4000 has the following memory blocks:
• The main Flash memory
• Secondary Flash memory
• SRAM.
The memory select signals for these blocks originate from the Decode PLD (DPLD) and
are user-defined in PSDsoft.
Table 7 summarizes which versions of the PSD4000 contain which memory blocks.
Table 7. Memory Blocks
Main Flash
Secondary Flash
Device
Flash Size
512KB
Sector Size
Block Size
32KB
Sector Size
SRAM
PSD4135G2
64KB
8KB
8KB
9.1.1 Main Flash and Secondary Flash Memory Description
The main Flash memory block is divided evenly into eight sectors. The secondary Flash
memory is divided into four sectors of eight Kbytes each. Each sector of either memory
can be separately protected from program and erase operations.
Flash memory may be erased on a sector-by-sector basis and programmed word-by-word.
Flash sector erasure may be suspended while data is read from other sectors of memory
and then resumed after reading.
During a program or erase of Flash, the status can be output on the Rdy/Bsy pin of Port
PE4. This pin is set up using PSDsoft.
9.1.1.1 Memory Block Selects
The decode PLD in the PSD4000 generates the chip selects for all the internal memory
blocks (refer to the PLD section). Each of the eight Flash memory sectors have a
Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the
four Secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can
contain up to three product terms. Having three product terms for each sector select signal
allows a given sector to be mapped in different areas of system memory. When using a
microcontroller (80C51XA) with separate Program and Data space, these flexible select
signals allow dynamic re-mapping of sectors from one space to the other before and after
IAP.
9.1.1.2 The Ready/Busy Pin (PE4)
Pin PE4 can be used to output the Ready/Busy status of the PSD4000. The output on the
pin will be a ‘0’ (Busy) when Flash memory blocks are being written to, or when the Flash
memory block is being erased. The output will be a ‘1’ (Ready) when no write or erase
operation is in progress.
15
PSD4000 Series
Preliminary Information
9.1.1.3 Memory Operation
The
The main Flash and secondary Flash memories are addressed through the microcontroller
interface on the PSD4000 device. The microcontroller can access these memories in one
of two ways:
PSD4000
Functional
Blocks
(cont.)
❏ The microcontroller can execute a typical bus write or read operation just as it would
if accessing a RAM or ROM device using standard bus cycles.
❏ The microcontroller can execute a specific instruction that consists of several write
and read operations. This involves writing specific data patterns to special addresses
within the Flash to invoke an embedded algorithm. These instructions are summarized
in Table 8.
Typically, Flash memory can be read by the microcontroller using read operations, just
as it would read a ROM device. However, Flash memory can only be erased and
programmed with specific instructions. For example, the microcontroller cannot write a
single word directly to Flash memory as one would write a word to RAM. To program a
word into Flash memory, the microcontroller must execute a program instruction sequence,
then test the status of the programming event. This status test is achieved by a read
operation or polling the Rdy/Busy pin (PE4).
The Flash memory can also be read by using special instructions to retrieve particular
Flash device information (sector protect status and ID).
9.1.1.3.1 Instructions
An instruction is defined as a sequence of specific operations. Each received byte is
sequentially decoded by the PSD and not executed as a standard write operation. The
instruction is executed when the correct number of bytes are properly received and the
time between two consecutive bytes is shorter than the time-out value. Some instructions
are structured to include read operations after the initial write operations.
The sequencing of any instruction must be followed exactly. Any invalid combination of
instruction bytes or time-out between two consecutive bytes while addressing Flash
memory will reset the device logic into a read array mode (Flash memory reads like a
ROM device).
The PSD4000 main Flash and secondary Flash support these instructions (see Table 8):
❏ Erase memory by chip or sector
❏ Suspend or resume sector erase
❏ Program a word
❏ Reset to read array mode
❏ Read Main Flash Identifier value
❏ Read sector protection status
❏ Bypass Instruction
These instructions are detailed in Table 8. For efficient decoding of the instructions, the
first two bytes of an instruction are the coded cycles and are followed by a command byte
or confirmation byte. The coded cycles consist of writing the data byte AAh to address
XAAAh during the first cycle and data byte 55h to address X554h during the second cycle
(unless the Bypass Instruction feature is used. See 9.1.1.7). Address lines A15-A12 are
don’t care during the instruction write cycles. However, the appropriate sector select signal
(FSi or CSBOOTi) must be selected.
The main Flash and the secondary Flash Block have the same set of instructions (except
Read main Flash ID). The chip selects of the Flash memory will determine which Flash will
receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is
active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active.
16
Preliminary Information
PSD4000 Series
Cycle 6 Cycle 7
The
Table 8. Instructions
PSD4000
Functional
Blocks
(cont.)
FS0-7
or
Instruction
(Note 14)
CSBOOT0-3 Cycle 1 Cycle 2 Cycle 3 Cycle 4
Cycle5
Read (Note 5)
1
1
“Read”
RA RD
Read Main Flash ID
(Note 6)
AAh
55h
90h
“Read”
ID
@XAAAh @X554h @XAAAh
@XX02h
Read Sector Protection
(Notes 6,8,13)
1
AAh
55h
90h
“Read”
@XAAAh @X554h @XAAAh 00h or 01h
@XX04h
Program a Flash Word
Erase One Flash Sector
1
1
AAh
55h
A0h
PD@PA
@XAAAh @X554h @XAAAh
AAh 55h 80h
AAh
55h
30h
30h
@XAAAh @X554h @XAAAh @XAAAh
@X554h
@SA
@next SA
(Note 7)
Erase Flash Block
(Bulk Erase)
1
1
1
1
1
1
1
AAh
55h
80h
AAh
55h
@X554h
10h
@XAAAh
@XAAAh @X554h @XAAAh @XAAAh
Suspend Sector Erase
(Note 11)
B0h
@xxxh
Resume Sector Erase
(Note 12)
30h
@xxxh
Reset (Note 6)
F0 @ any
address
Unlock Bypass
AAh
55h
20h
@XAAAh @X554h @XAAAh
Unlock Bypass Program
(Note 9)
A0h
@XXXXh
PD@PA
00h
Unlock Bypass Reset
(Note 10)
90h
@XXXXh @XXXXh
X
= Don’t Care. “xxxh” address in the above table must be an even address.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR#
(CNTL0) pulse. PA is an even address for PSD in word programming mode.
PD = Data (word) to be programmed at location PA. Data is latched on the rising edge of WR# (CNTL0) pulse.
SA = Address of the sector to be erased or verified. The chip select (FS0-7 or CSBOOT0-3) of the sector to be
erased must be active (high).
NOTES:
1. All bus cycles are write bus cycle except the ones with the “read” label.
2. All values are in hexadecimal.
3. FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft.
4. Only Address bits A11-A0 are used in Instruction decoding.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status
or if DQ5 (DQ13) goes high.
7. Additional sectors to be erased must be entered within 80µs.
8. The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip
select is active and (A1 = 1, A0 = 0).
9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
Unlock Bypass mode.
11. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector
Protect status, when in the Erase Suspend mode. The erase Suspend command is valid only during a sector
erase operation.
12. The Erase Resume command is valid only during the Erase Suspend mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the
instruction is intended. The MCU must fetch, for example, codes from the Secondary Flash memory when
reading the Sector Protection Status of the main Flash.
14. All write bus cycles in an instruction are byte write to even address (XA4Ah or X554h). Flash Programming
bys cycle is writing a word to even address.
17
PSD4000 Series
Preliminary Information
The
9.1.1.4 Power-Up Condition
The PSD4000 internal logic is reset upon power-up to the read array mode. The FSi and
CSBOOTi select signals, along with the write strobe signal, must be in the false state
during power-up for maximum security of the data contents and to remove the possibility of
data being written on the first edge of a write strobe signal. Any write cycle initiation is
PSD4000
Functional
Blocks
(cont.)
locked when V is below VLKO.
CC
9.1.1.5 Read
Under typical conditions, the microcontroller may read the Flash, or secondary Flash
memories using read operations just as it would a ROM or RAM device. Alternately, the
microcontoller may use read operations to obtain status information about a program or
erase operation in progress. Lastly, the microcontroller may use instructions to read
special data from these memories. The following sections describe these read functions.
9.1.1.5.1 Read the Contents of Memory
Main Flash and secodary Flash memories are placed in the read array mode after
power-up, chip reset, or a Reset Flash instruction (see Table 8). The microcontroller can
read the memory contents of main Flash or secondary Flash by using read operations any
time the read operation is not part of an instruction sequence.
9.1.1.5.2 Read the Main Flash Memory Identifier
The main Flash memory identifier is read with an instruction composed of 4 operations:
3 specific write operations and a read operation (see Table 8). The PSD4000 main Flash
memory ID is E8h. The Secondary Flash does not support this instruction.
9.1.1.5.3 Read the Flash Memory Sector Protection Status
The Flash memory sector protection status is read with an instruction composed of 4
operations: 3 specific write operations and a read operation (see Table 8). The read
operation will produce 01h if the Flash sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks (main Flash or secondary Flash) can also
be read by the microcontroller accessing the Flash Protection and Flash Boot Protection
registers in PSD I/O space. See section 9.1.1.9.1 for register definitions.
9.1.1.5.4 Read the Erase/Program Status Bits
The PSD4000 provides several status bits to be used by the microcontroller to confirm
the completion of an erase or programming instruction of Flash memory. These status bits
minimize the time that the microcontroller spends performing these tasks and are defined
in Table 9. The status byte resides in even location and can be read as many times as
needed. Please note DQ15-8 is even byte for Motorola MCUs with 16 bit data bus.
Table 9. Status Bits
FSi/
CSBOOTi
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Erase
Time-
out
Data Toggle Error
Flash
V
X
X
X
X
IH
Polling
Flag
Flag
Table 9A. Status Bits for Motorola
FSi/
CSBOOTi DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
Erase
Time-
out
Data Toggle Error
Polling Flag Flag
Flash
V
X
X
X
X
IH
NOTES: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ15-DQ0 represent the Data Bus bits, D15-D0.
3. FSi/CSBOOTi are active high.
For Flash memory, the microcontroller can perform a read operation to obtain these status
bits while an erase or program instruction is being executed by the embedded algorithm.
See section 9.1.1.6 for details.
18
Preliminary Information
PSD4000 Series
9.1.1.5.5 Data Polling Flag DQ7 (DQ15 for Motorola)
The
When Erasing or Programming the Flash memory bit DQ7 (DQ15) outputs the complement
of the bit being entered for Programming/Writing on DQ7 (DQ15). Once the Program
instruction or the Write operation is completed, the true logic value is read on DQ7 (DQ15)
(in a Read operation). Flash memory specific features:
PSD4000
Functional
Blocks
(cont.)
❏ Data Polling is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase). It must be performed at the address being programmed
or at an address within the Flash sector being erased.
❏ During an Erase instruction, DQ7 (DQ15) outputs a ‘0’. After completion of the
instruction, DQ7 (DQ15) will output the last bit programmed (it is a ‘1’ after erasing).
❏ If the location to be programmed is in a protected Flash sector, the instruction is
ignored.
❏ If all the Flash sectors to be erased are protected, DQ7 (DQ15) will be set to ‘0’ for
about 100 µs, and then return to the previous addressed location. No erasure will be
performed.
9.1.1.5.6 Toggle Flag DQ6 (DQ14 for Motorola)
The PSD4000 offers another way for determining when the Flash memory Program
instruction is completed. During the internal Write operation and when either the FSi or
CSBOOTi is true, the DQ6 (DQ14) will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent
attempts to read any word of the memory.
When the internal cycle is complete, the toggling will stop and the data read on the
Data Bus is the addressed memory location. The device is now accessible for a new
Read or Write operation. The operation is finished when two successive reads yield the
same output data. Flash memory specific features:
❏ The Toggle bit is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase).
❏ If the location to be programmed belongs to a protected Flash sector, the instruction
is ignored.
❏ If all the Flash sectors selected for erasure are protected, DQ6 (DQ14) will toggle to
‘0’ for about 100 µs and then return to the previous addressed location.
9.1.1.5.7 Error Flag DQ5 (DQ14 for Motorola)
During a correct Program or Erase, the Error bit will set to ‘0’. This bit is set to ‘1’ when
there is a failure during Flash programming, Sector erase, or Bulk Erase.
In the case of Flash programming, the Error Bit indicates the attempt to program a Flash
bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation.
The Error bit may also indicate a timeout condition while attempting to program a word.
In case of an error in Flash sector erase or word program, the Flash sector in which the
error occurred or to which the programmed location belongs must no longer be used.
Other Flash sectors may still be used. The Error bit resets after the Reset instruction. A
reset instruction is required after detecting the error bit.
9.1.1.5.8 Erase Time-out Flag DQ3 (DQ11 for Motorola)
The Erase Timer bit reflects the time-out period allowed between two consecutive Sector
Erase instructions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a
time period of 100 µs + 20% unless an additional Sector Erase instruction is decoded.
After this time period or when the additional Sector Erase instruction is decoded, DQ3
(DQ11) is set to ‘1’. A reset instruction is required after detecting the erase timer bit.
19
PSD4000 Series
Preliminary Information
The
9.1.1.6 Programming Flash Memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector. Flash memory sector erases to all logic ones, and its bits
are programmed to logic zeros. Although erasing Flash memory occurs on a sector or chip
basis, programming Flash memory occurs on a word basis.
PSD4000
Functional
Blocks
(cont.)
The PSD4000 main Flash and secondary Flash memories require the MCU to send an
instruction to program a word or perform an erase function (see Table 8).
Once the MCU issues a Flash memory program or erase instruction, it must check for the
status of completion. The embedded algorithms that are invoked inside the PSD4000
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.
9.1.1.6.1 Data Polling
Polling on DQ7 (DQ15) is a method of checking whether a Program or Erase instruction is
in progress or has completed. Figure 3 shows the Data Polling algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD4000 begins. The MCU then reads the location of the word to be programmed in Flash
to check status. Data bit DQ7 (DQ15) of this location becomes the compliment of data bit
7of the original data word to be programmed. The MCU continues to poll this location,
comparing DQ7 (DQ15) and monitoring the Error bit on DQ5 (DQ13). When the DQ7
(DQ15) matches data bit 7 of the original data, and the Error bit at DQ5 (DQ13) remains
‘0’, then the embedded algorithm is complete. If the Error bit at DQ5 is ‘1’, the MCU should
test DQ7 (DQ15) again since DQ7 (DQ15) may have changed simultaneously with DQ5
(DQ13) (see Figure 3).
The Error bit at DQ5 (DQ13) will be set if either an internal timeout occurred while the
embedded algorithm attempted to program the location or if the MCU attempted to
program a ‘1’ to a bit that was not erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the word that was written to Flash with
the word that was intended to be written.
When using the Data Polling method after an erase instruction, Figure 3 still applies.
However, DQ7 (DQ15) will be ‘0’ until the erase operation is complete. A ‘1’ on DQ5
(DQ13) will indicate a timeout failure of the erase operation, a ‘0’ indicates no error.
The MCU can read any location within the sector being erased to get DQ7 (DQ15) and
DQ5 (DQ13) .
PSDsoft generates ANSI C code functions which implement these Data Polling
algorithms.
20
Preliminary Information
PSD4000 Series
The
Figure 3. Data Polling Flow Chart
PSD4000
Functional
Blocks
(cont.)
START
READ DQ5 & DQ7
(DQ13 & DQ15)
at VALID EVEN ADDRESS
DQ7
(DQ15)
=
YES
DATA7
(DATA15)
NO
DQ5
(DQ13)
=1
NO
YES
READ DQ7
(DQ15)
DQ7
(DQ15)
YES
=
DATA7
(DATA15)
NO
FAIL
PASS
Program/Erase
Operation Failed
Issue Reset Instruction
Program/Erase
Operation is
Completed
9.1.1.6.2 Data Toggle
Checking the Data Toggle bit on DQ6 (DQ14) is a method of determining whether a
Program or Erase instruction is in progress or has completed. Figure 4 shows the Data
Toggle algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD4000 begins. The MCU then reads the location to be programmed in Flash to check
status. Data bit DQ6 (DQ14) of this location will toggle each time the MCU reads this
location until the embedded algorithm is complete. The MCU continues to read this
location, checking DQ6 (DQ14) and monitoring the Error bit on DQ5 (DQ13) . When
DQ6 (DQ14) stops toggling (two consecutive reads yield the same value), and the Error bit
on DQ5 (DQ13) remains ‘0’, then the embedded algorithm is complete. If the Error bit on
DQ5 (DQ13) is ‘1’, the MCU should test DQ6 (DQ14) again, since DQ6 (DQ14) may have
changed simultaneously with DQ5 (DQ13) (see Figure 4).
The Error bit at DQ5 (DQ13) will be set if either an internal timeout occurred while the
embedded algorithm attempted to program, or if the MCU attempted to program a ‘1’ to a
bit that was not erased (not erased is logic ‘0’).
21
PSD4000 Series
Preliminary Information
9.1.1.6.2 Data Toggle (cont.)
The
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the word that was written to Flash with
the word that was intended to be written.
PSD4000
Functional
Blocks
(cont.)
When using the Data Toggle method after an erase instructin, Figure 4 still applies. DQ6
(DQ14) will toggle until the erase operation is complete. A ‘1’ on DQ5 (DQ13) will indicate
a timeout failure of the erase operation, a ‘0’ indicates no error. The MCU can read any
even location within the sector being erased to get DQ6 (DQ14) and DQ5 (DQ13) .
PSDsoft generates ANSI C code functions which implement these Data Toggling
algorithms.
Figure 4. Data Toggle Flow Chart
START
READ DQ5 & DQ6
(DQ13 & DQ14)
at VALID EVEN ADDRESS
DQ6
(DQ14)
NO
=
TOGGLE
YES
DQ5
(DQ13)
=1
NO
YES
READ DQ6
(DQ14)
DQ6
(DQ14)
NO
=
TOGGLE
YES
FAIL
PASS
Program/Erase
Operation Failed
Issue Reset Instruction
Program/Erase
Operation is
Completed
22
Preliminary Information
PSD4000 Series
The
9.1.1.7 Unlock Bypass Instruction
The unlock bypass feature allows the system to program words to the flash memories
faster than using the standard program instruction. The unlock bypass instruction is
initiated by first writing two unlock cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h (see Table 8). The flash memory then enters the unlock
bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to
program in this mode. The first cycle in this instruction contains the unlock bypass
programm command, A0h; the second cycle contains the program address and data.
Additional data is programmed in the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program instruction, resulting in faster total pro-
gramming time. During the unlock bypass mode, only the Unlock Bypass Program and
Unlock Bypass Reset instructions are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset instruction. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The
flash memory then returns to reading array data mode.
PSD4000
Functional
Blocks
(cont.)
9.1.1.8 Erasing Flash Memory
9.1.1.8.1. Flash Bulk Erase Instruction
The Flash Bulk Erase instruction uses six write operations followed by a Read operation of
the status register, as described in Table 8. If any byte of the Bulk Erase instruction is
wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory
status.
During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6,
and DQ7 (DQ13, DQ14, DQ15), as detailed in section 9.1.1.6. The Error bit (returns a ‘1’ if
there has been an Erase Failure (maximum number of erase cycles have been executed).
It is not necessary to program the array with 00h because the PSD4000 will automatically
do this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory will not accept any
instructions.
9.1.1.8.2 Flash Sector Erase Instruction
The Sector Erase instruction uses six write operations, as described in Table 8. Additional
Flash Sector Erase confirm commands and Flash sector addresses can be written
subsequently to erase other Flash sectors in parallel, without further coded cycles, if the
additional instruction is transmitted in a shorter time than the timeout period of about
100 µs. The input of a new Sector Erase instruction will restart the time-out period.
The status of the internal timer can be monitored through the level of DQ3 (DQ11) (Erase
time-out bit). If DQ3 (DQ11) is ‘0’, the Sector Erase instruction has been received and the
timeout is counting. If DQ3 (DQ11) is ‘1’, the timeout has expired and the PSD4000 is busy
erasing the Flash sector(s). Before and during Erase timeout, any instruction other than
Erase suspend and Erase Resume will abort the instruction and reset the device to Read
Array mode. It is not necessary to program the Flash sector with 00h as the PSD4000 will
do this automatically before erasing.
During a Sector Erase, the memory status may be checked by reading status bits DQ5,
DQ6, and DQ7 (DQ13, DQ14, DQ15), as detailed in section 9.1.1.6.
During execution of the erase instruction, the Flash block logic accepts only Reset and
Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to
read data from another Flash sector, and then resumed.
23
PSD4000 Series
Preliminary Information
9.1.1.8.3 Flash Erase Suspend Instruction
The
When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will
suspend the operation by writing 0B0h to any even address when an appropriate Chip
Select (FSi or CSBOOTi) is true. (See Table 8). This allows reading of data from another
Flash sector after the Erase operation has been suspended. Erase suspend is accepted
only during the Flash Sector Erase instruction execution and defaults to read array
mode. An Erase Suspend instruction executed during an Erase timeout will, in addition to
suspending the erase, terminate the time out.
PSD4000
Functional
Blocks
(cont.)
The Toggle Bit DQ6 stops toggling when the PSD4000 internal logic is suspended. The
toggle Bit status must be monitored at an address within the Flash sector being erased.
The Toggle Bit will stop toggling between 0.1 µs and 15 µs after the Erase Suspend
instruction has been executed. The PSD4000 will then automatically be set to Read Flash
Block Memory Array mode.
If an Erase Suspend instruction was executed, the following rules apply:
• Attempting to read from a Flash sector that was being erased will output invalid data.
• Reading from a Flash sector that was not being erased is valid.
• The Flash memory cannot be programmed, and will only respond to Erase Resume
and Reset instructions (read is an operation and is OK).
• If a Reset instruction is received, data in the Flash sector that was being erased will
be invalid.
9.1.1.8.4 Flash Erase Resume Instruction
If an Erase Suspend instruction was previously executed, the erase operation may be
resumed by this instruction. The Erase Resume instruction consists of writing 030h to any
even address while an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 8.)
9.1.1.9 Specific Features
9.1.1.9.1 Main Flash and Secondary Flash Sector Protect
Each sector of Main Flash and Secondary Flash memory can be separately protected
against Program and Erase functions. Sector Protection provides additional data
security because it disables all program or erase operations. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a Device Programmer.
Sector protection can be selected for each sector using the PSDsoft program. This will
automatically protect selected sectors when the device is programmed through the JTAG
Port or a Device Programmer. Flash sectors can be unprotected to allow updating of their
contents using the JTAG Port or a Device Programmer. The microcontroller can read (but
cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash sector will be ignored by the device.
The Verify operation will result in a read of the protected data. This allows a guarantee of
the retention of the Protection status.
The sector protection status can either be read by the MCU through the Flash protection
and secondary Flash protection registers (CSIOP), or use the Read Sector Protection
instruction (Table 8).
24
Preliminary Information
PSD4000 Series
The
Table 10. Sector Protection/Security Bit Definition
Flash Protection Register
PSD4000
Functional
Blocks
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Main Flash Sector <i> is write protected.
0 = Main Flash Sector <i> is not write protected.
Flash Boot Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
*
Bit 3
Bit 2
Bit 1
Bit 0
Security_
Bit
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
*
*
*: Not used.
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Flash Boot Sector <i> is write protected.
0 = Flash Boot Sector <i> is not write protected.
Security_Bit
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
9.1.1.9.2 Reset Instruction
The Reset instruction consists of one write cycle (see Table 8). It can also be optionally
preceded by the standard two write decoding cycles (writing AAh to AAAh and 55h to
554h).
The Reset instruction must be executed after:
1. Reading the Flash Protection status or Flash ID using the Flash instruction.
2. When an error condition occurs (DQ5 (DQ13) goes high) during a Flash programming
or erase cycle.
The Reset instruction will reset the Flash to normal Read Mode immediately. However, if
there is an error condition (DQ5 (DQ13) goes high), the Flash memory will return to the
Read Mode in 25 µSeconds after the Reset instruction is issued.
The Reset instruction is ignored when it is issued during a Flash programming or Bulk
Erase cycle. The Reset instruction will abort the on going sector erase cycle and return the
Flash memory to normal Read Mode in 25 µSeconds.
9.1.1.9.3 Reset Pin Input
The reset pulse input from the pin will abort any operation in progress and reset the Flash
memory to Read Mode. When the reset occurs during a programming or erase cycle, the
Flash memory will take up to 25 µSeconds to return to Read Mode. It is recommended that
the reset pulse (except power on reset, see Reset Section) be at least 25 µSeconds such
that the Flash memory will always be ready for the MCU to fetch the boot code after reset
is over.
25
PSD4000 Series
Preliminary Information
The
9.1.2 SRAM
The SRAM is enabled when RS0—the SRAM chip select output from the DPLD—is high.
RS0 can contain up to three product terms, allowing flexible memory mapping.
PSD4000
Functional
Blocks
(cont.)
The SRAM can be backed up using an external battery. The external battery should be
connected to the Vstby pin (PE6). If you have an external battery connected to the
PSD4000, the contents of the SRAM will be retained in the event of a power loss. The
contents of the SRAM will be retained so long as the battery voltage remains at 2V or
greater. If the supply voltage falls below the battery voltage, an internal power switchover
to the battery occurs.
Pin PE7 can be configured as an output that indicates when power is being drawn from the
external battery. This Vbaton signal will be high with the supply voltage falls below the bat-
tery voltage and the battery on PE6 is supplying power to the internal SRAM.
The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using
PSDsoft.
9.1.3 Memory Select Signals
The main Flash (FSi), secondary Flash (CSBOOTi), and SRAM (RS0) memory select
signals are all outputs of the DPLD. They are defined using PSDsoft. The following rules
apply to the equations for the internal chip select signals:
1. Main Flash memory and secondary Flash memory sector select signals must not be
larger than the physical sector size.
2. Any main Flash memory sector must not be mapped in the same memory space as
another Main Flash sector.
3. A secondary Flash memory sector must not be mapped in the same memory space as
another Flash Boot sector.
4. SRAMand I/O spaces must not overlap.
5. A secondary Flash memory sector may overlap a main Flash memory sector. In case of
overlap, priority will be given to the Flash Boot sector.
6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority
will be given to the SRAM, and I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) will automatically address Boot memory segment 0. Any address
greater than 9FFFh will access the Flash memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this
example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to
BFFFh would not be valid.
Figure 5 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on
the same level must not overlap. Level one has the highest priority and level 3 has the
lowest.
26
Preliminary Information
PSD4000 Series
The
Figure 5. Priority Level of Memory and I/O Components
PSD4000
Functional
Blocks
(cont.)
Highest Priority
Level 1
SRAM, I/O
Level 2
Secondary Flash Memory
Level 3
Main Flash Memory
Lowest Priority
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 80C51XA and compatible family of microcontrollers, can be configured to have
separate address spaces for code memory (selected using PSEN) and data memory
(selected using RD). Any of the memories within the PSD4000 can reside in either space
or both spaces. This is controlled through manipulation of the VM register that resides in
the PSD’s CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and main Flash in Data Space at boot, and
secondary Flash memory in Program Space at boot, and later swap main and secondary
Flash memory. This is easily done with the VM register by using PSDsoft to configure it for
boot up and having the microcontroller change it when desired.
Table 11 describes the VM Register.
Table 11. VM Register
Bit 7
Bit 6* Bit 5* Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIO_EN
FL_Data Boot_Data FL_Code Boot_Code SRAM_Code
0 = disable
PIO mode
0 = RD 0 = RD
can’t can’t
access access
Flash
0 = PSEN 0 = PSEN
0 = PSEN
can’t
access
*
*
*
*
can’t
can’t
access
access
Boot Flash Flash
Boot Flash SRAM
1 = PSEN 1 = PSEN 1 = PSEN
access access access
Boot Flash Flash Boot Flash SRAM
1= enable
PIO mode
1 = RD 1 = RD
access access
Flash
NOTE: Bits 6-5 are not used.
27
PSD4000 Series
Preliminary Information
9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces
The
PSD4000
Functional
Blocks
(cont.)
9.1.3.2.1 Separate Space Modes
Code memory space is separated from data memory space. For example, the PSEN
signal is used to access the program code from the main Flash Memory, while the RD
signal is used to access data from the secondary Flash memory, SRAM and I/O Ports.
This configuration requires the VM register to be set to 0Ch.
9.1.3.2.2 . Combined Space Modes
The program and data memory spaces are combined into one space that allows the main
Flash Memory, secondary Flash memory, and SRAM to be accessed by either PSEN or
RD. For example, to configure the main Flash memory in combined space mode, bits 2
and 4 of the VM register are set to “1”.
9.1.3.3 80C51XA Memory Map Example
See Application Notes for examples.
Figure 6. 80C51XA Memory Modes – Separate Space Mode
MAIN
FLASH
FLASH
BOOT
SRAM
DPLD
RS0
BLOCK
CSBOOT0-3
FS0-7
CS
CS
CS
OE
OE
OE
PSEN
RD
Figure 7. 80C51XA Memory Mode – Combined Space Mode
MAIN
FLASH
FLASH
BOOT
SRAM
DPLD
RS0
BLOCK
RD
CSBOOT0-3
FS0-7
CS
CS
CS
OE
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
RD
VM REG BIT 2
VM REG BIT 0
28
Preliminary Information
PSD4000 Series
The
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller.
The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD decoder and
can be included in the Flash Memory, secondary Flash memory, and SRAM chip select
equations.
PSD4000
Functional
Blocks
(cont.)
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the PLD for general logic. See Application
Notes.
Figure 8 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus. The microcontroller can write to or read from the Page Register. The
Page Register can be accessed at address location CSIOP + E0h.
Figure 8. Page Register
RESET
PGR0
INTERNAL
SELECTS
AND LOGIC
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGR1
DATA BUS
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
DPLD
AND
GPLD
R/W
PAGE
REGISTER
FLASH
PLD
29
PSD4000 Series
Preliminary Information
The
9.1.5 Memory ID Registers
The 8-bit read only memory status registers are included in the CSIOP space. The user
can determine the memory configuration of the PSD device by reading the Memory ID0
and Memory ID1 registers. The content of the registers are defined as follow:
PSD4000
Functional
Blocks
(cont.)
Memory_ID0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
Bit Definition
F_size3
Main Flash Size
(Bit)
F_size2
F_size1
F_size0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
none
256K
512K
1M
2M
4M
8M
SRAM Size
(Bit)
S_size3
S_size2
S_size1
S_size0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
none
16K
32K
64K
Memory_ID1 Register
Bit 7
*
Bit 6
*
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
*Not used bit should be set to zero.
Bit Definition
Boot Block Size
(Bit)
B_size3
B_size2
B_size1
B_size0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
none
128K
256K
512K
B_type1
B_type0
Boot Block Type
0
0
0
1
Flash
EEPROM
30
Preliminary Information
PSD4000 Series
The
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD4000. After specifying the
logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon
power-up.
PSD4000
Functional
Blocks
(cont.)
The PSD4000 contains two PLDs: the Decode PLD (DPLD), and the General Purpose
PLD (GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more
detail in sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory,
registers, and I/O port selects.
The GPLD can be used to generate external chip selects, control signals or logic functions.
The GPLD has 24 outputs that are connected to Port A, B and C.
The AND array is used to form product terms. These product terms are specified using
PSDsoft. An Input Bus consisting of 66 signals is connected to the PLDs. The signals are
shown in Table 12. The complement of the 66 signals are also available as inputs to the
AND array.
Table 12. DPLD and GPLD Inputs
Input Source
Input Name
Number
of Signals
MCU Address Bus
A[15:0]*
16
3
1
1
8
8
8
4
8
8
1
MCU Control Signals
Reset
CNTL[2:0]
RST
Power Down
PDN
Port A Input
PA[7-0]
PB[7-0]
PC[7-0]
PD[3:0]
PF[7:0]
PGR(7:0)
Rdy/Bsy
Port B Input
Port C Input
Port D Inputs
Port F Inputs
Page Register
Flash Programming Status Bit
NOTE: The address inputs are A[19:4] in 80C51XA mode.
The Turbo Bit
The PLDs in the PSD4000 can minimize power consumption by switching to standby
when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo
mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if
no inputs are changing. Turbo-off mode increases propagation delays while reducing
power consumption. Refer to the Power Management Unit section on how to set the Turbo
Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals
from entering the PLDs. This reduces power consumption and can be used only when
these MCU control signals are not used in PLD logic equations.
31
PSD4000 Series
Preliminary Information
Figure 9. PLD Block Diagram
8
PAGE
REGISTER
DATA
BUS
8
FLASH MEMORY SELECTS
DECODE PLD
66
4
1
1
FLASH BOOT MEMORY SELECTS
SRAM SELECT
CSIOP SELECT
GENERAL PURPOSE PLD
PLD OUT
PLD OUT
PLD OUT
GPLD
8
8
8
PORT A
66
PORT B
PORT C
PORT A PLD INPUT
8
PORT B PLD INPUT
PORT C PLD INPUT
8
8
PORT D PLD INPUT
PORT F PLD INPUT
4
8
PORT D
PORT F
32
Preliminary Information
PSD4000 Series
9.2.1 Decode PLD (DPLD)
The
The DPLD, shown in Figure 10, is used for decoding the address for internal components.
The DPLD can generate the following decode signals:
PSD4000
Functional
Blocks
(cont.)
• 8 sector selects for the main Flash memory (three product terms each)
• 4 sector selects for the Secondary Flash memory (three product terms each)
• 1 internal SRAM select (three product terms)
• 1 internal CSIOP select (select PSD registers, one product term)
Inputs to the DPLD chip selects may include address inputs, Page Register inputs and
other user defined external inputs from Ports A, B, C, D or F.
9.2.2 General Purpose PLD (GPLD)
The General Purpose PLD implements user defined system combinatorial logic function
or chip selects for external devices. Figure 11 shows how the GPLD is connected to the
I/O Ports. The GPLD has 24 outputs and each are routed to a port pin. The port pin can
also be configured as input to the GPLD. When it is not used as GPLD output or input, the
pin can be configured to perform other I/O functions.
All GPLD outputs are identical except in the number of available product terms (PTs) for
logic implementation. Select the pin that can best meet the PT requirement of your logic
function or chip select. In general, a PT is consumed for each logic “OR” function that you
specify in PSDsoft. However, certain logic functions can consume more than one PT even
if no logic “OR” is specified (such as specifying an address range with boundaries of high
granularity).
Table 13 shows the number of “native” PTs for each GPLD output pin. A native PT means
that a particular PT is dedicated to an output pin. For example, Table 13 shows that PSD
Port A pin PA0 has 3 native product terms. This means a guaranteed minimum of 3 PTs is
available to implement logic for that pin.
PSD silicon and PSDsoft can include additional PTs beyong the native PTs to implement
logic. This is a transparent operation that occurs as needed through PT expansion
(internal feedback) or PT allocation (internal borrowing). You may notice in the fitter report
generated by PSDsoft that for a given GPLD output pin, more PTs were used to implement
logic than the number of native PTs available for that pin. This is because PSDsoft has
called on unused PTs from other GPLD output pins to make your logic design fit (PT
allocation or PT expansion). For optimum results, choose a GPLD output pin with a large
number of native PTs for complicated logic.
Table 13. GPLD Product Term Availability
GPLD Output on Port Pin
Number of Native
Product Terms
Port A, pins PA0-3
Port A, pins PA4-7
Port B, pins PB0-3
Port B, pins PB4-7
Port C, pins PC0-7
3
9
4
7
1
33
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
3
3
3
3
4 SECONDARY
FLASH MEMORY
SECTOR SELECTS
3
3
3
3
3
3
3
3
FS0
(INPUTS)
(32)
I/O PORTS (PORT A,B,C,F)
PGR0 -PGR7
8 FLASH MEMORY
SECTOR SELECTS
(8)
(16)
(4)
[
]
A 15:0
*
[
]
PD 3:0 (ALE,CLKIN,CSI)
PDN (APD OUTPUT)
(1)
(3)
(1)
(1)
FS7
[
] (
CNTRL 2:0 READ/WRITE CONTROL SIGNALS)
RESET
RS0
3
SRAM SELECT
RD_BSY
CSIOP
I/O DECODER
SELECT
*NOTES: 1. The address inputs are A[19:4] in 80C51XA mode.
2. Additional address lines can be brought into PSD via Port A, B, C, C or F.
Preliminary Information
PSD4000 Series
Figure 11. The Micro Cell and I/O Port
P L D I N P U T B U S
35
PSD4000 Series
Preliminary Information
The
9.3 Microcontroller Bus Interface
The “no-glue logic” PSD4000 Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 16-bit microcontrollers with
their bus types and control signals are shown in Table 14. The MCU interface type is
specified using the PSDsoft.
PSD4000
Functional
Blocks
(cont.)
Table 14. Microcontrollers and their Control Signals
MCU
CNTL0
CNTL1
CNTL2
PD3
PD0**
ADIO0
PF3-PF0
68302, 68306
MMC2001
R/W
LDS
UDS
AS
–
*
*
68330, 68331
68332, 68340
R/W
DS
OE
SIZ0
AS
AS
A0
*
*
*
68LC302,
MMC2001
WEL
WEH
–
68HC16
68HC912
68HC812***
80196
R/W
R/W
R/W
WR
DS
E
SIZ0
LSTRB
LSTRB
BHE
AS
E
A0
A0
A0
A0
A0
A0
*
*
*
*
*
*
*
DBE
E
*
*
*
RD
RD
RD
ALE
80196SP
80186
WRL
WR
WRH
ALE
ALE
*
BHE
*
*
80C161
80C164-80C167
WR
RD
BHE
ALE
A0
*
80C51XA
H8/3044
WRL
WRL
R/W
RD
RD
E
PSEN
WRH
WRH
ALE
AS
A4/D0
A0
A3-A1
–
*
M37702M2
BHE
ALE
A0
*
*
***Unused CNTL2 pin can be configured as GPLD input. Other unused pins (PD3-0, PF3-0) can be
***configured for other I/O functions.
***ALE/AS input is optional for microcontrollers with a non-multiplexed bus.
***This configuration is for 68C812A4_EC at 5MHz, 3V only.
9.3.1. PSD4000 Interface to a Multiplexed Bus
Figure 16 shows an example of a system using a microcontroller with a 16-bit multiplexed
bus and a PSD4000. The ADIO port on the PSD4000 is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port E, F or G. The PSD4000 drives the ADIO data bus
only when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or F may be used as additional
address inputs.
9.3.2. PSD4000 Interface to a Non-Multiplexed Bus
Figure 17 shows an example of a system using a microcontroller with a 16-bit
non-multiplexed bus and a PSD4000. The address bus is connected to the ADIO Port, and
the data bus is connected to Port F and G. Port F and G are in tri-state mode when the
PSD4000 is not accessed by the microcontroller. Should the system address bus exceed
sixteen bits, Ports A, B or C may be used for additional address inputs.
36
Preliminary Information
PSD4000 Series
The
Figure 12. An Example of a Typical 16-Bit Multiplexed Bus Interface
PSD4000
Functional
Blocks
(cont.)
PSD4135G2
[
]
AD 7:0
MICRO-
CONTROLLER
[
]
A 7:0
PORT
F
(
(
)
)
OPTIONAL
ADIO
PORT
[
]
AD 15:8
[
]
A 15:8
PORT
G
OPTIONAL
(
)
WR
RD
WR CNTRL0
(
)
RD CNTRL1
PORT
A,B, or
C
(
)
[
]
BHE
BHE CNTRL2
A 23:16
(
)
OPTIONAL
RST
ALE
(
)
ALE PD0
PORT D
RESET
Figure 13. An Example of a Typical 16-Bit Non-Multiplexed Bus Interface
PSD4135G2
[
]
D 15:0
[
]
D 7:0
PORT
F
MICRO-
ADIO
CONTROLLER
PORT
[
]
A 15:0
[
]
D 15:8
PORT
G
(OPTIONAL)
(
)
WR
RD
WR CNTRL0
(
)
RD CNTRL1
[
]
A 23:16
PORT
A,B or
C
(
)
BHE
BHE CNTRL2
RST
(OPTIONAL)
ALE
(
)
ALE PD0
PORT D
RESET
37
PSD4000 Series
Preliminary Information
9.3.3 Data Byte Enable Reference
The
Microcontrollers have different data byte orientations. The following tables show how the
PSD4135G2 interprets byte/word operation in different bus write configurations. Even-byte
refers to locations with address A0 equal to zero and odd byte as locations with A0 equal
to one.
PSD4000
Functional
Blocks
(cont.)
9.3.4 Microcontroller Interface Examples
Figures 14 through 17 show examples of the basic connections between the PSD4135G2
and some popular microcontrollers. The PSD4135G2 Control input pins are labeled as the
microcontroller function for which they are configured. The MCU interface is specified using
PSDsoft. The PE6 pin should be grounded if Vstby is not used.
9.3.4.1 80C196 and 80C186
In Figure 14, the Intel 80C196 microcontroller, which has a multiplexed sixteen-bit bus, is
shown connected to a PSD4135G2. The WR and RD signals are connected to the
CNTL0-1 pins. The BHE signal is used for high data byte selection. If BHE is not used, the
PSD can be configured to receive the WRL and WRH from the MCU. Higher address
inputs (A16-A19) can be routed to Port A, B or C as inputs to the PLD.
The AMD 80186 family has the same bus connection to the PSD as the 80C196.
Table 15. 16-Bit Data Bus with BHE
BHE
A0
D15-D8
D7-D0
0
0
1
0
1
0
Odd Byte
Odd Byte
–
Even Byte
–
Even Byte
Table 16. 16-Bit Data Bus with WRH and WRL
WRH
WRL
D15-D8
D7-D0
0
0
1
0
1
0
Odd Byte
Odd Byte
–
Even Byte
–
Even Byte
Table 17. 16-Bit Data Bus with SIZ0, A0 (Motorola MCU)
SIZ0
A0
D15-D8
D7-D0
0
1
1
0
0
1
Even Byte
Even Byte
–
Odd Byte
–
Odd Byte
Table 18. 16-Bit Data Bus with UDS, LDS (Motorola MCU)
LDS
UDS
D15-D8
D7-D0
0
1
0
0
0
1
Even Byte
Even Byte
–
Odd Byte
–
Odd Byte
38
Preliminary Information
PSD4000 Series
9.3.4.2 MC683XX and 68HC16
The
Figure 15 shows a Motorola MC68331 with non-multiplexed sixteen-bit data bus and 24-bit
address bus. The data bus from the MC68331 is connected to Port F (D0-7) and Port G
(D8-D15). The SIZ0 and A0 inputs determine the high/low byte selection. The R/W, DS
and SIZ0 are connected to the CNTL0-2 pins.
PSD4000
Functional
Blocks
(cont.)
The 68HC16 and other members of the 683XX family have the same connection as the
68331 shown in Figure 15.
9.3.4.3 80C51XA
The Philips 80C51XA microcontroller has a 16-bit multiplexed bus with burst cycles.
Address bits A[3:1] are not multiplexed while A[19:4] are multiplexed with data bits D[15:0].
The PSD4135G2 supports the 80C51XA burst mode. The WRH signal is connected to the
PD3 and the WRL is connected to CNTL0 pin. The RD and PSEN signal is connected to
CNTL1-2 pins. Figure 15 shows the XA schematic.
The 80C51XA improves bus throughput and performance by issuing Burst cycles to fetch
codes from memory. In Burst cycles, addresses A19-4 are latched internally by the PSD,
while the 80C51XA drives the A3-1 lines to sequentially fetch up to 16 bytes of code. The
PSD access time is then measured from address A3-A1 valid to data in valid. The PSD
bus timing requirement in Burst cycle is identical to the normal bus cycle except the
address set up or hold time with respect to ALE is not required.
9.3.4.4 H8/300
Figure 16 shows a Hitachi H8/2350 with non-multiplexed sixteen-bit data bus and 24-bit
address bus. The H8 data bus is connected to Port F (D0-7) and Port G (D8-15).
The WRL, WRH and RD signals are connected to the CNTL0, PD3 and CNTL1 pins
respectively. The AS connection is optional and is required if the address are to be
latched.
9.3.4.5 MMC2001
The Motorola MCORE MMC2001 microcontroller has a MOD input pin that selects internal
or external boot ROM. The PSD4000 can be configured as the external flash boot ROM or
as extension to the internal ROM.
The MMC2001 has a 16-bit external data bus and 20 address lines with external Chip
Select signals. The Chip Select Control Registers allow the user to customize the bus
interface and timing to fit the individual system requirement. A typical interface configura-
tion to the PSD4000 is shown in Figure 18. The MMC2001’s R/W signal is connected to
the cntl0 pin, while EB0 and EB1 (enable byte0 and byte1) are connected to the cntl1
(UDS) and cntl2 (LDS) pins. The WEN bit in the Chip Select Control Register should set to
1 to terminate the EB[0:1] earlier to provide the write data hold time for the PSD. The WSC
and WWS bits in the Control Register are set to wait states that meet the PSD access time
requirement.
Another option is to configure the EB0 and EB1 as WRL and WRH signals. In this case the
PSD4000 control setting will be: OE, WRL, WRH where OE is the read signal from the
MMC2001.
9.3.4.6 C16X Family
The PSD4000 supports Infineon’s C16X family of microcontrollers (C161-C167) in both the
multiplexed and non-multiplexed bus configuration. In Figure 19 the C167CR is shown
connected to the PSD4000 in a multiplexed bus configuration. The control signals from the
MCU are WR, RD, BHE and ALE and are routed to the corresponding PSD pins.
The C167 has another control signal setting (RD, WRL, WRH, ALE) which is also
supported by the PSD4000.
39
PSD4000 Series
Preliminary Information
Figure 14. Interfacing the PSD4135G2 with an 80C196
40
Preliminary Information
PSD4000 Series
Figure 15. Interfacing the PSD4135G2 with an MC68331
41
PSD4000 Series
Preliminary Information
Figure 16. Interfacing the PSD4135G2 with a 80C51XA-G3
42
Preliminary Information
PSD4000 Series
Figure 17. Interfacing a PSD4135G2 with a H83/2350
43
PSD4000 Series
Preliminary Information
Figure 18. Interfacing a PSD4135G2 with a MMC2001
J G N D
1 3 8
J V D D
1 3 7
Q G N D
1 3 4
Q V C C
1 3 3
Q V C C H
1 2 7
H G N D
1 2 3
H V D D
1 2 2
G G N D 1
1 1 1
G V D D 1
1 1 0
G G N D 0
9 8
G V D D 0
9 9
44
Preliminary Information
PSD4000 Series
Figure 19. Interfacing a PSD4135G2 with a C167R
45
PSD4000 Series
Preliminary Information
The
9.4 I/O Ports
There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each of the ports
is eight bits except Port D, which is 4 bits. Each port pin is individually user configurable,
thus allowing multiple functions per port. The ports are configured using PSDsoft or by the
microcontroller writing to on-chip registers in the CSIOP address space.
PSD4000
Functional
Blocks
(cont.)
The topics discussed in this section are:
• General Port Architecture
• Port Operating Modes
• Port Configuration Registers
• Port Data Registers
• Individual Port Functionality.
9.4.1 General Port Architecture
The general architecture of the I/O Port is shown in Figure 20. Individual Port architectures
are shown in Figures 21 through 23. In general, once the purpose for a port pin has been
defined, that pin will no longer be available for other purposes. Exceptions will be noted.
As shown in Figure 20, the ports contain an output multiplexer whose selects are driven
by the configuration bits in the Control Registers (Ports E, F and G only) and PSDsoft
Configuration. Inputs to the multiplexer include the following:
❏ Output data from the Data Out Register
❏ Latched address outputs
❏ GPLD outputs (External Chip Selects)
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The PDB is connected to the Internal Data Bus for feedback and can be read by the
microcontroller. The Data Out and Micro Cell outputs, Direction and Control Registers,
and port pin input are all connected to the PDB.
The contents of these registers can be altered by the microcontroller. The PDB feedback
path allows the microcontroller to check the contents of the registers.
9.4.2 Port Operating Modes
The I/O Ports have several modes of operation. Some modes can be defined using
PSDsoft, some by the microcontroller writing to the Registers in CSIOP space, and some
by both. The modes that can only be defined using PSDsoft must be programmed into the
device and cannot be changed unless the device is reprogrammed. The modes that can be
changed by the microcontroller can be done so dynamically at run-time. The PLD I/O,
Data Port, Address Input, and MCU Reset modes are the only modes that must be defined
before programming the device. All other modes can be changed by the microcontroller at
run-time.
Table 16 summarizes which modes are available on each port. Table 19 shows how and
where the different modes are configured. Each of the port operating modes are described
in the following subsections.
46
Preliminary Information
PSD4000 Series
The
Table 16. Port Operating Modes
PSD4000
Functional
Blocks
(cont.)
Port Mode
Port A Port B Port C Port D Port E Port F Port G
MCU I/O
Yes
Yes
Yes
No
Yes
Yes
Yes
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
PLD Outputs
PLD Inputs
Address Out
Yes
No
No
Yes
No
Yes
Yes
Yes
(A7-0)
or
(A7-0)
(A7-0)
(A15-8)
Address In
Yes
No
No
No
Yes
No
No
No
Yes
No
No
No
Yes
No
No
No
No
No
Yes
Yes
No
No
Yes
No
Data Port
JTAG ISP
Yes
No
MCU Reset Mode*
Yes
Yes
*Available to Motorola 16-bit 683XX and HC16family of MCUs.
Figure 20. General I/O Port Architecture
I N T E R N A L D A T A B U S
47
PSD4000 Series
Preliminary Information
Table 17. Port Operating Mode Settings
The
PSD4000
Functional
Blocks
(cont.)
Control
Register
Setting
Direction
Register
Setting
VM
Register
Setting
Defined In
PSDsoft
Mode
Declare
pins only
0
1 = output,
0 = input
MCU I/O
(Note 1)
NA
NA
Declare pins
and logic or chip
select equations
PLD I/O
NA
Selected for
MCU with
non-mux bus
Data Port
(Port F, G)
NA
1
NA
1
NA
NA
Address Out
(Port E, F, G)
Declare
pins only
Address In
Declare pins
(Port A,B,C,D,F)
NA
NA
NA
NA
NA
NA
Declare pins
only
JTAG ISP
MCU Reset
Mode
Specify pin
logic level
NA
NA
NA
*NA = Not Applicable
NOTE: 1. Control Register setting is not applicable to Ports A, B and C.
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD4000 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD4000 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register (Port E, F and G). The MCU I/O direction may be changed by writing
to the corresponding bit in the Direction Register. See the subsection on the Direction
Register in the “Port Registers” section. When the pin is configured as an output, the
content of the Data Out Register drives the pin. When configured as an input, the
microcontroller can read the port input through the Data In buffer. See Figure 20.
Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.
They can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro Cells, and/or
as an output from the GPLD. The corresponding bit in the Direction Register must not be
set to ‘1’ if the pin is defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified
in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft.
48
Preliminary Information
PSD4000 Series
9.4.2.3 Address Out Mode
The
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a ‘1’ for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 18 for the address output pin assignments on
Ports E, F and F for various MCUs.
PSD4000
Functional
Blocks
(cont.)
Note: Do not drive address lines with Address Out Mode to an external memory device if
it is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
Table 18. I/O Port Latched Address Output Assignments
MCU
Port E (3:0) Port E (7:4) Port F (3:0) Port F (7:4) Port G (3:0) Port G (7:4)
80C51XA
N/A
Addr (7:4)
Addr (7:4)
N/A
Addr (7:4)
Addr (7:4)
Addr (11:8) Addr (15:12)
All Other
MCU with
Multiplexed
Bus
Addr (3:0)
Addr (3:0)
Addr (11:8) Addr (15:12)
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Ports A, B, C, D or F and are routed as inputs to the PLDs. The address
input can be latched by the address strobe (ALE/AS). Any input that is included in the
DPLD equations for the Main Flash, Boot Flash, or SRAM is considered to be an address
input.
9.4.2.5 Data Port Mode
Port F and G can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port F and G if the ports are configured as Data Port.
Data Port Mode is automatically configured in PSDsoft when a non-multiplexed bus MCU
is selected.
9.4.2.6 JTAG ISP
Port E is JTAG compliant, and can be used for In-System Programming (ISP).
9.4.2.7 MCU Reset Mode
Port F and G can be configured to operate in “MCU Reset” mode. This mode is available
when PSD is configured for the Motorola 16-bit 683XX and HC16 family and is active only
during reset.
At the rising edge of the Reset input, the MCU reads the logic level on the Data Bus D15-0
pins. The MCU then configures some of its I/O pin functions according to the logic level
input on the data bus lines. Two dedicated buffers are usually enabled during reset to drive
the data bus lines to the desired logic level.
The PSD4135G2 can replace the two buffers by configuring Port F and G to operate in
MCU Reset Mode. In this mode, the PSD will drive the pre-defined logic level or data
pattern onto the MCU Data Bus when reset is active and there is no ongoing bus cycle.
After reset, Port F and G return to the normal Data Port Mode.
The MCU Reset Mode is enabled and configured in PSDsoft. The user defines the logic
level (data pattern) that will be driven out from Port F and G during reset.
49
PSD4000 Series
Preliminary Information
9.4.3 Port Configuration Registers (PCRs)
The
Each port has a set of PCRs used for configuration. The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the
CSIOP register.
PSD4000
Functional
Blocks
(cont.)
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
shown in Table 19, are used for setting the port configurations. The default power-up state
for each register in Table 22 is 00h.
Table 19. Port Configuration Registers
Register Name
Port
MCU Access
Control
E,F,G
Write/Read
Write/Read
Write/Read
Direction
Drive Select*
A,B,C,D,E,F,G
A,B,C,D,E,F,G
*NOTE: See Table 22 for Drive Register bit definition.
9.4.3.1 Control Register
Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,
and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and
G have an associated Control Register.
9.4.3.2 Direction Register
The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to ‘1’
in the Direction Register will cause the corresponding pin to be an output, and any bit set
to ‘0’ will cause it to be an input. The default mode for all port pins is input.
Figures 21 and 23 show the Port Architecture diagrams for Ports A/B/C and E/F/G
respectively. The direction of data flow for Ports A, B, C and F are controlled by the
direction register.
An example of a configuration for a port with the three least significant bits set to output
and the remainder set to input is shown in Table 21. Since Port D only contains four pins,
the Direction Register for Port D has only the four least significant bits active.
Table 20. Port Pin Direction Control
Direction Register Bit
Port Pin Mode
Input
0
1
Output
Table 21. Port Direction Assignment Example
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
50
Preliminary Information
PSD4000 Series
9.4.3.3 Drive Select Register
The
The Drive Select Register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should
be used for pins configured as Open Drain.
PSD4000
Functional
Blocks
(cont.)
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register
is set to a ‘1’. The default pin drive is CMOS.
Aside: the slew rate is a measurement of the rise and fall times of an output. A higher
slew rate means a faster output response and may create more electrical noise. A pin
operates in a high slew rate when the corresponding bit in the Drive Register is set to ‘1’.
The default rate is slow slew.
Table 22 shows the Drive Register for Ports A, B, C, D, E, F and G. It summarizes which
pins can be configured as Open Drain outputs and which pins the slew rate can be set for.
Table 22. Drive Register Pin Assignment
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port B
Port C
Port D
Port E
Port F
Port G
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
9.4.4 Port Data Registers
The Port Data Registers, shown in Table 23, are used by the microcontroller to write data
to or read data from the ports. Table 23 shows the register name, the ports having each
register type, and microcontroller access for each register type. The registers are
described below.
9.4.4.1 Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input
is read through the Data In buffer.
9.4.4.2 Data Out Register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
Register are driven out to the pins if the Direction Register or the output enable
product term is set to “1”. The contents of the register can also be read back by the
microcontroller.
Table 27. Port Data Registers
Register Name
Data In
Port
MCU Access
Read – input on pin
Write/Read
A,B,C,D,E,F,G
A,B,C,D,E,F,G
Data Out
51
PSD4000 Series
Preliminary Information
The
9.4.5 Ports A, B and C – Functionality and Structure
Ports A and B have similar functionality and structure, as shown in Figure 21. The two
ports can be configured to perform one or more of the following functions:
PSD4000
Functional
Blocks
(cont.)
❏ MCU I/O Mode
❏ GPLD Output – Combinatorial PLD outputs.
❏ PLD Input
– Input to the PLDs.
❏ Address In – Additional high address inputs may be latched by ALE.
❏ Open Drain/Slew Rate – pins PC[7:0]can be configured to fast slew rate,
pins PA[7:0] and PB[7:0] can be configured to Open Drain
Mode.
Figure 21. Port A, B and C
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT PIN
OUTPUT
MUX
GPLD OUTPUT
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
DIR REG.
D
Q
WR
PLD INPUT
52
Preliminary Information
PSD4000 Series
The
9.4.6 Port D – Functionality and Structure
Port D has four I/O pins. See Figure 22. Port D can be configured to program one or more
of the following functions:
PSD4000
Functional
Blocks
(cont.)
❏ MCU I/O Mode
❏ PLD Input – direct input to PLD
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
❏ PD0 – ALE, as address strobe input
❏ PD1 – CLKIN, as clock input to the PLD and APD counter
❏ PD2 – CSI, as active low chip select input. A high input will disable the
Flash/SRAM and CSIOP.
❏ PD3 – WRH, as active low Write Enable (high byte) input or as DBE input from
68HC912
9.4.7 Port E – Functionality and Structure
Port E can be configured to perform one or more of the following functions (see Figure 23):
❏ MCU I/O Mode
❏ In-System Programming – JTAG port can be enabled for programming/erase of the
PSD4000 device. (See Section 9.6 for more information on JTAG programming.)
Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O
functions.
❏ Open Drain – Port E pins can be configured in Open Drain Mode
❏ Battery Backup features – PE6 can be configured as a Battery Input (Vstby) pin.
PE7 can be configured as a Battery On Indicator output
pin, indicating when Vcc is less than Vbat.
❏ Latched Address Output – Provided latched address (A7-0) output
Figure 22. Port D Structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT D PIN
OUTPUT
MUX
READ MUX
OUTPUT
SELECT
P
D
B
DATA IN
DIR REG.
D
Q
WR
PLD INPUT
53
PSD4000 Series
Preliminary Information
The
9.4.8 Port F – Functionality and Structure
Port F can be configured to perform one or more of the following functions:
PSD4000
Functional
Blocks
(cont.)
❏ MCU I/O Mode
❏ PLD Input – as direct input ot the PLD array.
❏ Address In – additional high address inputs. Direct input to the PLD array.
❏ Latched Address Out – Provide latched address out per Table 29.
❏ Slew Rate – pins can be set up for fast slew rate.
❏ Data Port – connected to D[7:0] when Port F is configured as Data Port for a
non-multiplexed bus.
❏ MCU Reset Mode – for 16-bit Motorola 683XX and HC16 microcontrollers.
9.4.9 Port G – Functionality and Structure
Port G can be configured to perform one or more of the following functions:
❏ MCU I/O Mode
❏ Latched Address Out – provide latched address out per Table 29.
❏ Open Drain – pins can be configured in Open Drain Mode
❏ Data Port – connected to D[15:8] when Port G is configured as Data Port for a
non-multiplexed bus.
❏ MCU Reset Mode – for 16-bit Motorola 683XX and HC16 microcontrollers
Figure 23. Ports E, F and G Structure
DATA OUT
REG.
DATA OUT
D
Q
WR
ADDRESS
ALE
ADDRESS
PORT PIN
D
G
Q
[
]
[
]
A 7:0 OR A 15:8
OUTPUT
MUX
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
CONTROL REG.
D
Q
WR
WR
DIR REG.
D
Q
PLD INPUT (PORT F)
ISP OR BATTERY BACK-UP (PORT E)
CONFIGURATION
BIT
54
Preliminary Information
PSD4000 Series
The
9.5 Power Management
The PSD4000 offers configurable power saving options. These options may be used
individually or in combinations, as follows:
PSD4000
Functional
Blocks
(cont.)
❏ All memory types in a PSD (Flash, Secondary Flash, and SRAM) are built with
Zero-Power technology. In addition to using special silicon design methodology,
Zero-Power technology puts the memories into standby mode when address/data
inputs are not changing (zero DC current). As soon as a transition occurs on an input,
the affected memory “wakes up”, changes and latches its outputs, then goes back to
standby. The designer does not have to do anything special to achieve memory
standby mode when no inputs are changing—it happens automatically.
The PLD sections can also achieve standby mode when its inputs are not changing,
see PMMR registers below.
❏ Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The APD will block MCU address/data signals
from reaching the memories and PLDs. This feature is available on all PSD4000
devices. The APD unit is described in more detail in section 9.5.1.
Built in logic will monitor the address strobe of the MCU for activity. If there is no
activity for a certain time period (MCU is asleep), the APD logic initiates Power Down
Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked
from reaching PSD memories and PLDs, and the memories are deselected internally.
This allows the memories and PLDs to remain in standby mode even if the
address/data lines are changing state externally (noise, other devices on the MCU
bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states
keeps the PLD out of standby mode, but not the memories.
❏ The PSD Chip Select Input (CSI) can be used to disable the internal memories,
placing them in standby mode even if inputs are changing. This feature does not block
any internal signals or disable the PLDs. This is a good alternative to using the APD
logic, especially if your MCU has a chip select output. There is a slight penalty in
memory access time when the CSI signal makes its initial transition from deselected
to selected.
❏ The PMMR registers can be written by the MCU at run-time to manage power. All PSD
devices support “blocking bits” in these registers that are set to block designated
signals from reaching both PLDs. Current consumption of the PLDs is directly related
to the composite frequency of the changes on their inputs (see Figures 27 and 27a).
Significant power savings can be achieved by blocking signals that are not used in
PLD logic equations at run time. PSDsoft creates a fuse map that automatically blocks
the low address byte (A7-A0) or the control signals (CNTL0-2, ALE and WRH/DBE) if
none of these signals are used in PLD logic equations.
The PSD4000 devices have a Turbo Bit in the PMMR0 register. This bit can be set to
disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is
disabled, the PLDs can achieve standby current when no PLD inputs are changing
(zero DC current). Even when inputs do change, significant power can be saved at
lower frequencies (AC current), compared to when Turbo Mode is enabled. Conversely,
when the Turbo Mode is enabled, there is a significant DC current component and the
AC component is higher.
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode
The APD Unit, shown in Figure 24, puts the PSD into Power Down Mode by monitoring
the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity
on the address strobe stops, a four bit counter starts counting. If the address strobe
remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN)
signal becomes active, and the PSD will enter into Power Down Mode, discussed next.
55
PSD4000 Series
Preliminary Information
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)
Power Down Mode
The
PSD4000
Functional
Blocks
(cont.)
By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.
The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive
for fifteen CLKIN (pin PD1) clock periods.
The following should be kept in mind when the PSD is in Power Down Mode:
• If the address strobe starts pulsing again, the PSD will return to normal operation.
The PSD will also return to normal operation if either the CSI input returns low or the
Reset input returns high.
• The MCU address/data bus is blocked from all memories and PLDs.
• Various signals can be blocked (prior to Power Down Mode) from entering the PLDs
by setting the appropriate bits in the PMMR registers. The blocked signals include
MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from
the PLDs will not block CLKIN from the APD unit.
• All PSD memories enter Standby Mode and are drawing standby current. However,
the PLDs and I/O ports do not go into Standby Mode because you don’t want to
have to wait for the logic and I/O to “wake-up” before their outputs can change. See
Table 24 for Power Down Mode effects on PSD ports.
• Typical standby current is 50 µA for 5 V parts. This standby current value assumes
that there are no transitions on any PLD input.
Table 24. Power Down Mode’s Effect on
Ports
Port Function
MCU I/O
Pin Level
No Change
No Change
Undefined
PLD Out
Address Out
Data Port
Three-State
Three-State
Peripheral I/O
Table 25. PSD4000 Timing and Standby Current During Power
Down Mode
Access
Recovery Time
to Normal
Access
5V V ,
CC
PLD
Propagation
Delay
Memory
Access
Time
Typical
Standby
Current
Mode
Normal tpd
(Note 1)
50 µA
(Note 2)
Power Down
No Access
tLVDV
NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this
mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and
the PLD Turbo bit is off.
56
Preliminary Information
PSD4000 Series
The
Figure 24. APD Logic Block
PSD4000
Functional
Blocks
(cont.)
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
PD
CLR
APD
SECONDARY
FLASH SELECT
COUNTER
RESET
MAIN FLASH SELECT
EDGE
DETECT
PD
CSI
PLD
SRAM SELECT
POWER DOWN
CLKIN
(
)
PDN SELECT
DISABLE MAIN AND
SECONDARY FLASH/SRAM
Figure 25. Enable Power Down Flow Chart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bit 4
and PMMR2 bits 0.
ALE/AS idle
for 15 CLKIN
clocks?
No
Yes
PSD in Power
Down Mode
57
PSD4000 Series
Preliminary Information
The
Table 26. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
PSD4000
Functional
Blocks
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLD
Array clk
PLD
Turbo
APD
Enable
*
*
*
*
*
1 = off
1 = off
1 = on
***Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1.
***The PMMR0, and PMMR2 register bits are cleared to zero following power up.
***Subsequent reset pulses will not clear the registers.
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
PMMR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLD
array
WRH/DBE
PLD
array
ALE
PLD**
array
CNTL2
PLD**
array
CNTL1
PLD**
array
CNTL0
PLD
array
Addr.
*
*
1 = off
1 = off
1 = off
1 = off
1 = off
1 = off
**Unused bits should be set to 0.
**Refer to Table 14 the signals that are blocked on pins CNTL0-2.
Bit 0 0 = Address A[7:0] inputs to the PLD AND array are connected.
1 = Address A[7:0] inputs to the PLD AND array are disconnected, saving power.
Note: In 80C51XA mode, A[7:1] comes from Port F (PF1-PF3) and AD10 [3:0].
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
Bit 5 0 = ALE input to the PLD AND array is connected.
1 = ALE input to PLD AND array is disconnected, saving power.
Bit 6 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to PLD AND array is disconnected, saving power.
58
Preliminary Information
PSD4000 Series
The
Table 27. APD Counter Operation
APD ALE
PSD4000
Functional
Blocks
(cont.)
Enable Bit PD Polarity ALE Level
APD Counter
0
1
1
1
X
X
1
0
X
Not Counting
Not Counting
Pulsing
1
0
Counting (Generates PDN after 15 Clocks)
Counting (Generates PDN after 15 Clocks)
9.5.2 Other Power Saving Options
The PSD4000 offers other reduced power saving options that are independent of the
Power Down Mode. Except for the SRAM Standby and CSI input features, they are
enabled by setting bits in the PMMR0 and PMMR2 registers.
9.5.2.1 Zero Power PLD
The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0.
By setting the bit to “1”, the Turbo mode is disabled and the PLDs consume Zero Power
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time will be increased after the Turbo bit is set to “1” (turned off) when the inputs
change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a “0”
(turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s D.C.
power, AC power, and propagation delay. Refer to AC/DC spec for PLD timings.
Note: Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power
consumption.
9.5.2.2 SRAM Standby Mode (Battery Backup)
The PSD4000 supports a battery backup operation that retains the contents of the SRAM
in the event of a power loss. The SRAM has a Vstby pin (PE6) that can be connected to
an external battery. When V becomes lower than Vstby then the PSD will automatically
CC
connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
typically 0.5 µA. The SRAM data retention voltage is 2 V minimum. The battery-on
indicator (Vbaton) can be routed to PE7. This signal indicates when the V has dropped
CC
below the Vstby voltage and that the SRAM is running on battery power.
9.5.2.3 The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal
selects and enables the internal Flash, Boot Block, SRAM, and I/O for read or write
operations involving the PSD4000. A high on the CSI pin will disable the Flash memory,
Boot Block, and SRAM, and reduce the PSD power consumption. However, the PLD and
I/O pins remain operational when CSI is high. Note: there may be a timing penalty when
using the CSI pin depending on the speed grade of the PSD that you are using. See the
timing parameter t
in the AC/DC specs.
SLQV
9.5.2.4 Input Clock
The PSD4000 provides the option to turn off the CLKIN input to the PLD AND array to
save AC power consumption. During Power Down Mode, or, if the CLKIN input is not
being used as part of the PLD logic equation, the clock should be disabled to save AC
power. The CLKIN will be disconnected from the PLD AND array by setting bit 4 to a “1”
in PMMR0.
9.5.2.5 MCU Control Signals
The PSD4000 provides the option to turn off the address input (A7-0) and input control
signals (CNTL0-2, ALE, and WRH/DBE) to the PLD to save AC power consumption. These
signals are inputs to the PLD AND array. During Power Down Mode, or, if any of them are
not being used as part of the PLD logic equation, these control signals should be disabled
to save AC power. They will be disconnected from the PLD AND array by setting bits 0, 2,
3, 4, 5, and 6 to a “1” in the PMMR2.
59
PSD4000 Series
Preliminary Information
The
9.5.3 Reset and Power On Requirement
PSD4000
Functional
Blocks
(cont.)
9.5.3.1 Power On Reset
Upon power up the PSD4000 requires a reset pulse of tNLNH-PO (minimum 1 ms) after
is steady. During this time period the device loads internal configurations, clears
V
CC
some of the registers and sets the Flash into operating mode. After the rising edge of
reset, the PSD4000 remains in the reset state for an additional tOPR (maximum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD4000 Flash memory is reset to the read array mode upon power up. The FSi
and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove
the possibility of data being written on the first edge of a write strobe signal. Any Flash
memory write cycle initiation is prevented automatically when V is below VLKO.
CC
9.5.3.2 Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 26 shows the timing of the power on and warm reset.
Figure 26. Power On and Warm Reset Timing
OPERATING LEVEL
t
t
NLNH
NLNH-A
t
NLNH–PO
V
CC
RESET
t
t
OPR
OPR
WARM
RESET
POWER ON RESET
9.5.3.3 I/O Pin, Register and PLD Status at Reset
Table 28 shows the I/O pin, register and PLD status during power on reset, warm reset
and power down mode. PLD outputs are always valid during warm reset, and they are
valid in power on reset once the internal PSD configuration bits are loaded. This loading of
PSD is completed typically long before the V ramps up to operating level. Once the PLD
CC
is active, the state of the outputs are determined by the equations specified in PSDsoft.
60
Preliminary Information
PSD4000 Series
The
Table 28. Status During Power On Reset, Warm Reset and Power Down Mode
PSD4000
Functional
Blocks
(cont.)
Port Configuration Power On Reset
Warm Reset
Input Mode
Valid
Power Down Mode
Unchanged
MCU I/O
Input Mode
PLD Output
Valid after internal
PSD configuration
bits are loaded
Depend on inputs to
PLD (address are
blocked in PD mode)
Address Out
Data Port
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Not defined
Tri-stated
Register
PMMR0, 2
Power On Reset
Cleared to “0”
Warm Reset
Unchanged
Power Down Mode
Unchanged
VM Register*
Initialized based on
the selection in
PSDsoft
Initialized based on Unchanged
the selection in
PSDsoft
Configuration Menu.
Configuration Menu.
All other registers
Cleared to “0”
Cleared to “0”
Unchanged
*SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
9.5.3.4 Reset of Flash Erase and Programming Cycles
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 µs) time.
9.6 Programming In-Circuit using the JTAG-ISP Interface
The JTAG-ISP interface on the PSD4000 can be enabled on Port E (see Table 29). All
memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG-ISC interface. A blank part can be mounted on a printed
circuit board and programmed using JTAG-ISP.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note 54 for more details on JTAG In-System-Programming.
Table 29. JTAG Port Signals
Port E Pin
PE0
JTAG Signals
TMS
Description
Mode Select
Clock
PE1
TCK
PE2
TDI
Serial Data In
Serial Data Out
Status
PE3
TDO
PE4
TSTAT
TERR
PE5
Error Flag
61
PSD4000 Series
Preliminary Information
9.6.1 Standard JTAG Signals
The
The JTAG configuration bit (non-volatile) inside the PSD can be set by the user in the
PSDsoft. Once this bit is set and programmed in the PSD, the JTAG pins are dedicated to
JTAG at all times and is in compliance with IEEE 1149.1. After power up the standard
JTAG signals (TDI, TDO TCK and TMS) are inputs, waiting for a serial command from an
external JTAG controller device (such as FlashLink or Automated Test Equipment). When
the enabling command is received from the external JTAG controller, TDO becomes an
output and the JTAG channel is fully functional inside the PSD. The same command that
enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT
and TERR.
PSD4000
Functional
Blocks
(cont.)
The PSD4000 supports JTAG ISP commands, but not Boundary Scan. ST’s PSDsoft
software tool and FlashLink JTAG programming cable implement these JTAG-ISP
commands.
9.6.2 JTAG Extensions
TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received
over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed
programming and erase functions by indicating status on PSD pins instead of
having to scan the status out serially using the standard JTAG channel. See Application
Note 54.
TERR will indicate if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal will go low (active) when an error condition occurs, and stay
low until a special JTAG command is executed or a chip reset pulse is received after an
“ISC-DISABLE” command.
TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will
be high when the PSD4000 device is in read array mode (Flash memory and Boot Block
contents can be read). TSTAT will be low when Flash memory programming or erase
cycles are in progress, and also when data is being written to the Secondary Flash Block.
TSTAT and TERR can be configured as open-drain type signals with a JTAG command.
9.6.3 Security and Flash Memories Protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed.
All other program/erase/verify commands are blocked. Full chip erase returns the part to a
non-secured blank state. The Security Bit can be set in PSDsoft.
All Flash Memory and Boot sectors can individually be sector protected against erasures.
The sector protect bits can be set in PSDsoft.
62
Preliminary Information
PSD4000 Series
10.0
Symbol
Parameter
Storage Temperature
Condition
PLDCC
Min
– 65
0
Max
Unit
°C
°C
°C
V
Absolute
Maximum
Ratings
T
+ 125
+ 70
+ 85
+ 7
STG
Commercial
Operating Temperature
Voltage on any Pin
Industrial
– 40
– 0.6
With Respect to GND
Device Programmer
Supply Voltage
V
V
With Respect to GND
With Respect to GND
– 0.6
+ 14
+ 7
V
PP
CC
Supply Voltage
ESD Protection
– 0.6
V
V
>2000
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not recommended. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
11.0
Operating
Range
Range
Temperature
V
Tolerance
CC
Commercial
Industrial
0° C to +70°C
–40° C to +85°C
0° C to +70°C
+ 5 V ± 10%
+ 5 V ± 10%
3.0 V to 3.6 V
3.0 V to 3.6 V
Commercial
Industrial
–40° C to +85°C
12.0
Symbol
Parameter
Condition
Min
Typ Max
Unit
Recommended
Operating
Conditions
V
V
Supply Voltage
Supply Voltage
All Speeds
4.5
5
5.5
3.6
V
CC
CC
V-Versions
All Speeds
3.0
V
63
PSD4000 Series
Preliminary Information
The following tables describe the AD/DC parameters of the PSD4000 family:
AC/DC
Parameters
❏ DC Electrical Specification
❏ AC Timing Specification
• PLD Timing
– Combinatorial Timing
• Microcontroller Timing
– Read Timing
– Write Timing
– Power Down and Reset Timing
Following are issues concerning the parameters presented:
❏ In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that
the PSD4000 is in each mode. Also, the supply power is considerably different if the
Turbo bit is "OFF".
❏ The AC power component gives the PLD, Flash memory, and SRAM mA/MHz
specification. Figures 27 and 27a show the PLD mA/MHz as a function of the number
of Product Terms (PT) used.
❏ In the PLD timing parameters, add the required delay when Turbo bit is "OFF".
Figure 27. PLD I /FrequencyConsumption (V
= 5 V ± 10%)
CC
CC
110
100
90
V
CC
= 5V
80
70
60
50
40
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
64
Preliminary Information
PSD4000 Series
Figure 27a. PLD ICC/Frequency Consumption (PSD4135G2V Versions, VCC = 3 V)
AC/DC
Parameters
(cont.)
60
50
40
V
= 3V
CC
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
Example of PSD4000 Typical Power Calculation at V = 5.0 V
CC
Conditions
Highest Composite PLD input frequency
(Freq PLD)
=
=
8 MHz
4 MHz
MCU ALE frequency (Freq ALE)
% Flash Access
% SRAM access
% I/O access
=
=
=
80%
15%
5% (no additional power above base)
Operational Modes
% Normal
=
=
10%
90%
% Power Down Mode
Number of product terms used
(from fitter report)
=
=
45 PT
45/176 = 25.5%
% of total product terms
Turbo Mode
=
ON
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400 µA/PT
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+2 mA/MHz x 8 MHz
+ 45 x 0.4 mA/PT)
= 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA)
= 45 µA + 0.1 x 42.9
= 45 µA + 4.29 mA
= 4.34 mA
This is the operating power with no Flash writes or erases. Calculation is based
on IOUT = 0 mA.
65
PSD4000 Series
Preliminary Information
AC/DC
Example of Typical Power Calculation at V = 5.0 V in Turbo Off Mode
CC
Parameters
(cont.)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
=
=
8 MHz
MCU ALE frequency (Freq ALE)
4 MHz
% Flash Access
% SRAM access
% I/O access
=
=
=
80%
15%
5% (no additional power above base)
Operational Modes
% Normal
=
=
10%
90%
% Power Down Mode
Number of product terms used
(from fitter report)
=
=
45 PT
45/176 = 25.5%
% of total product terms
Turbo Mode
=
Off
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 24 mA)
= 45 µA + 0.1 x (8 + 0.9 + 24)
= 45 µA + 0.1 x 32.9
= 45 µA + 3.29 mA
= 3.34 mA
This is the operating power with no Flash writes or erases. Calculation is based
on IOUT = 0 mA.
66
Preliminary Information
PSD4000 Series
PSD4000 DC Characteristics (5 V ± 10% Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
VIH
Supply Voltage
All Speeds
4.5
5
5.5
VCC +.5
0.8
V
V
V
V
V
V
V
V
High Level Input Voltage
4.5 V < VCC < 5.5 V
4.5 V < VCC < 5.5 V
(Note 1)
2
–.5
VIL
Low Level Input Voltage
VIH1
VIL1
VHYS
VLKO
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
.8 VCC
–.5
VCC +.5
.2 VCC –.1
(Note 1)
0.3
VCC Min for Flash Erase and Program
2.5
4.2
0.1
I
OL = 20 µA, VCC = 4.5 V
IOL = 8 mA, VCC = 4.5 V
OH = –20 µA, VCC = 4.5 V
0.01
Output Low Voltage
VOL
0.25
4.49
0.45
V
V
I
4.4
VOH
Output High Voltage Except VSTBY On
IOH = –2 mA, VCC = 4.5 V
IOH1 = –1 µA
2.4
VSBY – 0.8
2.0
3.9
V
V
VOH
Output High Voltage VSTBY On
SRAM Standby Voltage
1
VSBY
ISBY
IIDLE
VDF
VCC
1
V
SRAM Standby Current (VSTBY Pin)
Idle Current (VSTBY Pin)
VCC = 0 V
0.5
µA
µA
V
VCC > VSBY
Only on VSTBY
–0.1
2
0.1
SRAM Data Retention Voltage
Standby Supply Current for Power
Down Mode
CSI > VCC –0.3 V
(Notes 2, 3 and 5)
ISB
100
200
µA
ILI
Input Leakage Current
Output Leakage Current
VSS < VIN < VCC
0.45 < VIN < VCC
–1
±.1
±5
1
µA
µA
ILO
–10
10
Refer to IOL and IOH in
the VOL and VOH row
IO
Output Current
PLD_TURBO = OFF,
f = 0 MHz (Note 3)
0
mA
µA/PT
mA
PLD Only
PLD_TURBO = ON,
f = 0 MHz
400
15
700
30
ICC (DC)
(Note 5)
Operating Supply
Current
During Flash Write/Erase
Only
Flash
Read Only, f = 0 MHz
f = 0 MHz
0
0
0
0
mA
mA
SRAM
Fig. 27
(Note 4)
PLD AC Base
ICC (AC)
(Note 5)
FLASH AC Adder
SRAM AC Adder
2.5
1.5
3.5
3.0
mA/MHz
mA/MHz
NOTE: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC
2. CSI deselected or internal Power Down mode is active.
3. PLD is in non-turbo mode and none of the inputs are switching
4. Refer to Figure 32 for PLD current calculation.
.
5. IO = 0 mA
67
PSD4000 Series
Preliminary Information
AC Symbols for PLD Timing.
Microcontroller
Interface –
AC/DC
Parameters
(5V ± 10% Versions)
Example: tAVLX – Time from Address Valid to ALE Invalid.
Signal Letters
A – Address Input
C – CEout Output
D – Input Data
E – E Input
I
– Interrupt Input
L – ALE Input
N – Reset Input or Output
P – Port Signal Output
R – UDS, LDS, DS, RD, PSEN Inputs
S – Chip Select Input
T – R/W Input
W – WR Input
B – Vstby Output
M – Output Micro Cell
Signal Behavior
t
– Time
L
H
V
X
Z
– Logic Level Low or ALE
– Logic Level High
– Valid
– No Longer a Valid Logic Level
– Float
PW – Pulse Width
68
Preliminary Information
PSD4000 Series
Microcontroller Interface – PSD4000 AC/DC Parameters
(5V ± 10% Versions)
Read Timing (5 V ± 10% Versions)
-70
-90
Turbo
Off
Symbol
tLVLX
Parameter
Conditions
Min Max Min Max
Unit
ns
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid
15
4
20
6
tAVLX
tLXAX
tAVQV
tSLQV
(Note 3)
(Note 3)
(Note 3)
ns
7
8
ns
70
75
24
90 Add 12** ns
100
32
ns
ns
(Note 5)
(Note 2)
tRLQV
RD or PSEN to Data Valid,
80C51XA Mode
31
38
25
ns
tRHQX
tRLRH
tRHQZ
tEHEL
tTHEH
tELTL
RD Data Hold Time
RD Pulse Width
(Note 1)
(Note 1)
(Note 1)
0
0
ns
ns
ns
ns
ns
ns
27
32
RD to Data High-Z
20
E Pulse Width
27
6
32
10
0
R/W Setup Time to Enable
R/W Hold Time After Enable
0
Address Input Valid to Address
Output Delay
tAVPV
(Note 4)
20
25
ns
NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD4000 function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
69
PSD4000 Series
Preliminary Information
Microcontroller Interface – PSD4000 AC/DC Parameters
(5V ± 10% Versions)
Write Timing (5 V ± 10% Versions)
-70
-90
Symbol
tLVLX
Parameter
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Conditions
Min Max Min Max Unit
15
4
20
6
tAVLX
(Note 1)
(Note 1)
ns
ns
tLXAX
7
8
Address Valid to Leading
Edge of WR
tAVWL
(Notes 1 and 3)
8
15
ns
tSLWL
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
(Note 3)
(Note 3)
(Note 3)
(Note 3)
12
25
4
15
35
5
ns
ns
ns
ns
tDVWH
tWHDX
tWLWH
WR Pulse Width
28
35
Trailing Edge of WR to Address
Invalid
tWHAX1
tWHAX2
tWHPV
tAVPV
(Note 3)
(Note 3 and 4)
(Note 3)
6
0
8
0
ns
ns
ns
ns
Trailing Edge of WR to DPLD
Address Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
27
20
30
25
Address Input Valid to Address
Output Delay
(Note 2)
NOTES: 1. Any input used to select an internal PSD4000 function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
4.
tWHAX2 is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
PLD Combinatorial Timing (5 V ± 10%)
-70
-90
Slew
Rate
(Note 1) Unit
TURBO
OFF
Symbol
Parameter
Conditions
Min Max Min
Max
PLD Input Pin/Feedback to
PLD Combinatorial Output
tPD
20
25
Add 12 Sub 2
ns
ns
tARD
PLD Array Delay
11
16
NOTE: 1. Fast Slew Rate output available on Port C and F.
70
Preliminary Information
PSD4000 Series
Microcontroller Interface – PSD4000 AC/DC Parameters
(5V ± 10% Versions)
Power Down Timing (5 V ± 10%)
-70
-90
Symbol
Parameter
Conditions
Min Max
Min Max Unit
ALE Access Time from
Power Down
tLVDV
80
90
ns
µs
Maximum Delay from APD Enable
to Internal PDN Valid Signal
Using CLKIN Input
15 * tCLCL (µs) (Note 1)
tCLWH
NOTE: 1. tCLCL is the CLKIN clock period.
V
stbyon
Timing (5 V ± 10%)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
Vstby Detection to Vstbyon Output High
(Note 1)
20
µs
V
Off Detection to V
stbyon
stby
Output Low
tBXBL
(Note 1)
20
µs
NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.
Reset Pin Timing (5 V ± 10%)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tNLNH
Warm RESET Active Low Time (Note 1)
RESET High to Operational Device
Power On Reset Active Low Time
150
ns
ns
tOPR
120
tNLNH-PO
1
ms
Warm RESET Active Low Time
(Note 2)
tNLNH-A
25
µs
NOTE: 1. RESET will not abort Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle.
71
PSD4000 Series
Preliminary Information
Microcontroller Interface – PSD4000 AC/DC Parameters
(5V ± 10% Versions)
Flash Program, Write and Erase Times (5 V ± 10%)
Symbol
Parameter
Flash Program
Min
Typ
Max
Unit
8.5
3
sec
sec
sec
sec
sec
µs
Flash Bulk Erase (Preprogrammed to 00) (Note 1)
Flash Bulk Erase
30
30
10
1
tWHQV3
tWHQV2
tWHQV1
Sector Erase (Preprogrammed to 00)
Sector Erase
2.2
14
Word Program
1200
Program/Erase Cycles (Per Sector)
Sector Erase Time-Out
100,000
cycles
µs
tWHWLO
tQ7VQV
100
DQ7 Valid to Output Valid
(Data Polling) (Notes 2 and 3)
30
ns
NOTE: 1. Programmed to all zeros before erase.
2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading.
3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus.
ISC Timing (5 V ± 10%)
-70
-90
Symbol
Parameter
Conditions
Min Max
Min Max Unit
tISCCF
TCK Clock Frequency (except for PLD)
TCK Clock High Time
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
20
18
MHz
ns
tISCCH
23
23
2
26
26
tISCCL
TCK Clock Low Time
ns
tISCCF-P
tISCCH-P
tISCCL-P
tISCPSU
tISCPH
TCK Clock Frequency (for PLD only)
TCK Clock High Time (for PLD only)
TCK Clock Low Time (for PLD only)
ISC Port Set Up Time
2
MHz
ns
240
240
6
240
240
8
ns
ns
ISC Port Hold Up Time
5
5
ns
tISCPCO
tISCPZV
ISC Port Clock to Output
21
21
23
23
ns
ISC Port High-Impedance to Valid Output
ns
ISC Port Valid Output to
High-Impedance
tISCPVZ
21
23
ns
NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode.
2. For program or erase PLD only.
72
Preliminary Information
PSD4000 Series
PSD4000 DC Characteristics (3.0 V to 3.6 V Versions) Advance Information
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
VIH
Supply Voltage
All Speeds
3.0
.7 VCC
–.5
3.6
VCC +.5
0.8
V
V
V
V
V
V
V
V
High Level Input Voltage
3.0 V < VCC < 3.6 V
3.0 V < VCC < 3.6 V
(Note 1)
VIL
Low Level Input Voltage
VIH1
VIL1
VHYS
VLKO
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
.8 VCC
–.5
VCC +.5
.2 VCC –.1
(Note 1)
0.3
VCC Min for Flash Erase and Program
1.5
2.3
0.1
I
OL = 20 µA, VCC = 3.0 V
IOL = 4 mA, VCC = 3.0 V
OH = –20 µA, VCC = 3.0 V
0.01
Output Low Voltage
VOL
0.15
2.99
0.45
V
V
I
2.9
VOH
Output High Voltage Except VSTBY On
IOH = –1 mA, VCC = 3.0 V
IOH1 = –1 µA
2.7
VSBY – 0.8
2.0
2.8
V
V
VOH
Output High Voltage VSTBY On
SRAM Standby Voltage
1
VSBY
ISBY
IIDLE
VDF
VCC
1
V
SRAM Standby Current (VSTBY Pin)
Idle Current (VSTBY Pin)
VCC = 0 V
0.5
µA
µA
V
VCC > VSBY
Only on VSTBY
–0.1
2
0.1
SRAM Data Retention Voltage
Standby Supply Current
for Power Down Mode
CSI >VCC –0.3 V
(Notes 2 and 3)
ISB
50
100
µA
ILI
Input Leakage Current
Output Leakage Current
VSS < VIN < VCC
0.45 < VIN < VCC
–1
±.1
±5
1
µA
µA
ILO
–10
10
Refer to IOL and IOH in
the VOL and VOH row
IO
Output Current
PLD_TURBO = OFF,
f = 0 MHz (Note 3)
0
mA
µA/PT
mA
PLD Only
PLD_TURBO = ON,
f = 0 MHz
200
10
400
25
ICC (DC)
(Note 5)
Operating
Supply Current
FLASH
During FLASH
Write/Erase Only
Read Only, f = 0 MHz
f = 0 MHz
0
0
0
0
mA
mA
SRAM
PLD AC Base
(Note 4)
Figure 27a
I
CC (AC)
FLASH
(Note 5)
AC Adder
1.5
0.8
2.0
1.5
mA/MHz
mA/MHz
SRAM AC Adder
NOTES: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC
2. CSI deselected or internal PD mode is active.
.
3. PLD is in non-turbo mode and none of the inputs are switching.
4. Refer to Figure 31a for PLD current calculation.
5. IO = 0 mA.
73
PSD4000 Series
Preliminary Information
AC Symbols for PLD Timing.
Microcontroller
Interface –
PSD4000
Example: tAVLX – Time from Address Valid to ALE Invalid.
Signal Letters
AC/DC
Parameters
(3.0 V to 3.6 V
A – Address Input
C – CEout Output
Versions)
D – Input Data
E – E Input
L – ALE Input
N – Reset Input or Output
P – Port Signal Output
Q – Output Data
R – WR, UDS, LDS, DS, IORD, PSEN Inputs
S – Chip Select Input
T – R/W Input
W – Internal PDN Signal
B – Vstby Output
Signal Behavior
t
– Time
L
H
V
X
Z
– Logic Level Low or ALE
– Logic Level High
– Valid
– No Longer a Valid Logic Level
– Float
PW – Pulse Width
74
Preliminary Information
PSD4000 Series
Microcontroller Interface – PSD4000 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Read Timing (3.0 V to 3.6 V Versions)
-90
-12
Turbo
Symbol
tLVLX
Parameter
Conditions
Min Max Min Max
Off
Unit
ns
ns
ns
ns
ns
ns
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid
22
7
24
9
tAVLX
tLXAX
tAVQV
tSLQV
(Note 3)
(Note 3)
(Note 3)
8
10
90
90
35
120 Add 20**
120
35
(Note 5)
(Note 2)
tRLQV
RD or PSEN to Data Valid,
80C51XA Mode
45
48
40
ns
tRHQX
tRLRH
tRHQZ
tEHEL
tTHEH
tELTL
RD Data Hold Time
RD Pulse Width
(Note 1)
(Note 1)
(Note 1)
0
0
ns
ns
ns
ns
ns
ns
36
40
RD to Data High-Z
38
E Pulse Width
38
10
0
42
16
0
R/W Setup Time to Enable
R/W Hold Time After Enable
Address Input Valid to
Address Output Delay
tAVPV
(Note 4)
30
35
ns
NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 80C51XA.
3. Any input used to select an internal PSD4135G2V function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
75
PSD4000 Series
Preliminary Information
Microcontroller Interface – PSD4000 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Write Timing (3.0 V to 3.6 V Versions)
-90
-12
Symbol
tLVLX
Parameter
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Conditions
Min Max Min Max Unit
22
7
24
9
tAVLX
tLXAX
(Note 1)
(Note 1)
ns
ns
8
10
Address Valid to Leading
Edge of WR
tAVWL
(Notes 1 and 3)
15
18
ns
tSLWL
CS Valid to Leading Edge of WR
WR Data Setup Time
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
15
40
5
18
45
8
ns
ns
ns
ns
ns
tDVWH
tWHDX
tWLWH
tWHAX1
WR Data Hold Time
WR Pulse Width
40
8
45
10
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Input Invalid
tWHAX2
tWHPV
tAVPV
(Notes 3 and 4)
(Note 3)
0
0
ns
ns
ns
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
33
30
33
35
Address Input Valid to Address
Output Delay
(Note 2)
NOTES: 1. Any input used to select an internal PSD4000 function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
4. tWHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
PLD Combinatorial Timing (3.0 V to 3.6 V Versions)
-90
-12
Slew
Rate
(Note 1) Unit
TURBO
OFF
Symbol
Parameter
Conditions
Min Max Min
Max
PLD Input Pin/Feedback to
PLD Combinatorial Output
tPD
38
43
Add 20 Sub 6
ns
ns
tARD
PLD Array Delay
23
27
NOTE: 1. Fast Slew Rate output available on Port C and F.
76
Preliminary Information
PSD4000 Series
Microcontroller Interface – PSD4000 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Power Down Timing (3.0 V to 3.6 V Versions)
-90
-12
Symbol
Parameter
Conditions
Min Max
Min Max Unit
ALE Access Time from
Power Down
tLVDV
128
135
ns
µs
Maximum Delay from APD Enable
to Internal PDN Valid Signal
tCLWH
Using CLKIN Input
15 tCLCL (µs) (Note 1)
*
NOTE: 1. tCLCL is the CLKIN clock period.
V
stbyon
Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
V
Detection to V
stbyon
Output
stby
(Note 1)
20
µs
High
tBXBL
V
Off Detection to V
stbyon
stby
(Note 1)
20
µs
Output Low
NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.
Reset Pin Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tNLNH
Warm RESET Active Low Time (Note 1)
RESET High to Operational Device
Power On Reset Active Low Time
300
ns
ns
tOPR
300
tNLNH-PO
1
ms
Warm RESETActive Low Time
(Note 2)
tNLNH-A
25
µs
NOTE: 1. RESET will not abort Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle.
77
PSD4000 Series
Preliminary Information
Microcontroller Interface – PSD4000 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Flash Program, Write and Erase Times (3.0 V to 3.6 V Versions)
Symbol
Parameter
Flash Program
Min
Typ
Max
Unit
8.5
3
sec
sec
sec
sec
sec
µs
Flash Bulk Erase (Preprogrammed to 00) (Note 1)
Flash Bulk Erase
30
30
10
1
tWHQV3
tWHQV2
tWHQV1
Sector Erase (Preprogrammed to 00)
Sector Erase
2.2
14
Word Program
1200
Program/Erase Cycles (Per Sector)
Sector Erase Time-Out
100,000
cycles
µs
tWHWLO
tQ7VQV
100
DQ7 Valid to Output Valid (Data Polling)
(Notes 2 and 3)
30
ns
NOTES: 1. Programmed to all zeros before erase.
2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading.
3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus.
ISC Timing (3.0 V to 3.6 V Versions)
-90
-12
Symbol
Parameter
Conditions
Min Max
Min Max Unit
tISCCF
TCK Clock Frequency (except for PLD)
TCK Clock High Time
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
15
12
MHz
ns
tISCCH
30
30
2
40
40
tISCCL
TCK Clock Low Time
ns
tISCCF-P
tISCCH-P
tISCCL-P
tISCPSU
tISCPH
TCK Clock Frequency (for PLD only)
TCK Clock High Time (for PLD only)
TCK Clock Low Time (for PLD only)
ISC Port Set Up Time
2
MHz
ns
240
240
11
5
240
240
12
ns
ns
ISC Port Hold Up Time
5
ns
tISCPCO
tISCPZV
tISCPVZ
ISC Port Clock to Output
26
26
26
32
32
32
ns
ISC Port High-Impedance to Valid Output
ISC Port Valid Output to High-Impedance
ns
ns
NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode.
2. For program or erase PLD only.
78
Preliminary Information
PSD4000 Series
Figure 28. Read Timing
t
t
AVLX
LXAX*
ALE/AS
t
LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
t
AVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
t
SLQV
CSI
t
t
RLQV
t
RHQX
RLRH
RD
(PSEN, DS)
tRHQZ
t
EHEL
E
t
THEH
t
ELTL
R/W
t
AVPV
ADDRESS OUT
*tAVLX and tLXAX are not required 80C51XA in Burst Mode.
79
PSD4000 Series
Preliminary Information
Figure 29. Write Timing
t
t
LXAX
AVLX
ALE/AS
t
LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
t
AVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
t
SLWL
CSI
t
t
DVWH
WHDX
t
WR
WLWH
t
WHAX
(DS)
t
EHEL
E
t
t
THEH
ELTL
R/ W
t
WLMV
t
t
AVPV
WHPV
STANDARD
MCU I/O OUT
ADDRESS OUT
80
Preliminary Information
PSD4000 Series
Figure 30. Combinatorial Timing – PLD
GPLD INPUT
t
PD
GPLD
OUTPUT
Figure 31. JTAG-ISP Timing
tISCCH
TCK
tISCCL
tISCPSU
tISCPH
TDI/TMS
t ISCPZV
tISCPCO
ISC OUTPUTS/TDO
tISCPVZ
ISC OUTPUTS/TDO
81
PSD4000 Series
Preliminary Information
Figure 32. Reset Timing
OPERATING LEVEL
t
t
NLNH
NLNH-A
t
NLNH–PO
V
CC
RESET
t
t
OPR
OPR
WARM
RESET
POWER ON RESET
Figure 33. Key to Switching Waveforms
INPUTS
OUTPUTS
WAVEFORMS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
82
Preliminary Information
PSD4000 Series
TA = 25 °C, f = 1 MHz
14.0
Pin Capacitance
Symbol
Parameter1
Conditions Typical2 Max Unit
CIN
Capacitance (for input pins only)
Capacitance (for input/output pins)
VIN = 0 V
VOUT = 0 V
VPP = 0 V
4
8
6
pF
pF
pF
COUT
CVPP
12
25
Capacitance (for CNTL2/VPP
)
18
NOTES: 1. These parameters are only sampled and are not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
15.0
Figure 34.
AC Testing
Input/Output
Waveform
3.0V
TEST POINT
1.5V
0V
16.0
2.01 V
Figure 35.
AC Testing
Load Circuit
195 Ω
DEVICE
UNDER TEST
CL = 30 pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
Upon delivery from ST, the PSD4000 device has all bits in the PLDs and memories in the
“1” or high state. The configuration bits are in the “0” or low state. The code, configuration,
and PLDs logic are loaded through the procedure of programming.
17.0
Programming
Information for programming the device is available directly from ST. Please contact your
local sales representative. (See the last page.)
83
PSD4000 Series
Preliminary Information
18.0
80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U)
PSD4000
Pin
Assignments
Pin No.
Pin Assignments
Pin No.
Pin Assignments
1
PD2
PD3
AD0
AD1
AD2
AD3
AD4
GND
VCC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
GND
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL0
CNTL1
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
VCC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
VCC
GND
PF0
GND
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PD0
PD1
PF1
PF2
PF3
PF4
PF5
PF6
PF7
RESET
CNTL2
84
Preliminary Information
PSD4000 Series
Figure 36. Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP)
(Package Type U)
19.0
PSD4000
Package
Information
PD2
PD3
AD0
AD1
AD2
AD3
AD4
GND
1
2
3
4
5
6
7
8
9
60 CNTL1
59 CNTL0
58 PA7
57 PA6
56 PA5
55 PA4
54 PA3
53 PA2
52 PA1
51 PA0
50 GND
49 GND
48 PC7
47 PC6
46 PC5
45 PC4
44 PC3
43 PC2
42 PC1
41 PC0
V
CC
AD5 10
AD6 11
AD7 12
AD8 13
AD9 14
AD10 15
AD11 16
AD12 17
AD13 18
AD14 19
AD15 20
85
PSD4000 Series
Preliminary Information
Figure 36A.
Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U)
D
D1
D3
80
1
2
3
Index
Mark
E
E3
E1
Standoff:
0.05 mm Min.
C
A1 A2
A
α
L
Load Coplanarity:
0.102 mm Max.
B
e1
Family: Plastic Thin Quad Flatpack (TQFP)
Millimeters
Inches
Symbol
Min
Max
Notes
Min
Max
Notes
α
0°
7°
0°
8°
A
–
1.20
1.05
–
0.047
0.041
0.011
0.008
0.551
0.472
A2
B
0.95
0.17
0.037
0.007
0.27
Reference
Reference
C
0.20
D
13.95
11.95
14.05
12.05
0.512
0.433
D1
D3
E
9.5
0.374
Reference
13.95
11.95
14.05
12.05
0.512
0.433
0.551
0.472
E1
E3
e1
L
9.5
Reference
Reference
0.374
0.019
Reference
Reference
0.50
0.45
0.75
0.018
0.030
N
80
80
060198R0
86
Selector Guide – PSD4000 Series
Part # MCU
PLDs/Decoders
I/O
Memory
Other
Software
5
Data Inputs Input Macrocells
Ports Flash Program Store
ISP via JTAG
IAP via MCU
Zero Power
Per. Mode
Security
PSDsoft
Express
Path
Volts
Output Macrocells
Outputs
2nd Flash Array
EEPROM
PSDsoft
2000
Page
Reg.
SRAM
w/BB
PMU
APD
PSD4135G2
PSD4235G2
16
16
57
57
–
–
24
24
8-bit
8-bit
52 4096Kb 256Kb
52 4096Kb 256Kb
–
–
64Kb
64Kb
X
X
X
X
X
X
–
–
X
X
X
X
X
X
X
X
24
16
X
PSD4000 Series
Preliminary Information
21.0
Part Number
Construction
Flash PSD Part Number Construction
CHARACTER # 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PART
NUMBER
P
S
D
4 2
1
3
F
2
–
A
–
1
5
J
TEMP RANGE
"Blank" = 0°C to 70°C (Commercial)
PSD BRAND NAME
PSD = Standard Low
Power Device
+
+
I = –40°C to 85°C (Industrial)
FAMILY/SERIES
8 = Flash PSD for 8-bit MCUs
PACKAGE TYPE
J = PLCC
U = TQFP
M = PQFP
B81 = BGA
9 = Flash PSD for 8-bit MUCs
(with simple PLD)
41 = Flash PSD for 16-bit MUCs
(with simple PLD)
42 = Flash PSD for 16-bit MUCs
(with CPLD)
SPEED
- 70 = 70ns
- 90 = 90ns
- 12 = 120ns
- 15 = 150ns
- 20 = 200ns
SRAM SIZE
0 = 0Kb
1 = 16Kb
2 = 32Kb
3 = 64Kb
REVISION
NVM SIZE
1 = 256Kb
2 = 512Kb
3 = 1Mb
"Blank" = no rev.
- A = Rev. A
- B = Rev. B
- C = Rev. C
4 = 2Mb
5 = 4Mb
V
VOLTAGE
cc
I/O COUNT & OTHER
F = 27 I/O
"blank" = 5 Volt
V = 3.0 Volt
G = 52 I/O
2ND NVM TYPE, SIZE
& CONFIGURATION
1 = EEPROM, 256Kb
2 = FLASH, 256Kb
3 = No 2nd Array
22.0
Ordering
Information
88
PSD4135G2
REVISION HISTORY
Table 1. Document Revision History
Date
Rev.
Description of Revision
01-May-2000
1.0
PSD4135G2: Document written in the WSI format. Initial release
PSD4135G2: Flash In-System-Programmable Peripherals for 16-Bit MCUs
Front page, and back two pages, in ST format, added to the PDF file
Any references to Waferscale, WSI, EasyFLASH and PSDsoft 2000
updated to ST, ST, Flash+PSD and PSDsoft Express
31-Jan-2002
1.1
2/3
PSD4135G2
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2002 STMicroelectronics - All Rights Reserved
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