PSD8131V70J1T [STMICROELECTRONICS]
SPECIALTY MEMORY CIRCUIT, PQCC54, ROHS COMPLIANT, PLASTIC, LCC-52;型号: | PSD8131V70J1T |
厂家: | ST |
描述: | SPECIALTY MEMORY CIRCUIT, PQCC54, ROHS COMPLIANT, PLASTIC, LCC-52 |
文件: | 总110页 (文件大小:899K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSD813F1V
Flash in-system programmable (ISP) peripherals
for 8-bit MCUs, 3.3 V
NOT FOR NEW DESIGN
FEATURES SUMMARY
■
DUAL BANK FLASH MEMORIES
Figure 1. Packages
–
–
–
1 Mbit of Primary Flash Memory (8
Uniform Sectors)
256 Kbit Secondary EEPROM (4 Uniform
Sectors)
Concurrent operation: read from one
memory while erasing and writing the
other
PQFP52 (M)
■
■
16 Kbit SRAM
PLD WITH MACROCELLS
–
–
–
Over 3,000 Gates Of PLD: DPLD and
CPLD
DPLD - User-defined Internal chip-select
decoding
CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
PLCC52 (J)
TQFQ64 (U)
■
27 RECONFIGURABLE I/Os
–
27 individually configurable I/O port pins
that can be used for the following
functions:
MCU I/Os;
PLD I/Os;
Latched MCU address output; and
Special function I/Os.
Note: 16 of the I/O ports may be
■
HIGH ENDURANCE:
configured as open-drain outputs.
–
100,000 Erase/WRITE Cycles of Flash
Memory
■
ENHANCED JTAG SERIAL PORT
–
Built-in JTAG-compliant serial port allows
full-chip In-System Programmability (ISP)
Efficient manufacturing allows for easy
product testing and programming
–
–
–
10,000 Erase/WRITE Cycles of EEPROM
1,000 Erase/WRITE Cycles of PLD
Data Retention: 15-year minimum at 90°C
(for Main Flash, Boot, PLD and
Configuration bits).
–
■
■
PAGE REGISTER
–
Internal page register that can be used to
expand the microcontroller address space
by a factor of 256.
■
SINGLE SUPPLY VOLTAGE:
3.3V 10ꢀ for PSD813F1V
–
■
■
STANDBY CURRENT AS LOW AS 50µA
Packages are ECOPACK
PROGRAMMABLE POWER MANAGEMENT
®
October 2008
Rev 4
1/110
This is information on a product still in production but not recommended for new designs.
PSD813F1V
TABLE OF CONTENTS
features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Microcontroller Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MEMORY BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Primary Flash Memory and Secondary EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Erase Time-out Flag DQ3 (Flash Memory only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Writing to the EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Writing the OTP Row. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/110
PSD813F1V
FLASH AND EEPROM MEMORY SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Flash Memory and EEPROM Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 31
Separate Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Combined Space Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PLD’S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DECODE PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
COMPLEX PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Data Byte Enable Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3/110
PSD813F1V
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Mask Macrocell Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Port C – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
For Users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 71
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Security, Flash memory and EEPROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4/110
PSD813F1V
APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5/110
PSD813F1V
with JTAG. No need to handle devices and bend
the fragile leads.
In-Application Programming (IAP)
SUMMARY DESCRIPTION
The PSD family of Programmable Microcontroller
(MCU) Peripherals brings In-System Programma-
bility (ISP) to Flash memory and programmable
logic. The result is a simple and flexible solution for
embedded designs. PSD devices combine many
of the peripheral functions found in MCU based
applications.
PSD devices integrate an optimized “microcon-
troller macrocell” logic architecture. The Macrocell
was created to address the unique requirements
of embedded system designs. It allows direct con-
nection between the system address/data bus and
the internal PSD registers to simplify communica-
tion between the MCU and other supporting devic-
es.
Two independent memory arrays (Flash and EE-
PROM) are included so the MCU can execute
code from one memory while erasing and pro-
gramming the other. Robust product firmware up-
dates in the field are possible over any
communication channel (CAN, Ethernet, UART,
J1850, etc.) using this unique architecture. De-
signers are relieved of these problems:
Simultaneous read and write to Flash memo-
ry. How can the MCU program the same memory
from which it is executing code? It cannot. The
PSD allows the MCU to operate the two memories
concurrently, reading code from one while erasing
and programming the other during IAP.
Complex memory mapping. I have only a 64K-
byte address space to start with. How can I map
these two memories efficiently? A Programmable
Decode PLD is the answer. The concurrent PSD
memories can be mapped anywhere in MCU ad-
dress space, segment by segment with extremely
high address resolution. As an option, the second-
ary Flash memory can be swapped out of the sys-
tem memory map when IAP is complete. A built-in
page register breaks the 64K-byte address limit.
The PSD family offers two methods to program
PSD Flash memory while the PSD is soldered to a
circuit board.
In-System Programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG interface is in-
cluded on the PSD enabling the entire device
(Flash memory, EEPROM, the PLD, and all con-
figuration) to be rapidly programmed while sol-
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even while completely blank.
Separate program and data space. How can I
write to Flash or EEPROM memory while it resides
in “program” space during field firmware updates,
my MCU won’t allow it! The Flash PSD provides
means to “reclassify” Flash or EEPROM memory
as “data” space during IAP, then back to “program”
space when complete.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
First time programming. How do I get firmware
into the Flash the very first time? JTAG is the an-
swer, program the PSD while blank with no MCU
involvement.
PSDsoft Express
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand? How many and what
version? JTAG is the answer, build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to customer. No more labels on chips and no more
wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets? JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
PSDsoft Express, a software development tool
from ST, guides you through the design process
step-by-step making it possible to complete an
embedded MCU design capable of ISP/IAP in just
hours. Select your MCU and PSDsoft Express
takes you through the remainder of the design with
point and click entry, covering PSD selection, pin
definitions, programmable logic inputs and out-
puts, MCU memory map definition, ANSI-C code
generation for your MCU, and merging your MCU
firmware with the PSD design. When complete,
two different device programmers are supported
directly from PSDsoft Express: FlashLINK (JTAG)
and PSDpro.
6/110
PSD813F1V
Figure 2. PQFP52 Connections
PD2 1
PD1 2
PD0 3
PC7 4
PC6 5
PC5 6
PC4 7
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
V
8
32 AD8
CC
GND 9
31 V
CC
PC3 10
PC2 11
PC1 12
PC0 13
30 AD7
29 AD6
28 AD5
27 AD4
AI02858
7/110
PSD813F1V
Figure 3. PLCC52 Connections
8
PD2
PD1
PD0
PC7
PC6
PC5
PC4
AD15
AD14
AD13
AD12
AD11
AD10
AD9
46
45
44
43
42
41
40
39
38
37
36
9
10
11
12
13
14
15
16
17
18
V
AD8
CC
GND
V
CC
PC3
PC2
AD7
AD6
19
20
PC1
PC0
AD5
AD4
35
34
AI02857
8/110
PSD813F1V
Figure 4. TQFP64 Connections
PD2 1
PD1 2
PD0 3
PC7 4
PC6 5
PC5 6
48 CNTL0
47 AD15
46 AD14
45 AD13
44 AD12
43 AD11
42 AD10
41 AD9
V
V
V
7
8
9
CC
CC
CC
40 AD8
GND 10
GND 11
PC3 12
PC2 13
PC1 14
PC0 15
NC 16
39 V
CC
38 V
CC
37 AD7
36 AD6
35 AD5
34 AD4
33 AD3
AI09644
9/110
PSD813F1V
PIN DESCRIPTION
Table 1. Pin Description (for the PLCC52 package)
(1)
Pin Name
Pin
Type
Description
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, or you are using an
ADIO0-7 30-37
I/O 80C251 in page mode, connect A0-A7 to this port.
3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is active
and one of the PSD functional blocks was selected. The addresses on this port are
passed to the PLDs.
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect A8-A15 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
ADIO8-15 39-46
I/O
3. If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
4. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is active
and one of the PSD functional blocks was selected. The addresses on this port are
passed to the PLDs.
The following control signals can be connected to this port, based on your MCU:
1. WR – active Low Write Strobe input.
2. R_W – active High READ/active Low write input.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL0
CNTL1
47
50
I
I
The following control signals can be connected to this port, based on your MCU:
1. RD – active Low Read Strobe input.
2. E – E clock input.
3. DS – active Low Data Strobe input.
4. PSEN – connect PSEN to this port when it is being used as an active Low READ
signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is
actually the READ signal.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
This port can be used to input the PSEN (Program Select Enable) signal from any MCU
that uses this signal for code exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This port is connected to the
PLDs.
CNTL2
Reset
49
48
I
I
Active Low Reset input. Resets I/O Ports, PLD macrocells and some of the Configuration
Registers. Must be Low at Power-up.
10/110
PSD813F1V
(1)
Pin Name
Pin
Type
Description
These pins make up Port A. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7) outputs.
3. Inputs to the PLDs.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
4. Latched address outputs (see Table 5).
I/O 5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.
6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
These pins make up Port B. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.
I/O
PC0 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC0) output.
PC0
20
I/O
3. Input to the PLDs.
2
4. TMS Input for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC1) output.
PC1
PC2
19
18
I/O
3. Input to the PLDs.
2
4. TCK Input for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC2 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
I/O 2. CPLD macrocell (McellBC2) output.
3. Input to the PLDs.
This pin can be configured as a CMOS or Open Drain output.
PC3 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC3) output.
3. Input to the PLDs.
PC3
PC4
17
14
I/O
I/O
2
4. TSTAT output for the JTAG Serial Interface.
5. Ready/Busy output for In-System parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC4) output.
3. Input to the PLDs.
2
4. TERR output for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
11/110
PSD813F1V
(1)
Pin Name
Pin
Type
Description
PC5 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC5) output.
PC5
13
12
I/O
3. Input to the PLDs.
2
4. TDI input for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC6 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC6) output.
PC6
I/O
I/O
3. Input to the PLDs.
2
4. TDO output for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC7 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC7) output.
3. Input to the PLDs.
4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.
PC7
PD0
PD1
11
10
9
This pin can be configured as a CMOS or Open Drain output.
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input latches address output from the MCU.
I/O 2. MCU I/O – write or read from a standard output or input port.
3. Input to the PLDs.
4. CPLD output (External Chip Select).
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. Input to the PLDs.
I/O
3. CPLD output (External Chip Select).
4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
the CPLD AND Array.
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (External Chip Select).
PD2
8
I/O
4. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/
O. When High, the PSD memory blocks are disabled to conserve power.
V
15, 38
Supply Voltage
Ground pins
CC
1, 16,
26
GND
Note: 1. The pin numbers in this table are for the PLCC package only. See the Figure 2., page 7, for pin numbers on other package type.
2. These functions can be multiplexed with other functions.
12/110
PSD813F1V
Figure 5. Block Diagram
AI02861g
13/110
PSD813F1V
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure 5 shows the architecture of the PSD
device. The functions of each block are described
briefly in the following sections. Many of the blocks
perform multiple functions and are user configu-
rable.
The PLDs consume minimal power by using Zero-
Power design techniques. The speed and power
consumption of the PLD is controlled by the Turbo
Bit (ZPSD only) in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the microcontroller at runtime. There is a
slight penalty to PLD propagation time when in-
voking the ZPSD features.
Memory
The PSD contains the following memories:
I/O Ports
■
■
■
a 1 Mbit Flash memory
a secondary 256 Kbit EEPROM memory
a 16 Kbit SRAM
The PSD has 27 I/O pins divided among four ports
(Port A, B, C, and D). Each I/O pin can be individ-
ually configured for different functions. Ports A, B,
C and D can be configured as standard MCU I/O
ports, PLD I/O, or latched address outputs for mi-
crocontrollers using multiplexed address/data
busses.
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled MEMORY
BLOCKS, page 18.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a n on-multiplexed bus or multiplexed Ad-
dress/Data buses for certain types of 16-bit micro-
controllers.
The 1 Mbit Flash memory is the main memory of
the PSD. It is divided into 8 equally-sized sectors
that are individually selectable.
The 256 Kbit EEPROM or Flash memory is divided
into 4 equally-sized sectors. Each sector is individ-
ually selectable.
Microcontroller Bus Interface
The 16 Kbit SRAM is intended for use as a
scratchpad memory or as an extension to the mi-
crocontroller SRAM.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
The PSD easily interfaces with most 8-bit micro-
controllers that have either multiplexed or non-
multiplexed address/data busses. The device is
configured to respond to the microcontroller’s con-
trol signals, which are also used as inputs to the
PLDs. Where there is a requirement to use a 16-
bit data bus to interface to a 16-bit microcontroller,
two PSDs must be used. For examples, please
see the section entitled MCU Bus Interface
Examples, page 47.
PLDs
The device contains two PLD blocks, each opti-
mized for a different function, as shown in Table 2.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
The Decode PLD (DPLD) is used to decode ad-
dresses and generate chip selects for the PSD in-
ternal memory and registers. The CPLD can
implement user-defined logic functions. The DPLD
has combinatorial outputs. The CPLD has 16 Out-
put macrocells and 3 combinatorial outputs. The
PSD also has 24 Input macrocells that can be con-
figured as inputs to the PLDs. The PLDs receive
their inputs from the PLD Input Bus and are differ-
entiated by their output destinations, number of
Product Terms, and macrocells.
Table 2. PLD I/O
Product
Name
Inputs Outputs
Terms
42
140
Decode PLD (DPLD)
73
17
19
Complex PLD (CPLD) 73
14/110
PSD813F1V
JTAG Port
Power Management Unit (PMU)
In-System Programming can be performed
through the JTAG pins on Port C. This serial inter-
face allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table 3 indicates the
JTAG signals pin assignments.
The Power Management Unit (PMU) in the PSD
gives the user control of the power consumption
on selected functional blocks based on system re-
quirements. The PMU includes an Automatic Pow-
er Down unit (APD) that will turn off device
functions due to microcontroller inactivity. The
APD unit has a Power Down Mode that helps re-
duce power consumption.
In-System Programming (ISP)
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The turbo bit in the PMMR0 reg-
ister can be turned off and the CPLD will latch its
outputs and go to sleep until the next transition on
its inputs.
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the microcontroller. The main Flash memo-
ry can also be programmed in-system by the mi-
crocontroller
executing
the
programming
algorithms out of the EEPROM or SRAM. The EE-
PROM can be programmed the same way by exe-
cuting out of the main Flash memory. The PLD
logic or other PSD configuration can be pro-
grammed through the JTAG port or a device pro-
grammer. Table 4 indicates which programming
methods can program different functional blocks
of the PSD.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the
section
entitled
POWER
MANAGEMENT, page 64 for more details.
Table 3. JTAG SIgnals on Port C
Port C Pins
PC0
JTAG Signal
Page Register
TMS
TCK
The 8-bit Page Register expands the address
range of the microcontroller by up to 256 times.
The paged address can be used as part of the ad-
dress space to access external memory and pe-
ripherals, or internal memory and I/O. The Page
Register can also be used to change the address
mapping of blocks of Flash memory into different
memory spaces for in-circuit programming.
PC1
PC3
PC4
PC5
PC6
TSTAT
TERR
TDI
TDO
Table 4. Methods of Programming Different Functional Blocks of the PSD
In-System Parallel
Programming
Functional Block
Main Flash Memory
JTAG Programming Device Programmer
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
EEPROM Memory
PLD Array (DPLD and CPLD)
PSD Configuration
No
Optional OTP Row
Yes
15/110
PSD813F1V
DEVELOPMENT SYSTEM
The PSD is supported by PSDsoft Express a Win-
dows-based (95, 98, NT) software development
tool. A PSD design is quickly and easily produced
in a point and click environment. The designer
does not need to enter Hardware Definition Lan-
guage (HDL) equations (unless desired) to define
PSD pin functions and memory map information.
The general design flow is shown in Figure 6 be-
low. PSDsoft Express is available from our web
site (www.st.com/psm) or other distribution chan-
nels.
PSDsoft Express directly supports two low cost
device programmers from ST, PSDpro and Flash-
LINK (JTAG). Both of these programmers may be
purchased through your local distributor/represen-
tative, or directly from our web site using a credit
card. The PSD is also supported by third party de-
vice programmers, see web site for current list.
Figure 6. PSDsoft Express Development Tool
Choose MCU and PSD
Automatically configures MCU
bus interface and other
PSD attributes
Define PSD Pin and
Node functions
C Code Generation
Point and click definition of
PSD pin functions, internal nodes,
and MCU system memory map
Generate C Code
Specific to PSD
Functions
Define General Purpose
Logic in CPLD
User's choice of
MCU Firmware
Point and click definition of
combinatorial and registered logic
in CPLD. Access to HDL is
available if needed
Microcontroller
Hex or S-Record
Compiler/Linker
format
Merge MCU Firmware
with PSD Configuration
A composite object file is created
containing MCU firmware and
PSD configuration.
*.OBJ FILE
ST PSD Programmer
*.OBJ file
available
PSDPro, or
for 3rd party
FlashLINK (JTAG)
programmers
(Conventional or JTAG-ISC)
AI09215
16/110
PSD813F1V
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 5 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
Table 5. I/O Port Latched Address Output Assignments
(2)
(2)
Port A
Port B
(1)
MCU
Port A (3:0)
Port A (7:4)
Port B (3:0)
Address a11-a8
Address a11-a8
Address a3-a0
Address a3-a0
Port B (7:4)
8051XA (8-bit)
N/A
N/A
Address a7-a4
N/A
N/A
80C251 (page mode)
All other 8-bit multiplexed
8-bit non-multiplexed bus
Address a15-a12
Address a7-a4
Address a7-a4
Address a3-a0
N/A
Address a7-a4
N/A
Note: 1. See the section entitled I/O PORTS, page 52, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
Table 6. Register Address Offset
Port
A
Port
B
Port
C
Port
D
(1)
Register Name
Description
Other
Data In
Control
00
02
01
03
10
11
Reads Port pin as input, MCU I/O input mode
Selects mode between MCU I/O or Address Out
Stores data for output to Port pins, MCU I/O output
mode
Data Out
Direction
04
06
05
07
12
14
13
15
Configures Port pin as input or output
Configures Port pins as either CMOS or Open Drain
on some pins, while selecting high slew rate on other
pins.
Drive Select
08
09
16
17
Input Macrocell
Enable Out
0A
0C
0B
0D
18
Reads Input Macrocells
Reads the status of the output enable to the I/O Port
driver
1A
1B
Output Macrocells
AB
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
20
20
21
22
23
Output Macrocells
BC
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
21
23
Mask Macrocells
AB
22
Blocks writing to the Output Macrocells AB
Blocks writing to the Output Macrocells BC
Read only – Flash Sector Protection
Mask Macrocells
BC
Primary Flash
Protection
C0
C2
Secondary Flash
memory
Protection
Read only – PSD Security and EEPROM Sector
Protection
JTAG Enable
PMMR0
PMMR2
Page
C7
B0
B4
E0
Enables JTAG Port
Power Management Register 0
Power Management Register 2
Page Register
Places PSD memory areas in Program and/or Data
space on an individual basis.
VM
E2
Note: 1. Other registers that are not part of the I/O ports.
17/110
PSD813F1V
DETAILED OPERATION
As shown in Figure 5., page 13, the PSD consists
of six major types of functional blocks:
transparent. The integrity of the data can be se-
cured with the help of Software Data Protection
(SDP). Any write operation to the EEPROM is in-
hibited during the first five milliseconds following
power-up.
During a program or erase of Flash, or during a
write of the EEPROM, the status can be output on
the Ready/Busy (PC3) pin of Port C3. This pin is
set up using PSDsoft Express Configuration.
■
■
■
■
■
■
Memory Blocks
PLD Blocks
MCU Bus Interface
I/O Ports
Power Management Unit (PMU)
JTAG Interface
Memory Block Select Signals. The
decode
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKS
The PSD has the following memory blocks (see
Table 7):
PLD in the PSD generates the chip selects for all
the internal memory blocks (refer to the section
entitled PLD’S, page 34). Each of the eight Flash
memory sectors have a Flash Select signal (FS0-
FS7) which can contain up to three product terms.
Each of the four EEPROM memory sectors have a
Select signal (EES0-3 or CSBOOT0-3) which can
contain up to three product terms. Having three
product terms for each sector select signal allows
a given sector to be mapped in different areas of
system memory. When using a microcontroller
with separate Program and Data space, these
flexible select signals allow dynamic re-mapping of
sectors from one space to the other.
–
–
–
The Main Flash memory
Secondary EEPROM memory
SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary
EEPROM Description
The 1Mb primary Flash memory is divided evenly
into eight 16-KByte sectors. The EEPROM memo-
ry is divided into four sectors of eight KBytes each.
Each sector of either memory can be separately
protected from Program and Erase operations.
Flash memory may be erased on a sector-by-sec-
tor basis and programmed byte-by-byte. Flash
sector erasure may be suspended while data is
read from other sectors of memory and then re-
sumed after reading.
Ready/Busy Pin (PC3). Pin PC3 can be used to
output the Ready/Busy status of the PSD. The out-
put on the pin will be a ‘0’ (Busy) when Flash or
EEPROM memory blocks are being written to, or
when the Flash memory block is being erased.
The output will be a ‘1’ (Ready) when no write or
erase operation is in progress.
Table 7. Memory Blocks
Device
Main Flash
EEPROM
SRAM
PSD813F1
128KB
32KB
2KB
EEPROM may be programmed byte-by-byte or
sector-by-sector, and erasing is automatic and
18/110
PSD813F1V
Memory Operation
The main Flash and EEPROM memory are ad-
dressed through the microcontroller interface on
the PSD device. The microcontroller can access
these memories in one of two ways:
into Flash memory, the microcontroller must exe-
cute a program instruction sequence, then test the
status of the programming event. This status test
is achieved by a READ operation or polling the
Ready/Busy pin (PC3).
The Flash memory can also be read by using spe-
cial instructions to retrieve particular Flash device
information (sector protect status and ID).
–
The microcontroller can execute a typical bus
WRITE or READ operation just as it would if
accessing a RAM or ROM device using
standard bus cycles.
–
The microcontroller can execute a specific
instruction that consists of several WRITE and
READ operations. This involves writing
specific data patterns to special addresses
within the Flash or EEPROM to invoke an
embedded algorithm. These instructions are
summarized in Table 8., page 20.
The EEPROM is a bit different. Data can be written
to EEPROM memory using write operations, like
writing to a RAM device, but the status of each
WRITE event must be checked by the microcon-
troller. A WRITE event can be one to 64 contigu-
ous bytes. The status test is very similar to that
used for Flash memory (READ operation or
Ready/Busy). Optionally, the EEPROM memory
may be put into a Software Data Protect (SDP)
mode where it requires instructions, rather than
operations, to alter its contents. SDP mode makes
writing to EEPROM much like writing to Flash
memory.
Typically, Flash memory can be read by the micro-
controller using READ operations, just as it would
read a ROM device. However, Flash memory can
only be erased and programmed with specific in-
structions. For example, the microcontroller can-
not write a single byte directly to Flash memory as
one would write a byte to RAM. To program a byte
19/110
PSD813F1V
Table 8. Instructions
EEPROM
Instruction SectorSelect
(EESi)
Flash Sector
Select (FSi)
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
(2)
Read
Identifier
AAh@ 55h@ 90h@
with
Read Flash
0
1
0
1
3,5
X555h XAAAh X555h
(A6,A1,A0
Identifier
at 0,0,1)
Read OTP
AAh@ 55h@ 90h@ Read byte Read
Read
byte N
1
4
X555h XAAAh X555h
1
byte 2
row
Read
Read Sector
identifier
with (A6,
A1; A0 =
0,1,0)
AAh@ 55h@ 90h@
X555h XAAAh X555h
Protection
0
3,5
Status
Program a
Flash Byte
AAh@ 55h@ A0h@ Data@
X555h XAAAh X555h address
0
0
1
1
5
30h@
Sector
30h@
Sector
address
Erase one
AAh@ 55h@ 80h@ AAh@
X555h XAAAh X555h X555h
55h@
XAAAh
5
Flash Sector
1
address
Erase the
AAh@ 55h@ 80h@ AAh@
X555h XAAAh X555h X555h
55h@
XAAAh X555h
10h@
0
0
0
1
1
1
1
0
5
Whole Flash
Suspend
B0h@
XXXXh
5
5
Sector Erase
Resume
30h@
XXXXh
Sector Erase
EEPROM
AAh@ 55h@ 30h@
X555h XAAAh X555h
4
Power Down
SDP Enable/
EEPROM
AAh@ 55h@ A0h@ Write byte Write
Write
byte N
1
0
X555h XAAAh X555h
1
byte 2
4
Write
AAh@ 55h@ 80h@ AAh@
X555h XAAAh X555h X555h
55h@
XAAAh X555h
20h@
4
1
1
0
0
SDP Disable
Write in OTP
AAh@ 55h@ B0h@ Write byte Write
Write
byte N
4,6
X555h XAAAh X555h
1
byte 2
Row
Return (from
OTP Read or
EEPROM
F0h@
XXXX
1
0
4
Power-Down)
AAh@ 55h@ F0h@
X555h XAAAh XXXX
3.5
0
0
1
1
Reset
Reset (short
F0h@
XXXX
5
instruction)
Note: 1. Additional sectors to be erased must be entered within 80 µs. A Sector Address is any address within the Sector.
2. Flash and EEPROM Sector Selects are active high. Addresses A15-A12 are don’t cares in Instruction Bus Cycles.
3. The Reset instruction is required to return to the normal READ mode if DQ5 goes high or after reading the Flash Identifier or Pro-
tection status.
4. The MCU cannot invoke these instructions while executing code from EEPROM. The MCU must be operating from some other
memory when these instructions are performed.
5. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the instruction is intended.
The MCU must operate from some other memory when these instructions are executed.
6. Writing to OTP Row is allowed only when SDP mode is disabled.
20/110
PSD813F1V
INSTRUCTIONS
An instruction is defined as a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
write operation. The instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out value. Some instructions
are structured to include READ operations after
the initial WRITE operations.
These instructions are detailed in Table
8., page 20. For efficient decoding of the instruc-
tions, the first two bytes of an instruction are the
coded cycles and are followed by a command byte
or confirmation byte. The coded cycles consist of
writing the data AAh to address X555h during the
first cycle and data 55h to address XAAAh during
the second cycle. Address lines A15-A12 are don’t
cares during the instruction WRITE cycles. How-
ever, the appropriate sector select signal (FSi or
EESi) must be selected.
The sequencing of any instruction must be fol-
lowed exactly. Any invalid combination of instruc-
tion bytes or time-out between two consecutive
bytes while addressing Flash memory will reset
the device logic into READ mode (Flash memory
reads like a ROM device). An invalid combination
or time-out while addressing the EEPROM block
will cause the offending byte to be interpreted as a
single operation.
Power-down Instruction and Power-up Mode
EEPROM Power Down Instruction. The
EE-
PROM can enter power down mode with the help
of the EEPROM power down instruction (see Ta-
ble 8., page 20). Once the EEPROM power down
instruction is decoded, the EEPROM memory can-
not be accessed unless a Return instruction (also
in Table 8., page 20) is decoded. Alternately, this
power down mode will automatically occur when
the APD circuit is triggered (see section entitled
Automatic Power-down (APD) Unit and Power-
down Mode, page 65). Therefore, this instruction
is not required if the APD circuit is used.
The PSD supports these instructions (see Table
8., page 20):
Flash memory:
■
■
■
■
■
■
Erase memory by chip or sector
Suspend or resume sector erase
Program a Byte
Reset to READ mode
Read Flash Identifier value
Read Sector Protection Status
Power-up Mode. The PSD internal logic is reset
upon power-up to the READ mode. Any write op-
eration to the EEPROM is inhibited during the first
5ms following power-up. The FSi and EESi select
signals, along with the write strobe signal, must be
in the false state during power-up for maximum se-
curity of the data contents and to remove the pos-
sibility of a byte being written on the first edge of a
write strobe signal. Any write cycle initiation is
EEPROM:
■
■
■
■
■
■
Write data to OTP Row
Read data from OTP Row
Power down memory
Enable Software Data Protect (SDP)
Disable SDP
Return from read OTP Row read mode or
power down mode.
locked when V is below V
.
LKO
CC
21/110
PSD813F1V
READ
Under typical conditions, the microcontroller may
read the Flash or EEPROM memory using READ
operations just as it would a ROM or RAM device.
Alternately, the microcontroller may use READ op-
erations to obtain status information about a Pro-
gram or Erase operation in progress. Lastly, the
microcontroller may use instructions to read spe-
cial data from these memories. The following sec-
tions describe these READ functions.
Read Memory Contents. Main Flash is placed in
the READ mode after power-up, chip reset, or a
Reset Flash instruction (see Table 8., page 20).
The microcontroller can read the memory contents
of main Flash or EEPROM by using READ opera-
tions any time the READ operation is not part of an
instruction sequence.
Read Main Flash Memory Identifier. The main
Flash memory identifier is read with an instruction
composed of 4 operations:
3 specific write operations and a READ operation
(see Table 8). During the READ operation, ad-
dress bits A6, A1, and A0 must be 0,0,1, respec-
tively, and the appropriate sector select signal
(FSi) must be active. The Flash ID is E3h for the
PSD. The MCU can read the ID only when it is ex-
ecuting from the EEPROM.
Read Main Flash Memory Sector Protection
Status. The main Flash memory sector protection
status is read with an instruction composed of 4
operations: 3 specific WRITE operations and a
READ operation (see Table 8., page 20). During
the READ operation, address bits A6, A1, and A0
must be 0,1,0, respectively, while the chip select
FSi designates the Flash sector whose protection
has to be verified. The READ operation will pro-
duce 01h if the Flash sector is protected, or 00h if
the sector is not protected.
The sector protection status for all NVM blocks
(main Flash or EEPROM) can be read by the mi-
crocontroller accessing the Flash Protection and
PSD/EE Protection registers in PSD I/O space.
See Flash Memory and EEPROM Sector
Protect, page 30 for register definitions.
Reading the OTP Row. There are 64 bytes of
One-Time-Programmable (OTP) memory that re-
side in EEPROM. These 64 bytes are in addition
to the 32 Kbytes of EEPROM memory. A READ of
the OTP row is done with an instruction composed
of at least 4 operations: 3 specific WRITE opera-
tions and one to 64 READ operations (see Table
8., page 20). During the READ operation(s), ad-
dress bit A6 must be zero, while address bits A5-
A0 define the OTP Row byte to be read while any
EEPROM sector select signal (EESi) is active. Af-
ter reading the last byte, an EEPROM Return in-
struction must be executed (see Table
8., page 20).
Reading the Erase/Program Status Bits. The
PSD provides several status bits to be used by the
microcontroller to confirm the completion of an
erase or programming instruction of Flash memo-
ry. Bits are also available to show the status of
WRITES to EEPROM. These status bits minimize
the time that the microcontroller spends perform-
ing these tasks and are defined in Table 9. The
status bits can be read as many times as needed.
For Flash memory, the microcontroller can per-
form a READ operation to obtain these status bits
while an Erase or Program instruction is being ex-
ecuted by the embedded algorithm. See the sec-
tion
entitled
PROGRAMMING
FLASH
MEMORY, page 27 for details.
For EEPROM not in SDP mode, the microcon-
troller can perform a READ operation to obtain
these status bits just after a data WRITE opera-
tion. The microcontroller may write one to 64 bytes
before reading the status bits. See the section en-
titled Writing to the EEPROM, page 24 for details.
For EEPROM in SDP mode, the microcontroller
will perform a READ operation to obtain these sta-
tus bits while an SDP write instruction is being ex-
ecuted by the embedded algorithm. See section
entitled EEPROM Software Data Protect
(SDP), page 24 for details.
Table 9. Status Bit
FSi/
Device
EESi
DQ7
DQ6
DQ5
DQ4
X
DQ3
DQ2 DQ1 DQ0
CSBOOTi
Toggle
Flag
Error
Flag
Erase
Timeout
V
V
Flash
Data Polling
Data Polling
X
X
X
X
X
X
IH
IL
Toggle
Flag
V
V
EEPROM
X
X
X
IL
IH
Note: 1. X = not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus Bits, D7-D0.
3. FSi and EESi are active High.
22/110
PSD813F1V
Data Polling Flag (DQ7)
The operation is finished when two successive
reads yield the same output data. Flash memory
specific features:
When Erasing or Programming the Flash memory
(or when Writing into the EEPROM memory), bit
DQ7 outputs the complement of the bit being en-
tered for Programming/Writing on DQ7. Once the
Program instruction or the WRITE operation is
completed, the true logic value is read on DQ7 (in
a Read operation). Flash memory specific fea-
tures:
■
■
■
The Toggle bit is effective after the fourth
WRITE pulse (for programming) or after the
sixth WRITE pulse (for Erase).
If the byte to be programmed belongs to a
protected Flash sector, the instruction is
ignored.
If all the Flash sectors selected for erasure are
protected, DQ6 will toggle to ‘0’ for about 100
µs and then return to the previous addressed
byte.
–
Data Polling is effective after the fourth WRITE
pulse (for programming) or after the sixth
WRITE pulse (for Erase). It must be performed
at the address being programmed or at an
address within the Flash sector being erased.
Error Flag (DQ5)
–
During an Erase instruction, DQ7 outputs a ‘0.’
After completion of the instruction, DQ7 will
output the last bit programmed (it is a ‘1’ after
erasing).
During a correct Program or Erase, the Error bit
will set to ‘0.’ This bit is set to ‘1’ when there is a
failure during Flash byte programming, Sector
erase, or Bulk Erase.
In the case of Flash programming, the Error Bit in-
dicates the attempt to program a Flash bit(s) from
the programmed state ('0') to the erased state ('1'),
which is not a valid operation. The Error bit may
also indicate a timeout condition while attempting
to program a byte.
In case of an error in Flash sector erase or byte
program, the Flash sector in which the error oc-
curred or to which the programmed byte belongs
must no longer be used. Other Flash sectors may
still be used. The Error bit resets after the Reset in-
struction.
–
–
If the byte to be programmed is in a protected
Flash sector, the instruction is ignored.
If all the Flash sectors to be erased are
protected, DQ7 will be set to ‘0’ for about
100µs, and then return to the previous
addressed byte. No erasure will be performed.
Toggle Flag (DQ6)
The PSD offers another way for determining when
the EEPROM write or the Flash memory Program
instruction is completed. During the internal
WRITE operation and when either the FSi or EESi
is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to
‘0’ on subsequent attempts to read any byte of the
memory.
When the internal cycle is complete, the toggling
will stop and the data read on the Data Bus D0-7
is the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
Erase Time-out Flag DQ3 (Flash Memory only)
The Erase Timer bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase timer bit is set to ‘0’ after a
Sector Erase instruction for a time period of 100µs
+ 20ꢀ unless an additional Sector Erase instruc-
tion is decoded. After this time period or when the
additional Sector Erase instruction is decoded,
DQ3 is set to ‘1.’
23/110
PSD813F1V
Writing to the EEPROM
EEPROM Software Data Protect (SDP). The
SDP feature is useful for protecting the contents of
EEPROM from inadvertent write cycles that may
occur during uncontrolled MCU bus conditions.
These may happen if the application software gets
lost or when VCC is not within normal operating
range.
Instructions from the MCU are used to enable and
disable SDP mode (see Table 8., page 20). Once
enabled, the MCU must write an instruction se-
quence to EEPROM before writing data (much like
writing to Flash memory). SDP mode can be used
for both byte and page writes to EEPROM. The
device will remain in SDP mode until the MCU is-
sues a valid SDP disable instruction.
PSD devices are shipped with SDP mode dis-
abled. However, within PSDsoft Express, SDP
mode may be enabled as part of programming the
device with a device programmer (PSDpro).
To enable SDP mode at run time, the MCU must
write three specific data bytes at three specific
memory locations, as shown in Figure 7., page 25.
Any further writes to EEPROM when SDP is set
will require this same sequence, followed by the
byte(s) to write. The first SDP enable sequence
can be followed directly by the byte(s) to be writ-
ten.
Data may be written a byte at a time to the EE-
PROM using simple write operations, much like
writing to an SRAM. Unlike SRAM though, the
completion of each byte write must be checked be-
fore the next byte is written. To speed up this pro-
cess, the PSD offers a Page write feature to allow
writing of several bytes before checking status.
To prevent inadvertent writes to EEPROM, the
PSD offers a Software Data Protect (SDP) mode.
Once enabled, SDP forces the MCU to “unlock”
the EEPROM before altering its contents, much
like Flash memory programming.
Writing a Byte to EEPROM. A write operation is
initiated when an EEPROM select signal (EESi) is
true and the write strobe signal (WR) into the PSD
is true. If the PSD detects no additional writes with-
in 120µsec, an internal storage operation is initiat-
ed. Internal storage to EEPROM memory
technology typically takes a few milliseconds to
complete.
The status of the write operation is obtained by the
MCU reading the Data Polling or Toggle bits (as
detailed in section entitled READ, page 22), or the
Ready/Busy output pin (section Ready/Busy Pin
(PC3), page 18).
Keep in mind that the MCU does not need to erase
a location in EEPROM before writing it. Erasure is
performed automatically as an internal process.
To disable SDP mode, the MCU must write specif-
ic bytes to six specific locations, as shown in Fig-
ure 8., page 26.
The MCU must not be executing code from EE-
PROM when these instructions are invoked. The
MCU must be operating from some other memory
when enabling or disabling SDP mode.
Writing a Page to EEPROM. Writing data to EE-
PROM using page mode is more efficient than
writing one byte at a time. The PSD EEPROM has
a 64 byte volatile buffer that the MCU may fill be-
fore an internal EEPROM storage operation is ini-
tiated. Page mode timing approaches a 64:1
advantage over the time it takes to write individual
bytes.
To invoke page mode, the MCU must write to EE-
PROM locations within a single page, with no
more than 120µs between individual byte writes. A
single page means that address lines A14 to A6
must remain constant. The MCU may write to the
64 locations on a page in any order, which is de-
termined by address lines A5 to A0. As soon as
120µs have expired after the last page write, the
internal EEPROM storage process begins and the
MCU checks programming status. Status is
checked the same way it is for byte writes, de-
scribed above.
The state of SDP mode is not changed by power
on/off sequences (nonvolatile). When either the
SDP enable or SDP disable instructions are is-
sued from the MCU, the MCU must use the Toggle
bit (status bit DQ6) or the Ready/Busy
output pin
to check programming status. The Ready/Busy
output is driven low from the first write of AAh @
555h until the completion of the internal storage
sequence. Data Polling (status bit DQ7) is not sup-
ported when issuing the SDP enable or SDP dis-
able commands.
Note: Using the SDP sequence (enabling, dis-
abling, or writing data) is initiated when specific
bytes are written to addresses on specific “pages”
of EEPROM memory, with no more than 120µs
between WRITES. The addresses 555h and
AAAh are located on different pages of EEPROM.
This is how the PSD distinguishes these instruc-
tion sequences from ordinary writes to EEPROM,
which are expected to be within a single EEPROM
page.
Note: Be aware that if the upper address bits (A14
to A6) change during page write operations, loss
of data may occur. Ensure that all bytes for a given
page have been successfully stored in the EE-
PROM before proceeding to the next page. Cor-
rect management of MCU interrupts during
EEPROM page write operations is essential.
24/110
PSD813F1V
Writing the OTP Row
Writing to the OTP row (64 bytes) can only be
done once per byte, and is enabled by an instruc-
tion. This instruction is composed of three specific
WRITE operations of data bytes at three specific
memory locations followed by the data to be
stored in the OTP row (refer to Table 8., page 20).
During the WRITE operations, address bit A6 must
be zero, while address bits A5-A0 define the OTP
Row byte to be written while any EEPROM Sector
Select signal (EESi) is active. Writing the OTP
Row is allowed only when SDP mode is not en-
abled.
Figure 7. EEPROM SDP Enable Flowcharts
SDP SDP
Set not Set
WRITE AAh to
Address 555h
WRITE AAh to
Address 555h
Page Write
Instruction
WRITE 55h to
Address AAAh
WRITE 55h to
Address AAAh
Page Write
Instruction
WRITE A0h to
Address 555h
WRITE A0h to
Address 555h
WRITE
is enabled
SDP is set
WRITE Data to
be Written in
any Address
SDP ENABLE ALGORITHM
Write
in Memory
Write Data
+
SDP Set
after tWC
(Write Cycle Time)
ai09219
25/110
PSD813F1V
Figure 8. Software Data Protection Disable Flowchart
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE 80h to
Address 555h
Page Write
Instruction
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE 20h to
Address 555h
Unprotected State
after
tWC (Write Cycle time)
ai09220
26/110
PSD813F1V
PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. A byte
of Flash memory erases to all logic ones (FF hex),
and its bits are programmed to logic zeros. Al-
though erasing Flash memory occurs on a sector
basis, programming Flash memory occurs on a
byte basis.
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed to compare the byte
that was written to Flash with the byte that was in-
tended to be written.
When using the Data Polling method after an
erase instruction, Figure 9 still applies. However,
DQ7 will be ‘0’ until the erase operation is com-
plete. A ‘1’ on DQ5 will indicate a timeout failure of
the erase operation, a ‘0’ indicates no error. The
MCU can read any location within the sector being
erased to get DQ7 and DQ5.
The PSD main Flash and optional boot Flash re-
quire the MCU to send an instruction to program a
byte or perform an erase function (see Table
8., page 20). This differs from EEPROM, which
can be programmed with simple MCU bus write
operations (unless EEPROM SDP mode is en-
abled).
PSDsoft Express will generate ANSI C code func-
tions which implement these Data Polling algo-
rithms.
Once the MCU issues a Flash memory program or
erase instruction, it must check for the status of
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or the Ready/Busy output pin.
Figure 9. Data Polling Flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
Data Polling
Polling on DQ7 is a method of checking whether a
Program or Erase instruction is in progress or has
completed. Figure 9 shows the Data Polling algo-
rithm.
DQ7
=
YES
DATA
When the MCU issues a programming instruction,
the embedded algorithm within the PSD begins.
The MCU then reads the location of the byte to be
programmed in Flash to check status. Data bit
DQ7 of this location becomes the compliment of
data bit 7of the original data byte to be pro-
grammed. The MCU continues to poll this location,
comparing DQ7 and monitoring the Error bit on
DQ5. When the DQ7 matches data bit 7 of the
original data, and the Error bit at DQ5 remains ‘0’,
then the embedded algorithm is complete. If the
Error bit at DQ5 is ‘1’, the MCU should test DQ7
again since DQ7 may have changed simultane-
ously with DQ5 (see Figure 9).
NO
NO
DQ5
= 1
YES
READ DQ7
DQ7
=
YES
DATA
NO
FAIL
PASS
The Error bit at DQ5 will be set if either an internal
timeout occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a ‘1’ to a bit that was not
erased (not erased is logic ‘0’).
AI01369B
27/110
PSD813F1V
Data Toggle
Checking the Data Toggle bit on DQ6 is a method
of determining whether a Program or Erase in-
struction is in progress or has completed. Figure
10 shows the Data Toggle algorithm.
PSDsoft Express will generate ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
When the MCU issues a programming instruction,
the embedded algorithm within the PSD begins.
The MCU then reads the location of the byte to be
programmed in Flash to check status. Data bit
DQ6 of this location will toggle each time the MCU
reads this location until the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking DQ6 and monitoring the Error bit on
DQ5. When DQ6 stops toggling (two consecutive
reads yield the same value), and the Error bit on
DQ5 remains ‘0’, then the embedded algorithm is
complete. If the Error bit on DQ5 is ‘1’, the MCU
should test DQ6 again, since DQ6 may have
changed simultaneously with DQ5 (see Figure
10).
Figure 10. Data Toggle Flowchart
START
READ
DQ5 & DQ6
DQ6
TOGGLE
NO
=
YES
NO
DQ5
= 1
The Error bit at DQ5 will be set if either an internal
timeout occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a ‘1’ to a bit that was not
erased (not erased is logic ‘0’).
YES
READ DQ6
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed to compare the byte
that was written to Flash with the byte that was in-
tended to be written.
DQ6
=
NO
TOGGLE
YES
When using the Data Toggle method after an
erase instruction, Figure 10 still applies. DQ6 will
toggle until the erase operation is complete. A ‘1’
on DQ5 will indicate a timeout failure of the erase
operation, a ‘0’ indicates no error. The MCU can
read any location within the sector being erased to
get DQ6 and DQ5.
FAIL
PASS
AI01370B
28/110
PSD813F1V
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six write op-
erations followed by a Read operation of the status
register, as described in Table 8., page 20. If any
byte of the Bulk Erase instruction is wrong, the
Bulk Erase instruction aborts and the device is re-
set to the Read Flash memory status.
During a Bulk Erase, the memory status may be
checked by reading status bits DQ5, DQ6, and
DQ7, as detailed in section entitled PROGRAM-
MING FLASH MEMORY, page 27. The Error bit
(DQ5) returns a ‘1’ if there has been an Erase Fail-
ure (maximum number of erase cycles have been
executed).
Suspend instructions. Erasure of one Flash sector
may be suspended, in order to read data from an-
other Flash sector, and then resumed.
Flash Erase Suspend
When a Flash Sector Erase operation is in prog-
ress, the Erase Suspend instruction will suspend
the operation by writing 0B0h to any address when
an appropriate Chip Select (FSi) is true. (See Ta-
ble 8., page 20). This allows reading of data from
another Flash sector after the Erase operation has
been suspended. Erase suspend is accepted only
during the Flash Sector Erase instruction execu-
tion and defaults to READ mode. An Erase Sus-
pend instruction executed during an Erase timeout
will, in addition to suspending the erase, terminate
the time out.
It is not necessary to program the array with 00h
because the PSD will automatically do this before
erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory will not accept any instructions.
The Toggle Bit DQ6 stops toggling when the PSD
internal logic is suspended. The toggle Bit status
must be monitored at an address within the Flash
sector being erased. The Toggle Bit will stop tog-
gling between 0.1 µs and 15 µs after the Erase
Suspend instruction has been executed. The PSD
will then automatically be set to Read Flash Block
Memory Array mode.
Flash Sector Erase. The Sector Erase instruc-
tion uses six write operations, as described in Ta-
ble 8., page 20. Additional Flash Sector Erase
confirm commands and Flash sector addresses
can be written subsequently to erase other Flash
sectors in parallel, without further coded cycles, if
the additional instruction is transmitted in a shorter
time than the timeout period of about 100 µs. The
input of a new Sector Erase instruction will restart
the time-out period.
The status of the internal timer can be monitored
through the level of DQ3 (Erase time-out bit). If
DQ3 is ‘0’, the Sector Erase instruction has been
received and the timeout is counting. If DQ3 is ‘1’,
the timeout has expired and the PSD is busy eras-
ing the Flash sector(s). Before and during Erase
timeout, any instruction other than Erase suspend
and Erase Resume will abort the instruction and
reset the device to READ mode. It is not neces-
sary to program the Flash sector with 00h as the
PSD will do this automatically before erasing
(byte=FFh).
If an Erase Suspend instruction was executed, the
following rules apply:
■
■
■
Attempting to read from a Flash sector that
was being erased will output invalid data.
Reading from a Flash sector that was not
being erased is valid.
The Flash memory cannot be programmed,
and will only respond to Erase Resume and
Reset instructions (READ is an operation and
is OK).
■
If a Reset instruction is received, data in the
Flash sector that was being erased will be
invalid.
Flash Erase Resume
If an Erase Suspend instruction was previously ex-
ecuted, the erase operation may be resumed by
this instruction. The Erase Resume instruction
consists of writing 030h to any address while an
appropriate Chip Select (FSi) is true. (See Table
8., page 20.)
During a Sector Erase, the memory status may be
checked by reading status bits DQ5, DQ6, and
DQ7, as detailed in section entitled PROGRAM-
MING FLASH MEMORY, page 27.
During execution of the erase instruction, the
Flash block logic accepts only Reset and Erase
29/110
PSD813F1V
FLASH AND EEPROM MEMORY SPECIFIC FEATURES
Flash Memory and EEPROM Sector Protect
Each Flash and EEPROM sector can be separate-
ly protected against Program and Erase functions.
Sector Protection provides additional data security
because it disables all program or erase opera-
tions. This mode can be activated through the
JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Configuration program. This will
automatically protect selected sectors when the
device is programmed through the JTAG Port or a
Device Programmer. Flash and EEPROM sectors
can be unprotected to allow updating of their con-
tents using the JTAG Port or a Device Program-
mer. The microcontroller can read (but cannot
change) the sector protection bits.
Any attempt to program or erase a protected Flash
or EEPROM sector will be ignored by the device.
The Verify operation will result in a READ of the
protected data. This allows a guarantee of the re-
tention of the Protection status.
The sector protection status can be read by the
MCU through the Flash protection and PSD/EE
protection registers (CSIOP). See Table 10.
Reset
The Reset instruction resets the internal memory
logic state machine in a few milliseconds. Reset is
an instruction of either one write operation or three
write operations (refer to Table 8., page 20).
Table 10. Sector Protection/Security Bit Definition – Flash Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Note: 1. Bit Definitions:
Sec<i>_Prot 1 = Flash <i> is write protected.
Sec<i>_Prot 0 = Flash <i> is not write protected.
Table 11. Sector Protection/Security Bit Definition – PSD/EE Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit not used
Note: 1. Bit Definitions:
not used
not used
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Sec<i>_Prot 1 = EEPROM Boot Sector <i> is write protected.
Sec<i>_Prot 0 = EEPROM Boot Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
SRAM
The SRAM is a 16 Kbit (2K x 8) memory. The
SRAM is enabled when RS0—the SRAM chip se-
lect output from the DPLD—is high. RS0 can con-
tain up to two product terms, allowing flexible
memory mapping.
The chip select signal (RS0) for the SRAM is con-
figured using PSDsoft Express Configuration.
30/110
PSD813F1V
MEMORY SELECT SIGNALS
The main Flash (FSi), EEPROM (EESi), and
SRAM (RS0) memory select signals are all out-
puts of the DPLD. They are setup by entering
equations for them in PSDsoft Express. The fol-
lowing rules apply to the equations for the internal
chip select signals:
Components on the same level must not overlap.
Level one has the highest priority and level 3 has
the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 8031 and compatible family of microcon-
trollers, which includes the 80C51, 80C151,
80C251, 80C51XA, and the C500 family, have
separate address spaces for code memory (se-
lected using PSEN) and data memory (selected
using RD). Any of the memories within the PSD
can reside in either space or both spaces. This is
controlled through manipulation of the VM register
that resides in the PSD’s CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the microcontroller so that memory
mapping can be changed on-the-fly. For example,
I may wish to have SRAM and Flash in Data
Space at boot, and EEPROM in Program Space at
boot, and later swap EEPROM and Flash. This is
easily done with the VM register by using PSDsoft
Express to configure it for boot up and having the
microcontroller change it when desired. Table 12
describes the VM Register.
1. Flash memory and EEPROM sector select
signals must not be larger than the physical
sector size.
2. Any main Flash memory sector must not be
mapped in the same memory space as
another Flash sector.
3. An EEPROM sector must not be mapped in
the same memory space as another EEPROM
sector.
4. SRAM, I/O, and Peripheral I/O spaces must
not overlap.
5. An EEPROM sector may overlap a main Flash
memory sector. In case of overlap, priority will
be given to the EEPROM.
6. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority will
be given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, EES0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 will always ac-
cess the SRAM. Any address in the range of EES0
greater than 87FFh (and less than 9FFFh) will au-
tomatically address EEPROM segment 0. Any ad-
dress greater than 9FFFh will access the Flash
memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of EE-
PROM segment 0 can not be accessed in this ex-
ample. Also note that an equation that defined FS1
to anywhere in the range of 8000h to BFFFh would
not be valid.
Figure 11. Priority Level of Memory and I/O
Components
Highest Priority
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
EEPROM Memory
Level 3
Flash Memory
Figure 11 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level.
Lowest Priority
AI09221
Table 12. VM Register
Bit 7
PIO_EN
Bit 4
FL_Data
Bit 3
EE_Data
Bit 2
FL_Code
Bit 1
EE_Code
Bit 0
SRAM_Code
Bit 6
Bit 5
0 = RD can’t
access
Flash
0 = PSEN
can’t access 0 = PSEN can’t
access EEPROM Flash
memory
0 = PSEN
can’t access
SRAM
0 = disable
PIO mode
0 = RD can’t
not used not used
not used not used
access EEPROM
memory
1 = RD
access
Flash
1 = PSEN
access
Flash
1 = PSEN
access
SRAM
1= enable
PIO mode
1 = RD access
EEPROM
1 = PSEN
access EEPROM
memory
memory
31/110
PSD813F1V
Separate Space Modes
Combined Space Modes
Code memory space is separated from data mem-
ory space. For example, the PSEN signal is used
to access the program code from the Flash Mem-
ory, while the RD signal is used to access data
from the EEPROM, SRAM and I/O Ports. This
configuration requires the VM register to be set to
0Ch. See Figure 12.
The program and data memory spaces are com-
bined into one space that allows the main Flash
Memory, EEPROM, and SRAM to be accessed by
either PSEN or RD. For example, to configure the
main Flash memory in combined space mode, bits
2 and 4 of the VM register are set to “1” (see Figure
13).
Figure 12. 80C31 Memory Modes - Separate Space
Flash
Memory
EEPROM
Memory
SRAM
DPLD
RS0
EES0-EES3
FS0-FS7
CS
CS
OE
CS
OE
OE
PSEN
RD
AI09222
Figure 13. 80C31 Memory Mode - Combined Space
Flash
Memory
EEPROM
Memory
SRAM
DPLD
RS0
RD
EES0-EES3
FS0-FS7
CS
CS
OE
CS
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
RD
VM REG BIT 2
VM REG BIT 0
AI09223
32/110
PSD813F1V
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the microcontroller by a factor of up to
256. The contents of the register can also be read
by the microcontroller. The outputs of the Page
Register (PGR0-PGR7) are inputs to the DPLD
decoder and can be included in the Flash Memory,
EEPROM, and SRAM chip select equations.
Figure 14 shows the Page Register. The eight flip
flops in the register are connected to the internal
data bus D0-D7. The microcontroller can write to
or read from the Page Register. The Page Regis-
ter can be accessed at address location CSIOP +
E0h.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure 14. Page Register
RESET
PGR0
INTERNAL
SELECTS
AND LOGIC
D0
D1
D2
D3
D4
D5
D6
D7
Q0
PGR1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGR2
D0 - D7
Flash DPLD
AND
Flash CPLD
PGR3
PGR4
PGR5
PGR6
PGR7
R/W
PAGE
REGISTER
PLD
AI09224
33/110
PSD813F1V
PLD’S
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using the PSDabel tool in PSDsoft Express, the
logic is programmed into the device and available
upon power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the sections entitled DE-
CODE PLD (DPLD) and COMPLEX PLD (CPLD).
Figure 15., page 35 shows the configuration of the
PLDs.
The DPLD performs address decoding for internal
and external components, such as memory, regis-
ters, and I/O port selects.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output macrocells (OMCs), 24 Input macrocells
(IMCs), and the AND array. The CPLD can also be
used to generate external chip selects.
The AND array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 13.
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns. Each
of the two PLDs has unique characteristics suited
for its applications. They are described in the fol-
lowing sections.
Table 13. DPLD and CPLD Inputs
Number
Input Source
Input Name
of
Signals
1
A15-A0
16
3
MCU Address Bus
MCU Control Signals
Reset
CNTL2-CNTL0
RST
1
Power-down
PDN
1
Port A Input
Macrocells
PA7-PA0
PB7-PB0
PC7-PC0
8
8
8
Port B Input
Macrocells
Port C Input
Macrocells
The Turbo Bit in PSD
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns.
Setting the Turbo mode bit to off (Bit 3 of the
PMMR0 register) automatically places the PLDs
into standby if no inputs are changing. Turbo-off
mode increases propagation delays while reduc-
ing power consumption. See the section entitled
POWER MANAGEMENT, page 64, on how to set
the Turbo Bit.
Port D Inputs
Page Register
PD2-PD0
3
8
PGR7-PGR0
Macrocell AB
Feedback
MCELLAB.FB7-
FB0
8
8
1
Macrocell BC
Feedback
MCELLBC.FB7-
FB0
EEPROM Program
Status Bit
Ready/Busy
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
34/110
PSD813F1V
Figure 15. PLD Diagram
I / O P O R T S
P L D I N P U T B U S
35/110
PSD813F1V
DECODE PLD (DPLD)
The DPLD, shown in Figure 16, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
■
■
■
■
1 internal SRAM select signal (two product
terms)
1 internal CSIOP (PSD configuration register)
select signal
1 JTAG select signal (enables JTAG on Port
C)
2 internal peripheral select signals (peripheral
I/O mode).
■
8 sector selects for the main Flash memory
(three product terms each)
■
4 sector selects for the EEPROM (three
product terms each)
Figure 16. DPLD Logic Array
EES 0
EES 1
EES 2
EES 3
3
3
3
3
EEPROM
SELECTS
(INPUTS)
(24)
3
3
3
3
3
3
3
3
FS0
I/O PORTS (PORT A,B,C)
FS1
FS2
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
(8)
(8)
FS3
FS4
FS5
8 FLASH MEMORY
SECTOR SELECTS
PGR0 -PGR7
(1)
(16)
(3)
[
]
A 15:0
[
]
PD 2:0 (ALE,CLKIN,CSI)
PDN (APD OUTPUT)
FS6
FS7
(1)
[
] (
(3)
(1)
(1)
CNTRL 2:0 READ/WRITE CONTROL SIGNALS)
RESET
RS0
2
1
SRAM SELECT
RD_BSY
CSIOP
I/O DECODER
SELECT
PSEL0
1
1
1
PERIPHERAL I/O
MODE SELECT
PSEL1
JTAGSEL
AI09226
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
36/110
PSD813F1V
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate 3 external chip selects,
routed to Port D.
■
■
AND array capable of generating up to 137
product terms
Four I/O ports.
Each of the blocks are described in the subsec-
tions that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the microcon-
troller. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND logic array as required in
most standard PLD macrocell architectures.
Although external chip selects can be produced by
any Output Macrocell, these three external chip
selects on Port D do not consume any Output
macrocells.
As shown in Figure 15., page 35, the CPLD has
the following blocks:
■
■
■
■
24 Input macrocells (IMCs)
16 Output macrocells (OMCs)
Macrocell Allocator
Product Term Allocator
Figure 17. Macrocell and I/O Port
PRODUCT TERMS
FROM OTHER
MACROCELLS
MCU ADDRESS / DATA BUS
TO OTHER I/O PORTS
CPLD MACROCELLS
I/O PORTS
DATA
LOAD
CONTROL
LATCHED
ADDRESS OUT
PT PRESET
MCU DATA IN
MCU LOAD
PRODUCT TERM
ALLOCATOR
I/O PIN
DATA
D
Q
MUX
WR
UP TO 10
PRODUCT TERMS
MACROCELL
OUT TO
MCU
CPLD OUTPUT
POLARITY
SELECT
PR DI LD
D/T
SELECT
Q
PT
CPLD
OUTPUT
PDR
CLOCK
INPUT
D/T/JK FF
SELECT
COMB.
/REG
SELECT
GLOBAL
CLOCK
MACROCELL
CK
TO
I/O PORT
ALLOC.
CL
CLOCK
SELECT
Q
DIR
REG.
D
WR
PT CLEAR
(
)
PT OUTPUT ENABLE OE
MACROCELL FEEDBACK
I/O PORT INPUT
INPUT MACROCELLS
Q
Q
D
PT INPUT LATCH GATE/CLOCK
D
G
ALE/AS
AI02874
37/110
PSD813F1V
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator will assign it to either Port
A or B. The same is true for a McellBC output on
Port B or C. Table 14 shows the macrocells and
Port assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 18., page 40. As shown in the fig-
ure, there are native product terms available from
the AND array, and borrowed product terms avail-
able (if unused) from other OMCs. The polarity of
the product term is controlled by the XOR gate.
The OMC can implement either sequential logic,
using the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a Port pin and has a feedback path to the
AND array inputs.
The flip-flop in the OMC can be configured as a D,
T, JK, or SR type in the PSDabel program. The
flip-flop’s clock, preset, and clear inputs may be
driven from a product term of the AND array. Alter-
natively, the external CLKIN signal can be used for
the clock input to the flip-flop. The flip-flop is
clocked on the rising edge of the clock input. The
preset and clear are active-high inputs. Each clear
input can use up to two product terms.
Table 14. Output Macrocell Port and Data Bit Assignments
Output
Macrocell
Port
Assignment
Maximum Borrowed
Product Terms
Data Bit for Loading or
Reading
Native Product Terms
McellAB0
McellAB1
McellAB2
McellAB3
McellAB4
McellAB5
McellAB6
McellAB7
McellBC0
McellBC1
McellBC2
McellBC3
McellBC4
McellBC5
McellBC6
McellBC7
Port A0, B0
Port A1, B1
Port A2, B2
Port A3, B3
Port A4, B4
Port A5, B5
Port A6, B6
Port A7, B7
Port B0, C0
Port B1, C1
Port B2, C2
Port B3, C3
Port B4, C4
Port B5, C5
Port B6, C6
Port B7, C7
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
38/110
PSD813F1V
Product Term Allocator
The CPLD has a Product Term Allocator. The PS-
Dabel compiler uses the Product Term Allocator to
borrow and place product terms from one macro-
cell to another. The following list summarizes how
product terms are allocated:
and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the OMCs on the trailing
edge of the WR signal (edge loading) or during the
time that the WR signal is active (level loading).
The method of loading is specified in PSDsoft Ex-
press Configuration.
■
■
■
McellAB0-McellAB7 all have three native
product terms and may borrow up to six more
McellBC0-McellBC3 all have four native
product terms and may borrow up to five more
McellBC4-McellBC7 all have four native
product terms and may borrow up to six more.
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight OMCs. The Mask Registers can be
used to block the loading of data to individual
OMCs. The default value for the Mask Registers is
00h, which allows loading of the OMCs. When a
given bit in a Mask Register is set to a ‘1’, the MCU
will be blocked from writing to the associated
OMC. For example, suppose McellAB0-3 are be-
ing used for a state machine. You would not want
a MCU write to McellAB to overwrite the state ma-
chine registers. Therefore, you would want to load
the Mask Register for McellAB (Mask Macrocell
AB) with the value 0Fh.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which will consume other Output
Macrocells (OMC). If external product terms are
used, extra delay will be added for the equation
that required the extra product terms.
The Output Enable of the OMC
This is called product term expansion. PSDsoft
Express will perform this expansion as needed.
The OMC can be connected to an I/O port pin as
a PLD output. The output enable of each Port pin
driver is controlled by a single product term from
the AND array, ORed with the Direction Register
output. The pin is enabled upon power up if no out-
put enable equation is defined and if the pin is de-
clared as a PLD output in PSDsoft Express.
If the OMC output is declared as an internal node
and not as a Port pin output in the PSDabel file,
then the Port pin can be used for other I/O func-
tions. The internal node feedback can be routed as
an input to the AND array.
Loading and Reading the Output Macrocells
(OMC). The OMCs occupy a memory location in
the MCU address space, as defined by the CSIOP
(refer to the I/O section). The flip-flops in each of
the 16 OMCs can be loaded from the data bus by
a microcontroller. Loading the OMCs with data
from the MCU takes priority over internal func-
tions. As such, the preset, clear, and clock inputs
to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read them back is
useful in such applications as loadable counters
39/110
PSD813F1V
Figure 18. CPLD Output Macrocell
A N D A R R A Y
P L D I N P U T B U S
40/110
PSD813F1V
Input Macrocells (IMC)
The CPLD has 24 IMCs, one for each pin on Ports
A, B, and C. The architecture of the IMC is shown
in Figure 19., page 42. The IMCs are individually
configurable, and can be used as a latch, register,
or to pass incoming Port signals prior to driving
them onto the PLD input bus. The outputs of the
IMCs can be read by the microcontroller through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND array or the
MCU address strobe (ALE/AS). Each product term
output is used to latch or clock four IMCs. Port in-
puts 3-0 can be controlled by one product term
and 7-4 by another.
the IMC buffer. See the I/O Port section on how to
read the IMCs.
IMCs can use the address strobe to latch address
bits higher than A15. Any latched addresses are
routed to the PLDs as inputs.
IMCs are particularly useful with handshaking
communication applications where two proces-
sors pass data back and forth through a common
mailbox. Figure 20., page 43 shows a typical con-
figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to the Port A IMCs and
the Master can then read the IMCs directly.
Note that the “Slave-Read” and “Slave-wr” signals
are product terms that are derived from the Slave
MCU inputs RD, WR, and Slave_CS.
Configurations for the IMCs are specified by equa-
tions written in PSDabel (see Application Note 55).
Outputs of the IMCs can be read by the MCU via
41/110
PSD813F1V
Figure 19. Input Macrocell
A N D A R R A Y
P L D I N P U T B U S
42/110
PSD813F1V
Figure 20. Handshaking Communication Using Input Macrocells
43/110
PSD813F1V
MCU BUS INTERFACE
The “no-glue logic” PSD MCU Bus Interface block
can be directly connected to most popular MCUs
and their control signals.
Key 8-bit MCUs, with their bus types and control
signals, are shown in Table 15. The interface type
is specified using the PSDsoft Express Configura-
tion.
Table 15. MCUs and their Control Signals
DataBus
2
MCU
CNTL0 CNTL1 CNTL2
PC7
ADIO0 PA3-PA0 PA7-PA3
PD0
ALE
Width
1
1
1
8031
8
8
8
8
8
8
8
8
8
8
8
WR
WR
WR
WR
WR
R/W
R/W
WR
R/W
R/W
R/W
RD
RD
PSEN
RD
RD
E
PSEN
PSEN
A0
A4
A0
A0
A0
A0
A0
A0
A0
A0
A0
(Note )
(Note )
(Note )
1
1
80C51XA
80C251
80C251
80198
ALE
ALE
ALE
ALE
AS
A3-A0
(Note )
(Note )
1
1
1
1
(Note ) (Note )
(Note )
(Note )
1
1
1
PSEN
(Note )
(Note )
(Note )
1
1
1
1
(Note ) (Note )
(Note )
(Note )
1
1
1
1
68HC11
68HC912
Z80
(Note ) (Note )
(Note )
(Note )
1
1
1
E
DBE
AS
(Note )
(Note )
(Note )
1
1
1
RD
DS
DS
E
D3-D0
D7-D4
(Note ) (Note ) (Note )
1
1
1
1
Z8
AS
(Note ) (Note )
(Note )
(Note )
1
1
1
1
68330
AS
(Note ) (Note )
(Note )
(Note )
1
1
M37702M2
ALE
D3-D0
D7-D4
(Note ) (Note )
Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-
tions.
2. ALE/AS input is optional for MCUs with a non-multiplexed bus
44/110
PSD813F1V
PSD Interface to a Multiplexed 8-Bit Bus
Figure 21 shows an example of a system using a
MCU with an 8-bit multiplexed bus and a PSD. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port A or
B. The PSD drives the ADIO data bus only when
one of its internal resources is accessed and Read
Strobe (RD, CNTL1) is active. Should the system
address bus exceed sixteen bits, Ports A, B, C, or
D may be used as additional address inputs.
Figure 21. An Example of a Typical 8-bit Multiplexed Bus Interface
MCU
PSD
[
]
AD 7:0
[
]
A 7:0
PORT
A
(
(
)
)
OPTIONAL
ADIO
PORT
[
]
A 15:8
[
]
A 15:8
PORT
B
OPTIONAL
(
)
WR
RD
WR CNTRL0
(
)
RD CNTRL1
(
)
BHE
BHE CNTRL2
PORT
C
RST
ALE
(
)
ALE PD0
PORT D
RESET
AI02878C
45/110
PSD813F1V
PSD Interface to a Non-Multiplexed 8-Bit Bus
Figure 22 shows an example of a system using a
microcontroller with an 8-bit non-multiplexed bus
and a PSD. The address bus is connected to the
ADIO Port, and the data bus is connected to Port
A. Port A is in tri-state mode when the PSD is not
accessed by the microcontroller. Should the sys-
tem address bus exceed sixteen bits, Ports B, C,
or D may be used for additional address inputs.
Figure 22. An Example of a Typical 8-bit Non-Multiplexed Bus Interface
PSD
MCU
[
]
D 7:0
[
]
D 7:0
PORT
A
ADIO
PORT
[
]
A 15:0
[
]
A 23:16
PORT
B
(OPTIONAL)
(
)
WR
RD
WR CNTRL0
(
)
RD CNTRL1
(
)
BHE
BHE CNTRL2
RST
PORT
C
ALE
(
)
ALE PD0
PORT D
RESET
AI02879C
46/110
PSD813F1V
Data Byte Enable Reference
MCU Bus Interface Examples
Microcontrollers have different data byte orienta-
tions. The following table shows how the PSD in-
terprets byte/word operations in different bus
WRITE configurations. Even-byte refers to loca-
tions with address A0 equal to zero and odd byte
as locations with A0 equal to one.
Figure 23 to 26 show examples of the basic con-
nections between the PSD and some popular
MCUs. The PSD Control input pins are labeled as
to the MCU function for which they are configured.
The MCU bus interface is specified using the PSD-
soft Express Configuration.
The first configuration is 80C31-compatible, and
the bus interface to the PSD is identical to that
shown in Figure 23. The second and third configu-
rations have the same bus connection as shown in
Table 17., page 48. There is only one READ input
(PSEN) connected to the CNTL1 pin on the PSD.
The A16 connection to the PA0 pin allows for a
larger address input to the PSD. Configuration 4 is
shown in Figure 24., page 49. The RD signal is
connected to Cntl1 and the PSEN signal is con-
nected to the CNTL2.
Table 16. Eight-Bit Data Bus
BHE
X
A0
0
D7-D0
Even Byte
Odd Byte
X
1
80C31
Figure 23 shows the bus interface for the 80C31,
which has an 8-bit multiplexed address/data bus.
The lower address byte is multiplexed with the
data bus. The MCU control signals Program Se-
lect Enable (PSEN, CNTL2), Read Strobe (RD,
CNTL1), and Write Strobe (WR, CNTL0) may be
used for accessing the internal memory and I/O
Ports. The ALE input (pin PD0) latches the ad-
dress.
Figure 23. Interfacing the PSD with an 80C31
AD7-AD0
[
]
AD 7:0
PSD
80C31
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
29
30
31
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
31
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
28
27
25
24
23
22
21
EA/VP
X1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
32
33
34
35
36
37
19
18
9
X2
RESET
RESET
12
13
14
15
INT0
INT1
T0
21
22
23
24
25
26
27
28
A8
A9
39
40
41
42
43
44
45
46
7
6
5
4
3
2
52
51
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ADIO8
ADIO9
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A10
A11
A12
A13
A14
A15
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
T1
1
2
3
4
5
6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
17
16
29
30
11
10
RD
RD
WR
PSEN
ALE/P
TXD
20
19
18
17
14
13
12
11
WR
47
50
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
CNTL0(WR)
CNTL1(RD)
7
8
PSEN
ALE
49
CNTL2(PSEN)
10
9
RXD
PD0-ALE
PD1
8
PD2
RESET
48
RESET
RESET
AI02880C
47/110
PSD813F1V
80C251
The Intel 80C251 MCU features a user-configu-
rable bus interface with four possible bus configu-
rations, as shown in Table 18., page 49.
The 80C251 has two major operating modes:
Page Mode and Non-Page Mode. In Non-Page
Mode, the data is multiplexed with the lower ad-
dress byte, and ALE is active in every bus cycle.
In Page Mode, data D[7:0] is multiplexed with ad-
dress A[15:8]. In a bus cycle where there is a Page
hit, the ALE signal is not active and only addresses
A[7:0] are changing. The PSD supports both
modes. In Page Mode, the PSD bus timing is iden-
tical to Non-Page Mode except the address hold
time and setup time with respect to ALE is not re-
quired. The PSD access time is measured from
address A[7:0] valid to data in valid.
Table 17. Interfacing the PSD with the 80C251, with One READ Input
PSD
80C251SB
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
A6
A7
30
31
32
33
34
35
36
37
A0
A1
A2
A3
A4
A5
A6
A7
2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
A16
29
28
27
25
24
23
22
21
3
4
5
6
7
8
9
PA0
PA1
PA2
PA3
PA4
PA5
1
A17
PA6
PA7
24
25
26
27
28
AD8
AD9
AD10
AD11
AD12
21
20
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
X1
X2
AD8
AD9
39
40
41
42
43
44
45
46
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
7
6
5
4
3
2
52
51
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
AD10
AD11
AD12
AD13
AD14
AD15
11
13
14
15
16
17
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
29
30
AD13
AD14
AD15
31
P2.7
ALE
RD
47
50
33
32
P3.5/T1
(
)
CNTL0 WR
ALE
10
RST
RESET
(
)
CNTL1 RD
PSEN
20
19
18
17
14
13
12
11
18
19
WR
A16
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
WR
RD/A16
35
49
CNTL2(PSEN)
EA
10
9
8
PD0-ALE
PD1
PD2
48
RESET
RESET
RESET
AI02881C
Note: 1. The A16 and A17 connections are optional.
2. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.
48/110
PSD813F1V
Figure 24. Interfacing the PSD with the 80C251, with RD and PSEN Inputs
80C251SB
PSD
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
A6
A7
30
31
32
33
34
35
36
37
A0
A1
A2
A3
A4
A5
A6
A7
2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
29
3
4
5
6
7
8
9
PA0
28
PA1
27
PA2
25
PA3
24
PA4
23
PA5
22
PA6
21
PA7
24
25
26
27
28
AD8
AD9
AD10
AD11
AD12
21
20
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
X1
X2
AD8
AD9
39
40
41
42
43
44
45
46
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
7
PB0
6
AD10
AD11
AD12
AD13
AD14
AD15
PB1
5
11
13
14
15
16
17
PB2
4
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
29
30
AD13
AD14
AD15
PB3
3
PB4
2
31
PB5
52
P2.7
PB6
51
PB7
P3.5/T1
33
32
ALE
RD
47
50
(
)
CNTL0 WR
ALE
10
RST
EA
RESET
(
)
CNTL1 RD
PSEN
20
PC0
19
18
19
WR
WR
RD/A16
PC1
18
PSEN
35
49
CNTL2(PSEN)
PC2
17
PC3
14
10
9
8
PC4
13
PD0-ALE
PD1
PD2
PC5
12
PC6
11
PC7
48
RESET
RESET
RESET
AI02882C
Table 18. 80C251 Configurations
80C251 READ/WRITE
Pins
Configuration
Connecting to PSD Pins
Page Mode
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31
compatible A7-A0 multiplex with
D7-D0
1
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A7-A0 multiplex with D7-D0
2
3
WR
PSEN only
CNTL0
CNTL1
Page Mode
A15-A8 multiplex with D7-D0
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A15-A8 multiplex with D7-D0
4
49/110
PSD813F1V
80C51XA
The Philips 80C51XA microcontroller family sup-
ports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multi-
plexed, while (A19-A4) are multiplexed with data
bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-
A4) are multiplexed with data bits (D7-D0).
The 80C51XA improves bus throughput and per-
formance by executing Burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 lines to fetch up to 16 bytes of code. The
PSD access time is then measured from address
A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the nor-
mal bus cycle, except the address setup and hold
time with respect to ALE does not apply.
The 80C51XA can be configured to operate in
eight-bit data mode. (shown in Figure 25).
Figure 25. Interfacing the PSD with the 80C51X, 8-bit Data Bus
80C51XA
PSD
21
20
30
31
32
33
34
35
36
37
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
2
3
4
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A15
A16
A17
A18
A19
XTAL1
XTAL2
ADIO0
A0/WRH
A1
29 A0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
28 A1
27 A2
25 A3
24
23
22
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
5
43
42
41
40
39
11
13
6
RXD0
TXD0
RXD1
TXD1
7
21
PA7
38
37
A12
A13
A14
A15
A16
A17
A18
A19
39
40
41
42
43
44
45
46
ADIO8
ADIO9
9
8
16
7
36
24
25
26
27
28
29
30
31
T2EX
T2
T0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
6
5
4
3
2
52
51
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
10
14
15
RST
INT0
INT1
RESET
47
50
(
)
CNTL0 WR
20
19
18
17
14
13
12
11
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
(
)
CNTL1 RD
PSEN
32
49
35
17
PSEN
RD
CNTL2(PSEN)
EA/WAIT
BUSW
19
18
33
RD
WR
10
8
9
PD0-ALE
PD1
WRL
ALE
ALE
PD2
48
RESET
RESET
AI02883C
50/110
PSD813F1V
68HC11
Figure 26 shows an interface to a 68HC11 where
the PSD is configured in 8-bit multiplexed mode
with E and R/W settings. The DPLD can generate
the READ and WR signals for external devices.
Figure 26. Interfacing the PSD with a 68HC11
AD7-AD0
AD7-AD0
PSD
30
31
32
33
34
35
36
37
AD0
AD1
29
28
27
25
24
23
22
21
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
68HC11
AD2
AD3
AD4
AD5
AD6
AD7
31
PA3
PA4
PA5
PA6
PA7
8
7
30
29
28
27
XT
EX
17
19
18
RESET
RESET
IRQ
XIRQ
39
40
41
42
43
44
45
46
7
6
5
4
3
2
52
51
42
41
40
39
38
37
36
35
A8
A9
A10
A11
A12
A13
A14
A15
ADIO8
ADIO9
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
2
MODB
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
34
33
32
PA0
PA1
PA2
9
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
43
44
45
46
47
48
49
50
20
19
18
17
14
13
12
11
10
11
12
13
14
15
16
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
47
50
_
CNTL0(R W)
CNTL1(E)
49
CNTL2
10
9
8
PD0 AS
–
PD1
PD2
20
21
22
23
24
25
52
51
PD0
PD1
PD2
PD3
PD4
PD5
VRH
VRL
48
RESET
3
MODA
5
4
6
E
E
AS
AS
R/W
R/W
RESET
AI02884C
51/110
PSD813F1V
I/O PORTS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP address space.
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND array enable product term
and the Direction Register. If the enable product
term of any of the array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The topics discussed in this section are:
The contents of these registers can be altered by
the microcontroller. The PDB feedback path al-
lows the microcontroller to check the contents of
the registers.
Ports A, B, and C have embedded Input Macro-
cells (IMCs). The IMCs can be configured as latch-
es, registers, or direct inputs to the PLDs. The
latches and registers are clocked by the address
strobe (AS/ALE) or a product term from the PLD
AND array. The outputs from the IMCs drive the
PLD input bus and can be read by the microcon-
troller. See the section entitled Input
Macrocell, page 42.
■
■
■
■
■
General Port architecture
Port Operating Modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port Functionality.
General Port Architecture
The general architecture of the I/O Port is shown
in Figure 27., page 53. Individual Port architec-
tures are shown in Figure 29., page 60 to Figure
32., page 63. In general, once the purpose for a
port pin has been defined, that pin will no longer be
available for other purposes. Exceptions will be
noted.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the microcontroller writing to the Control
Registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft Ex-
press must be programmed into the device and
cannot be changed unless the device is repro-
grammed. The modes that can be changed by the
microcontroller can be done so dynamically at run-
time. The PLD I/O, Data Port, Address Input, and
Peripheral I/O modes are the only modes that
must be defined before programming the device.
All other modes can be changed by the microcon-
troller at run-time.
As shown in Figure 27., page 53, the ports contain
an output multiplexer whose selects are driven by
the configuration bits in the Control Registers
(Ports A and B only) and PSDsoft Express Config-
uration. Inputs to the multiplexer include the fol-
lowing:
■
■
■
■
Output data from the Data Out Register
Latched address outputs
CPLD Macrocell output
External Chip Select from CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
PDB is connected to the Internal Data Bus for
feedback and can be read by the microcontroller.
The Data Out and Macrocell outputs, Direction
and Control Registers, and port pin input are all
connected to the PDB.
Table 19., page 54 summarizes which modes are
available on each port. Table 22., page 57 shows
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following subsections.
52/110
PSD813F1V
Figure 27. General I/O Port Architecture
DATA OUT
REG.
DATA OUT
ADDRESS
D
Q
WR
ADDRESS
ALE
PORT PIN
D
G
Q
OUTPUT
MUX
MACROCELL OUTPUTS
EXT CS
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
CONTROL REG.
ENABLE OUT
D
Q
WR
WR
DIR REG.
D
Q
(
)
ENABLE PRODUCT TERM .OE
INPUT
MACROCELL
CPLD-INPUT
AI02885
53/110
PSD813F1V
MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the
PSD ports to expand its own I/O ports. By setting
up the CSIOP space, the ports on the PSD are
mapped into the microcontroller address space.
The addresses of the ports are listed in Table
6., page 17.
A port pin can be put into MCU I/O mode by writing
a ‘0’ to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled Peripheral I/O
Mode, page 56. When the pin is configured as an
output, the content of the Data Out Register drives
the pin. When configured as an input, the micro-
controller can read the port input through the Data
In buffer. See Figure 27., page 53.
from the PLD, or by setting the corresponding bit
in the Direction Register to ‘0.’ The corresponding
bit in the Direction Register must not be set to ‘1’ if
the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by de-
claring the port pins, and then writing an equation
assigning the PLD I/O to a port.
Address Out Mode
For microcontrollers with a multiplexed address/
data bus, Address Out Mode can be used to drive
latched addresses onto the port pins. These port
pins can, in turn, drive external devices. Either the
output enable or the corresponding bits of both the
Direction Register and Control Register must be
set to a ‘1’ for pins to use Address Out Mode. This
must be done by the MCU at run-time. See Table
21., page 55 for the address output pin assign-
ments on Ports A and B for various MCUs.
For non-multiplexed 8-bit bus mode, address lines
A7-A0 are available to Port B in Address Out
Mode.
Note: do not drive address lines with Address Out
Mode to an external memory device if it is intended
for the MCU to boot from the external device. The
MCU must first boot from PSD memory so the Di-
rection and Control register bits can be set.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equation are written for them in PS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells, and/or as an output from
the CPLD’s Output Macrocells. The output can be
tri-stated with a control signal. This output enable
control signal can be defined by a product term
Table 19. Port Operating Modes
Port Mode
MCU I/O
Port A
Port B
Port C
Port D
Yes
Yes
Yes
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Yes
No
Yes
Yes
No
No
Yes
No
No
No
Yes
Additional Ext. CS Outputs No
PLD Inputs
Yes
Yes
Yes
Yes
Yes (A7-A0)
or (A15-A8)
Address Out
Yes (A7-A0
No
No
Address In
Data Port
Yes
Yes
No
No
No
Yes
No
No
Yes
No
No
No
Yes (D7-D0)
Peripheral I/O
JTAG ISP
Yes
No
1
Yes
Note: 1. Can be multiplexed with other I/O functions.
54/110
PSD813F1V
Table 20. Port Operating Mode Settings
Control
Direction
VM
Defined in
PSDabel
Defined in PSD
Configuration
Mode
Register Register Register JTAG Enable
Setting
Setting
Setting
1 = output,
0 = input
1
MCU I/O
Declare pins only
0
N/A
N/A
N/A
2
(Note )
2
PLD I/O
Logic equations
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
(Note )
Data Port (Port A)
Specify bus type
N/A
N/A
2
Address Out (Port A,B) Declare pins only
1 (Note )
Address In
(Port A,B,C,D)
Logic equation for
Input Macrocells
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
N/A
PIO bit = 1 N/A
N/A JTAG_Enable
3
JTAGSEL
JTAG Configuration N/A
JTAG ISP (Note )
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port C.
Table 21. I/O Port Latched Address Output Assignments
MCU
Port A (PA3-PA0)
Port A (PA7-PA4)
Port B (PB3-PB0)
Port B (PB7-PB4)
N/A
1
8051XA (8-Bit)
Address a7-a4
Address A11-A8
N/A
80C251
(Page Mode)
N/A
N/A
Address A11-A8
Address A3-A0
Address A3-A0
Address A15-A12
Address A7-A4
Address A7-A4
All Other
8-Bit Multiplexed
Address A3-A0
N/A
Address A7-A4
N/A
8-Bit
Non-Multiplexed Bus
Note: 1. N/A = Not Applicable.
55/110
PSD813F1V
Address In Mode
Peripheral I/O Mode
For microcontrollers that have more than 16 ad-
dress lines, the higher addresses can be connect-
ed to Port A, B, C, and D. The address input can
be latched in the Input Macrocell by the address
strobe (ALE/AS). Any input that is included in the
DPLD equations for the PLD’s Flash, EEPROM, or
SRAM is considered to be an address input.
Peripheral I/O Mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-stateable, bi-directional data buffer
for the microcontroller. Peripheral I/O Mode is en-
abled by setting Bit 7 of the VM Register to a ‘1.’
Figure 28 shows how Port A acts as a bi-direction-
al buffer for the microcontroller data bus if Periph-
eral I/O Mode is enabled. An equation for PSEL0
and/or PSEL1 must be written in PSDabel. The
buffer is tri-stated when PSEL 0 or PSEL1 is not
active.
Data Port Mode
Port A can be used as a data bus port for a micro-
controller with a non-multiplexed address/data
bus. The Data Port is connected to the data bus of
the microcontroller. The general I/O functions are
disabled in Port A if the port is configured as a
Data Port.
Figure 28. Peripheral I/O Mode
RD
PSEL0
PSEL
PSEL1
D0-D7
VM REGISTER BIT 7
PA0-PA7
DATA BUS
WR
AI02886
56/110
PSD813F1V
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port C
because ISP is not performed during normal sys-
tem operation. For more information on the JTAG
Port, see the section entitled PROGRAMMING IN-
CIRCUIT
INTERFACE, page 71.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 6., page 17. The addresses in Ta-
ble 6., page 17 are the offsets in hexadecimal from
the base of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 22, are used for setting the
Port configurations. The default Power-up state for
each register in Table 22 is 00h.
USING
THE
JTAG
SERIAL
Control Register
Any bit reset to ‘0’ in the Control Register sets the
corresponding port pin to MCU I/O Mode, and a ‘1’
sets it to Address Out Mode. The default mode is
MCU I/O. Only Ports A and B have an associated
Control Register.
Table 22. Port Configuration Registers (PCR)
Register Name
Control
Port
MCU Access
WRITE/READ
WRITE/READ
WRITE/READ
A,B
Direction
A,B,C,D
A,B,C,D
1
Drive Select
Note: 1. See Table 26., page 58 for Drive Register bit definition.
57/110
PSD813F1V
Direction Register
The Direction Register, in conjunction with the out-
put enable (except for Port D), controls the direc-
tion of data flow in the I/O Ports. Any bit set to ‘1’
in the Direction Register will cause the corre-
sponding pin to be an output, and any bit set to ‘0’
will cause it to be an input. The default mode for all
port pins is input.
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to ‘1.’ The default rate is slow slew.
Table 26 shows the Drive Register for Ports A, B,
C, and D. It summarizes which pins can be config-
ured as Open Drain outputs and which pins the
slew rate can be set for.
Figure 29., page 60 and Figure 30., page 61 show
the Port Architecture diagrams for Ports A/B and
C, respectively. The direction of data flow for Ports
A, B, and C are controlled not only by the direction
register, but also by the output enable product
term from the PLD AND array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
Table 23. Port Pin Direction Control, Output
Enable P.T. Not Defined
Direction Register Bit
Port Pin Mode
0
1
Input
Output
An example of a configuration for a port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 25. Since
Port D only contains three pins (shown in Figure
32., page 63), the Direction Register for Port D
has only the three least significant bits active.
Table 24. Port Pin Direction Control, Output
Enable P.T. Defined
Direction
Output Enable
P.T.
Port Pin Mode
Register Bit
Drive Select Register
0
0
1
1
0
Input
The Drive Select Register configures the pin driver
as Open Drain or CMOS for some port pins, and
controls the slew rate for the other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain.
1
0
1
Output
Output
Output
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
‘1.’ The default pin drive is CMOS.
Aside: the slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
Table 25. Port Direction Assignment Example
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
1
1
1
Table 26. Drive Register Pin Assignment
Drive
Bit 7
Bit 6
Bit 5
Bit 4
Open
Bit 3
Bit 2
Bit 1
Bit 0
Register
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port A
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Port C
Port D
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
1
1
1
1
1
NA
NA
NA
NA
NA
Note: 1. NA = Not Applicable.
58/110
PSD813F1V
Port Data Registers
The Port Data Registers, shown in Table 27, are
used by the MCU to write data to or read data from
the ports. Table 27 shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
below.
Output Macrocells (OMC)
The CPLD Output Macrocells (OMC) occupy a lo-
cation in the microcontroller’s address space. The
microcontroller can read the output of the OMCs.
If the Mask Macrocell Register bits are not set,
writing to the Macrocell loads data to the Macrocell
flip flops. See the section entitled PLD’S, page 34.
Data In
Port pins are connected directly to the Data In buf-
fer. In MCU I/O input mode, the pin input is read
through the Data In buffer.
Mask Macrocell Register
Each Mask Register bit corresponds to an OMC
flip flop. When the Mask Register bit is set to a “1”,
loading data into the OMC flip flop is blocked. The
default value is “0” or unblocked.
Data Out Register
Stores output data written by the MCU in the MCU
I/O output mode. The contents of the Register are
driven out to the pins if the Direction Register or
the output enable product term is set to ‘1.’ The
contents of the register can also be read back by
the MCU.
Input Macrocells (IMC)
The IMCs can be used to latch or store external in-
puts. The outputs of the IMCs are routed to the
PLD input bus, and can be read by the microcon-
troller.
Refer
to
the
section
entitled
PLD’S, page 34 for a detailed description.
Table 27. Port Data Registers
Register Name
Port
MCU Access
Data In
A,B,C,D
A,B,C,D
READ – input on pin
Data Out
WRITE/READ
READ – outputs of macrocells
WRITE – loading macrocell flip-flop
Output Macrocell
Mask Macrocell
A,B,C
A,B,C
WRITE/READ – prevents loading into a given
macrocell
Input Macrocell
Enable Out
A,B,C
A,B,C
READ – outputs of the Input Macrocells
READ – the output enable control of the port driver
59/110
PSD813F1V
Enable Out
The Enable Out register can be read by the micro-
controller. It contains the output enable values for
a given port. A ‘1’ indicates the driver is in output
mode. A ‘0’ indicates the driver is in tri-state and
the pin is in input mode.
■
■
CPLD Input – Via the Input Macrocells (IMC).
Latched Address output – Provide latched
address output as per Table 21., page 55.
Address In – Additional high address inputs
using the Input Macrocells (IMC).
Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be
configured to Open Drain Mode.
Data Port – Port A to D7-D0 for 8 bit non-
multiplexed bus
Multiplexed Address/Data port for certain
types of MCU bus interfaces.
■
■
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure 29. The two ports can be
configured to perform one or more of the following
functions:
■
■
■
■
MCU I/O Mode
■
CPLD Output – Macrocells McellAB7-
McellAB0 can be connected to Port A or Port
B. McellBC7-McellBC0 can be connected to
Port B or Port C.
Peripheral Mode – Port A only
Figure 29. Port A and Port B Structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT
A OR B PIN
ADDRESS
ALE
ADDRESS
D
G
Q
[
]
[
]
A 7:0 OR A 15:8
OUTPUT
MUX
MACROCELL OUTPUTS
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
CONTROL REG.
ENABLE OUT
D
Q
WR
WR
DIR REG.
D
Q
(
)
ENABLE PRODUCT TERM .OE
CPLD-INPUT
INPUT
MACROCELL
AI02887
60/110
PSD813F1V
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 30):
PSD device. (See the section entitled
PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE, page 71, for
more information on JTAG programming.)
■
MCU I/O Mode
■
CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
■
Open Drain – Port C pins can be configured in
Open Drain Mode
■
■
CPLD Input – via the Input Macrocells (IMC)
Address In – Additional high address inputs
using the Input Macrocells (IMC).
Port C does not support Address Out mode, and
therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in
certain MCU interfaces.
■
In-System Programming (ISP) – JTAG port
can be enabled for programming/erase of the
Figure 30. Port C Structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT C PIN
1
SPECIAL FUNCTION
OUTPUT
MUX
[
]
MCELLBC 7:0
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
ENABLE OUT
DIR REG.
D
Q
WR
(
)
ENABLE PRODUCT TERM .OE
INPUT
MACROCELL
1
SPECIAL FUNCTION
CPLD-INPUT
CONFIGURATION
BIT
AI02888B
Note: 1. ISP.
61/110
PSD813F1V
Port D – Functionality and Structure
Port D has three I/O pins. See Figure 31 and Fig-
ure 32., page 63. This port does not support Ad-
dress Out mode, and therefore no Control
Register is required. Port D can be configured to
perform one or more of the following functions:
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
■
PD0 – ALE, as address strobe input
■
PD1 – CLKIN, as clock input to the macrocells
flip-flops and APD counter
■
MCU I/O Mode
■
PD2 – CSI, as active Low chip select input. A
High input will disable the Flash memory,
EEPROM, SRAM and CSIOP.
■
CPLD Output – External Chip Select (ECS0-
ECS2)
■
■
CPLD Input – direct input to the CPLD, no
Input Macrocells (IMC)
Slew rate – pins can be set up for fast slew
rate
Figure 31. Port D Structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT D PIN
OUTPUT
MUX
[
]
ECS 2:0
READ MUX
OUTPUT
SELECT
P
D
B
DATA IN
ENABLE PRODUCT
TERM (.OE)
DIR REG.
D
Q
WR
CPLD-INPUT
AI02889
62/110
PSD813F1V
External Chip Select
The CPLD also provides three External Chip Se-
lect (ECS0-ECS2) outputs on Port D pins that can
be used to select external devices. Each External
Chip Select (ECS0-ECS2) consists of one product
term that can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 32.)
Figure 32. Port D External Chip Select Signals
ENABLE (.OE)
DIRECTION
REGISTER
PD0 PIN
ECS0
PT0
PT1
PT2
POLARITY
BIT
ENABLE (.OE)
DIRECTION
REGISTER
PD1 PIN
ECS1
POLARITY
BIT
ENABLE (.OE)
DIRECTION
REGISTER
PD2 PIN
ECS2
POLARITY
BIT
AI02890
63/110
PSD813F1V
POWER MANAGEMENT
The PSD offers configurable power saving op-
tions. These options may be used individually or in
combinations, as follows:
changing state externally (noise, other
devices on the MCU bus, etc.). Keep in mind
that any unblocked PLD input signals that are
changing states keeps the PLD out of standby
mode, but not the memories.
The PSD Chip Select Input (CSI) on all
families can be used to disable the internal
memories, placing them in standby mode
even if inputs are changing. This feature does
not block any internal signals or disable the
PLDs. This is a good alternative to using the
APD logic, especially if your MCU has a chip
select output. There is a slight penalty in
memory access time when the CSI signal
makes its initial transition from deselected to
selected.
–
All memory types in a PSD (Flash, EEPROM,
and SRAM) are built with Zero-Power
technology. In addition to using special silicon
design methodology, Zero-Power technology
puts the memories into standby mode when
address/data inputs are not changing (zero
DC current). As soon as a transition occurs on
an input, the affected memory “wakes up”,
changes and latches its outputs, then goes
back to standby. The designer does not have
to do anything special to achieve memory
standby mode when no inputs are changing—
it happens automatically.
–
The PLD sections can also achieve standby
mode when its inputs are not changing, as de-
scribed in the section entitled PLD Power
Management, page 66.
Like the Zero-Power feature, the Automatic
Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The
APD will block MCU address/data signals from
reaching the memories and PLDs. This
feature is available on all PSD devices. The
APD Unit is described in more detail in the
sections entitled Automatic Power-down
(APD) Unit and Power-down Mode, page 65.
Built in logic will monitor the address strobe of
the MCU for activity. If there is no activity for a
certain time period (MCU is asleep), the APD
logic initiates Power Down Mode (if enabled).
Once in Power Down Mode, all address/data
signals are blocked from reaching PSD
memories and PLDs, and the memories are
deselected internally. This allows the
–
The PMMR registers can be written by the
MCU at run-time to manage power. PSD
supports “blocking bits” in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 36., page 73 and Figure 37., page 73).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations.
The PSD has a Turbo Bit in the PMMR0
register. This bit can be set to disable the
Turbo Mode feature (default is Turbo Mode
on). While Turbo Mode is disabled, the PLDs
can achieve standby current when no PLD
inputs are changing (zero DC current). Even
when inputs do change, significant power can
be saved at lower frequencies (AC current),
compared to when Turbo Mode is enabled.
When the Turbo Mode is enabled, there is a
significant DC current component and the AC
component is higher.
–
memories and PLDs to remain in standby
mode even if the address/data lines are
64/110
PSD813F1V
Automatic Power-down (APD) Unit and Power-down Mode
The APD Unit, shown in Figure 33, puts the PSD
into Power-down mode by monitoring the activity
of Address Strobe (ALE/AS, PD0). If the APD Unit
is enabled, as soon as activity on Address Strobe
(ALE/AS, PD0) stops, a four bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), the Power-down (PDN) signal becomes ac-
tive, and the PSD enters Power-down mode, as
discussed next.
setting the appropriate bits in the PMMR
registers. The blocked signals include MCU
control signals and the common clock
(CLKIN). Note that blocking CLKIN from the
PLDs will not block CLKIN from the APD unit.
All PSD memories enter Standby Mode and
are drawing standby current. However, the
PLDs and I/O ports do not go into Standby
Mode because you don’t want to have to wait
for the logic and I/O to “wake-up” before their
outputs can change. See Table 28 for Power
Down Mode effects on PSD ports.
Typical standby current are of the order of the
microampere (see Table 29). These standby
current values assume that there are no
transitions on any PLD input.
–
–
Power-down Mode
By default, if you enable the PSD APD unit, Power
Down Mode is automatically enabled. The device
will enter Power Down Mode if the address strobe
(ALE/AS) remains inactive for fifteen CLKIN (pin
PD1) clock periods.
The following should be kept in mind when the
PSD is in Power Down Mode:
Table 28. Power-down Mode’s Effect on Ports
–
If the address strobe starts pulsing again, the
PSD will return to normal operation. The PSD
will also return to normal operation if either the
CSI input returns low or the Reset input
returns high.
The MCU address/data bus is blocked from all
memories and PLDs.
Port Function
MCU I/O
Pin Level
No Change
PLD Out
No Change
Undefined
Tri-State
Address Out
Data Port
–
–
Various signals can be blocked (prior to Power
Down Mode) from entering the PLDs by
Peripheral I/O
Tri-State
Figure 33. APD Unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
PD
CLR
APD
EEPROM SELECT
FLASH SELECT
COUNTER
RESET
EDGE
DETECT
PD
CSI
PLD
SRAM SELECT
POWER DOWN
CLKIN
(
)
PDN SELECT
DISABLE
FLASH/EEPROM/SRAM
AI02891
Table 29. PSD Timing and Stand-by Current during Power-down Mode
Typical Stand-by Current
PLD Propagation
Delay
Memory
Access Time
Access Recovery Time
to Normal Access
Mode
5V V
3V V
CC
CC
(1)
(2)
(2)
t
Power-down
No Access
Normal t
LVDV
50µA
25µA
PD
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
65/110
PSD813F1V
For Users of the HC11 (or compatible)
PLD and I/O pins remain operational when CSI is
High.
The HC11 turns off its E clock when it sleeps.
Therefore, if you are using an HC11 (or compati-
ble) in your design, and you wish to use the Pow-
er-down mode, you must not connect the E clock
to CLKIN (PD1). You should instead connect an
independent clock signal to the CLKIN input
(PD1). The clock frequency must be less than 15
times the frequency of AS. The reason for this is
that if the frequency is greater than 15 times the
frequency of AS, the PSD will keep going into
Power-down mode.
Note: There may be a timing penalty when using
the CSI pin depending on the speed grade of the
PSD that you are using. See the timing parameter
t
in Table 63., page 95 or Table 64., page 95.
SLQV
Input Clock
The PSD provides the option to turn off the CLKIN
input to the PLD to save AC power consumption.
The CLKIN is an input to the PLD AND array and
the Output Macrocells. During Power Down Mode,
or, if the CLKIN input is not being used as part of
the PLD logic equation, the clock should be dis-
abled to save AC power. The CLKIN will be dis-
connected from the PLD AND array or the
Macrocells by setting bits 4 or 5 to a ‘1’ in PMMR0.
Other Power Saving Options
The PSD offers other reduced power saving op-
tions that are independent of the Power-down
mode. Except for the Chip Select Input (CSI, PD2)
feature, they are enabled by setting bits in the
PMMR0 and PMMR2 registers.
Figure 34. Enable Power-down Flow Chart
PLD Power Management
RESET
The power and speed of the PLDs are controlled
by the Turbo bit (bit 3) in the PMMR0. By setting
the bit to ‘1’, the Turbo mode is disabled and the
PLDs consume Zero Power current when the in-
puts are not switching for an extended time of
70ns. The propagation delay time will be in-
creased by 10ns after the Turbo bit is set to ‘1’
(turned off) when the inputs change at a composite
frequency of less than 15 MHz. When the Turbo bit
is set to a ‘0’ (turned on), the PLDs run at full power
and speed. The Turbo bit affects the PLD’s D.C.
power, AC power, and propagation delay.
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
Note: Blocking MCU control signals with PMMR2
bits can further reduce PLD AC power consump-
tion.
ALE/AS idle
for 15 CLKIN
clocks?
No
PSD Chip Select Input (CSI, PD2)
Pin PD2 of Port D can be configured in PSDsoft
Express as the CSI input. When low, the signal se-
lects and enables the internal Flash, EEPROM,
SRAM, and I/O for READ or WRITE operations in-
volving the PSD. A high on the CSI pin will disable
the Flash memory, EEPROM, and SRAM, and re-
duce the PSD power consumption. However, the
Yes
PSD in Power
Down Mode
AI02892
66/110
PSD813F1V
Table 30. Power Management Mode Registers PMMR0 (Note 1)
Bit 0
Bit 1
Bit 2
Bit 3
X
0
Not used, and should be set to zero.
0 = off Automatic Power-down (APD) is disabled.
1 = on Automatic Power-down (APD) is enabled.
APD Enable
X
0
Not used, and should be set to zero.
0 = on PLD Turbo mode is on
PLD Turbo
1 = off PLD Turbo mode is off, saving power.
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo bit is 0.
0 = on
Bit 4
Bit 5
PLD Array clk
PLD MCell clk
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
0 = on CLKIN (PD1) input to the PLD macrocells is connected.
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6
Bit 7
X
X
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Table 31. Power Management Mode Registers PMMR2 (Note 1)
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
X
0
Not used, and should be set to zero.
0 = on Cntl0 input to the PLD AND Array is connected.
PLD Array
CNTL0
Bit 2
Bit 3
Bit 4
Bit 5
1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
0 = on Cntl1 input to the PLD AND Array is connected.
PLD Array
CNTL1
1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
0 = on Cntl2 input to the PLD AND Array is connected.
PLD Array
CNTL2
1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
0 = on ALE input to the PLD AND Array is connected.
PLD Array
ALE
1 = off ALE input to PLD AND Array is disconnected, saving power.
0 = on DBE input to the PLD AND Array is connected.
PLD Array
DBE
Bit 6
Bit 7
1 = off DBE input to PLD AND Array is disconnected, saving power.
X
0
Not used, and should be set to zero.
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
67/110
PSD813F1V
Input Control Signals
The PSD provides the option to turn off the input
control signals (CNTL0, CNTL1, CNTL2, ALE, and
DBE) to the PLD to save AC power consumption.
These control signals are inputs to the PLD AND
array.
During Power Down Mode, or, if any of them are
not being used as part of the PLD logic equation,
these control signals should be disabled to save
AC power. They will be disconnected from the
PLD AND array by setting bits 2, 3, 4, 5, and 6 to
a ‘1’ in the PMMR2.
Table 32. APD Counter Operation
APD Enable Bit ALE PD Polarity
ALE Level
APD Counter
Not Counting
0
1
1
1
X
X
1
0
X
Pulsing
Not Counting
1
0
Counting (Generates PDN after 15 Clocks)
Counting (Generates PDN after 15 Clocks)
68/110
PSD813F1V
RESET TIMING AND DEVICE STATUS AT RESET
Power-On Reset
Warm Reset
Once the device is up and running, the device can
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration t
(See Tables 67
be reset with a much shorter pulse of t
(See
time
NLNH-PO
CC
NLNH
and 68 for values) after V is steady. During this
Tables 67 and 68 for values). The same t
OPR
period, the device loads internal configurations,
clears some of the registers and sets the Flash
memory or EEPROM into Operating mode. After
the rising edge of Reset (RESET), the PSD re-
mains in the Reset mode for an additional period,
is needed before the device is operational after
warm reset. Figure 35 shows the timing of the
power on and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 33., page 70 shows the I/O pin, register and
PLD status during Power On Reset, Warm reset
and Power-down mode. PLD outputs are always
valid during warm reset, and they are valid in Pow-
er On Reset once the internal PSD Configuration
bits are loaded. This loading of PSD is completed
t
(See Tables 67 and 68 for values), before the
OPR
first memory access is allowed.
The PSD Flash or EEPROM memory is reset to
the READ mode upon power up. The FSi and
EESi select signals along with the write strobe sig-
nal must be in the false state during power-up re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of a write strobe signal. The PSD au-
tomatically prevents write strobes from reaching
typically long before the V ramps up to operat-
CC
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDabel equa-
tions.
the EEPROM memory array for about 5ms (t
WL
EEH-
). Any Flash memory WRITE cycle initiation is
prevented automatically when V is below V
.
CC
LKO
Figure 35. Reset (RESET) Timing
VCC(min)
V
CC
t
NLNH
t
t
OPR
t
t
OPR
NLNH-PO
NLNH-A
Power-On Reset
Warm Reset
RESET
AI02866b
69/110
PSD813F1V
Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
Port Configuration
MCU I/O
Power-On Reset
Input mode
Warm Reset
Input mode
Power-down Mode
Unchanged
Valid after internal PSD
configuration bits are
loaded
Depends on inputs to PLD
(addresses are blocked in
PD mode)
PLD Output
Valid
Address Out
Data Port
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Not defined
Tri-stated
Tri-stated
Peripheral I/O
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to ‘0’
Unchanged
Unchanged
Cleared to ‘0’ by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
Macrocells flip-flop status
Initialized, based on the
selection in PSDsoft
Express
Initialized, based on the
selection in PSDsoft
Express
1
Unchanged
Unchanged
VM Register
Configuration menu
Configuration menu
All other registers
Cleared to ‘0’
Cleared to ‘0’
Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to ‘0’ on Power-On Reset or Warm Reset.
70/110
PSD813F1V
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG interface on the PSD can be enabled on
Port C (see Table 34., page 72). All memory
(Flash and EEPROM), PLD logic, and PSD config-
uration bits may be programmed through the
JTAG interface. A blank part can be mounted on a
printed circuit board and programmed using
JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up program and erase operations.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the PSD
is set by the designer in the PSDsoft
Express Configuration utility. This
dedicates the pins for JTAG at all
times (compliant with IEEE 1149.1) */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-
time by writing to the PSD register,
JTAG Enable. This register is located
at address CSIOP + offset C7h. Setting
the JTAG_ENABLE bit in this register
will enable the pins for JTAG use. This
bit is cleared by a PSD reset or the
microcontroller. See Table
Note: By default, on a blank PSD (as shipped from
factory or after erasure), four pins on Port C are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO.
35., page 72 for bit definition. */
PSD_product_term_enabled;
Standard JTAG Signals
/* A dedicated product term (PT) inside the
PSDcanbeusedtoenablethe JTAG pins.
This PT has the reserved name JTAGSEL.
Once defined as a node in PSDabel, the
designer can write an equation for
JTAGSEL. This method is used when the
Port C JTAG pins are multiplexed with
other I/O signals. It is recommended to
logically tie the node JTAGSEL to the
JEN\ signal on the Flashlink cable when
multiplexing JTAG signals. (AN1153)
The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
serial command from an external JTAG controller
device (such as FlashLink or Automated Test
Equipment). When the enabling command is re-
ceived from the external JTAG controller, TDO be-
comes an output and the JTAG channel is fully
functional inside the PSD. The same command
that enables the JTAG channel may optionally en-
able the two additional JTAG pins, TSTAT and
TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port C pins. For purposes of discussion, the logic
label JTAG_ON will be used. When JTAG_ON is
true, the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
The PSD supports JTAG In-System-Configuration
(ISC) commands, but not Boundary Scan. A defi-
nition of these JTAG-ISC commands and se-
quences are defined in a supplemental document
available from ST. ST’s PSDsoft Express software
tool and FlashLink JTAG programming cable im-
plement these JTAG-ISC commands. This docu-
ment is needed only as a reference for designers
who use a FlashLink to program their PSD.
71/110
PSD813F1V
JTAG Extensions
Security, Flash memory and EEPROM
Protection
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG pins (TMS, TCK, TDI,
and TDO). They are used to speed programming
and erase functions by indicating status on PSD
pins instead of having to scan the status out seri-
ally using the standard JTAG channel.
TERR will indicate if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal will go Low (active) when an
error condition occurs, and stay Low until an
“ISC_CLEAR” command is executed or a chip re-
set pulse is received after an “ISC-DISABLE” com-
mand. TERR does not apply to EEPROM.
When the security bit is set, the device cannot be
read on a device programmer or through the JTAG
Port. When using the JTAG Port, only a full chip
erase command is allowed. All other program/
erase/verify commands are blocked. Full chip
erase returns the part to a non-secured blank
state. The Security Bit can be set in PSDsoft Ex-
press Configuration.
All Flash Memory and EEPROM sectors can indi-
vidually be sector protected against erasures. The
sector protect bits can be set in PSDsoft Express
Configuration.
TSTAT behaves the same as the Ready/Busy sig-
nal described in the section entitled Ready/Busy
Pin (PC3), page 18. TSTAT will be High when the
PSD device is in READ mode (Flash memory and
EEPROM contents can be read). TSTAT will be
Low when Flash memory programming or erase
cycles are in progress, and also when data is be-
ing written to EEPROM.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand. This facilitates a wired-OR connection of
TSTAT signals from several PSD devices and a
wired-OR connection of TERR signals from those
same devices. This is useful when several PSD
devices are “chained” together in a JTAG environ-
ment.
Table 34. JTAG Port Signals
Port C Pin
PC0
JTAG Signals
TMS
Description
Mode Select
PC1
TCK
Clock
PC3
TSTAT
TERR
TDI
Status
PC4
Error Flag
Serial Data In
Serial Data Out
PC5
PC6
TDO
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to '1.' The PSD
Configuration Register bits are set to '0.' The code,
configuration, and PLD logic are loaded using the
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact your local sales representative.
Table 35. JTAG Enable Register
0 = off JTAG port is disabled.
Bit 0
JTAG_Enable
1 = on JTAG port is enabled.
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
X
X
X
X
X
X
X
0
0
0
0
0
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Note: The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configura-
tion bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is used
to enable the JTAG signals.
72/110
PSD813F1V
AC/DC PARAMETERS
The following tables describe the AD and DC pa-
rameters of the PSD:
The following are issues concerning the parame-
ters presented:
■
DC Electrical Specification
AC Timing Specification
PLD Timing
■
In the DC specification the supply current is
given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the PSD
is in each mode. Also, the supply power is
considerably different if the Turbo bit is ‘0.’
The AC power component gives the PLD,
EEPROM and SRAM mA/MHz specification.
Figures 36 and 37 show the PLD mA/MHz as
a function of the number of Product Terms
(PT) used.
■
–
–
–
–
Combinatorial Timing
Synchronous Clock Mode
Asynchronous Clock Mode
Input Macrocell Timing
■
■
MCU Timing
–
–
–
–
READ Timing
WRITE Timing
Peripheral Mode Timing
Power-down and Reset Timing
In the PLD timing parameters, add the
required delay when Turbo bit is ‘0.'
Figure 36. PLD I /Frequency Consumption (5V range)
CC
110
100
90
V
CC
= 5V
80
70
60
50
40
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI02894
Figure 37. PLD I /Frequency Consumption (3V range)
CC
60
V
CC
= 3V
50
40
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI03100
73/110
PSD813F1V
Table 36. Example of PSD Typical Power Calculation at V = 5.0V (Turbo Mode On)
CC
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
ꢀ Flash memory Access
ꢀ SRAM access
= 8MHz
= 4MHz
= 80ꢀ
= 15ꢀ
ꢀ I/O access
= 5ꢀ (no additional power above base)
Operational Modes
ꢀ Normal
= 10ꢀ
= 90ꢀ
ꢀ Power-down Mode
Number of product terms used
(from fitter report)
= 45 PT
ꢀ of total product terms
Turbo Mode
= 45/182 = 24.7ꢀ
= ON
Calculation (using typical values)
I
total
= Ipwrdown x ꢀpwrdown + ꢀnormal x (I (ac) + I (dc))
CC CC
CC
= Ipwrdown x ꢀpwrdown + ꢀ normal x (ꢀflash x 2.5mA/MHz x Freq ALE
+ ꢀSRAM x 1.5mA/MHz x Freq ALE
+ ꢀ PLD x 2mA/MHz x Freq PLD
+ #PT x 400µA/PT)
= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4MHz
+ 0.15 x 1.5mA/MHz x 4MHz
+ 2mA/MHz x 8MHz
+ 45 x 0.4mA/PT)
= 45µA + 0.1 x (8 + 0.9 + 16 + 18mA)
= 45µA + 0.1 x 42.9
= 45µA + 4.29mA
= 4.34mA
This is the operating power with no EEPROM WRITE or Flash memory Erase cycles. Calculation is based on I
0mA.
=
OUT
74/110
PSD813F1V
Table 37. Example of PSD Typical Power Calculation at V = 5.0V (Turbo Mode Off)
CC
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
ꢀ Flash memory Access
ꢀ SRAM access
= 8MHz
= 4MHz
= 80ꢀ
= 15ꢀ
ꢀ I/O access
= 5ꢀ (no additional power above base)
Operational Modes
ꢀ Normal
= 10ꢀ
= 90ꢀ
ꢀ Power-down Mode
Number of product terms used
(from fitter report)
= 45 PT
ꢀ of total product terms
Turbo Mode
= 45/182 = 24.7ꢀ
= Off
Calculation (using typical values)
I
total
= Ipwrdown x ꢀpwrdown + ꢀnormal x (I (ac) + I (dc))
CC CC
CC
= Ipwrdown x ꢀpwrdown + ꢀ normal x (ꢀflash x 2.5mA/MHz x Freq ALE
+ ꢀSRAM x 1.5mA/MHz x Freq ALE
+ ꢀ PLD x (from graph using Freq PLD))
= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4MHz
+ 0.15 x 1.5mA/MHz x 4MHz
+ 24mA)
= 45µA + 0.1 x (8 + 0.9 + 24)
= 45µA + 0.1 x 32.9
= 45µA + 3.29mA
= 3.34mA
This is the operating power with no EEPROM WRITE or Flash memory Erase cycles. Calculation is based on I
0mA.
=
OUT
75/110
PSD813F1V
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 38. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
125
235
7.0
Unit
°C
°C
V
T
Storage Temperature
–65
STG
1
T
LEAD
Lead Temperature during Soldering (20 seconds max.)
V
Input and Output Voltage (Q = V or Hi-Z)
–0.6
–0.6
IO
OH
V
Supply Voltage
7.0
V
CC
V
Device Programmer Supply Voltage
–0.6
14.0
2000
V
PP
2
V
–2000
V
ESD
Electrostatic Discharge Voltage (Human Body model)
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
76/110
PSD813F1V
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 39. Operating Conditions (5V devices)
Symbol
Parameter
Min.
4.5
–40
0
Max.
5.5
85
Unit
V
V
Supply Voltage
CC
Ambient Operating Temperature (Industrial)
Ambient Operating Temperature (Commercial)
°C
°C
T
A
70
Table 40. Operating Conditions (3V devices)
Symbol
Parameter
Min.
3.0
–40
0
Max.
3.6
85
Unit
V
V
Supply Voltage
CC
Ambient Operating Temperature (Industrial)
Ambient Operating Temperature (Commercial)
°C
°C
T
A
70
Table 41. AC Signal Letters for PLD Timings
Table 42. AC Signal Behavior Symbols for PLD
Timings
A
C
D
E
G
I
Address Input
t
Time
CEout Output
L
Logic Level Low or ALE
Logic Level High
Valid
Input Data
H
V
X
Z
E Input
Internal WDOG_ON signal
Interrupt Input
No Longer a Valid Logic Level
Float
L
ALE Input
PW
Pulse Width
N
P
Q
R
S
T
Reset Input or Output
Port Signal Output
Output Data
Note: Example: t
= Time from Address Valid to ALE Invalid.
AVLX
WR, UDS, LDS, DS, IORD, PSEN Inputs
Chip Select Input
R/W Input
W
Internal PDN Signal
Output Macrocell
M
Note: Example: t
= Time from Address Valid to ALE Invalid.
AVLX
Table 43. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
C
Load Capacitance
30
pF
L
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
77/110
PSD813F1V
Table 44. Capacitance
Symbol
2
Parameter
Test Condition
Max.
Unit
pF
Typ.
C
V
= 0V
= 0V
Input Capacitance (for input pins)
4
6
IN
IN
Output Capacitance (for input/
output pins)
pF
C
V
OUT
8
12
25
OUT
C
Capacitance (for CNTL2/V
)
PP
V = 0V
PP
pF
18
VPP
Note: 1. Sampled only, not 100ꢀ tested.
2. Typical values are for T = 25°C and nominal supply voltages.
A
Figure 38. AC Measurement I/O Waveform
Figure 39. AC Measurement Load Circuit
2.01 V
3.0V
195 Ω
Test Point
1.5V
Device
Under Test
0V
CL = 30 pF
(Including Scope and
AI03103b
Jig Capacitance)
AI03104b
Figure 40. Switching Waveforms – Key
INPUTS
OUTPUTS
WAVEFORMS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
AI03102
Table 45. DC Characteristics (5V devices)
Test Condition (in addition
to those in Table 39)
Symbol
Parameter
Min.
Typ.
Max.
+0.5
Unit
V
4.5V < V < 5.5V
V
Input High Voltage
Input Low Voltage
2
V
V
IH
IL
CC
CC
V
4.5V < V < 5.5V
–0.5
0.8
CC
78/110
PSD813F1V
Test Condition (in addition
to those in Table 39)
Symbol
Parameter
Min.
0.8V
Typ.
Max.
+0.5
Unit
1
V
V
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
V
V
V
IH1
IL1
CC
CC
(Note )
1
V
V
0.2V –0.1
–0.5
0.3
CC
(Note )
HYS
V
(min) for Flash Erase and
CC
V
2.5
4.2
V
LKO
Program
I
= 20µA, V = 4.5V
0.01
0.25
4.49
3.9
0.1
V
V
V
V
OL
CC
V
Output Low Voltage
OL
I
= 8mA, V = 4.5V
0.45
OL
CC
I
= –20µA, V = 4.5V
4.4
2.4
OH
CC
V
I
Output High Voltage
OH
I
= –2mA, V = 4.5V
OH
CC
Stand-by Supply Current
for Power-down Mode
2,3
50
200
µA
SB
CSI >V –0.3V (Notes
)
CC
I
I
V
< V < V
SS IN CC
Input Leakage Current
Output Leakage Current
–1
0.1
5
1
µA
µA
LI
0.45 < V
< V
CC
–10
10
LO
OUT
ZPLD_TURBO = Off,
0
mA
5
f = 0MHz (Note )
ZPLD Only
ZPLD_TURBO = On,
f = 0MHz
400
700
30
µA/PT
Operating
Supply
Current
I
(DC)
CC
During Flash memory or
EEPROM WRITE/Erase
Only
5
(Note )
15
mA
Flash memory
or EEPROM
Read only, f = 0MHz
f = 0MHz
0
0
0
0
mA
mA
SRAM
See Figure
ZPLD AC Adder
4
36, note
I
(AC)
CC
Flash memory or EEPROM AC
Adder
mA/
MHz
2.5
1.5
3.5
3.0
5
(Note )
mA/
MHz
SRAM AC Adder
Note: 1. Reset (RESET) has hysteresis. V is valid at or below 0.2V –0.1. V
is valid at or above 0.8V
.
CC
IL1
CC
IH1
2. CSI deselected or internal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 36., page 73 for the PLD current calculation.
5. I
= 0mA
OUT
Table 46. DC Characteristics (3V devices)
Symbol
Parameter
Conditions
Min.
0.7V
Typ.
Max.
Unit
V
V
3.0V < V < 3.6V
V
V
+0.5
High Level Input Voltage
Low Level Input Voltage
Reset High Level Input Voltage
IH
CC
CC
CC
V
V
V
3.0V < V < 3.6V
–0.5
0.8V
0.8
V
IL
CC
1
+0.5
V
IH1
CC
CC
(Note )
1
0.2V –0.1
Reset Low Level Input Voltage
–0.5
V
IL1
CC
(Note )
79/110
PSD813F1V
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
V
Reset Pin Hysteresis
0.3
V
HYS
V
(min) for Flash Erase and
CC
1.5
2.2
V
LKO
Program
I
= 20µA, V = 3.0V
0.01
0.15
2.99
2.8
0.1
V
V
V
V
OL
CC
V
Output Low Voltage
OL
I
= 4mA, V = 3.0V
0.45
OL
CC
I
= –20µA, V = 3.0V
2.9
2.7
OH
CC
V
I
Output High Voltage
OH
I
= –1mA, V = 3.0V
OH
CC
Stand-by Supply Current
for Power-down Mode
2
25
100
µA
SB
CSI >V –0.3V (Notes )
CC
I
I
V
< V < V
SS IN CC
Input Leakage Current
Output Leakage Current
–1
0.1
5
1
µA
µA
LI
0.45 < V < V
CC
–10
10
LO
IN
ZPLD_TURBO = Off,
0
µA/PT
µA/PT
3
f = 0MHz (Note )
ZPLD Only
ZPLD_TURBO = On,
f = 0MHz
200
400
25
Operating
Supply
Current
I
(DC)
CC
During Flash memory or
EEPROM WRITE/Erase
Only
3
(Note )
10
mA
Flash memory
or EEPROM
Read only, f = 0MHz
f = 0MHz
0
0
0
0
mA
mA
SRAM
ZPLD AC Adder
See Figure 37., page 73
Flash memory or EEPROM AC
Adder
mA/
MHz
I
(AC)
CC
1.5
0.8
2.0
1.5
3
(Note )
mA/
MHz
SRAM AC Adder
Note: 1. Reset (RESET) has hysteresis. V is valid at or below 0.2V –0.1. V
is valid at or above 0.8V
.
CC
IL1
CC
IH1
2. CSI deselected or internal PD is active.
3. I
= 0mA
OUT
Figure 41. Input to Output Disable / Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
80/110
PSD813F1V
Figure 42. Combinatorial Timing PLD
CPLD INPUT
t
PD
CPLD
OUTPUT
ai09228
Table 47. CPLD Combinatorial Timing (5V devices)
-90
-12
-15
Fast
PT
Aloc
Turbo Slew
Symbol
Parameter
Conditions
Unit
2
1
Off
rate
Min Max Min Max Min Max
CPLD Input Pin/
Feedback to CPLD
Combinatorial Output
t
25
30
32
+ 2
+ 10
– 2
ns
PD
CPLD Input to CPLD
Output Enable
t
t
t
t
t
26
26
26
30
30
30
32
32
33
+ 10
+ 10
+ 10
+ 10
– 2
– 2
– 2
ns
ns
ns
ns
ns
EA
CPLD Input to CPLD
Output Disable
ER
CPLD Register Clear
or Preset Delay
ARP
ARPW
ARD
CPLD Register Clear
or Preset Pulse Width
20
24
29
Any
macrocell
CPLD Array Delay
16
18
22
+ 2
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. ZPSD versions only.
81/110
PSD813F1V
Table 48. CPLD Combinatorial Timing (3V devices)
-15
-20
Turbo Slew
PT
Aloc
Symbol
Parameter
Conditions
Unit
2
1
Off
rate
Min Max Min Max
CPLD Input Pin/Feedback
to CPLD Combinatorial
Output
t
48
55
+ 4
+ 20
– 6
ns
PD
CPLD Input to CPLD Output
Enable
t
t
t
t
t
43
43
48
50
50
55
+ 20
+ 20
+ 20
+ 20
– 6
– 6
– 6
ns
ns
ns
ns
ns
EA
CPLD Input to CPLD Output
Disable
ER
CPLD Register Clear or
Preset Delay
ARP
ARPW
ARD
CPLD Register Clear or
Preset Pulse Width
30
35
Any
macrocell
CPLD Array Delay
29
33
+ 4
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. ZPSD versions only.
Figure 43. Synchronous Clock Mode Timing – PLD
t
t
CL
CH
CLKIN
INPUT
t
t
H
S
t
CO
REGISTERED
OUTPUT
AI02860
82/110
PSD813F1V
Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)
-90
-12
-15
Fast
PT
Aloc
Slew
rate
Turbo
Off
Symbol
Parameter
Conditions
Unit
1
Min Max Min Max Min Max
Maximum
Frequency
External
30.3
0
1/(t +t
)
CO
26.3
23.8
MHz
S
Feedback
Maximum
Frequency
Internal
f
43.4
8
MAX
1/(t +t –10)
35.7
31.25
33.3
MHz
MHz
S
CO
Feedback
(f
)
CNT
Maximum
Frequency
Pipelined Data
50.0
0
1/(t +t
)
41.67
CH CL
Input Setup
Time
t
t
t
t
t
15
0
18
0
20
0
+ 2
+ 10
ns
ns
ns
ns
ns
S
Input Hold Time
H
Clock High
Time
Clock Input
Clock Input
Clock Input
10
10
12
12
15
15
CH
CL
CO
Clock Low Time
Clock to Output
Delay
18
16
20
18
22
22
– 2
CPLD Array
Delay
t
Any macrocell
+ 2
ns
ns
ARD
MIN
Minimum Clock
t
t
+t
CH CL
20
24
30
2
Period
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) t = t + t
.
CL
CLCL
CH
83/110
PSD813F1V
Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices)
-15
-20
Slew
rate
PT
Aloc
Turbo
Off
Symbol
Parameter
Conditions
Unit
1
Min Max Min Max
Maximum Frequency
External Feedback
1/(t +t
)
17.8
19.6
33.3
14.7
17.2
31.2
MHz
MHz
MHz
S
CO
Maximum Frequency
f
1/(t +t –10)
S CO
MAX
Internal Feedback (f
)
CNT
Maximum Frequency
Pipelined Data
1/(t +t
)
CH CL
t
t
t
t
t
t
t
Input Setup Time
Input Hold Time
27
0
35
0
+ 4
+ 20
ns
ns
ns
ns
ns
ns
ns
S
H
Clock High Time
Clock Low Time
Clock Input
Clock Input
Clock Input
Any macrocell
15
15
16
16
CH
CL
CO
ARD
MIN
Clock to Output Delay
CPLD Array Delay
35
29
39
33
– 6
+ 4
2
t +t
CH CL
29
32
Minimum Clock Period
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0.
2. CLKIN (PD1) t = t + t
.
CL
CLCL
CH
Figure 44. Asynchronous Reset / Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 45. Asynchronous Clock Mode Timing (Product Term Clock)
tCHA
tCLA
CLOCK
INPUT
tSA
tHA
tCOA
REGISTERED
OUTPUT
AI02859
84/110
PSD813F1V
Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)
-90
-12
-15
Turbo
Off
PT
Aloc
Slew
Rate
Symbol
Parameter
Conditions
Unit
1
Min Max Min Max Min Max
Maximum
Frequency
External
26.3
2
1/(t +t
)
23.25
30.30
35.71
20.4
25.64
33.3
MHz
SA COA
Feedback
Maximum
Frequency
Internal
35.7
1
f
1/(t +t
–10)
MHz
MHz
MAXA
SA COA
Feedback
(f
)
CNTA
Maximum
Frequency
Pipelined
Data
41.6
7
1/(t
+t
)
CHA CLA
Input Setup
Time
t
t
t
t
t
t
t
8
10
14
14
14
12
14
15
15
+ 2
+ 10
ns
ns
ns
ns
ns
ns
ns
SA
Input Hold
Time
12
12
12
HA
Clock Input
High Time
+ 10
+ 10
+ 10
CHA
CLA
COA
ARDA
MINA
Clock Input
Low Time
Clock to
Output Delay
30
16
33
18
37
22
– 2
CPLD Array
Delay
Any macrocell
+ 2
Minimum
Clock Period
1/f
28
33
39
CNTA
Note: 1. ZPSD versions only.
85/110
PSD813F1V
Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices)
-15
-20
Turbo
Off
PT
Aloc
Slew
Rate
Symbol
Parameter
Conditions
Unit
1
Min
Max
Min
Max
Maximum Frequency
External Feedback
1/(t +t
)
19.2
16.9
MHz
SA COA
Maximum Frequency
Internal Feedback
f
1/(t +t
–10)
23.8
27
20.4
24.4
MHz
MHz
MAXA
SA COA
(f
)
CNTA
Maximum Frequency
Pipelined Data
1/(t
+t
)
CHA CLA
t
t
t
t
t
t
t
Input Setup Time
Input Hold Time
12
15
22
15
13
17
25
16
+ 4
+ 20
ns
ns
ns
ns
ns
ns
ns
SA
HA
Clock High Time
+ 20
+ 20
+ 20
CHA
CLA
COA
ARD
MINA
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
40
29
46
33
– 6
Any macrocell
+ 4
1/f
CNTA
42
49
Note: 1. ZPSD Versions only.
86/110
PSD813F1V
Figure 46. Input Macrocell Timing (product term clock)
t
t
INL
INH
PT CLOCK
INPUT
t
t
IH
IS
OUTPUT
t
INO
AI03101
Table 53. Input Macrocell Timing (5V devices)
-90
-12
-15
Turbo
Off
PT
Aloc
Symbol
Parameter
Conditions
Unit
2
Min Max Min Max Min Max
1
t
Input Setup Time
Input Hold Time
0
0
0
ns
IS
(Note )
1
t
t
t
20
12
12
22
15
15
26
18
18
+ 10
ns
ns
ns
IH
(Note )
1
NIB Input High Time
NIB Input Low Time
INH
INL
(Note )
1
(Note )
NIB Input to Combinatorial
Delay
1
t
46
50
59
+ 2
+ 10
ns
INO
(Note )
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t
2. ZPSD versions only.
and t
.
LXAX
AVLX
Table 54. Input Macrocell Timing (3V Devices)
-15
-20
Turbo
Off
PT
Aloc
Symbol
Parameter
Input Setup Time
Conditions
Unit
2
Min
0
Max
Min
0
Max
1
t
IS
ns
ns
ns
ns
ns
(Note )
1
t
t
t
t
Input Hold Time
25
13
13
30
15
15
+ 20
IH
(Note )
1
NIB Input High Time
NIB Input Low Time
INH
INL
INO
(Note )
1
(Note )
1
NIB Input to Combinatorial Delay
62
70
+ 4
+ 20
(Note )
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t
2. ZPSD Versions only.
and t
.
LXAX
AVLX
87/110
PSD813F1V
Figure 47. READ Timing
1
t
t
LXAX
AVLX
ALE/AS
t
LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
t
AVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
t
SLQV
CSI
t
t
RLQV
t
RHQX
RLRH
RD
tRHQZ
(PSEN, DS)
t
EHEL
E
t
t
THEH
ELTL
R/W
t
AVPV
ADDRESS OUT
AI02895
Note: 1. t
and t
are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
AVLX
LXAX
88/110
PSD813F1V
Table 55. READ Timing (5V devices)
-90
-12
-15
Turbo
Unit
Off
Symbol
Parameter
Conditions
Min Max Min Max Min Max
t
ALE or AS Pulse Width
Address Setup Time
20
6
22
8
28
10
11
ns
ns
ns
LVLX
AVLX
LXAX
AVQV
SLQV
3
t
t
t
t
(Note )
3
Address Hold Time
8
9
(Note )
3,6
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid 8-Bit Bus
90
100
32
120
135
35
150 + 10
ns
ns
ns
(Notes
)
150
40
5
(Note )
t
RLQV
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
2
38
42
45
38
ns
(Note )
1
t
t
RD Data Hold Time
RD Pulse Width
0
0
0
ns
ns
RHQX
(Note )
1
32
35
38
RLRH
(Note )
1
t
t
t
t
RD to Data High-Z
25
35
ns
ns
ns
ns
RHQZ
EHEL
THEH
ELTL
(Note )
E Pulse Width
32
10
0
36
13
0
38
18
0
R/W Setup Time to Enable
R/W Hold Time After Enable
Address Input Valid to
Address Output Delay
4
t
25
28
32
ns
AVPV
(Note )
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
6. In Turbo Off mode, add 10ns to t
.
AVQV
89/110
PSD813F1V
Table 56. READ Timing (3V devices)
-15
-20
Turbo
Off
Symbol
Parameter
ALE or AS Pulse Width
Conditions
Unit
Min
26
Max
Min
30
Max
t
ns
ns
ns
ns
ns
ns
LVLX
AVLX
LXAX
AVQV
SLQV
3
t
t
t
t
Address Setup Time
10
12
(Note )
3
Address Hold Time
12
14
(Note )
3,6
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid 8-Bit Bus
150
150
35
200
200
40
+ 20
(Note
)
5
(Note )
t
RLQV
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251
2
50
55
ns
(Note )
1
t
t
RD Data Hold Time
0
0
ns
ns
ns
ns
RHQX
(Note )
RD Pulse Width (also DS, LDS, UDS)
RD or PSEN Pulse Width (8031, 80251)
RD to Data High-Z
40
55
45
60
RLRH
1
t
t
t
t
40
45
RHQZ
EHEL
THEH
ELTL
(Note )
E Pulse Width
45
18
0
52
20
0
ns
ns
ns
R/W Setup Time to Enable
R/W Hold Time After Enable
Address Input Valid to
Address Output Delay
4
t
35
40
ns
AVPV
(Note )
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
6. In Turbo Off mode, add 20ns to t
.
AVQV
90/110
PSD813F1V
Figure 48. WRITE Timing
t
t
LXAX
AVLX
ALE/AS
t
LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
t
AVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
t
SLWL
CSI
t
t
DVWH
WHDX
t
WR
(DS)
WLWH
t
WHAX
t
EHEL
E
t
t
THEH
ELTL
R/ W
t
WLMV
t
t
AVPV
WHPV
STANDARD
MCU I/O OUT
ADDRESS OUT
AI02896
91/110
PSD813F1V
Table 57. WRITE, Erase and Program Timing (5V devices)
-90
-12
-15
Symbol
Parameter
ALE or AS Pulse Width
Conditions
Unit
Min Max Min Max Min Max
t
20
6
22
8
28
10
11
ns
ns
ns
LVLX
AVLX
LXAX
1
t
t
Address Setup Time
Address Hold Time
(Note )
1
8
9
(Note )
Address Valid to Leading
Edge of WR
1,3
t
15
18
20
ns
AVWL
(Notes
)
3
t
t
t
t
t
CS Valid to Leading Edge of WR
WR Data Setup Time
15
35
5
18
40
5
20
45
5
ns
ns
ns
ns
ns
SLWL
(Note )
3
DVWH
WHDX
WLWH
WHAX1
(Note )
3
WR Data Hold Time
(Note )
3
WR Pulse Width
35
8
40
9
45
10
(Note )
3
Trailing Edge of WR to Address Invalid
(Note )
Trailing Edge of WR to DPLD Address
Invalid
3,6
t
0
0
0
ns
ns
WHAX2
WHPV
(Note
)
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
3
t
30
55
35
60
38
65
(Note )
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
3,5
t
ns
DVMV
(Notes
)
Address Input Valid to Address
Output Delay
2
t
t
25
55
28
60
30
65
ns
ns
AVPV
(Note )
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
3,4
WLMV
(Notes
)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. T
is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
WHAX2
92/110
PSD813F1V
Table 58. WRITE Timing (3V devices)
-15
-20
Symbol
Parameter
ALE or AS Pulse Width
Conditions
Unit
Min
26
Max
Min
30
Max
t
LVLX
AVLX
LXAX
1
t
t
Address Setup Time
Address Hold Time
10
12
ns
ns
(Note )
1
12
20
14
25
(Note )
Address Valid to Leading
Edge of WR
1,3
t
ns
AVWL
(Notes
)
3
t
t
t
t
t
t
CS Valid to Leading Edge of WR
WR Data Setup Time
20
45
8
25
50
10
53
17
0
ns
ns
ns
ns
ns
ns
SLWL
(Note )
3
DVWH
WHDX
WLWH
WHAX1
WHAX2
(Note )
3
WR Data Hold Time
(Note )
3
WR Pulse Width
48
12
0
(Note )
3
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address Invalid
(Note )
3,6
(Note
)
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
3
t
t
t
t
45
90
48
90
50
100
55
ns
ns
ns
ns
WHPV
DVMV
AVPV
WLMV
(Note )
Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear
3,5
(Notes
)
Address Input Valid to Address
Output Delay
2
(Note )
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
3,4
100
(Notes
)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Table 59. Flash Program, WRITE and Erase Times (5V devices)
Symbol
Parameter
Min.
Typ.
8.5
3
Max.
30
Unit
Flash Program
s
1
s
Flash Bulk Erase (pre-programmed)
Flash Bulk Erase (not pre-programmed)
Sector Erase (pre-programmed)
Sector Erase (not pre-programmed)
Byte Program
10
1
s
s
t
t
t
30
WHQV3
2.2
14
s
WHQV2
WHQV1
1200
µs
Program / Erase Cycles (per Sector)
Sector Erase Time-Out
100,000
cycles
µs
t
t
100
WHWLO
2
30
ns
Q7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid t
time units before the data byte, DQ0-DQ7, is valid for reading.
Q7VQV
93/110
PSD813F1V
Table 60. Flash Program, WRITE and Erase Times (3V devices)
Symbol
Parameter
Min.
Typ.
8.5
3
Max.
30
Unit
Flash Program
s
1
s
Flash Bulk Erase (pre-programmed)
Flash Bulk Erase (not pre-programmed)
Sector Erase (pre-programmed)
Sector Erase (not pre-programmed)
Byte Program
10
1
s
s
t
t
t
30
WHQV3
2.2
14
s
WHQV2
WHQV1
1200
µs
Program / Erase Cycles (per Sector)
Sector Erase Time-Out
100,000
cycles
µs
t
t
100
WHWLO
2
30
ns
Q7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid t
time units before the data byte, DQ0-DQ7, is valid for reading.
Q7VQV
Table 61. EEPROM WRITE Times (5V devices)
Symbol
Parameter
Min
Typ
Max
Unit
ms
t
Write Protect After Power Up
5
EEHWL
1
t
0.2
120
10
µs
BLC
EEPROM Byte Load Cycle Timing (Note )
EEPROM Byte Write Cycle Time
t
4
6
ms
WCB
2
t
30
ms
WCP
EEPROM Page Write Cycle Time (Note )
Program/Erase Cycles (Per Sector)
10,000
cycles
Note: 1. If the maximum time has elapsed between successive WRITE cycles to an EEPROM page, the transfer of this data to EEPROM
cells will begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type.
2. These specifications are for writing a page to EEPROM cells.
Table 62. EEPROM WRITE Times (3V devices)
Symbol
Parameter
Min
Typ
Max
Unit
ms
t
Write Protect After Power Up
5
EEHWL
1
t
0.2
120
10
µs
BLC
EEPROM Byte Load Cycle Timing (Note )
EEPROM Byte Write Cycle Time
t
4
6
ms
WCB
2
t
30
ms
WCP
EEPROM Page Write Cycle Time (Note )
Program/Erase Cycles (Per Sector)
10,000
cycles
Note: 1. If the maximum time has elapsed between successive WRITE cycles to an EEPROM page, the transfer of this data to EEPROM
cells will begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type.
2. These specifications are for writing a page to EEPROM cells.
94/110
PSD813F1V
Figure 49. Peripheral I/O Read Timing
ALE/AS
ADDRESS
DATA VALID
A/D BUS
t
(PA)
(PA)
AVQV
t
SLQV
CSI
RD
t
t
(PA)
(PA)
RLQV
t
t
(PA)
(PA)
QXRH
RHQZ
RLRH
t
(PA)
DVQV
DATA ON PORT A
AI02897
Table 63. Port A Peripheral Data Mode READ Timing (5V devices)
-90
-12
-15
Turbo
Off
Symbol
Parameter
Conditions
Unit
Min Max Min Max Min Max
3
t
t
Address Valid to Data Valid
CSI Valid to Data Valid
RD to Data Valid
40
35
32
38
30
45
40
35
42
35
45
45
40
45
38
+ 10
+ 10
ns
ns
ns
ns
ns
ns
ns
AVQV–PA
(Note )
SLQV–PA
1,4
(Notes
)
t
RLQV–PA
RD to Data Valid 8031 Mode
Data In to Data Out Valid
RD Data Hold Time
t
t
t
DVQV–PA
QXRH–PA
RLRH–PA
0
0
0
1
RD Pulse Width
32
35
38
(Note )
1
t
RD to Data High-Z
25
28
30
ns
RHQZ–PA
(Note )
Table 64. Port A Peripheral Data Mode READ Timing (3V devices)
-15
-20
Turbo
Off
Symbol
Parameter
Conditions
Unit
Min
Max
55
Min
Max
3
t
t
Address Valid to Data Valid
CSI Valid to Data Valid
RD to Data Valid
60
50
45
50
65
+ 20
+ 20
ns
ns
ns
ns
ns
ns
ns
AVQV–PA
(Note )
45
SLQV–PA
1,4
40
(Notes
)
t
RLQV–PA
RD to Data Valid 8031 Mode
Data In to Data Out Valid
RD Data Hold Time
45
t
t
t
60
DVQV–PA
QXRH–PA
RLRH–PA
0
0
1
RD Pulse Width
36
46
(Note )
1
t
RD to Data High-Z
40
45
ns
RHQZ–PA
(Note )
95/110
PSD813F1V
Figure 50. Peripheral I/O WRITE Timing
ALE/AS
ADDRESS
DATA OUT
A/D BUS
tWHQZ (PA)
tWLQV (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI02898
Table 65. Port A Peripheral Data Mode WRITE Timing (5V devices)
-90
-12
-15
Symbol
Parameter
Conditions
Unit
Min Max Min Max Min Max
2
t
t
t
WR to Data Propagation Delay
Data to Port A Data Propagation Delay
WR Invalid to Port A Tri-state
35
30
25
38
35
30
40
38
33
ns
ns
ns
WLQV–PA
DVQV–PA
WHQZ–PA
(Note )
5
(Note )
2
(Note )
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Table 66. Port A Peripheral Data Mode WRITE Timing (3V devices)
-15
-20
Symbol
Parameter
Conditions
Unit
Min
Max
45
Min
Max
55
2
t
t
t
WR to Data Propagation Delay
Data to Port A Data Propagation Delay
WR Invalid to Port A Tri-state
ns
ns
ns
WLQV–PA
DVQV–PA
WHQZ–PA
(Note )
5
40
45
(Note )
2
33
35
(Note )
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
96/110
PSD813F1V
Figure 51. Reset (RESET) Timing
VCC(min)
V
CC
t
NLNH
t
t
OPR
t
t
NLNH-PO
NLNH-A
OPR
Power-On Reset
Warm Reset
RESET
AI02866b
Table 67. Reset (RESET) Timing (5V devices)
Symbol
Parameter
Conditions
Min
150
1
Max
Unit
ns
1
t
t
t
NLNH
RESET Active Low Time
Power On Reset Active Low Time
RESET High to Operational Device
ms
ns
NLNH–PO
OPR
120
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 68. Reset (RESET) Timing (3V devices)
Symbol
Parameter
Conditions
Min
300
1
Max
Unit
ns
1
t
t
t
NLNH
RESET Active Low Time
2
ms
ns
NLNH–PO
OPR
Power On Reset Active Low Time
RESET High to Operational Device
300
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. t is 10ms for devices manufactured before the rev.A.
NLNH-PO
97/110
PSD813F1V
Figure 52. ISC Timing
tISCCH
TCK
tISCCL
tISCPSU
tISCPH
TDI/TMS
t ISCPZV
tISCPCO
ISC OUTPUTS/TDO
tISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 69. ISC Timing (5V devices)
-90
-12
-15
Symbol
Parameter
Conditions
Unit
Min Max Min Max Min Max
Clock (TCK, PC1) Frequency (except for
PLD)
1
t
18
16
14 MHz
ISCCF
ISCCH
ISCCL
(Note )
Clock (TCK, PC1) High Time (except for
PLD)
1
t
t
26
26
29
29
31
31
ns
ns
(Note )
Clock (TCK, PC1) Low Time (except for
PLD)
1
(Note )
2
t
t
Clock (TCK, PC1) Frequency (PLD only)
Clock (TCK, PC1) High Time (PLD only)
2
2
2
MHz
ns
ISCCFP
(Note )
2
240
240
240
ISCCHP
(Note )
2
t
t
t
t
t
Clock (TCK, PC1) Low Time (PLD only)
ISC Port Set Up Time
240
8
240
10
5
240
10
5
ns
ns
ns
ns
ns
ISCCLP
ISCPSU
ISCPH
(Note )
ISC Port Hold Up Time
5
ISC Port Clock to Output
23
23
24
24
25
25
ISCPCO
ISCPZV
ISC Port High-Impedance to Valid Output
ISC Port Valid Output to
High-Impedance
t
23
24
25
ns
ISCPVZ
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
98/110
PSD813F1V
Table 70. ISC Timing (3V devices)
-15
-20
Symbol
Parameter
Conditions
Unit
Min
Max
Min
Max
1
t
Clock (TCK, PC1) Frequency (except for PLD)
Clock (TCK, PC1) High Time (except for PLD)
Clock (TCK, PC1) Low Time (except for PLD)
Clock (TCK, PC1) Frequency (PLD only)
Clock (TCK, PC1) High Time (PLD only)
10
9
MHz
ns
ISCCF
(Note )
1
t
t
t
t
45
45
51
51
ISCCH
(Note )
1
ns
ISCCL
(Note )
2
2
2
MHz
ns
ISCCFP
ISCCHP
(Note )
2
240
240
(Note )
2
t
t
t
t
t
Clock (TCK, PC1) Low Time (PLD only)
ISC Port Set Up Time
240
13
240
15
ns
ns
ns
ns
ns
ISCCLP
ISCPSU
ISCPH
(Note )
ISC Port Hold Up Time
10
10
ISC Port Clock to Output
36
36
40
40
ISCPCO
ISCPZV
ISC Port High-Impedance to Valid Output
ISC Port Valid Output to
High-Impedance
t
36
40
ns
ISCPVZ
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Table 71. Power-down Timing (5V devices)
-90
-12
-15
Symbol
Parameter
Conditions
Unit
Min Max Min Max Min Max
t
ALE Access Time from Power-down
90
120
150
ns
LVDV
Maximum Delay from
APD Enable to Internal PDN Valid
Signal
Using CLKIN
(PD1)
1
t
µs
15 * t
CLWH
CLCL
Note: 1. t
is the period of CLKIN (PD1).
CLCL
Table 72. Power-down Timing (3V devices)
-15
-20
Symbol
Parameter
Conditions
Unit
Min
Max
150
Min
Max
200
t
ALE Access Time from Power-down
ns
µs
LVDV
Maximum Delay from APD Enable to
Internal PDN Valid Signal
Using CLKIN
(PD1)
1
t
CLWH
15 * t
CLCL
Note: 1. t
is the period of CLKIN (PD1).
CLCL
99/110
PSD813F1V
PACKAGE MECHANICAL
In order to meet environmental requirements, ST
box label, in compliance with JEDEC Standard
JESD97.
®
offers these devices in ECOPACK packages.
These packages have a Lead-free second level in-
terconnect . The category of second level intercon-
nect is marked on the package and on the inner
The maximum ratings related to soldering condi-
tions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 53. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing
D
D1
D2
A2
e
b
Ne
E2 E1 E
N
1
Nd
A
CP
L1
c
A1
α
L
QFP-A
Note: Drawing is not to scale.
100/110
PSD813F1V
Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions
mm
inches
Symb.
Typ.
Min.
Max.
2.35
0.25
2.10
0.38
0.23
13.25
10.05
–
Typ.
Min.
Max.
0.093
0.010
0.083
0.015
0.009
0.522
0.396
–
A
A1
A2
b
2.00
1.80
0.22
0.11
13.15
9.95
–
0.079
0.077
0.009
0.004
0.518
0.392
–
c
D
13.20
10.00
7.80
0.520
0.394
0.307
0.520
0.394
0.307
0.026
0.035
0.063
D1
D2
E
13.20
10.00
7.80
13.15
9.95
–
13.25
10.05
–
0.518
0.392
–
0.522
0.396
–
E1
E2
e
0.65
–
–
L
0.88
0.73
–
1.03
–
0.029
0.041
7°
L1
α
1.60
0°
7°
0°
52
13
13
N
52
Nd
Ne
CP
13
13
0.10
0.004
101/110
PSD813F1V
Figure 54. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing
D
A1
D1
A2
M1
M
1 N
b1
e
E1 E
D2/E2 D3/E3
b
L1
L
C
A
CP
PLCC-B
Note: Drawing is not to scale.
Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions
mm
Min.
4.19
2.54
–
inches
Min.
0.165
0.100
–
Symbol
Typ.
Max.
4.57
2.79
0.91
0.53
0.81
0.261
20.19
19.15
18.54
20.19
19.15
18.54
–
Typ.
Max.
0.180
0.110
0.036
0.021
0.032
0.0103
0.795
0.754
0.730
0.795
0.754
0.730
–
A
A1
A2
B
0.33
0.66
0.246
19.94
19.05
17.53
19.94
19.05
17.53
–
0.013
0.026
0.0097
0.785
0.750
0.690
0.785
0.750
0.690
–
B1
C
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
R
–
–
–
–
N
52
52
Nd
Ne
13
13
13
13
102/110
PSD813F1V
Figure 55. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline
D
D1
D2
A2
e
b
Ne
E2 E1 E
N
1
Nd
A
CP
L1
c
A1
α
L
QFP-A
Note: Drawing is not to scale.
103/110
PSD813F1V
Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
1.42
0.07
1.36
0.0°
0.33
Max.
1.54
Typ.
Max.
0.061
0.005
0.057
7.0°
A
A1
A2
α
0.056
0.003
0.054
0.0°
0.10
1.40
3.5°
0.35
0.14
0.004
0.055
3.5°
1.44
7.0°
b
0.38
0.014
0.013
0.015
0.006
0.634
0.552
0.474
0.634
0.552
0.474
0.033
0.030
0.042
c
0.17
D
16.00
14.00
12.00
16.00
14.00
12.00
0.80
15.90
13.98
11.95
15.90
13.98
11.95
0.75
16.10
14.03
12.05
16.10
14.03
12.05
0.85
0.630
0.551
0.472
0.630
0.551
0.472
0.031
0.024
0.039
0.004
0.626
0.550
0.470
0.626
0.550
0.470
0.030
0.018
0.037
D1
D2
E
E1
E2
e
L
0.60
0.45
0.75
L1
CP
N
1.00
0.94
1.06
0.10
64
16
16
64
16
16
Nd
Ne
104/110
PSD813F1V
PART NUMBERING
Table 76. Ordering Information Scheme
Example:
PSD8
1
3
F
1
V
12
J
1
T
Device Type
PSD8 = 8-bit PSD with Register Logic
SRAM Capacity
1 = 16 Kbit
Flash Memory Capacity
3 = 1 Mbit (128Kb x 8)
2nd Flash Memory
1 = 256 Kbit EEPROM
Operating Voltage
V = V = 3.0 to 3.6V
CC
Speed
70 = 70ns
90 = 90ns
12 = 120ns
Package
J = ECOPACK PLCC52
M = ECOPACK PQFP52
U = ECOPACK TQFP64
Temperature Range
blank = 0 to 70°C (commercial)
1= –40 to 85°C (industrial)
Option
T = Tape & Reel Packing
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
105/110
PSD813F1V
APPENDIX A. PQFP52 PIN ASSIGNMENTS
Table 77. PQFP52 Connections (Figure 2)
Pin Number
Pin Assignments
Pin Number
Pin Assignments
1
PD2
PD1
PD0
PC7
PC6
PC5
PC4
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
AD4
AD5
AD6
AD7
2
3
4
5
V
CC
6
AD8
AD9
7
V
8
AD10
AD11
AD12
AD13
AD14
AD15
CNTL0
RESET
CNTL2
CNTL1
PB7
CC
9
GND
PC3
PC2
PC1
PC0
PA7
PA6
PA5
PA4
PA3
GND
PA2
PA1
PA0
AD0
AD1
AD2
AD3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PB6
GND
PB5
PB4
PB3
PB2
PB1
PB0
106/110
PSD813F1V
APPENDIX B. PLCC52 PIN ASSIGNMENTS
Table 78. PLCC52 Connections
Pin Number
Pin Assignments
Pin Number
Pin Assignments
1
GND
PB5
PB4
PB3
PB2
PB1
PB0
PD2
PD1
PD0
PC7
PC6
PC5
PC4
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PA2
PA1
PA0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V
CC
AD8
AD9
V
AD10
AD11
AD12
AD13
AD14
AD15
CNTL0
RESET
CNTL2
CNTL1
PB7
CC
GND
PC3
PC2
PC1
PC0
PA7
PA6
PA5
PA4
PA3
GND
PB6
107/110
PSD813F1V
APPENDIX C. TQFP64 PIN ASSIGNMENTS
Table 79. TQFP64 Connections (Figure 4)
Pin Number
Pin Assignments
Pin Number
33
Pin Assignments
1
PD2
PD1
PD0
PC7
PC6
PC5
AD3
AD4
AD5
AD6
AD7
2
34
3
35
4
36
5
37
6
V
38
CC
V
7
V
39
CC
CC
V
8
40
AD8
AD9
CC
V
41
9
CC
42
AD10
AD11
AD12
AD13
AD14
AD15
CNTL0
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
GND
PC3
PC2
PC1
PC0
NC
43
44
45
46
47
48
NC
49
NC
50
RESET
CNTL2
CNTL1
PB7
PA7
PA6
PA5
PA4
PA3
GND
GND
PA2
PA1
PA0
AD0
AD1
N/D
AD2
51
52
53
54
PB6
55
GND
GND
PB5
56
57
58
PB4
59
PB3
60
PB2
61
PB1
62
PB0
63
NC
64
NC
108/110
PSD813F1V
REVISION HISTORY
Table 80. Document Revision History
Date
Rev.
Description of Revision
August-2000
1.0 Document written in WSI format.
Front page, and back two pages, in ST format, added to the PDF file. References to
1.1 Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST, Flash+PSD and PSDsoft
Express.
04-Jan-03
06-Dec-03
3-Jun-04
2.0 Document converted to ST format. Package references corrected (Figure 1).
Document reformatted for DMS; Ordering Information corrected (Table 76); added TQFP64
3.0
package (Figure 1, 55; Table 75)
Added ECOPACK text in cover page and in section PACKAGE MECHANICAL, page 100.
Updated datasheet status to “not for new design”.
Backup battery feature removed: updated features summary, Table 1 (pins PC2 and PC4
configurations ), PSD ARCHITECTURAL OVERVIEW, Memory section, SRAM section, Port C
– Functionality and Structure section. Removed SRAM standby mode in POWER
03-Oct-2008
4
MANAGEMENT. Updated PC2 in Table 78. PLCC52 Connections. Removed V
, I
,
STBY STBY
V
, V
, V , and I
from Table 45 and Table 46. Removed V timings tables.
STBYON OH1
DF
IDLE
STBYON
Updated disclaimer text.
109/110
PSD813F1V
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) rese
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assu
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any par
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party p
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IM
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IM
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGH
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR
SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESU
PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE
SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediate
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoev
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2008 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Ja
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
110/110
相关型号:
©2020 ICPDF网 联系我们和版权申明