PSD813F3-A-90UI [STMICROELECTRONICS]
Parallel I/O Port, 27 I/O, CMOS, PQFP64, PLASTIC, TQFP-64;型号: | PSD813F3-A-90UI |
厂家: | ST |
描述: | Parallel I/O Port, 27 I/O, CMOS, PQFP64, PLASTIC, TQFP-64 |
文件: | 总122页 (文件大小:481K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Revision A Flash PSD
PSD813F2-A PSD813F3-A
PSD813F4-A PSD813F5-A
PSD833F2 PSD834F2
Flash In-System-Programmable
Microcontroller Peripherals
“ZPSD For Free” – All of the power saving features of our
ZPSD family have been integrated into the standard Rev. A PSD813,
PSD833F2, and PSD834F2.
June, 2000
Preliminary Information
47280 Kato Road, Fremont, California 94538
Tel: 510-656-5400 Fax: 510-657-8495
800-TEAM-WSI (800-832-6974)
Web Site: http://www.waferscale.com
E-mail: info@waferscale.com
Return to Main Menu
PSD8XXF2 PSD8XXF3
PSD8XXF4 PSD8XXF5
Flash In-System-Programmable Microcontroller Peripherals
Table of Contents
1.0 Introduction...........................................................................................................................................................1
2.0 Key Features ........................................................................................................................................................2
PSD8XXF Block Diagram...............................................................................................................................4
3.0 General Information..............................................................................................................................................5
4.0 PSD8XXF Family..................................................................................................................................................5
5.0 PSD8XXF Architectural Overview ........................................................................................................................6
5.1 Memory...................................................................................................................................................6
5.2 Page Register.........................................................................................................................................6
5.3 PLDs.......................................................................................................................................................6
5.4 I/O Ports..................................................................................................................................................7
5.5 Microcontroller Bus Interface..................................................................................................................7
5.6 JTAG Port...............................................................................................................................................7
5.7 In-System Programming.........................................................................................................................8
5.8 Power Management................................................................................................................................8
6.0 Development System............................................................................................................................................9
7.0 PSD8XXF Pin Descriptions ................................................................................................................................10
8.0 PSD8XXF Register Description and Address Offset ..........................................................................................14
9.0 PSD8XXF Functional Blocks ..............................................................................................................................15
9.1 Memory Blocks .....................................................................................................................................15
9.1.1 Main Flash and Flash Boot Memory Description........................................................................15
9.1.2 SRAM.........................................................................................................................................27
9.1.3 Memory Select Signals...............................................................................................................27
9.1.4 Page Register.............................................................................................................................30
9.2 PLDs.....................................................................................................................................................31
9.2.1 Decode PLD (DPLD)..................................................................................................................33
9.2.2 Complex PLD (CPLD) ................................................................................................................33
9.3 Microcontroller Bus Interface................................................................................................................42
9.3.1 PSD8XXF Interface to a Multiplexed 8-Bit Bus ..........................................................................42
9.3.2 PSD8XXF Interface to a Non-Multiplexed 8-bit Bus...................................................................42
9.3.3 Data Byte Enable Reference......................................................................................................45
9.3.4 Microcontroller Interface Examples............................................................................................45
9.4 I/O Ports................................................................................................................................................50
9.4.1 General Port Architecture...........................................................................................................50
9.4.2 Port Operating Modes ................................................................................................................52
9.4.3 Port Configuration Registers (PCRs) .........................................................................................55
9.4.4 Port Data Registers....................................................................................................................58
9.4.5 Ports A and B – Functionality and Structure ............................................................................59
9.4.6 Port C – Functionality and Structure ........................................................................................61
9.4.7 Port D – Functionality and Structure ........................................................................................61
9.5 Power Management..............................................................................................................................65
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode .....................................................65
9.5.2 Other Power Saving Options......................................................................................................69
9.5.3 Reset and Power On Requirement ............................................................................................70
i
PSD8XXF2 PSD8XXF3
PSD8XXF4 PSD8XXF5
Flash In-System-Programmable Microcontroller Peripherals
Table of Contents (cont.)
9.6 Programming In-Circuit Using the JTAG Interface ...............................................................................71
9.6.1 Standard JTAG Signals..............................................................................................................72
9.6.2 JTAG Extensions........................................................................................................................73
9.6.3 Security and Flash Memories Protection....................................................................................73
Absolute Maximum Ratings.........................................................................................................................................74
AD/DC Parameters......................................................................................................................................................75
Example of PSD8XXF Typical Power Calculation at V = 5.0 V......................................................................76
CC
Example of PSD8XXF Typical Power Calculation at V = 5.0 V in Turbo Off Mode........................................77
CC
PSD8XXF DC Characteristics (5 V ± 10% Versions)..........................................................................................78
PSD8XXF AD/DC Parameters – CPLD Timing Parameters (5 V ± 10% versions) ..........................................79
PSD8XXF DC Characteristics (3.0 V to 3.6 V Versions) ....................................................................................87
PSD8XXF AD/DC Parameters – CPLD Timing Parameters (3.0 V to 3.6 V Versions) ....................................88
Timing Diagrams .........................................................................................................................................................96
Programming.............................................................................................................................................................103
Pin Assignments........................................................................................................................................................104
Package Information .................................................................................................................................................107
Selector Guide...........................................................................................................................................................112
Part Number Construction.........................................................................................................................................113
Ordering Information..................................................................................................................................................113
Product Revisions......................................................................................................................................................116
Worldwide Sales, Service and Technical Support.....................................................................................................118
For additional information,
Call 800-TEAM-WSI (800-832-6974).
Fax: 510-657-8495
Web Site: http://www.waferscale.com
E-mail: info@waferscale.com
ii
PSD8XXF Family
Preliminary Information
For additional information,
Call 800-TEAM-WSI (800-832-6974).
Fax: 510-657-8495
Web Site: http://www.waferscale.com
E-mail: info@waferscale.com
iii
Programmable Peripheral
PSD813F2-A, PSD813F3-A
PSD813F4-A, PSD813F5-A
PSD833F2, PSD834F2
Flash In-System-Programmable
Microcontroller Peripherals
Preliminary Information
The PSD8XXF family of Programmable Microcontroller (MCU) Peripherals brings
In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a
simple and flexible solution for embedded designs. PSD8XXF devices combine many of
the peripheral functions found in MCU based applications:
1.0
Introduction
• Up to 2 Mbit of Flash memory
• A second Flash Boot memory
• Over 3,000 gates of Flash programmable logic
• Up to 64 Kbit SRAM
• Reconfigurable I/O ports
• Programmable power management.
PSD8XXF devices integrate an optimized “microcontroller macrocell” logic architecture
called the Micro CellTM. The Micro Cell was created to address the unique requirements
of embedded system designs. It allows direct connection between the system address/data
bus and the internal PSD registers to simplify communication between the MCU and other
supporting devices.
1
PSD8XXF Family
Preliminary Information
The PSD8XXF family includes a JTAG serial programming interface to allow in-system-
programming of the entire device. This feature reduces development time, simplifies the
manufacturing flow, and dramatically lowers the cost of field upgrades. Using Waferscale’s
special Fast-JTAG programming, a design can be programmed into the PSD8XXF in as
little as seven seconds.
1.0
Introduction
(Cont.)
The innovative Flash PSD8XXF family solves key problems faced by designers when
managing discrete Flash memory devices, such as:
• First-time programming
• Complex address decoding
• Simultaneous read and write to Flash.
The PSD8XXF’s serial JTAG interface allows in-system-programming and eliminates the
need for a boot EPROM or an external programmer. To simplify Flash updates, the
devices perform program execution out of a Flash Boot block while the main Flash memory
is being updated. This solution avoids the complicated overhead circuitry and
software necessary to implement in-system Flash memory updates.
PSDsoft —Waferscale’s software development tool—now has the ability to generate
ANSI-C compliant code for use with your target MCU. The code generated allows you to
manipulate the non-volatile memory (NVM) within the PSD. Code examples are also
provided for:
• Flash ISP via the UART of the host MCU
• Memory paging to execute code across several PSD memory pages
• Loading, reading, and manipulation of PSD Micro Cells by the MCU
The PSD8XXF is available in 52-pin PLCC and PQFP package, and a 64-pin plastic Thin
Quad Flatpack (TQFP) package.
❏ A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
2.0
Key Features
• Intel 8031, 80196, 80186, 80C251, and 80386EX
• Motorola 68HC11, 68HC16, 68HC12, and 683XX
• Philips 8031 and 8051XA
• Zilog Z80 and Z8
❏ Internal 1 or 2 Mbit Flash memory. This is the main Flash memory. It is divided into
eight equal-sized blocks that can be accessed with user-specified addresses.
❏ Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently.
❏ Optional 16 or 64 Kbit SRAM. The SRAM’s contents can be protected from a
power failure by connecting an external battery.
Please refer to the revision block at the end of this
document for updated information.
2
Preliminary Information
PSD8XXF Family
❏ CPLD with 16 Output Micro Cells (OMCs) and 24 Input Micro Cells (IMCs). The
2.0
Key Features
(cont.)
CPLD may be used to efficiently implement a variety of logic functions for internal
and external control. Examples include state machines, loadable shift registers, and
loadable counters.
❏ Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
❏ 27 individually configurable I/O port pins that can be used for the following functions:
• MCU I/Os
• PLD I/Os
• Latched MCU address output
• Special function I/Os.
• 16 of the I/O ports may be configured as open-drain outputs.
❏ Standby current as low as 50 µA for 5 V devices.
❏ Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the
field.
❏ Internal page register that can be used to expand the microcontroller address space by
a factor of 256.
❏ Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD8XXF into Power Down Mode.
❏ Erase/Write cycles:
• Flash memory – 100,000 minimum
• PLD – 1,000 minimum
• Data Retention: 15 year minimum at 90 degrees Celsius (for Main Flash, Boot, PLD
and Configuration bits)
3
PSD8XXF Family
Preliminary Information
Figure 1. PSD8XXF Block Diagram
4
Preliminary Information
PSD8XXF Family
The PSD8XXF series architecture allows In-System Programming of all Memory, PLD
Logic and Device Configuration. The embedded Input and Output Micro Cells enable
efficient implementation of user defined logic functions that require both software and
hardware interaction. The devices eliminate the need for discrete ‘glue’ logic, and allow the
development of entire systems using only a few highly integrated devices.
3.0
General
Information
There are 5 variants in the PSD8XXF family. All PSD8XXF devices provide these base
features: 1 or 2 Mbit main Flash Memory, JTAG port, CPLD, DPLD, power management,
and 27 I/O pins. The following table summarizes all the devices in the PSD8XXF family.
4.0
PSD8XXF
Family
Table 1. PSD8XXF Product Matrix
Part #
Flash
Flash
No. of
I/O Micro Cells JTAG/ISC
Serial ISP Main Memory Boot Memory
PSD8XXF
Family
Kbit
Kbit
SRAM
Kbit
Turbo
Mode
Supply
Voltage
Device
Pins Input/Output
Port
(8 Sectors)
(4 Sectors)
PSD8XXFX
PSD813F2
PSD813F3
PSD813F4
PSD813F5
PSD833F2
PSD834F2
27
27
27
27
27
27
24/16
24/16
24/16
24/16
24/16
24/16
Yes
Yes
Yes
Yes
Yes
Yes
1024
1024
1024
1024
1024
2048
256
none
256
16
16
Yes
Yes
Yes
Yes
Yes
Yes
5V
5V
5V
5V
5V
5V
none
none
64
none
256
256
64
5
PSD8XXF Family
Preliminary Information
PSD8XXF devices contain several major functional blocks. Figure 1 on page 3 shows the
architecture of the PSD8XXF device family. The functions of each block are described
briefly in the following sections. Many of the blocks perform multiple functions and are user
configurable.
5.0
PSD8XXF
Architectural
Overview
5.1 Memory
The PSD8XXF contains the following memories:
• A 1 or 2 Mbit Flash
• A secondary 256 Kbit Flash boot memory
• An optional 16 or 64 Kbit SRAM.
Each of the memories is briefly discussed in the following paragraphs. A more detailed
discussion can be found in section 9.
The 1 or 2 Mbit Flash is the main memory of the PSD8XXF. It is divided into eight
equally-sized sectors that are individually selectable.
The 256 Kbit Flash Boot memory is divided into four equally-sized sectors. Each sector is
individually selectable.
The optional 16 or 64 Kbit SRAM is intended for use as a scratchpad memory or as an
extension to the microcontroller SRAM. If an external battery is connected to the
PSD8XXF’s Vstby pin, data will be retained in the event of a power failure.
Each block of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
5.2 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access
external memory and peripherals or internal memory and I/O. The Page Register can also
be used to change the address mapping of blocks of Flash memory into different memory
spaces for in-circuit reprogramming.
5.3 PLDs
The device contains two PLD blocks, each optimized for a different function, as shown in
Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes
cost/performance, and eases design entry.
The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the
PSD8XXF internal memory and registers. The CPLD can implement user-defined logic
functions. The DPLD has combinatorial outputs. The CPLD has 16 Output Micro Cells
and 3 combinatorial outputs. The PSD8XXF also has 24 Input Micro Cells that can be
configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations, number of Product Terms, and
Micro Cells.
The PLDs consume minimal power by using Zero-Power design techniques. The speed
and power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register
and other bits in the PMMR2 registers. These registers are set by the microcontroller at
runtime. There is a slight penalty to PLD propagation time when invoking the non-Turbo
bit.
Table 2. PLD I/O Table
Name
Abbreviation
Inputs
Outputs
Product Terms
Decode PLD
Complex PLD
DPLD
CPLD
73
73
17
19
42
140
6
Preliminary Information
PSD8XXF Family
PSD8XXF
Architectural
Overview
(cont.)
5.4 I/O Ports
The PSD8XXF has 27 I/O pins divided among four ports (Port A, B, C, and D). Each
I/O pin can be individually configured for different functions. Ports A, B, C and D can
be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for
microcontrollers using multiplexed address/data busses.
The JTAG pins can be enabled on Port C for In-System Programming (ISP).
Ports A and B can also be configured as a data port for a non-multiplexed bus.
5.5 Microcontroller Bus Interface
The PSD8XXF easily interfaces with most 8-bit microcontrollers that have either
multiplexed or non-multiplexed address/data busses. The device is configured to respond
to the microcontroller’s control signals, which are also used as inputs to the PLDs. Section
9.3.5 contains microcontroller interface examples.
5.6 JTAG Port
In-System Programming can be performed through the JTAG pins on Port C. This serial
interface allows complete programming of the entire PSD8XXF device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on Port C. Table 3 indicates the JTAG signals pin
assignments.
Table 3. JTAG Signals on Port C
Port C Pins
JTAG Signal
PC0
PC1
PC3
PC4
PC5
PC6
TMS
TCK
TSTAT
TERR
TDI
TDO
7
PSD8XXF Family
Preliminary Information
PSD8XXF
Architectural
Overview
(cont.)
5.7 In-System Programming
Using the JTAG signals on Port C, the entire PSD8XXF device can be programmed or
erased without the use of the microcontroller. The main Flash memory can also be
programmed in-system by the microcontroller executing the programming algorithms out
of the Flash Boot memory, or SRAM. The Flash Boot memory can be programmed the
same way by executing out of the main Flash memory. The PLD logic or other PSD8XXF
configuration can be programmed through the JTAG port or a device programmer. Table 4
indicates which programming methods can program different functional blocks of the
PSD8XXF.
Table 4. Methods of Programming Different Functional Blocks of the PSD8XXF
JTAG
Device
In-System Parallel
Programming
Functional Block
Programming Programmer
Main Flash memory
Flash Boot memory
PLD Array (DPLD and CPLD)
PSD Configuration
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
5.8 Power Management Unit
The Power Management Unit (PMU) in the PSD8XXF gives the user control of the
power consumption on selected functional blocks based on system requirements. The
PMU includes an Automatic Power Down unit (APD) that will turn off device functions due
to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce
power consumption.
The PSD8XXF also has some bits that are configured at run-time by the MCU to reduce
power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off
and the CPLD will latch its outputs and go to sleep until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the CPLD to reduce power consumption. See section 9.5.
8
Preliminary Information
PSD8XXF Family
The PSD8XXF family is supported by the Windows-based PSDsoft Development System.
The PSDsoft design flow is shown in Figure 2. The PLD design entry is done using
PSDabel, which creates a minimized logic implementation, and provides logic simulation
of the PLDs. The PSD8XXF MCU Bus Interface and I/O Port configuration are entered in
PSD Configuration.
6.0
Development
System
PSDsoft can generate ANSI C functions specific to the PSD. The user can merge these
C functions with their own, and then compile and link it using any embedded C compiler on
the market.
PSD Fitter is comprised of a fitter and address translator. It generates a programming data
file (.obj) based on PSD configuration data, the PSDabel file, and the microcontroller
firmware. The object file can be downloaded to a programmer or to PSD Simulator for
device-level simulation.
PSDsoft offers direct support for two Waferscale device programmers, PSDpro, and
FlashLink (JTAG). PSDsoft makes available a file to support third party programmers. The
*.obj file is in Intel hex format, and is compatible with conventional device programmers.
Figure 2. PSDsoft Development Tools
PSDabel
ZPLD DESCRIPTION
MODIFY ABEL TEMPLATE FILE
OR GENERATE NEW FILE
PSD Configuration
PSD TOOLS
CONFIGURE MCU BUS
INTERFACE AND OTHER
PSD ATTRIBUTES
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
PSD Fitter
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
LOGIC SYNTHESIS
AND FITTING
FIRMWARE
HEX OR S-RECORD
FORMAT
ADDRESS TRANSLATION
AND MEMORY MAPPING
*.OBJ FILE
PSD Simulator
PSD Programmer
*.OBJ FILE
AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG-ISC)
PSDsilos III
DEVICE SIMULATION
(OPTIONAL)
PSDPro, or
FlashLink (JTAG)
9
PSD8XXF Family
Preliminary Information
The following table describes the pin names and pin functions of the PSD8XXF. Pins that
have multiple names and/or functions are defined using PSD Configuration.
7.0
Table 5.
PSD8XXF
Pin
Pin Name Pin* Type
Description
Descriptions
ADIO0-7
30-37 I/O This is the lower Address/Data port. Connect your MCU
address or address/data bus according to the following rules:
1. If your MCU has a multiplexed address/data bus where
the data is multiplexed with the lower address bits,
connect AD[0:7] to this port.
2. If your MCU does not have a multiplexed address/data
bus, or you are using an 80C251 in page mode, connect
A[0:7] to this port.
3. If you are using an 80C51XA in burst mode, connect
A4/D0 through A11/D7 to this port.
ALE or AS latches the address. The PSD drives data out only
if the read signal is active and one of the PSD functional
blocks was selected. The addresses on this port are passed
to the PLDs.
ADIO8-15
39-46 I/O This is the upper Address/Data port. Connect your MCU
address or address/data bus according to the following rules:
1. If your MCU has a multiplexed address/data bus where
the data is multiplexed with the lower address bits,
connect A[8:15] to this port.
2. If your MCU does not have a multiplexed address/data
bus, connect A[8:15] to this port.
3. If you are using an 80C251 in page mode, connect
AD[8:15] to this port.
4. If you are using an 80C51XA in burst mode, connect
A12/D8 through A19/D15 to this port.
ALE or AS latches the address. The PSD drives data out only
if the read signal is active and one of the PSD functional
blocks was selected. The addresses on this port are passed
to the PLDs.
CNTL0
CNTL1
47
50
I
I
The following control signals can be connected to this port,
based on your MCU:
1. WR — active-low write input.
2. R_W — active-high read/active low write input.
This pin is connected to the PLDs. Therefore, these signals
can be used in decode and other logic equations.
The following control signals can be connected to this port,
based on your MCU:
1. RD — active-low read input.
2. E — E clock input.
3. DS — active-low data strobe input.
4. PSEN — connect PSEN to this port when it is being used
as an active-low read signal. For example, when the
80C251 outputs more than 16 address bits, PSEN is
actually the read signal.
This pin is connected to the PLDs. Therefore, these
signals can be used in decode and other logic equations.
10
Preliminary Information
PSD8XXF Family
Table 5.
PSD8XXF
Pin
Descriptions
(cont.)
Pin Name Pin* Type
Description
CNTL2
49
I
This pin can be used to input the PSEN (Program Select
Enable) signal from any MCU that uses this signal for code
exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This
port is connected to the PLDs.
Reset
48
I
Active low reset input. Resets I/O Ports, PLD Micro Cells
and some of the configuration registers. Must be active at
power up.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
I/O
These pins make up Port A. These port pins are configurable
and can have the following functions:
28
27
25
24
23
22
21
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
5. Address inputs. For example, PA0-3 could be used for
A[0:3] when using an 80C51XA in burst mode.
6. As the data bus inputs D[0:7] for non-multiplexed
address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-3 can only output CMOS signals with an option
for high slew rate. However, PA4-7 can be configured as
CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
I/O
These pins make up Port B. These port pins are configurable
and can have the following functions:
5
4
1. MCU I/O — write to or read from a standard output or
input port.
3
2
2. CPLD Micro Cell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
52
51
4. Latched address outputs (see Table 6).
Note: PB0-3 can only output CMOS signals with an option
for high slew rate. However, PB4-7 can be configured as
CMOS or Open Drain Outputs.
PC0
20
I/O
PC0 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellBC0) output.
3. Input to the PLDs.
4. TMS Input** for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1
19
I/O
PC1 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellBC1) output.
3. Input to the PLDs.
4. TCK Input** for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
11
PSD8XXF Family
Preliminary Information
Table 5.
PSD8XXF
Pin
Descriptions
(cont.)
Pin Name Pin* Type
Description
PC2
18
I/O
PC2 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellBC2) output.
3. Input to the PLDs.
4. Vstby — SRAM standby voltage input for SRAM battery
backup.
This pin can be configured as a CMOS or Open Drain output.
PC3
17
I/O
PC3 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellBC3) output.
3. Input to the PLDs.
4. TSTAT output** for the JTAG interface.
5. Rdy/Bsy output for in-system parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4
14
I/O
PC4 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellBC4) output.
3. Input to the PLDs.
4. TERR output** for the JTAG interface.
5. Vbaton — battery backup indicator output. Goes high
when power is being drawn from an external battery.
This pin can be configured as a CMOS or Open Drain output.
PC5
13
I/O
PC5 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellBC5) output.
3. Input to the PLDs.
4. TDI input** for the JTAG interface.
This pin can be configured as a CMOS or Open Drain output.
PC6
12
I/O
PC6 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellBC6) output.
3. Input to the PLDs.
4. TDO output** for the JTAG interface.
This pin can be configured as a CMOS or Open Drain output.
12
Preliminary Information
PSD8XXF Family
Table 5.
PSD8XXF
Pin
Descriptions
(cont.)
Pin Name Pin* Type
Description
PC7
11
I/O PC7 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro Cell (McellBC7) output.
3. Input to the PLDs.
4. DBE — active-low Data Byte Enable input from 68HC912
type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0
PD1
10
I/O PD0 pin of Port D. This port pin can be configured to have
the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O — write or read from a standard output or input
port.
3. Input to the PLDs.
4. CPLD output (external chip select).
9
I/O PD1 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. CPLD output (external chip select).
4. CLKIN — clock input to the CPLD Micro Cells, the
automatic power-down unit’s power-down counter, and
the CPLD AND array.
PD2
8
I/O PD2 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. CPLD output (external chip select).
4. CSI — chip select input. When low, the MCU can access
the PSD memory and I/O. When high, the PSD memory
blocks are disabled to conserve power.
V
15, 38
Power pins
CC
GND
1,16,26
Ground pins
**The pin numbers in this table are for the PLCC package only. See the package information section for pin
numbers on other package types.
**These functions can be multiplexed with other functions.
Table 6. I/O Port Latched Address Output Assignments*
Port A
Port B
Port B (7:4)
Microcontroller
Port A (3:0) Port A (7:4) Port B (3:0)
8051XA (8-bit)
N/A
N/A
Address [7:4] Address [11:8] N/A
N/A Address [11:8] Address [15:12]
80C251 (page mode)
All other 8-bit
multiplexed
Address [3:0] Address [7:4] Address [3:0] Address [7:4]
N/A N/A Address [3:0] Address [7:4]
8-bit non-multiplexed
bus
N/A = Not Applicable
**Refer to the I/O Port Section on how to enable the Latched Address Output function.
13
PSD8XXF Family
Preliminary Information
Table 7 shows the offset addresses to the PSD8XXF registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD8XXF registers. Table 7 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
8.0
PSD8XXF
Register
Description
and Address
Offset
Table 7. Register Address Offset
Register Name Port A Port B Port C Port D Other*
Description
Reads Port pin as input,
MCU I/O input mode
Data In
Control
00
02
01
03
10
11
Selects mode between
MCU I/O or Address Out
Stores data for output
to Port pins, MCU I/O
output mode
Data Out
Direction
04
06
05
07
12
14
13
15
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Drive Select
08
09
16
17
1B
Input Micro Cell
Enable Out
0A
0C
0B
0D
18
1A
Reads Input Micro Cells
Reads the status of the
output enable to the I/O
Port driver
Read – reads output of
Micro Cells AB
Write – loads Micro cell
Flip-Flops
Output
Micro Cells AB
20
20
21
Read – reads output of
Micro Cells BC
Write – loads Micro cell
Flip-Flops
Output
Micro Cells BC
21
23
Mask
Micro Cells AB
Blocks writing to the
22
22
23
Output Micro Cells AB
Mask
Micro Cells BC
Blocks writing to the
Output Micro Cells BC
Read only – Flash Sector
Protection
Flash Protection
C0
C2
Read only – PSD Security
and Flash Boot Sector
Protection
Flash Boot
Protection
JTAG Enable
PMMR0
C7
B0
Enables JTAG Port
Power Management
Register 0
Power Management
Register 2
PMMR2
Page
B4
E0
Page Register
Places PSD memory
areas in Program and/or
Data space on an
VM
E2
individual basis.
*Other registers that are not part of the I/O ports.
14
Preliminary Information
PSD8XXF Family
As shown in Figure 1, the PSD8XXF consists of six major types of functional blocks:
9.0
The
❏ Memory Blocks
❏ PLD Blocks
❏ Bus Interface
❏ I/O Ports
PSD8XXF
Functional
Blocks
❏ Power Management Unit
❏ JTAG Interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
9.1 Memory Blocks
The PSD8XXF has the following memory blocks:
• The main Flash memory
• Flash boot memory
• Optional SRAM.
The memory select signals for these blocks originate from the Decode PLD (DPLD) and
are user-defined in PSDsoft.
Table 8 summarizes which versions of the PSD8XXF contain which memory blocks.
Table 8. Memory Blocks
Main Flash
Flash Boot Block
Device
Flash Size
Sector Size Block Size Sector Size
SRAM
PSD813F2
PSD813F3
PSD813F4
PSD813F5
128KB
128KB
128KB
128KB
16KB
16KB
16KB
16KB
32KB
none
32KB
none
8KB
–
2KB
2KB
8KB
–
none
none
PSD833F2
PSD834F2
128KB
256KB
16KB
32KB
32KB
32KB
8KB
8KB
8KB
8KB
9.1.1 Main Flash and Flash Boot Memory Description
The main Flash memory block is divided evenly into eight sectors. The Flash Boot memory
is divided into four sectors of eight Kbytes each. Each sector of either memory can be
separately protected from program and erase operations.
Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte.
Flash sector erasure may be suspended while data is read from other sectors of memory
and then resumed after reading.
During a program or erase of Flash, the status can be output on the Rdy/Bsy pin of Port
C3. This pin is set up using PSDsoft Configuration.
15
PSD8XXF Family
Preliminary Information
9.1.1.1 Memory Block Selects
The
The decode PLD in the PSD8XXF generates the chip selects for all the internal memory
blocks (refer to the PLD section). Each of the eight Flash memory sectors have a
Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the
four Flash Boot memory sectors have a Select signal (CSBOOT0-3) which can contain
up to three product terms. Having three product terms for each sector select signal
allows a given sector to be mapped in different areas of system memory. When using a
microcontroller with separate Program and Data space, these flexible select signals allow
dynamic re-mapping of sectors from one space to the other.
PSD8XXF
Functional
Blocks
(cont.)
9.1.1.2 The Ready/Busy Pin (PC3)
Pin PC3 can be used to output the Ready/Busy status of the PSD8XXF. The output on the
pin will be a ‘0’ (Busy) when Flash memory blocks are being written to, or when the Flash
memory block is being erased. The output will be a ‘1’ (Ready) when no write or erase
operation is in progress.
9.1.1.3 Memory Operation
The main Flash and Flash Boot memories are addressed through the microcontroller
interface on the PSD8XXF device. The microcontroller can access these memories in one
of two ways:
❏ The microcontroller can execute a typical bus write or read operation just as it would
if accessing a RAM or ROM device using standard bus cycles.
❏ The microcontroller can execute a specific instruction that consists of several write
and read operations. This involves writing specific data patterns to special addresses
within the Flash to invoke an embedded algorithm. These instructions are summarized
in Table 9.
Typically, Flash memory can be read by the microcontroller using read operations, just
as it would read a ROM device. However, Flash memory can only be erased and
programmed with specific instructions. For example, the microcontroller cannot write a
single byte directly to Flash memory as one would write a byte to RAM. To program a byte
into Flash memory, the microcontroller must execute a program instruction sequence, then
test the status of the programming event. This status test is achieved by a read operation
or polling the Rdy/Busy pin (PC3).
The Flash memory can also be read by using special instructions to retrieve particular
Flash device information (sector protect status and ID).
16
Preliminary Information
PSD8XXF Family
9.1.1.3.1 Instructions
The
An instruction is defined as a sequence of specific operations. Each received byte is
sequentially decoded by the PSD and not executed as a standard write operation. The
instruction is executed when the correct number of bytes are properly received and the
time between two consecutive bytes is shorter than the time-out value. Some instructions
are structured to include read operations after the initial write operations.
PSD8XXF
Functional
Blocks
(cont.)
The sequencing of any instruction must be followed exactly. Any invalid combination of
instruction bytes or time-out between two consecutive bytes while addressing Flash
memory will reset the device logic into a read array mode (Flash memory reads like a
ROM device).
The PSD8XXF main Flash and Boot Flash support these instructions (see Table 9):
❏ Erase memory by chip or sector
❏ Suspend or resume sector erase
❏ Program a byte
❏ Reset to read array mode
❏ Read Main Flash Identifier value
❏ Read sector protection status
❏ Bypass Instruction (PSD8X4F only)
These instructions are detailed in Table 9. For efficient decoding of the instructions, the
first two bytes of an instruction are the coded cycles and are followed by a command byte
or confirmation byte. The coded cycles consist of writing the data AAh to address X555h
during the first cycle and data 55h to address XAAAh during the second cycle. Address
lines A15-A12 are don’t care during the instruction write cycles. However, the appropriate
sector select signal (FSi or CSBOOTi) must be selected.
The main Flash and the Flash Boot Block have the same set of instructions (except Read
main Flash ID). The chip selects of the Flash memory will determine which Flash will
receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is
active, and the Flash Boot Block is selected if any one of the CS BOOT0-3 is active.
17
PSD8XXF Family
Preliminary Information
The
Table 9. Instructions
PSD8XXF
Functional
Blocks
(cont.)
FS0-7
or
Instruction
CSBOOT0-3 Cycle 1 Cycle 2 Cycle 3 Cycle 4
Cycle5
Cycle 6 Cycle 7
Read (Note 5)
1
1
“Read”
RA RD
Read Main Flash ID
(Notes 6,13)
AAh
@555h
55h
90h
“Read”
ID
@AAAh @555h
@x01h
Read Sector Protection
(Notes 6,8,13)
1
AAh
@555h
55h
90h
“Read”
@AAAh @555h 00h or 01h
@x02h
Program a Flash Byte
1
1
AAh
@555h
55h
A0h
PD@PA
@AAAh @555h
Erase One Flash Sector
AAh
55h 80h
AAh
55h
30h
30h
@555h
@AAAh @555h
@555h
@AAAh
@SA
@next SA
(Note 7)
Erase Flash Block
(Bulk Erase)
1
1
1
1
1
1
1
AAh
@555h
55h
80h
AAh
@555h
55h
@AAAh
10h
@555h
@AAAh @555h
Suspend Sector Erase
(Note 11)
B0h
@xxxh
Resume Sector Erase
(Note 12)
30h
@xxxh
Reset (Note 6)
F0 @ any
address
Unlock Bypass
(Note 14)
AAh
@555h
55h
20h
@AAAh @555h
Unlock Bypass Program
(Note 9,14)
A0h
@xxxh
PD@PA
Unlock Bypass Reset
(Note 10,14)
90h
@xxxh
00h
@xxxh
X
= Don’t Care.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR#
(CNTL0) pulse.
PD = Data to be programmed at location PA. Data is latched o the rising edge of WR# (CNTL0) pulse.
SA = Address of the sector to be erased or verified. The chip select (FS0-7 or CSBOOT0-3) of the sector to be
erased must be active (high).
NOTES:
1. All bus cycles are write bus cycle except the ones with the “read” label.
2. All values are in hexadecimal.
3. FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft.
4. Only Address bits A11-A0 are used in Instruction decoding. A15-12 (or A16-A12) are don’t care.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status
or if DQ5 (error flag) goes high.
7. Additional sectors to be erased must be entered within 80µs.
8. The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip
select is active and (A1 = 1, A0 = 0).
9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
Unlock Bypass mode.
11. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector
Protect status, when in the Erase Suspend mode. The erase Suspend command is valid only during a sector
erase operation.
12. The Erase Resume command is valid only during the Erase Suspend mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the
instruction is intended. The MCU must fetch, for example, codes from the Boot block when reading the
Sector Protection Status of the main Flash.
14. Available to PSD8X4F device only.
18
Preliminary Information
PSD8XXF Family
The
9.1.1.4 Power-Up Condition
The PSD8XXF internal logic is reset upon power-up to the read array mode. The FSi and
CSBOOTi select signals, along with the write strobe signal, must be in the false state
during power-up for maximum security of the data contents and to remove the possibility of
a byte being written on the first edge of a write strobe signal. Any write cycle initiation is
PSD8XXF
Functional
Blocks
(cont.)
locked when V is below VLKO.
CC
9.1.1.5 Read
Under typical conditions, the microcontroller may read the Flash, or Flash Boot
memories using read operations just as it would a ROM or RAM device. Alternately, the
microcontoller may use read operations to obtain status information about a program or
erase operation in progress. Lastly, the microcontroller may use instructions to read
special data from these memories. The following sections describe these read functions.
9.1.1.5.1 Read the Contents of Memory
Main Flash and Flash Boot memories are placed in the read array mode after power-up,
chip reset, or a Reset Flash instruction (see Table 9). The microcontroller can read the
memory contents of main Flash or Flash Boot by using read operations any time the read
operation is not part of an instruction sequence.
9.1.1.5.2 Read the Main Flash Memory Identifier
The main Flash memory identifier is read with an instruction composed of 4 operations:
3 specific write operations and a read operation (see Table 9). During the read operation,
address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select
signal (FSi) must be active. The PSD8XXF main Flash memory ID is E7h. (PSD833F2,
PSD834F2) and E4h (PSD813FX).
9.1.1.5.3 Read the Flash Memory Sector Protection Status
The Flash memory sector protection status is read with an instruction composed of 4
operations: 3 specific write operations and a read operation (see Table 9). During the read
operation, address bits A6, A1, and A0 must be 0,1,0, respectively, while the chip select
(FSi or CSBOOTi) designates the Flash sector whose protection has to be verified. The
read operation will produce 01h if the Flash sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks (main Flash or Boot Flash) can also be
read by the microcontroller accessing the Flash Protection and Flash Boot Protection
registers in PSD I/O space. See section 9.1.1.9.1 for register definitions.
9.1.1.5.4 Read the Erase/Program Status Bits
The PSD8XXF provides several status bits to be used by the microcontroller to confirm
the completion of an erase or programming instruction of Flash memory. These status bits
minimize the time that the microcontroller spends performing these tasks and are defined
in Table 10. The status bits can be read as many times as needed.
Table 10. Status Bits
FSi/
CSBOOTi
DQ7
Data Toggle Error
Polling Flag Flag
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Erase
Time-
out
Flash
V
X
X
X
X
IH
NOTES: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FSi/CSBOOTi are active high.
For Flash memory, the microcontroller can perform a read operation to obtain these status
bits while an erase or program instruction is being executed by the embedded algorithm.
See section 9.1.1.7 for details.
19
PSD8XXF Family
Preliminary Information
9.1.1.5.5 Data Polling Flag DQ7
The
When Erasing or Programming the Flash memory bit DQ7 outputs the complement of the
bit being entered for Programming/Writing on DQ7. Once the Program instruction or the
Write operation is completed, the true logic value is read on DQ7 (in a Read operation).
Flash memory specific features:
PSD8XXF
Functional
Blocks
(cont.)
❏ Data Polling is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase). It must be performed at the address being programmed
or at an address within the Flash sector being erased.
❏ During an Erase instruction, DQ7 outputs a ‘0’. After completion of the instruction,
DQ7 will output the last bit programmed (it is a ‘1’ after erasing).
❏ If the byte to be programmed is in a protected Flash sector, the instruction is
ignored.
❏ If all the Flash sectors to be erased are protected, DQ7 will be set to ‘0’ for
about 100 µs, and then return to the previous addressed byte. No erasure will be
performed.
9.1.1.5.6 Toggle Flag DQ6
The PSD8XXF offers another way for determining when the Flash memory Program
instruction is completed. During the internal Write operation and when either the FSi or
CSBOOTi is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent attempts to
read any byte of the memory.
When the internal cycle is complete, the toggling will stop and the data read on the
Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new
Read or Write operation. The operation is finished when two successive reads yield the
same output data. Flash memory specific features:
❏ The Toggle bit is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase).
❏ If the byte to be programmed belongs to a protected Flash sector, the instruction is
ignored.
❏ If all the Flash sectors selected for erasure are protected, DQ6 will toggle to ‘0’ for
about 100 µs and then return to the previous addressed byte.
9.1.1.5.7 Error Flag DQ5
During a correct Program or Erase, the Error bit will set to ‘0’. This bit is set to ‘1’ when
there is a failure during Flash byte programming, Sector erase, or Bulk Erase.
In the case of Flash programming, the Error Bit indicates the attempt to program a Flash
bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation.
The Error bit may also indicate a timeout condition while attempting to program a byte.
In case of an error in Flash sector erase or byte program, the Flash sector in which the
error occurred or to which the programmed byte belongs must no longer be used.
Other Flash sectors may still be used. The Error bit resets after the Reset instruction.
9.1.1.5.8 Erase Time-out Flag DQ3
The Erase Timer bit reflects the time-out period allowed between two consecutive Sector
Erase instructions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a
time period of 100 µs + 20% unless an additional Sector Erase instruction is decoded.
After this time period or when the additional Sector Erase instruction is decoded, DQ3 is
set to ‘1’.
20
Preliminary Information
PSD8XXF Family
The
9.1.1.6 Programming Flash Memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all
logic ones (FF hex), and its bits are programmed to logic zeros. Although erasing Flash
memory occurs on a sector basis, programming Flash memory occurs on a byte basis.
PSD8XXF
Functional
Blocks
(cont.)
The PSD8XXF main Flash and boot Flash memories require the MCU to send an
instruction to program a byte or perform an erase function (see Table 9).
Once the MCU issues a Flash memory program or erase instruction, it must check for the
status of completion. The embedded algorithms that are invoked inside the PSD8XXF
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.
9.1.1.6.1 Data Polling
Polling on DQ7 is a method of checking whether a Program or Erase instruction is in
progress or has completed. Figure 3 shows the Data Polling algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD8XXF begins. The MCU then reads the location of the byte to be programmed in Flash
to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the
original data byte to be programmed. The MCU continues to poll this location, comparing
DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of the original
data, and the Error bit at DQ5 remains ‘0’, then the embedded algorithm is complete.
If the Error bit at DQ5 is ‘1’, the MCU should test DQ7 again since DQ7 may have changed
simultaneously with DQ5 (see Figure 3).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a ‘1’ to a bit
that was not erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the byte that was written to Flash with
the byte that was intended to be written.
When using the Data Polling method after an erase instruction, Figure 3 still applies.
However, DQ7 will be ‘0’ until the erase operation is complete. A ‘1’ on DQ5 will indicate
a timeout failure of the erase operation, a ‘0’ indicates no error. The MCU can read any
location within the sector being erased to get DQ7 and DQ5.
PSDsoft will generate ANSI C code functions which implement these Data Polling
algorithms.
21
PSD8XXF Family
Preliminary Information
The
Figure 3. Data Polling Flow Chart
PSD8XXF
Functional
Blocks
(cont.)
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA7
YES
NO
NO
DQ5
=1
YES
READ DQ7
YES
DQ7
=
DATA
NO
FAIL
PASS
9.1.1.6.2 Data Toggle
Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or
Erase instruction is in progress or has completed. Figure 4 shows the Data Toggle
algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD8XXF begins. The MCU then reads the location of the byte to be programmed in
Flash to check status. Data bit DQ6 of this location will toggle each time the MCU reads
this location until the embedded algorithm is complete. The MCU continues to read this
location, checking DQ6 and monitoring the Error bit on DQ5. When DQ6 stops toggling
(two consecutive reads yield the same value), and the Error bit on DQ5 remains ‘0’, then
the embedded algorithm is complete. If the Error bit on DQ5 is ‘1’, the MCU should test
DQ6 again, since DQ6 may have changed simultaneously with DQ5 (see Figure 4).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte, or if the MCU attempted to program a ‘1’ to a bit
that was not erased (not erased is logic ‘0’).
22
Preliminary Information
PSD8XXF Family
9.1.1.6.2 Data Toggle (cont.)
The
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the byte that was written to Flash with
the byte that was intended to be written.
PSD8XXF
Functional
Blocks
(cont.)
When using the Data Toggle method after an erase instructin, Figure 4 still applies. DQ6
will toggle until the erase operation is complete. A ‘1’ on DQ5 will indicate a timeout failure
of the erase operation, a ‘0’ indicates no error. The MCU can read any location within the
sector being erased to get DQ6 and DQ5.
PSDsoft will generate ANSI C code functions which implement these Data Toggling
algorithms.
Figure 4. Data Toggle Flow Chart
START
READ
DQ5 & DQ6
DQ6
NO
=
TOGGLE
YES
NO
DQ5
=1
YES
READ DQ6
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
23
PSD8XXF Family
Preliminary Information
The
9.1.1.7 Unlock Bypass Instruction (PSD8X4F only)
The unlock bypass feature allows the system to program bytes to the flash memories
faster than using the standard program instruction. The unlock bypass instruction is
initiated by first writing two unlock cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h (see Table 9). The flash memory then enters the unlock
bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to
program in this mode. The first cycle in this instruction contains the unlock bypass
programm command, A0h; the second cycle contains the program address and data.
Additional data is programmed in the same manner. This mode dispenses with the initial
two unlock cycles requiredc in the standard program instruction, resulting in faster total
programming time. During the unlock bypass mode, only the Unlock Bypass Program and
Unlock Bypass Reset instructions are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset instruction. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The
falsh memory then returns to reading array data mode.
PSD8XXF
Functional
Blocks
(cont.)
9.1.1.8 Erasing Flash Memory
9.1.1.8.1. Flash Bulk Erase Instruction
The Flash Bulk Erase instruction uses six write operations followed by a Read operation of
the status register, as described in Table 9. If any byte of the Bulk Erase instruction is
wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory
status.
During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6,
and DQ7, as detailed in section 9.1.1.6. The Error bit (DQ5) returns a ‘1’ if there has been
an Erase Failure (maximum number of erase cycles have been executed).
It is not necessary to program the array with 00h because the PSD8XXF will automatically
do this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory will not accept any
instructions.
9.1.1.8.2 Flash Sector Erase Instruction
The Sector Erase instruction uses six write operations, as described in Table 9. Additional
Flash Sector Erase confirm commands and Flash sector addresses can be written
subsequently to erase other Flash sectors in parallel, without further coded cycles, if the
additional instruction is transmitted in a shorter time than the timeout period of about
100 µs. The input of a new Sector Erase instruction will restart the time-out period.
The status of the internal timer can be monitored through the level of DQ3 (Erase time-out
bit). If DQ3 is ‘0’, the Sector Erase instruction has been received and the timeout is
counting. If DQ3 is ‘1’, the timeout has expired and the PSD8XXF is busy erasing the
Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend
and Erase Resume will abort the instruction and reset the device to Read Array mode.
It is not necessary to program the Flash sector with 00h as the PSD8XXF will do this
automatically before erasing (byte=FFh).
During a Sector Erase, the memory status may be checked by reading status bits DQ5,
DQ6, and DQ7, as detailed in section 9.1.1.6.
During execution of the erase instruction, the Flash block logic accepts only Reset and
Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to
read data from another Flash sector, and then resumed.
24
Preliminary Information
PSD8XXF Family
9.1.1.8.3 Flash Erase Suspend Instruction
The
When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will
suspend the operation by writing 0B0h to any address when an appropriate Chip Select
(FSi or CSBOOTi) is true. (See Table 9). This allows reading of data from another Flash
sector after the Erase operation has been suspended. Erase suspend is accepted only
during the Flash Sector Erase instruction execution and defaults to read array mode. An
Erase Suspend instruction executed during an Erase timeout will, in addition to suspending
the erase, terminate the time out.
PSD8XXF
Functional
Blocks
(cont.)
The Toggle Bit DQ6 stops toggling when the PSD8XXF internal logic is suspended. The
toggle Bit status must be monitored at an address within the Flash sector being erased.
The Toggle Bit will stop toggling between 0.1 µs and 15 µs after the Erase Suspend
instruction has been executed. The PSD8XXF will then automatically be set to Read Flash
Block Memory Array mode.
If an Erase Suspend instruction was executed, the following rules apply:
• Attempting to read from a Flash sector that was being erased will output invalid data.
• Reading from a Flash sector that was not being erased is valid.
• The Flash memory cannot be programmed, and will only respond to Erase Resume
and Reset instructions (read is an operation and is OK).
• If a Reset instruction is received, data in the Flash sector that was being erased will
be invalid.
9.1.1.8.4 Flash Erase Resume Instruction
If an Erase Suspend instruction was previously executed, the erase operation may be
resumed by this instruction. The Erase Resume instruction consists of writing 030h to any
address while an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 9.)
9.1.1.9 Specific Features
9.1.1.9.1 Flash and Flash Boot Sector Protect
Each Flash and Flash Boot sector can be separately protected against Program and
Erase functions. Sector Protection provides additional data security because it disables all
program or erase operations. This mode can be activated through the JTAG Port or a
Device Programmer.
Sector protection can be selected for each sector using the PSDsoft Configuration
program. This will automatically protect selected sectors when the device is programmed
through the JTAG Port or a Device Programmer. Flash sectors can be unprotected to
allow updating of their contents using the JTAG Port or a Device Programmer. The
microcontroller can read (but cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash sector will be ignored by the device.
The Verify operation will result in a read of the protected data. This allows a guarantee of
the retention of the Protection status.
The sector protection status can be read by the MCU through the Flash protection and
Flash Boot protection registers (CSIOP). See Table 11.
25
PSD8XXF Family
Preliminary Information
The
Table 11. Sector Protection/Security Bit Definition
Flash Protection Register
PSD8XXF
Functional
Blocks
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Main Flash Sector <i> is write protected.
0 = Main Flash Sector <i> is not write protected.
Flash Boot Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
*
Bit 3
Bit 2
Bit 1
Bit 0
Security_
Bit
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
*
*
*: Not used.
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Flash Boot Sector <i> is write protected.
0 = Flash Boot Sector <i> is not write protected.
Security_Bit
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
9.1.1.9.2 Reset Instruction – PSD8X3F2
The Reset instruction consists of one write cycle (see Table 9). It can also be optionally
preceded by the standard two write decoding cycles (writing AAh to 555h and 55h to
AAAh).
The Reset instruction must be executed after:
1. Reading the Flash Protection status or Flash ID
2. When an error condition occurs (DQ5 goes high) during a Flash programming or erase
cycle.
The Reset instruction will reset the Flash to normal Read Mode. It may take the Flash
memory up to few mSeconds to complete the reset cycle.
The Reset instruction is ignored when it is issued during a Flash programming or Bulk
Erase cycle. During Sector Erase cycle, the Reset instruction will abort the on going sector
erase cycle and return the Flash to normal Read Mode in up to few mSeconds.
9.1.1.9.2 Reset Instruction – PSD8X4F2
The Reset instruction consists of one write cycle (see Table 9). It can also be optionally
preceded by the standard two write decoding cycles (writing AAh to 555h and 55h to
AAAh).
The Reset instruction must be executed after:
1. Reading the Flash Protection status or Flash ID
2. When an error condition occurs (DQ5 goes high) during a Flash programming or erase
cycle.
The Reset instruction will reset the Flash to normal Read Mode. However, if there is an
error condition (DQ5 goes high), the Flash memory will return to the Read Mode in 25
µSeconds after the Reset instruction is issued.
The Reset instruction is ignored when it is issued during a Flash programming or Bulk
Erase cycle. The Reset instruction will abort the on going sector erase cycle and return the
Flash memory to normal Read Mode in 25 µSeconds.
26
Preliminary Information
PSD8XXF Family
9.1.1.9.3 Reset Pin Input – PSD8X4F2
The
The reset pulse input from the pin will abort any operation in progress and reset the Flash
memory to Read Mode. When the reset occurs during a programming or erase cycle, the
Flash memory will take up to 25 µSeconds to return to Read Mode. It is recommended that
the reset pulse (except power on reset, see Reset Section) be at least 25 µSeconds such
that the Flash memory will always be ready for the MCU to fetch the boot codes after reset
is over.
PSD8XXF
Functional
Blocks
(cont.)
9.1.2 SRAM
The SRAM is enabled when RS0—the SRAM chip select output from the DPLD—is high.
RS0 can contain up to two product terms, allowing flexible memory mapping.
The SRAM can be backed up using an external battery. The external battery should be
connected to the Vstby pin (PC2). If you have an external battery connected to the
PSD8XXF, the contents of the SRAM will be retained in the event of a power loss. The
contents of the SRAM will be retained so long as the battery voltage remains at 2V or
greater. If the supply voltage falls below the battery voltage, an internal power switchover
to the battery occurs.
Pin PC4 can be configured as an output that indicates when power is being drawn from the
external battery. This Vbaton signal will be high with the supply voltage falls below the bat-
tery voltage and the battery on PC2 is supplying power to the internal SRAM.
The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using
PSDsoft Configuration.
9.1.3 Memory Select Signals
The main Flash (FSi), Flash Boot (CSBOOTi), and SRAM (RS0) memory select signals
are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The
following rules apply to the equations for the internal chip select signals:
1. Main Flash memory and Flash Boot memory sector select signals must not be larger
than the physical sector size.
2. Any main Flash memory sector must not be mapped in the same memory space as
another Main Flash sector.
3. A Flash Boot memory sector must not be mapped in the same memory space as
another Flash Boot sector.
4. SRAM, I/O, and Peripheral I/O spaces must not overlap.
5. A Flash Boot memory sector may overlap a main Flash memory sector. In case of
overlap, priority will be given to the Flash Boot sector.
6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority
will be given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) will automatically address Boot memory segment 0. Any address
greater than 9FFFh will access the Flash memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this
example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to
BFFFh would not be valid.
Figure 5 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on
the same level must not overlap. Level one has the highest priority and level 3 has the
lowest.
27
PSD8XXF Family
Preliminary Information
The
Figure 5. Priority Level of Memory and I/O Components
PSD8XXF
Functional
Blocks
(cont.)
Highest Priority
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Flash Boot Memory
Level 3
Main Flash Memory
Lowest Priority
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151,
80C251, and 80C51XA, have separate address spaces for code memory (selected using
PSEN) and data memory (selected using RD). Any of the memories within the PSD8XXF
can reside in either space or both spaces. This is controlled through manipulation of the
VM register that resides in the PSD’s CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and Flash in Data Space at boot, and Boot
Block in Program Space at boot, and later swap Boot Block and Flash. This is easily done
with the VM register by using PSDsoft Configuration to configure it for boot up and having
the microcontroller change it when desired.
Table 13 describes the VM Register.
Table 13. VM Register
Bit 7
Bit 6* Bit 5* Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIO_EN
FL_Data Boot_Data FL_Code Boot_Code SRAM_Code
0 = disable
PIO mode
0 = RD 0 = RD
can’t can’t
access access
Flash
0 = PSEN 0 = PSEN
0 = PSEN
can’t
access
*
*
*
*
can’t
can’t
access
access
Boot Flash Flash
Boot Flash SRAM
1 = PSEN 1 = PSEN 1 = PSEN
access access access
Boot Flash Flash Boot Flash SRAM
1= enable
PIO mode
1 = RD 1 = RD
access access
Flash
NOTE: Bits 6-5 are not used.
28
Preliminary Information
PSD8XXF Family
9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces
9.1.3.2.1 Separate Space Modes
The
PSD8XXF
Functional
Blocks
(cont.)
Code memory space is separated from data memory space. For example, the PSEN
signal is used to access the program code from the Flash Memory, while the RD signal is
used to access data from the Boot memory, SRAM and I/O Ports. This configuration
requires the VM register to be set to 0Ch.
9.1.3.2.2 . Combined Space Modes
The program and data memory spaces are combined into one space that allows the main
Flash Memory, Boot memory, and SRAM to be accessed by either PSEN or RD. For
example, to configure the main Flash memory in combined space mode, bits 2 and 4 of the
VM register are set to “1”.
9.1.3.3 80C31 Memory Map Example
See Application Note 57 and 64 for examples.
Figure 6. 8031 Memory Modes – Separate Space Mode
MAIN
FLASH
FLASH
BOOT
SRAM
DPLD
RS0
BLOCK
CSBOOT0-3
FS0-7
CS
CS
CS
OE
OE
OE
PSEN
RD
Figure 7. 80C31 Memory Mode – Combined Space Mode
MAIN
FLASH
FLASH
BOOT
SRAM
DPLD
RS0
BLOCK
RD
CSBOOT0-3
FS0-7
CS
CS
CS
OE
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
RD
VM REG BIT 2
VM REG BIT 0
29
PSD8XXF Family
Preliminary Information
The
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller.
The outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can
be included in the Flash Memory, Flash Boot Block, and SRAM chip select equations.
PSD8XXF
Functional
Blocks
(cont.)
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See Application
Note 57.
Figure 8 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus D0-D7. The microcontroller can write to or read from the Page Register.
The Page Register can be accessed at address location CSIOP + E0h.
Figure 8. Page Register
RESET
PGR0
INTERNAL
SELECTS
AND LOGIC
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
D0 - D7
DPLD
AND
CPLD
R/W
PAGE
REGISTER
FLASH
PLD
30
Preliminary Information
PSD8XXF Family
The
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD8XXF. After specifying the
logic for the PLDs using the PSDabel tool in PSDsoft, the logic is programmed into the
device and available upon power-up.
PSD8XXF
Functional
Blocks
(cont.)
The PSD8XXF contains two PLDs: the Decode PLD (DPLD), and the Complex PLD
(CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in
sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory,
registers, and I/O port selects.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be
constructed using the 16 Output Micro Cells (OMCs), 24 Input Micro Cells (IMCs), and
the AND array. The CPLD can also be used to generate external chip selects.
The AND array is used to form product terms. These product terms are specified using
PSDabel. An Input Bus consisting of 73 signals is connected to the PLDs. The signals are
shown in Table 15.
Table 15. DPLD and CPLD Inputs
Input Source
Input Name
Number
of Signals
MCU Address Bus
A[15:0]*
16
3
1
1
8
8
8
3
8
8
8
1
MCU Control Signals
Reset
CNTL[2:0]
RST
Power Down
PDN
Port A Input Micro Cells
Port B Input Micro Cells
Port C Input Micro Cells
Port D Inputs
PA[7-0]
PB[7-0]
PC[7-0]
PD[2:0]
Page Register
PGR(7:0)
MCELLAB.FB[7:0]
MCELLBC.FB[7:0]
Rdy/Bsy
Micro Cell AB Feedback
Micro Cell BC Feedback
Boot Flash Programming Status Bit
NOTE: The address inputs are A[19:4] in 80C51XA mode.
The Turbo Bit
The PLDs in the PSD8XXF can minimize power consumption by switching off when inputs
remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off
(Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs
are changing. Turbo-off mode increases propagation delays while reducing power
consumption. Refer to the Power Management Unit section on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2 register to block MCU control signals
from entering the PLDs. This reduces power consumption and can be used only when
these MCU control signals are not used in PLD logic equations.
31
PSD8XXF Family
Preliminary Information
Figure 9. PLD Block Diagram
I / O P O R T S
P L D I N P U T B U S
32
Preliminary Information
PSD8XXF Family
Each of the two PLDs has unique characteristics suited for its applications They are
The
described in the following sections.
PSD8XXF
Functional
Blocks
(cont.)
9.2.1 Decode PLD (DPLD)
The DPLD, shown in Figure 10, is used for decoding the address for internal and external
components. The DPLD can generate the following decode signals:
• 8 sector selects for the main Flash memory (three product terms each)
• 4 sector selects for the Flash Boot memory
(three product terms each)
• 1 internal SRAM select signal (two product terms)
• 1 internal CSIOP (PSD configuration register) select signal
• 1 JTAG select signal (enables JTAG on Port C)
• 2 internal peripheral select signals (peripheral I/O mode).
9.2.2 Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters
and shift registers, system mailboxes, handshaking protocols, state machines, and random
logic. The CPLD can also be used to generate 3 external chip selects, routed to Port D.
Although external chip selects can be produced by any Output Micro Cell, these three
external chip selects on Port D do not consume any Output Micro Cells.
As shown in Figure 9, the CPLD has the following blocks:
• 24 Input Micro Cells (IMCs)
• 16 Output Micro Cells (OMCs)
• Micro Cell Allocator
• Product Term Allocator
• AND array capable of generating up to 137 product terms
• Four I/O ports.
Each of the blocks are described in the subsections that follow.
The Input and Output Micro Cells are connected to the PSD8XXF internal data bus and
can be directly accessed by the microcontroller. This enables the MCU software to load
data into the Output Micro Cells or read data from both the Input and Output
Micro Cells. This feature allows efficient implementation of system logic and eliminates
the need to connect the data bus to the AND logic array as required in most standard PLD
macrocell architectures.
33
PSD8XXF Family
Preliminary Information
Figure 10. DPLD Logic Array
34
Preliminary Information
PSD8XXF Family
Figure 11. The Micro Cell and I/O Port
U X M
M U X
M U X
M U X
A N D A R R A Y
P L D I N P U T B U S
P L D I N P U T B U S
35
PSD8XXF Family
Preliminary Information
9.2.2.1 Output Micro Cell
The
Eight of the Output Micro Cells are connected to Ports A and B pins and are named as
McellAB0-7. The other eight Micro Cells are connected to Ports B and C pins and are
named as McellBC0-7. If an McellAB output is not assigned to a specific pin in PSDabel,
the Micro Cell Allocator will assign it to either Port A or B. The same is true for a McellBC
output on Port B or C. Table 16 shows the Micro Cells and Port assignment.
PSD8XXF
Functional
Blocks
(cont.)
Table 16. Output Micro Cell Port and Data Bit Assignments
Maximum
Native
Product
Terms
Borrowed
Product
Terms
Data Bit for
Loading or
Reading
Output
Micro Cell
Port
Assignment
McellAB0
McellAB1
McellAB2
McellAB3
McellAB4
McellAB5
McellAB6
McellAB7
McellBC0
McellBC1
McellBC2
McellBC3
McellBC4
McellBC5
McellBC6
McellBC7
Port A0, B0
Port A1, B1
Port A2, B2
Port A3, B3
Port A4, B4
Port A5, B5
Port A6, B6
Port A7, B7
Port B0, C0
Port B1, C1
Port B2, C2
Port B3, C3
Port B4, C4
Port B5, C5
Port B6, C6
Port B7, C7
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
The Output Micro Cell (OMC) architecture is shown in Figure 12. As shown in the figure,
there are native product terms available from the AND array, and borrowed product terms
available (if unused) from other OMCs. The polarity of the product term is controlled by the
XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or
combinatorial logic. The multiplexer selects between the sequential or combinatorial logic
outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND
array inputs.
The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDabel
program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term
of the AND array. Alternatively, the external CLKIN signal can be used for the clock input
to the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and
clear are active-high inputs. Each clear input can use up to two product terms.
36
Preliminary Information
PSD8XXF Family
9.2.2.2 The Product Term Allocator
The
The CPLD has a Product Term Allocator. The PSDabel compiler uses the Allocator to
borrow and place product terms from one Micro Cell to another. The following list
summarizes how product terms are allocated:
PSD8XXF
Functional
Blocks
(cont.)
• McellAB0-7 all have three native product terms and may borrow up to six more
• McellBC0-3 all have four native product terms and may borrow up to five more
• McellBC4-7 all have four native product terms and may borrow up to six more.
Each Micro Cell may only borrow product terms from certain other Micro Cells. Product
terms already in use by one Micro Cell will not be available for a different Micro Cell.
If an equation requires more product terms than what is available to it, then “external”
product terms will be required, which will consume other OMCs. If external product terms
are used, extra delay will be added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft will perform this expansion as needed.
9.2.2.3 Loading and Reading the Output Micro Cells (OMCs)
The OMCs occupy a memory location in the MCU address space, as defined by the
CSIOP (refer to the I/O section). The flip-flops in each of the 16 OMCs can be loaded from
the data bus by a microcontroller. Loading the OMCs with data from the MCU takes priority
over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be
overridden by the MCU. The ability to load the flip-flops and read them back is useful in
such applications as loadable counters and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the OMCs on the trailing edge of the WR signal (edge loading) or
during the time that the WR signal is active (level loading). The method of loading is
specified in PSDsoft Configuration.
9.2.2.4 The OMC Mask Register
There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers
can be used to block the loading of data to individual OMCs. The default value for the
Mask Registers is 00h, which allows loading of the OMCs. When a given bit in a Mask
Register is set to a ‘1’, the MCU will be blocked from writing to the associated OMC. For
example, suppose McellAB0-3 are being used for a state machine. You would not want a
MCU write to McellAB to overwrite the state machine registers. Therefore, you would want
to load the Mask Register for McellAB (Mask Micro Cell AB) with the value 0Fh.
9.2.2.5 The Output Enable of the OMC
The OMC can be connected to an I/O port pin as a PLD output. The output enable of each
Port pin driver is controlled by a single product term from the AND array, ORed with the
Direction Register output. The pin is enabled upon power up if no output enable equation
is defined and if the pin is declared as a PLD output in PSDsoft.
If the OMC output is declared as an internal node and not as a Port pin output in the
PSDabel file, then the Port pin can be used for other I/O functions. The internal node
feedback can be routed as an input to the AND array.
37
PSD8XXF Family
Preliminary Information
The
Figure 12. CPLD Output Micro Cell
PSD8XXF
Functional
Blocks
(cont.)
A N D A R R A Y
P L D I N P U T B U S
38
Preliminary Information
PSD8XXF Family
9.2.2.6 Input Micro Cells (IMCs)
The
The CPLD has 24 IMCs, one for each pin on Ports A, B, and C. The architecture of the IMC
is shown in Figure 13. The IMCs are individually configurable, and can be used as a latch,
register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The
outputs of the IMCs can be read by the microcontroller through the internal data bus.
PSD8XXF
Functional
Blocks
(cont.)
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND array or the MCU address strobe (ALE/AS). Each
product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by
one product term and 7-4 by another.
Configurations for the IMCs are specified by equations written in PSDabel (see Application
Note 55). Outputs of the IMCs can be read by the MCU via the IMC buffer. See the I/O Port
section on how to read the IMCs.
IMCs can use the address strobe to latch address bits higher than A15. Any latched
addresses are routed to the PLDs as inputs.
IMCs are particularly useful with handshaking communication applications where two
processors pass data back and forth through a common mailbox. Figure 14 shows a typical
configuration where the Master MCU writes to the Port A Data Out Register. This, in turn,
can be read by the Slave MCU via the activation of the “Slave-Read” output enable product
term. The Slave can also write to the Port A IMCs and the Master can then read the IMCs
directly. Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are
derived from the Slave MCU inputs RD, WR, and Slave_CS.
39
PSD8XXF Family
Preliminary Information
The
Figure 13. Input Micro Cell
PSD8XXF
Functional
Blocks
(cont.)
A N D A R R A Y
P L D I N P U T B U S
40
Preliminary Information
PSD8XXF Family
The
Figure 14. Handshaking Communication Using Input Micro Cells
PSD8XXF
Functional
Blocks
(cont.)
41
PSD8XXF Family
Preliminary Information
The
9.3 Microcontroller Bus Interface
The “no-glue logic” PSD8XXF Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their
bus types and control signals are shown in Table 17. The interface type is specified using
the PSDsoft Configuration.
PSD8XXF
Functional
Blocks
(cont.)
Table 17. Microcontrollers and their Control Signals
Data
Bus
MCU
Width CNTL0 CNTL1
CNTL2
PC7 PD0** ADIO0 PA3-PA0 PA7-PA3
8031
8
8
8
8
8
8
8
8
8
8
8
WR
WR
WR
WR
WR
R/W
R/W
WR
R/W
R/W
R/W
RD
RD
PSEN
RD
RD
E
PSEN
*
*
*
*
*
*
ALE
ALE
ALE
ALE
ALE
AS
A0
A4
A0
A0
A0
A0
A0
A0
A0
A0
A0
*
*
*
*
*
*
*
*
80C51XA
80C251
80C251
80198
PSEN
A3-A0
*
*
*
*
*
*
PSEN
*
*
*
*
*
*
*
68HC11
68HC912
Z80
E
DBE
AS
RD
DS
DS
E
*
*
*
*
*
AS
D3-D0 D7-D4
Z8
*
*
*
*
68330
AS
M37702M2
ALE
D3-D0 D7-D4
**Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be
**configured for other I/O functions.
**ALE/AS input is optional for microcontrollers with a non-multiplexed bus
9.3.1. PSD8XXF Interface to a Multiplexed 8-Bit Bus
Figure 15 shows an example of a system using a microcontroller with an 8-bit multiplexed
bus and a PSD8XXF. The ADIO port on the PSD8XXF is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port A or B. The PSD8XXF drives the ADIO data bus
only when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or D may be used as additional
address inputs.
9.3.2. PSD8XXF Interface to a Non-Multiplexed 8-Bit Bus
Figure 16 shows an example of a system using a microcontroller with an 8-bit
non-multiplexed bus and a PSD8XXF. The address bus is connected to the ADIO Port,
and the data bus is connected to Port A. Port A is in tri-state mode when the PSD8XXF is
not accessed by the microcontroller. Should the system address bus exceed sixteen bits,
Ports B, C, or D may be used for additional address inputs.
42
Preliminary Information
PSD8XXF Family
The
Figure 15. An Example of a Typical 8-Bit Multiplexed Bus Interface
PSD8XXF
Functional
Blocks
(cont.)
43
PSD8XXF Family
Preliminary Information
The
Figure 16. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface
PSD8XXF
Functional
Blocks
(cont.)
44
Preliminary Information
PSD8XXF Family
9.3.3 Data Byte Enable Reference
The
Microcontrollers have different data byte orientations. The following table shows how the
PSD8XXF interprets byte/word operations in different bus write configurations. Even-byte
refers to locations with address A0 equal to zero and odd byte as locations with A0 equal
to one.
PSD8XXF
Functional
Blocks
(cont.)
Table 18. Eight-Bit Data Bus
BHE
A0
D7-D0
X
X
0
1
Even Byte
Odd Byte
9.3.4 Microcontroller Interface Examples
Figures 17 through 21 show examples of the basic connections between the PSD8XXF
and some popular microcontrollers. The PSD8XXF Control input pins are labeled as to the
microcontroller function for which they are configured. The MCU interface is specified using
the PSDsoft Configuration.
9.3.4.1 80C31
Figure 17 shows the interface to the 80C31, which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller control
signals PSEN, RD, and WR may be used for accessing the internal memory components
and I/O Ports. The ALE input (pin PD0) latches the address.
9.3.4.2 80C251
The Intel 80C251 microcontroller features a user-configurable bus interface with four
possible bus configurations, as shown in Table 19.
Configuration 1 is 80C31 compatible, and the bus interface to the PSD8XXF is identical to
that shown in Figure 17. Configurations 2 and 3 have the same bus connection as shown
in Figure 18. There is only one read input (PSEN) connected to the Cntl1 pin on the
PSD8XXF. The A16 connection to the PA0 pin allows for a larger address input to the
PSD8XXF. Configuration 4 is shown in Figure 19. The RD signal is connected to Cntl1 and
the PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In
Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in
every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus
cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0]
are changing. The PSD8XXF supports both modes. In Page Mode, the PSD bus timing
is identical to Non-Page Mode except the address hold time and setup time with respect
to ALE is not required. The PSD access time is measured from address A[7:0] valid to
data in valid.
45
PSD8XXF Family
Preliminary Information
The
Table 19. 80C251 Configurations
PSD8XXF
Functional
Blocks
(cont.)
Configuration
80C251
Read/Write
Pins
Connecting to
PSD8XXF
Pins
Page Mode
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31 compatible
A[7:0] multiplex with D[7:0}
1
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A[7:0] multiplex with D[7:0}
2
3
4
WR
PSEN only
CNTL0
CNTL1
Page Mode
A[15:8] multiplex with D[7:0}
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A[15:8] multiplex with D[7:0}
9.3.4.3 80C51XA
The Philips 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that
can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are
multiplexed with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed
with data bits D[7:0].
The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 20).
The 80C51XA improves bus throughput and performance by executing Burst cycles for
code fetches. In Burst Mode, address A19-4 are latched internally by the PSD8XXF, while
the 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access
time is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the normal bus cycle, except the address setup
and hold time with respect to ALE does not apply.
9.3.4.4 68HC11
Figure 21 shows an interface to a 68HC11 where the PSD8XXF1 is configured in 8-bit
multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR
signals for external devices.
46
Preliminary Information
PSD8XXF Family
Figure 17. Interfacing the PSD8XXF with an 80C31
[
]
AD 7:0
[
]
AD 7:0
PSD8XXF
80C31
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
29
28
27
25
24
23
22
21
30
31
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
31
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
EA/VP
X1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
32
33
34
35
36
37
19
18
9
X2
RESET
RESET
12
13
14
15
INT0
INT1
T0
21
22
23
24
25
26
27
28
A8
A9
39
40
41
42
43
44
45
46
7
6
5
4
3
2
52
51
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ADIO8
ADIO9
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A10
A11
A12
A13
A14
A15
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
T1
1
2
3
4
5
6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
17
16
RD
RD
WR
20
19
18
17
14
13
12
11
WR
47
50
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
CNTL0(WR)
CNTL1(RD)
7
8
29
30
11
10
PSEN
ALE
PSEN
ALE/P
TXD
49
CNTL2(PSEN)
10
9
RXD
PD0-ALE
PD1
8
PD2
RESET
48
RESET
RESET
Figure 18. Interfacing the PSD8XXF to the 80C251, with One Read Input
PSD8XXF
80C251SB
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
A6
A7
30
31
32
33
34
35
36
37
A0
A1
A2
A3
A4
A5
A6
A7
2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
**
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
A16
29
28
27
25
24
23
22
21
*
3
4
5
6
7
8
9
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
A17
*
A17
24
25
26
AD8
AD9
AD10
21
20
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
X1
X2
AD8
39
40
41
42
43
44
45
46
ADIO8
ADIO9
7
6
5
4
3
2
52
51
AD9
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
27
28
AD11
AD12
AD10
AD11
AD12
AD13
AD14
AD15
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
11
13
14
15
16
17
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
29
30
AD13
AD14
AD15
31
P2.7
ALE
RD
47
50
33
32
P3.5/T1
(
)
CNTL0 WR
ALE
10
RST
RESET
(
)
CNTL1 RD
PSEN
20
19
18
17
14
13
12
11
18
19
WR
A16
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
WR
RD/A16
35
49
CNTL2(PSEN)
EA
10
9
8
PD0-ALE
PD1
PD2
48
RESET
RESET
RESET
**Connection is optional.
**Non-page mode: AD[7:0] - ADIO[7:0].
47
PSD8XXF Family
Preliminary Information
Figure 19. Interfacing the PSD8XXF to the 80C251, with Read and PSEN Inputs
80C251SB
PSD8XXF
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
A6
A7
30
31
32
33
34
35
36
37
A0
A1
A2
A3
A4
A5
A6
A7
2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
29
3
4
5
6
7
8
9
PA0
28
PA1
27
PA2
25
PA3
24
PA4
23
PA5
22
PA6
21
PA7
24
25
26
AD8
AD9
AD10
21
20
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
X1
X2
AD8
39
40
41
42
43
44
45
46
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
7
AD9
PB0
6
27
28
AD11
AD12
AD10
AD11
AD12
AD13
AD14
AD15
PB1
5
11
13
14
15
16
17
PB2
4
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
29
30
AD13
AD14
PB3
3
PB4
2
AD15
31
PB5
52
P2.7
PB6
51
PB7
P3.5/T1
33
32
ALE
RD
47
50
(
)
CNTL0 WR
ALE
10
RST
EA
RESET
(
)
CNTL1 RD
PSEN
20
PC0
18
19
WR
19
WR
RD/A16
PC1
PSEN
35
49
18
17
14
13
12
11
CNTL2(PSEN)
PC2
PC3
PC4
PC5
PC6
PC7
10
9
8
PD0-ALE
PD1
PD2
48
RESET
RESET
RESET
Figure 20. Interfacing the PSD8XXF to the 80C51XA, 8-Bit Data Bus
80C51XA
PSD8XXF
21
20
30
31
32
33
34
35
36
37
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
2
3
4
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A15
A16
A17
A18
A19
XTAL1
XTAL2
ADIO0
A0/WRH
A1
29
A0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
PA0
PA1
28
27
25
24
23
22
21
A1
A2
A3
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
5
PA2
43
42
41
40
39
PA3
PA4
PA5
PA6
11
13
6
RXD0
TXD0
RXD1
TXD1
7
PA7
38
37
A12
A13
A14
A15
A16
A17
A18
A19
39
40
41
42
43
44
45
46
ADIO8
ADIO9
9
8
16
7
36
24
25
26
27
28
29
30
31
T2EX
T2
T0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
6
5
4
3
2
52
51
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
10
RST
INT0
INT1
RESET
14
15
47
50
(
)
CNTL0 WR
20
19
18
17
14
13
12
11
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
(
)
CNTL1 RD
PSEN
32
49
35
17
PSEN
RD
CNTL2(PSEN)
EA/WAIT
BUSW
19
18
33
RD
WR
10
8
9
PD0-ALE
PD1
WRL
ALE
ALE
PD2
48
RESET
RESET
48
Preliminary Information
PSD8XXF Family
Figure 21. Interfacing the PSD8XXF with a 68HC11
AD[7:0]
AD[7:0]
PSD8XXF
30
31
32
33
34
35
36
37
AD0
AD1
29
28
27
25
24
23
22
21
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
68HC11
AD2
AD3
AD4
AD5
AD6
AD7
31
PA3
PA4
PA5
PA6
PA7
8
7
30
29
28
27
XT
EX
17
19
18
RESET
RESET
IRQ
XIRQ
39
40
41
42
43
44
45
46
7
6
5
4
3
2
52
51
42
41
40
39
38
37
36
35
A8
A9
A10
A11
A12
A13
A14
A15
ADIO8
ADIO9
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
2
MODB
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
34
33
32
PA0
PA1
PA2
9
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
43
44
45
46
47
48
49
50
20
19
18
17
14
13
12
11
10
11
12
13
14
15
16
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PC0
PC1
PC2
PC3
PC4
47
50
_
CNTL0(R W)
CNTL1(E)
49
CNTL2
PC5
PC6
PC7
10
9
8
PD0 AS
–
PD1
PD2
20
21
22
23
24
25
52
51
PD0
PD1
PD2
PD3
PD4
PD5
VRH
VRL
48
RESET
3
MODA
5
4
6
E
E
AS
R/W
AS
R/W
RESET
49
PSD8XXF Family
Preliminary Information
The
9.4 I/O Ports
There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits
except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing
multiple functions per port. The ports are configured using PSDsoft Configuration or by the
microcontroller writing to on-chip registers in the CSIOP address space.
PSD8XXF
Functional
Blocks
(cont.)
The topics discussed in this section are:
• General Port Architecture
• Port Operating Modes
• Port Configuration Registers
• Port Data Registers
• Individual Port Functionality.
9.4.1 General Port Architecture
The general architecture of the I/O Port is shown in Figure 22. Individual Port architectures
are shown in Figures 24 through 27. In general, once the purpose for a port pin has been
defined, that pin will no longer be available for other purposes. Exceptions will be noted.
As shown in Figure 22, the ports contain an output multiplexer whose selects are driven
by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft
Configuration. Inputs to the multiplexer include the following:
❏ Output data from the Data Out Register
❏ Latched address outputs
❏ CPLD Micro Cell output
❏ External Chip Select from CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The PDB is connected to the Internal Data Bus for feedback and can be read by the
microcontroller. The Data Out and Micro Cell outputs, Direction and Control Registers,
and port pin input are all connected to the PDB.
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND array enable product term and the Direction Register. If
the enable product term of any of the array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDabel file, then the Direction Register has sole control
of the buffer that drives the port pin.
The contents of these registers can be altered by the microcontroller. The PDB feedback
path allows the microcontroller to check the contents of the registers.
Ports A, B, and C have embedded Input Micro Cells (IMCs). The IMCs can be configured
as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by
the address strobe (AS/ALE) or a product term from the PLD AND array. The outputs from
the IMCs drive the PLD input bus and can be read by the microcontroller. Refer to the IMC
subsection of the PLD section.
50
Preliminary Information
PSD8XXF Family
The
Figure 22. General I/O Port Architecture
PSD8XXF
Functional
Blocks
(cont.)
I N T E R N A L D A T A B U S
51
PSD8XXF Family
Preliminary Information
9.4.2 Port Operating Modes
The
The I/O Ports have several modes of operation. Some modes can be defined using
PSDabel, some by the microcontroller writing to the Control Registers in CSIOP space,
and some by both. The modes that can only be defined using PSDsoft must be
programmed into the device and cannot be changed unless the device is reprogrammed.
The modes that can be changed by the microcontroller can be done so dynamically at
run-time. The PLD I/O, Data Port, Address Input, and Peripheral I/O modes are the only
modes that must be defined before programming the device. All other modes can be
changed by the microcontroller at run-time. See Application Note 55 for more detail.
PSD8XXF
Functional
Blocks
(cont.)
Table 20 summarizes which modes are available on each port. Table 23 shows how and
where the different modes are configured. Each of the port operating modes are described
in the following subsections.
Table 20. Port Operating Modes
Port Mode
Port A
Port B
Port C
Port D
MCU I/O
PLD I/O
McellAB Outputs
McellBC Outputs
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
No
Yes
No
No
Additional Ext. CS Outputs No
Yes
Yes
PLD Inputs
Yes
Yes
Yes
Address Out
Yes (A7– 0) Yes (A7 – 0)
or A15 – 8)
No
No
Address In
Data Port
Yes
Yes
Yes
No
Yes
No
No
No
Yes (D7– 0) No
Peripheral I/O
JTAG ISP
Yes
No
No
No
No
Yes*
*Can be multiplexed with other I/O functions.
52
Preliminary Information
PSD8XXF Family
VM
The
Table 21. Port Operating Mode Settings
PSD8XXF
Functional
Blocks
(cont.)
Control Direction
Defined In
PSDabel
Defined In
PSDconfiguration Setting
Register Register Register JTAG
Mode
Setting
Setting Enable
1= output,
0 = input
(Note 1)
Declare
pins only
MCU I/O
NA*
NA
0
NA
NA
NA
NA
Logic
equations
NA
(Note 1)
PLD I/O
Data Port
(Port A)
NA
Specify bus type
NA
NA
1
NA
NA
NA
NA
NA
Address Out
(Port A,B)
Declare
pins only
1 (Note 1)
Logic equation
for Input
Micro Cells
Address In
(Port A,B,C,D)
NA
NA
NA
NA
NA
NA
NA
NA
NA
Peripheral I/O Logic equations
PIO bit =1
(Port A)
(PSEL0 & 1)
JTAG ISP
(Note 2)
JTAG_
Enable
JTAGSEL
JTAG Configuration
NA
NA
NA
*NA = Not Applicable
NOTE: 1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the
individual output enable product term (.oe) from the CPLD AND array.
2. Any of these three methods will enable JTAG pins on Port C.
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD8XXF ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD8XXF are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding
bit in the Direction Register, or by the output enable product term. See the subsection on
the Direction Register in the “Port Registers” section. When the pin is configured as an
output, the content of the Data Out Register drives the pin. When configured as an input,
the microcontroller can read the port input through the Data In buffer. See Figure 22.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if equation are written for them in PSDabel.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro Cells, and/or as an
output from the CPLD’s Output Micro Cells. The output can be tri-stated with a control
signal. This output enable control signal can be defined by a product term from the PLD, or
by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the
Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by declaring the port pins, and then writing an
equation assigning the PLD I/O to a port.
53
PSD8XXF Family
Preliminary Information
9.4.2.3 Address Out Mode
The
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a ‘1’ for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 22 for the address output pin assignments on
Ports A and B for various MCUs.
PSD8XXF
Functional
Blocks
(cont.)
For non-multiplexed 8 bit bus mode, address lines A[7:0] are available to Port B in
Address Out Mode.
Note: do not drive address lines with Address Out Mode to an external memory device if it
is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
Table 22. I/O Port Latched Address Output Assignments
Microcontroller
Port A (3:0) Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-Bit)
N/A*
N/A
Address (7:4) Address (11:8) N/A
N/A Address (11:8) Address (15:12)
80C251
(Page Mode)
All Other
8-Bit Multiplexed
Address (3:0) Address (7:4) Address (3:0)
N/A N/A Address [3:0]
Address (7:4)
Address [7:4]
8-Bit
Non-Multiplexed Bus
N/A = Not Applicable.
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Port A, B, C, and D. The address input can be latched in the Input
Micro Cell by the address strobe (ALE/AS). Any input that is included in the DPLD
equations for the Main Flash, Boot Flash, or SRAM is considered to be an address input.
9.4.2.5 Data Port Mode
Port A can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port A if the port is configured as a Data Port.
9.4.2.6 Peripheral I/O Mode
Peripheral I/O Mode can be used to interface with external peripherals. In this mode, all of
Port A serves as a tri-stateable, bi-directional data buffer for the microcontroller. Peripheral
I/O Mode is enabled by setting Bit 7 of the VM Register to a ‘1’. Figure 23 shows how Port
A acts as a bi-directional buffer for the microcontroller data bus if Peripheral I/O Mode is
enabled. An equation for PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is
tri-stated when PSEL 0 or 1 is not active.
9.4.2.7 JTAG ISP
Port C is JTAG compliant, and can be used for In-System Programming (ISP). You can
multiplex JTAG operations with other functions on Port C because ISP is not performed
during normal system operation. For more information on the JTAG Port, refer to
section 9.6.
54
Preliminary Information
PSD8XXF Family
The
Figure 23. Peripheral I/O Mode
PSD8XXF
Functional
Blocks
(cont.)
RD
PSEL0
PSEL
PSEL1
D0-D7
VM REGISTER BIT 7
PA0-PA7
DATA BUS
WR
9.4.3 Port Configuration Registers (PCRs)
Each port has a set of PCRs used for configuration. The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 7. The addresses in Table 7 are the offsets in hex from the base of the
CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
shown in Table 23, are used for setting the port configurations. The default power-up state
for each register in Table 23 is 00h.
Table 23. Port Configuration Registers
Register Name
Port
MCU Access
Control
A,B
Write/Read
Write/Read
Write/Read
Direction
Drive Select*
A,B,C,D
A,B,C,D
*NOTE: See Table 27 for Drive Register bit definition.
55
PSD8XXF Family
Preliminary Information
9.4.3.1 Control Register
The
Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,
and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B
have an associated Control Register.
PSD8XXF
Functional
Blocks
(cont.)
9.4.3.2 Direction Register
The Direction Register, in conjunction with the output enable (except for Port D), controls
the direction of data flow in the I/O Ports. Any bit set to ‘1’ in the Direction Register will
cause the corresponding pin to be an output, and any bit set to ‘0’ will cause it to be an
input. The default mode for all port pins is input.
Figures 24 and 26 show the Port Architecture diagrams for Ports A/B and C, respectively.
The direction of data flow for Ports A, B, and C are controlled not only by the direction
register, but also by the output enable product term from the PLD AND array. If the output
enable product term is not active, the Direction Register has sole control of a given pin’s
direction.
An example of a configuration for a port with the three least significant bits set to output
and the remainder set to input is shown in Table 26. Since Port D only contains three pins,
the Direction Register for Port D has only the three least significant bits active.
Table 24. Port Pin Direction Control,
Output Enable P.T. Not Defined
Direction Register Bit
Port Pin Mode
Input
0
1
Output
Table 25. Port Pin Direction Control, Output Enable P.T. Defined
Direction Register Bit
Output Enable P.T.
Port Pin Mode
Input
0
0
1
1
0
1
0
1
Output
Output
Output
Table 26. Port Direction Assignment Example
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
56
Preliminary Information
PSD8XXF Family
9.4.3.3 Drive Select Register
The
The Drive Select Register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should
be used for pins configured as Open Drain.
PSD8XXF
Functional
Blocks
(cont.)
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register
is set to a ‘1’. The default pin drive is CMOS.
Aside: the slew rate is a measurement of the rise and fall times of an output. A higher
slew rate means a faster output response and may create more electrical noise. A pin
operates in a high slew rate when the corresponding bit in the Drive Register is set to ‘1’.
The default rate is slow slew.
Table 27 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can
be configured as Open Drain outputs and which pins the slew rate can be set for.
Table 27. Drive Register Pin Assignment
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Port C
Port D
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
NA
NA
NA
NA
NA
NOTE: NA = Not Applicable.
57
PSD8XXF Family
Preliminary Information
The
9.4.4 Port Data Registers
The Port Data Registers, shown in Table 28, are used by the microcontroller to write data
to or read data from the ports. Table 28 shows the register name, the ports having each
register type, and microcontroller access for each register type. The registers are
described below.
PSD8XXF
Functional
Blocks
(cont.)
9.4.4.1 Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input
is read through the Data In buffer.
9.4.4.2 Data Out Register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
Register are driven out to the pins if the Direction Register or the output enable
product term is set to “1”. The contents of the register can also be read back by the
microcontroller.
9.4.4.3 Output Micro Cells (OMCs)
The CPLD OMCs occupy a location in the microcontroller’s address space. The
microcontroller can read the output of the OMCs. If the Mask Micro Cell Register bits are
not set, writing to the Micro Cell loads data to the Micro Cell flip flops. Refer to the PLD
section for more details.
9.4.4.4 Mask Micro Cell Register
Each Mask Register bit corresponds to an OMC flip flop. When the Mask Register bit
is set to a “1”, loading data into the OMC flip flop is blocked. The default value is “0” or
unblocked.
9.4.4.5 Input Micro Cells (IMCs)
The IMCs can be used to latch or store external inputs. The outputs of the IMCs
are routed to the PLD input bus, and can be read by the microcontroller. Refer to the PLD
section for a detailed description.
9.4.4.6 Enable Out
The Enable Out register can be read by the microcontroller. It contains the output enable
values for a given port. A “1” indicates the driver is in output mode. A “0” indicates the
driver is in tri-state and the pin is in input mode.
Table 28. Port Data Registers
Register Name
Port
MCU Access
Data In
A,B,C,D
A,B,C,D
A,B,C
Read – input on pin
Data Out
Write/Read
Output Micro Cell
Read – outputs of Micro Cells
Write – loading Micro Cells Flip-Flop
Mask Micro Cell
A,B,C
Write/Read – prevents loading into a given
Micro Cell
Input Micro Cell
Enable Out
A,B,C
A,B,C
Read – outputs of the Input Micro Cells
Read – the output enable control of the port driver
58
Preliminary Information
PSD8XXF Family
The
9.4.5 Ports A and B – Functionality and Structure
Ports A and B have similar functionality and structure, as shown in Figure 24. The two
ports can be configured to perform one or more of the following functions:
PSD8XXF
Functional
Blocks
(cont.)
❏ MCU I/O Mode
❏ CPLD Output – Micro Cells McellAB[7:0] can be connected to Port A or Port B.
McellBC[7:0] can be connected to Port B or Port C.
❏ CPLD Input – Via the input Micro Cells.
❏ Latched Address output – Provide latched address output per Table 30.
❏ Address In – Additional high address inputs using the Input Micro Cells.
❏ Open Drain/Slew Rate – pins PA[3:0] and PB[3:0] can be configured to fast slew rate,
pins PA[7:4] and PB[7:4] can be configured to Open Drain
Mode.
❏ Data Port – Port A to D[7:0] for 8 bit non-multiplexed bus
❏ Multiplexed Address/Data port for certain types of microcontroller interfaces.
❏ Peripheral Mode – Port A only
59
PSD8XXF Family
Preliminary Information
The
Figure 24. Ports A and B Structure
PSD8XXF
Functional
Blocks
(cont.)
I N T E R N A L D A T A B U S
60
Preliminary Information
PSD8XXF Family
The
9.4.6 Port C – Functionality and Structure
Port C can be configured to perform one or more of the following functions (see Figure 25):
PSD8XXF
Functional
Blocks
(cont.)
❏ MCU I/O Mode
❏ CPLD Output – McellBC[7:0] outputs can be connected to Port B or Port C.
❏ CPLD Input – via the Input Micro Cells
❏ Address In – Additional high address inputs using the Input Micro Cells.
❏ In-System Programming – JTAG port can be enabled for programming/erase of the
PSD8XXF device. (See Section 9.6 for more information on JTAG programming.)
❏ Open Drain – Port C pins can be configured in Open Drain Mode
❏ Battery Backup features – PC2 can be configured as a Battery Input (Vstby) pin.
PC4 can be configured as a Battery On Indicator output
pin, indicating when Vcc is less than Vbat.
Port C does not support Address Out mode, and therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in certain microcontroller interfaces.
9.4.7 Port D – Functionality and Structure
Port D has three I/O pins. See Figure 26. This port does not support Address Out mode,
and therefore no Control Register is required. Port D can be configured to perform one or
more of the following functions:
❏ MCU I/O Mode
❏ CPLD Output – (external chip select)
❏ CPLD Input – direct input to CPLD, no Input Micro Cells
❏ Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
❏ PD0 – ALE, as address strobe input
❏ PD1 – CLKIN, as clock input to the Micro Cells Flip Flops and APD counter
❏ PD2 – CSI, as active low chip select input. A high input will disable the
Flash/EEPROM/SRAM and CSIOP.
9.4.7.1 External Chip Select
The CPLD also provides three chip select outputs on Port D pins that can be used to
select external devices. Each chip select (ECS0-2) consists of one product term that can
be configured active high or low. The output enable of the pin is controlled by either the
output enable product term or the Direction Register. (See Figure 27.)
61
PSD8XXF Family
Preliminary Information
The
Figure 25. Port C Structure
PSD8XXF
Functional
Blocks
(cont.)
I N T E R N A L D A T A B U S
62
Preliminary Information
PSD8XXF Family
The
Figure 26. Port D Structure
PSD8XXF
Functional
Blocks
(cont.)
I N T E R N A L D A T A B U S
63
PSD8XXF Family
Preliminary Information
The
Figure 27. Port D External Chip Selects
PSD8XXF
Functional
Blocks
(cont.)
C P L D A N D A R R A Y
P L D I N P U T B U S
64
Preliminary Information
PSD8XXF Family
The
9.5 Power Management
The PSD8XXF offers configurable power saving options. These options may be used
individually or in combinations, as follows:
PSD8XXF
Functional
Blocks
(cont.)
❏ All memory types in a PSD (Flash, Flash Boot Block, and SRAM) are built with
Zero-Power technology. In addition to using special silicon design methodology,
Zero-Power technology puts the memories into standby mode when address/data
inputs are not changing (zero DC current). As soon as a transition occurs on an input,
the affected memory “wakes up”, changes and latches its outputs, then goes back to
standby. The designer does not have to do anything special to achieve memory
standby mode when no inputs are changing—it happens automatically.
The PLD sections can also achieve standby mode when its inputs are not changing,
see PMMR registers below.
❏ Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The APD will block MCU address/data signals
from reaching the memories and PLDs. This feature is available on all PSD8XXF
devices. The APD unit is described in more detail in section 9.5.1.
Built in logic will monitor the address strobe of the MCU for activity. If there is no
activity for a certain time period (MCU is asleep), the APD logic initiates Power Down
Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked
from reaching PSD memories and PLDs, and the memories are deselected internally.
This allows the memories and PLDs to remain in standby mode even if the
address/data lines are changing state externally (noise, other devices on the MCU
bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states
keeps the PLD out of standby mode, but not the memories.
❏ The PSD Chip Select Input (CSI) on all families can be used to disable the internal
memories, placing them in standby mode even if inputs are changing. This feature
does not block any internal signals or disable the PLDs. This is a good alternative to
using the APD logic, especially if your MCU has a chip select output. There is a slight
penalty in memory access time when the CSI signal makes its initial transition from
deselected to selected.
❏ The PMMR registers can be written by the MCU at run-time to manage power. All PSD
devices support “blocking bits” in these registers that are set to block designated
signals from reaching both PLDs. Current consumption of the PLDs is directly related
to the composite frequency of the changes on their inputs (see Figures 31 and 31a).
Significant power savings can be achieved by blocking signals that are not used in
DPLD or CPLD logic equations.
The PSD8XXF devices have a Turbo Bit in the PMMR0 register. This bit can be set to
disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is
disabled, the PLDs can achieve standby current when no PLD inputs are changing
(zero DC current). Even when inputs do change, significant power can be saved at
lower frequencies (AC current), compared to when Turbo Mode is enabled. Conversely,
when the Turbo Mode is enabled, there is a significant DC current component and the
AC component is higher.
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode
The APD Unit, shown in Figure 28, puts the PSD into Power Down Mode by monitoring
the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity
on the address strobe stops, a four bit counter starts counting. If the address strobe
remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN)
signal becomes active, and the PSD will enter into Power Down Mode, discussed next.
65
PSD8XXF Family
Preliminary Information
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)
Power Down Mode
The
PSD8XXF
Functional
Blocks
(cont.)
By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.
The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive
for fifteen CLKIN (pin PD1) clock periods.
The following should be kept in mind when the PSD is in Power Down Mode:
• If the address strobe starts pulsing again, the PSD will return to normal operation.
The PSD will also return to normal operation if either the CSI input returns low or the
Reset input returns high.
• The MCU address/data bus is blocked from all memories and PLDs.
• Various signals can be blocked (prior to Power Down Mode) from entering the PLDs
by setting the appropriate bits in the PMMR registers. The blocked signals include
MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from
the PLDs will not block CLKIN from the APD unit.
• All PSD memories enter Standby Mode and are drawing standby current. However,
the PLDs and I/O ports do not go into Standby Mode because you don’t want to
have to wait for the logic and I/O to “wake-up” before their outputs can change. See
table 29 for Power Down Mode effects on PSD ports.
• Typical standby current is 50 µA. This standby current value assumes that there are
no transitions on any PLD input.
Table 29. Power Down Mode’s Effect on
Ports
Port Function
MCU I/O
Pin Level
No Change
No Change
Undefined
PLD Out
Address Out
Data Port
Three-State
Three-State
Peripheral I/O
Table 30. PSD8XXF Timing and Standby Current During Power
Down Mode
Access
Recovery Time
to Normal
Access
5V V ,
CC
PLD
Propagation
Delay
Memory
Access
Time
Typical
Standby
Current
Mode
Normal tpd
(Note 1)
50 µA
(Note 2)
Power Down
No Access
tLVDV
NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this
mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and
the PLD Turbo bit is off.
HC11 (or compatible) Users Note
The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11
(or compatible) in your design, and you wish to use the Power Down, you must not
connect the E clock to the CLKIN input (PD1). You should instead connect an
independent clock signal to the CLKIN input. The clock frequency must be less than
15 times the frequency of AS. The reason for this is that if the frequency is greater than
15 times the frequency of AS, the PSD8XXF will keep going into Power Down Mode.
66
Preliminary Information
PSD8XXF Family
The
Figure 28. APD Logic Block
PSD8XXF
Functional
Blocks
(cont.)
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
PD
CLR
APD
BOOT SELECT
COUNTER
RESET
FLASH SELECT
EDGE
DETECT
PD
CSI
PLD
SRAM SELECT
POWER DOWN
CLKIN
(
)
PDN SELECT
DISABLE
FLASH/BOOT/SRAM
Figure 29. Enable Power Down Flow Chart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
ALE/AS idle
for 15 CLKIN
clocks?
No
Yes
PSD in Power
Down Mode
67
PSD8XXF Family
Preliminary Information
The
Table 31. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
PSD8XXF
Functional
Blocks
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLD
PLD
PLD
Turbo
APD
Enable
*
*
*
*
Mcell clk Array clk
1 = off 1 = off
1 = off
1 = on
***Bits 0, 2, 6, and 7 are not used, and should be set to 0.
***The PMMR0, and PMMR2 register bits are cleared to zero following power up.
***Subsequent reset pulses will not clear the registers.
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 5 0 = CLKIN input to the PLD Micro Cells is connected.
1 = CLKIN input to PLD Micro Cells is disconnected, saving power.
PMMR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLD
array
DBE
PLD
array
ALE
PLD**
array
CNTL2
PLD**
array
CNTL1
PLD**
array
CNTL0
*
*
*
1 = off
1 = off
1 = off
1 = off
1 = off
**Unused bits should be set to 0.
**Refer to Table 17 the signals that are blocked on pins CNTL0-2.
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
Bit 5 0 = ALE input to the PLD AND array is connected.
1 = ALE input to PLD AND array is disconnected, saving power.
Bit 6 0 = DBE input to the PLD AND array is connected.
1 = DBE input to PLD AND array is disconnected, saving power.
68
Preliminary Information
PSD8XXF Family
The
Table 32. APD Counter Operation
APD ALE
PSD8XXF
Functional
Blocks
(cont.)
Enable Bit PD Polarity ALE Level
APD Counter
0
1
1
1
X
X
1
0
X
Not Counting
Not Counting
Pulsing
1
0
Counting (Generates PDN after 15 Clocks)
Counting (Generates PDN after 15 Clocks)
9.5.2 Other Power Saving Options
The PSD8XXF offers other reduced power saving options that are independent of the
Power Down Mode. Except for the SRAM Standby and CSI input features, they are
enabled by setting bits in the PMMR0 and PMMR2 registers.
9.5.2.1 Zero Power PLD
The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0.
By setting the bit to “1”, the Turbo mode is disabled and the PLDs consume Zero Power
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time will be increased by 10 ns after the Turbo bit is set to “1” (turned off) when the
inputs change at a composite frequency of less than 15 MHz. When the Turbo bit is set to
a “0” (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s
D.C. power, AC power, and propagation delay.
Note: Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power
consumption.
9.5.2.2 SRAM Standby Mode (Battery Backup)
The PSD8XXF supports a battery backup operation that retains the contents of the SRAM
in the event of a power loss. The SRAM has a Vstby pin (PC2) that can be connected to
an external battery. When V becomes lower than Vstby then the PSD will automatically
CC
connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
typically 0.5 µA. The SRAM data retention voltage is 2 V minimum. The battery-on
indicator (Vbaton) can be routed to PC4. This signal indicates when the V has dropped
CC
below the Vstby voltage.
9.5.2.3 The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal
selects and enables the internal Flash, Boot Block, SRAM, and I/O for read or write
operations involving the PSD8XXF. A high on the CSI pin will disable the Flash memory,
Boot Block, and SRAM, and reduce the PSD power consumption. However, the PLD and
I/O pins remain operational when CSI is high. Note: there may be a timing penalty when
using the CSI pin depending on the speed grade of the PSD that you are using. See the
timing parameter t
in the AC/DC specs.
SLQV
9.5.2.4 Input Clock
The PSD8XXF provides the option to turn off the CLKIN input to the PLD to save AC
power consumption. The CLKIN is an input to the PLD AND array and the Output
Micro Cells. During Power Down Mode, or, if the CLKIN input is not being used as part of
the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be
disconnected from the PLD AND array or the Micro Cells by setting bits 4 or 5 to a “1” in
PMMR0.
9.5.2.5 Input Control Signals
The PSD8XXF provides the option to turn off the input control signals (CNTL0-2, ALE, and
DBE) to the PLD to save AC power consumption. These control signals are inputs to the
PLD AND array. During Power Down Mode, or, if any of them are not being used as part of
the PLD logic equation, these control signals should be disabled to save AC power. They
will be disconnected from the PLD AND array by setting bits 2, 3, 4, 5, and 6 to a “1” in the
PMMR2.
69
PSD8XXF Family
Preliminary Information
The
9.5.3 Reset and Power On Requirement
PSD8XXF
Functional
Blocks
(cont.)
9.5.3.1 Power On Reset
Upon power up the PSD8XXF requires a reset pulse of tNLNH-PO (minimum 1 ms) after
is steady. During this time period the device loads internal configurations, clears
V
CC
some of the registers and sets the Flash into operating mode. After the rising edge of
reset, the PSD8XXF remains in the reset state for an additional tOPR (minimum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD8XXF Flash memory is reset to the read array mode upon power up. The FSi
and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove
the possibility of a byte being written on the first edge of a write strobe signal. Any Flash
memory write cycle initiation is prevented automatically when V is below VLKO.
CC
9.5.3.2 Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 30 shows the timing of the power on and warm reset.
Figure 30. Power On and Warm Reset Timing
OPERATING LEVEL
t
NLNH
t
NLNH–PO
V
CC
RESET
t
t
OPR
OPR
WARM
RESET
POWER ON RESET
9.5.3.3 I/O Pin, Register and PLD Status at Reset
Table 33 shows the I/O pin, register and PLD status during power on reset, warm reset
and power down mode. PLD outputs are always valid during warm reset, and they are
valid in power on reset once the internal PSD configuration bits are loaded. This loading of
PSD is completed typically long before the V ramps up to operating level. Once the PLD
CC
is active, the state of the outputs are determined by the PSDabel equations.
70
Preliminary Information
PSD8XXF Family
The
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
PSD8XXF
Functional
Blocks
(cont.)
Port Configuration Power On Reset
Warm Reset
Input Mode
Valid
Power Down Mode
Unchanged
MCU I/O
Input Mode
PLD Output
Valid after internal
PSD configuration
bits are loaded
Depend on inputs to
PLD (address are
blocked in PD mode)
Address Out
Data Port
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Not defined
Tri-stated
Tri-stated
Peripheral I/O
Register
Power On Reset
Warm Reset
Power Down Mode
PMMR0, 2
Cleared to “0”
Unchanged
Unchanged
Micro Cells Flip
Flop status
Cleared to “0” by
internal power on
reset
Depend on .re and Depend on .re and
.pr equations .pr equations
VM Register*
Initialized based on
the selection in
PSDsoft
Initialized based on Unchanged
the selection in
PSDsoft
Configuration Menu.
Configuration Menu.
All other registers
Cleared to “0”
Cleared to “0”
Unchanged
*SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset.
**
9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD8X4F Only)
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 µs) time.
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD8XXF can be enabled on Port C (see Table 34). All
memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG interface. A blank part can be mounted on a printed circuit
board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See WSI Application Note 54 for more details on JTAG In-System-Programming.
Table 34. JTAG Port Signals
Port C Pin
PC0
JTAG Signals
TMS
Description
Mode Select
Clock
PC1
TCK
PC3
TSTAT
TERR
TDI
Status
PC4
Error Flag
PC5
Serial Data In
Serial Data Out
PC6
TDO
71
PSD8XXF Family
Preliminary Information
9.6.1 Standard JTAG Signals
The
The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three
different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are
inputs, waiting for a serial command from an external JTAG controller device (such as
FlashLink or Automated Test Equipment). When the enabling command is received from
the external JTAG controller, TDO becomes an output and the JTAG channel is fully
functional inside the PSD. The same command that enables the JTAG channel may
optionally enable the two additional JTAG pins, TSTAT and TERR.
PSD8XXF
Functional
Blocks
(cont.)
The following symbolic logic equation specifies the conditions enabling the four basic
JTAG pins (TMS, TCK, TDI, and TDO) on their respective Port C pins. For purposes of
discussion, the logic label JTAG_ON will be used. When JTAG_ON is true, the four pins
are enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD
I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the PSD is set by the designer
in the PSDsoft Configuration utility. This dedicates the pins for
JTAG at all times (compliant with IEEE 1149.1) */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-time by writing to the
PSD register, JTAG Enable. This register is located at address
CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this
register will enable the pins for JTAG use. This bit is cleared
by a PSD reset or the microcontroller. See Table 35 for bit
definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the PSD can be used to
enable the JTAG pins. This PT has the reserved name
JTAGSEL. Once defined as a node in PSDabel, the designer
can write an equation for JTAGSEL. This method is used when
the Port C JTAG pins are multiplexed with other I/O signals.
It is recommended to logically tie the node JTAGSEL to the
JEN\ signal on the Flashlink cable when multiplexing JTAG
signals. See Application Note 54 for details.
Table 35. JTAG Enable Register
JTAG Enable
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
JTAG_ENABLE
*
*
*
*
*
*
*
*Bits 1-7 are not used and should set to 0.
Bit definitions:
JTAG_ENABLE 1 = JTAG Port is Enabled.
0 = JTAG Port is Disabled.
NOTE:
The state of the PSD reset input signal will not interrupt (or prevent) JTAG operations if
the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft). However, the
PSD reset input will prevent or interrupt JTAG operations if the JTAG enable register is
used to enable the JTAG pins.
72
Preliminary Information
PSD8XXF Family
The
9.6.1 Standard JTAG Signals (cont.)
PSD8XXF
Functional
Blocks
(cont.)
The PSD8XXF supports JTAG In-System-Configuration (ISC) commands, but not
Boundary Scan. A definition of these JTAG-ISC commands and sequences are defined in
a supplemental document available from WSI. WSI’s PSDsoft software tool and FlashLink
JTAG programming cable implement these JTAG-ISC commands. This document is
needed only as a reference for designers who use a FlashLink to program their PSD8XXF.
9.6.2 JTAG Extensions
TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE”
command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They
are used to speed programming and erase functions by indicating status on PSD pins
instead of having to scan the status out serially using the standard JTAG channel. See
Application Note 54.
TERR will indicate if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal will go low (active) when an error condition occurs, and stay
low until an “ISC_CLEAR” command is executed or a chip reset pulse is received after an
“ISC-DISABLE” command.
TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will
be high when the PSD8XXF device is in read array mode (Flash memory and Boot Block
contents can be read). TSTAT will be low when Flash memory programming or erase
cycles are in progress, and also when data is being written to the Flash Boot Block.
TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE”
command. This facilitates a wired-OR connection of TSTAT signals from several PSD8XXF
devices and a wired-OR connection of TERR signals from those same devices. This is
useful when several PSD8XXF devices are “chained” together in a JTAG environment.
9.6.3 Security and Flash Memories Protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed.
All other program/erase/verify commands are blocked. Full chip erase returns the part to a
non-secured blank state. The Security Bit can be set in PSDsoft Configuration.
All Flash Memory and Boot sectors can individually be sector protected against erasures.
The sector protect bits can be set in PSDsoft Configuration.
73
PSD8XXF Family
Preliminary Information
Absolute
Maximum
Ratings
Symbol
Parameter
Storage Temperature
Condition
PLDCC
Min
– 65
0
Max
+ 125
+ 70
+ 85
+ 7
Unit
°C
°C
°C
V
T
STG
Commercial
Operating Temperature
Voltage on any Pin
Industrial
– 40
– 0.6
With Respect to GND
Device Programmer
Supply Voltage
V
V
With Respect to GND
With Respect to GND
– 0.6
+ 14
+ 7
V
PP
CC
Supply Voltage
ESD Protection
– 0.6
V
V
>2000
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not recommended. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Range
Temperature
V
Tolerance
CC
Commercial
Industrial
0° C to +70°C
–40° C to +85°C
0° C to +70°C
+ 5 V ± 10%
+ 5 V ± 10%
3.0 V to 3.6 V
3.0 V to 3.6 V
Commercial
Industrial
–40° C to +85°C
Recommended
Operating
Conditions
Symbol
Parameter
Condition
Min
Typ Max
Unit
V
V
Supply Voltage
Supply Voltage
All Speeds
4.5
5
5.5
3.6
V
CC
CC
V-Versions
All Speeds
3.0 V to 3.6 V
V
74
Preliminary Information
PSD8XXF Family
The following tables describe the AD/DC parameters of the PSD8XXF family:
AC/DC
Parameters
❏ DC Electrical Specification
❏ AC Timing Specification
• PLD Timing
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Micro Cell Timing
• Microcontroller Timing
– Read Timing
– Write Timing
– Peripheral Mode Timing
– Power Down and Reset Timing
Following are issues concerning the parameters presented:
❏ In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that
the PSD8XXF is in each mode. Also, the supply power is considerably different if the
Turbo bit is "OFF".
❏ The AC power component gives the PLD, Flash memory, and SRAM mA/MHz
specification. Figures 31 and 31a show the PLD mA/MHz as a function of the number
of Product Terms (PT) used.
❏ In the PLD timing parameters, add the required delay when Turbo bit is "OFF".
Figure 31. PLD ICC/FrequencyConsumption (VCC = 5 V ± 10%)
110
100
90
V
CC
= 5V
80
70
60
50
40
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
75
PSD8XXF Family
Preliminary Information
Figure 31a. PLD ICC/Frequency Consumption (PSD8XXFV Versions, VCC = 3 V)
AC/DC
Parameters
(cont.)
60
50
40
V
CC
= 3V
30
20
10
0
PT 100%
PT 25%
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
Example of PSD8XXF Typical Power Calculation at V = 5.0 V
CC
Conditions
Highest Composite PLD input frequency
(Freq PLD)
=
=
8 MHz
4 MHz
MCU ALE frequency (Freq ALE)
% Flash Access
% SRAM access
% I/O access
=
=
=
80%
15%
5% (no additional power above base)
Operational Modes
% Normal
=
=
10%
90%
% Power Down Mode
Number of product terms used
(from fitter report)
=
=
45 PT
45/182 = 24.7%
% of total product terms
Turbo Mode
=
ON
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400 µA/PT
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+2 mA/MHz x 8 MHz
+ 45 x 0.4 mA/PT)
= 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA)
= 45 µA + 0.1 x 42.9
= 45 µA + 4.29 mA
= 4.34 mA
This is the operating power with no Flash writes or erases. Calculation is based
on IOUT = 0 mA.
76
Preliminary Information
PSD8XXF Family
AC/DC
Example of Typical Power Calculation at V = 5.0 V in Turbo Off Mode
CC
Parameters
(cont.)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
=
=
8 MHz
MCU ALE frequency (Freq ALE)
4 MHz
% Flash Access
% SRAM access
% I/O access
=
=
=
80%
15%
5% (no additional power above base)
Operational Modes
% Normal
=
=
10%
90%
% Power Down Mode
Number of product terms used
(from fitter report)
=
=
45 PT
45/182 = 24.7%
% of total product terms
Turbo Mode
=
Off
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 24 mA)
= 45 µA + 0.1 x (8 + 0.9 + 24)
= 45 µA + 0.1 x 32.9
= 45 µA + 3.29 mA
= 3.34 mA
This is the operating power with no Flash writes or erases. Calculation is based
on IOUT = 0 mA.
77
PSD8XXF Family
Preliminary Information
PSD8XXF DC Characteristics (5 V ± 10% Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
VIH
Supply Voltage
All Speeds
4.5
5
5.5
VCC +.5
0.8
V
V
V
V
V
V
V
V
High Level Input Voltage
4.5 V < VCC < 5.5 V
4.5 V < VCC < 5.5 V
(Note 1)
2
–.5
VIL
Low Level Input Voltage
VIH1
VIL1
VHYS
VLKO
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
.8 VCC
–.5
VCC +.5
.2 VCC –.1
(Note 1)
0.3
VCC Min for Flash Erase and Program
2.5
4.2
0.1
I
OL = 20 µA, VCC = 4.5 V
IOL = 8 mA, VCC = 4.5 V
OH = –20 µA, VCC = 4.5 V
0.01
Output Low Voltage
VOL
0.25
4.49
0.45
V
V
I
4.4
VOH
Output High Voltage Except VSTBY On
IOH = –2 mA, VCC = 4.5 V
IOH1 = 1 µA
2.4
VSBY – 0.8
2.0
3.9
V
V
VOH
Output High Voltage VSTBY On
SRAM Standby Voltage
1
VSBY
ISBY
IIDLE
VDF
VCC
1
V
SRAM Standby Current (VSTBY Pin)
Idle Current (VSTBY Pin)
VCC = 0 V
0.5
µA
µA
V
VCC > VSBY
Only on VSTBY
–0.1
2
0.1
SRAM Data Retention Voltage
Standby Supply Current for Power
Down Mode
CSI > VCC –0.3 V
(Notes 2 and 3)
ISB
50
200
µA
ILI
Input Leakage Current
Output Leakage Current
VSS < VIN < VCC
0.45 < VIN < VCC
–1
±.1
±5
1
µA
µA
ILO
–10
10
ZPLD_TURBO = OFF,
f = 0 MHz (Note 5)
0
mA
ZPLD Only
ZPLD_TURBO = ON,
f = 0 MHz
400
700
µA/PT
ICC (DC)
(Note 5)
Operating Supply
Current
During Flash Write/Erase
Only
15
0
30
0
mA
mA
mA
Flash
Read Only, f = 0 MHz
f = 0 MHz
SRAM
0
0
Fig. 31
(Note 4)
ZPLD AC Adder
ICC (AC)
(Note 5)
FLASH AC Adder
SRAM AC Adder
2.5
1.5
3.5
3.0
mA/MHz
mA/MHz
NOTE: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC
2. CSI deselected or internal Power Down mode is active.
3. PLD is in non-turbo mode and none of the inputs are switching
4. Refer to Figure 32 for PLD current calculation.
.
5. IOUT = 0 mA
78
Preliminary Information
PSD8XXF Family
PSD8XXF AC/DC Parameters – CPLD Timing Parameters
(5 V ± 10% Versions)
CPLD Combinatorial Timing (5 V ± 10%)
-90
-15
Fast
PT
TURBO Slew
Symbol
tPD
Parameter
Conditions Min Max Min Max Aloc
OFF (Note 1) Unit
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
25
26
26
26
32
32
32
33
Add 2 Add 10 Sub 2
ns
ns
ns
ns
ns
ns
tEA
CPLD Input to CPLD
Output Enable
Add 10 Sub 2
Add 10 Sub 2
Add 10 Sub 2
Add 10
tER
CPLD Input to CPLD
Output Disable
tARP
tARPW
CPLD Register Clear or
Preset Delay
CPLD Register Clear or
Preset Pulse Width
20
29
Any
Micro Cell
tARD
CPLD Array Delay
16
22
Add 2
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
CPLD Micro Cell Synchronous Clock Mode Timing (5 V ± 10% Versions)
-90 -15
Fast
PT TURBO Slew
Symbol
Parameter
Conditions
Min Max Min Max Aloc
OFF (Note 1) Unit
Maximum Frequency
External Feedback
1/(tS +tCO
)
30.30
43.48
50.00
25.00
31.25
35.71
MHz
Maximum Frequency
Internal Feedback
fMAX
1/(tS +tCO–10)
MHz
MHz
(fCNT
)
Maximum Frequency
Pipelined Data
1/(tCH +tCL
)
tS
Input Setup Time
Input Hold Time
15
0
20
0
Add 2 Add 10
ns
ns
ns
ns
ns
ns
ns
tH
tCH
tCL
tCO
tARD
tMIN
Clock High Time
Clock Low Time
Clock Input
Clock Input
Clock Input
10
10
15
15
Clock to Output Delay
CPLD Array Delay
18
16
22
Sub 2
Any Micro Cell
22 Add 2
Minimum Clock Period tCH+tCL (Note 2)
20
30
NOTES: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
2. CLKIN tCLCL = tCH + tCL
.
79
PSD8XXF Family
Preliminary Information
PSD8XXF AC/DC Parameters – CPLD Timing Parameters
(5 V ± 10% Versions)
CPLD Micro Cell Asynchronous Clock Mode Timing (5 V ± 10% Versions)
-90
-15
PT TURBO Slew
Symbol
Parameter
Conditions
1/(tSA+tCOA
Min Max Min Max Aloc
OFF
Rate Unit
Maximum Frequency
External Feedback
)
26.32
35.71
41.67
21.27
27.78
35.71
MHz
Maximum Frequency
Internal Feedback
fMAXA
1/(tSA+tCOA–10)
MHz
MHz
(fCNTA
)
Maximum Frequency
Pipelined Data
1/(tCH A+tCLA
)
tSA
Input Setup Time
8
12
14
15
15
Add 2 Add 10
ns
ns
ns
ns
tHA
Input Hold Time
12
12
12
tCHA
tCLA
tCOA
tARDA
tMINA
Clock Input High Time
Clock Input Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
Add 10
Add 10
30
16
37
Add 10 Sub 2
ns
ns
ns
Any Micro Cell
1/fCNTA
22 Add 2
28
43
Input Micro Cell Timing (5 V ± 10% Versions)
-90
-15
PT TURBO
Min Max Min Max Aloc OFF
Symbol
Parameter
Conditions
Unit
tIS
Input Setup Time
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
0
0
ns
tIH
Input Hold Time
20
12
12
26
18
18
Add 10 ns
tINH
tINL
tINO
NIB Input High Time
NIB Input Low Time
NIB Input to Combinatorial Delay
ns
ns
46
59 Add 2 Add 10 ns
NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX
.
80
Preliminary Information
PSD8XXF Family
AC Symbols for PLD Timing.
Microcontroller
Interface –
AC/DC
Parameters
(5V ± 10% Versions)
Example: tAVLX – Time from Address Valid to ALE Invalid.
Signal Letters
A – Address Input
C – CEout Output
D – Input Data
E – E Input
G – Internal WDOG_ON signal
I
– Interrupt Input
L – ALE Input
N – Reset Input or Output
P – Port Signal Output
Q – Output Data
R – WR, UDS, LDS, DS, IORD, PSEN Inputs
S – Chip Select Input
T – R/W Input
W – Internal PDN Signal
B – Vstby Output
M – Output Micro Cell
Signal Behavior
t
– Time
L
H
V
X
Z
– Logic Level Low or ALE
– Logic Level High
– Valid
– No Longer a Valid Logic Level
– Float
PW – Pulse Width
81
PSD8XXF Family
Preliminary Information
Microcontroller Interface – PSD8XXF AC/DC Parameters
(5V ± 10% Versions)
Read Timing (5 V ± 10% Versions)
-90
-15
Turbo
Symbol
tLVLX
Parameter
Conditions
Min Max Min Max
Off
Unit
ns
ns
ns
ns
ns
ns
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
20
6
28
10
11
tAVLX
tLXAX
tAVQV
tSLQV
(Note 3)
(Note 3)
(Note 3)
8
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid 8-Bit Bus
90
100
32
150 Add 10
150
40
(Note 5)
(Note 2)
tRLQV
RD or PSEN to Data Valid 8-Bit Bus,
8-Bit Bus, 8031, 80251
38
45
30
ns
tRHQX
tRLRH
tRHQZ
tEHEL
tTHEH
tELTL
RD Data Hold Time
RD Pulse Width
(Note 1)
(Note 1)
(Note 1)
0
0
ns
ns
ns
ns
ns
ns
32
38
RD to Data High-Z
25
E Pulse Width
32
10
0
38
18
0
R/W Setup Time to Enable
R/W Hold Time After Enable
Address Input Valid to Address
Output Delay
tAVPV
(Note 4)
25
32
ns
NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD8XXF function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
82
Preliminary Information
PSD8XXF Family
Microcontroller Interface – PSD8XXF AC/DC Parameters
(5V ± 10% Versions)
Write Timing (5 V ± 10% Versions)
-90
-15
Symbol
tLVLX
Parameter
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Conditions
Min Max Min Max Unit
20
6
28
10
11
tAVLX
tLXAX
(Note 1)
(Note 1)
ns
ns
8
Address Valid to Leading
Edge of WR
tAVWL
(Notes 1 and 3)
15
20
ns
tSLWL
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
(Note 3)
(Note 3)
(Note 3)
(Note 3)
15
35
5
20
45
5
ns
ns
ns
ns
tDVWH
tWHDX
tWLWH
WR Pulse Width
35
45
Trailing Edge of WR to Address
Invalid
tWHAX1
tWHAX2
tWHPV
tWLMV
(Note 3)
(Note 3 and 6)
(Note 3)
8
0
10
0
ns
ns
ns
ns
Trailing Edge of WR to DPLD
Address Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
30
55
38
65
WR Valid to Port Output Valid Using
Micro Cell Register Preset/Clear
(Notes 3 and 4)
Data Valid to Port Output Valid
Using Micro Cell Register
Preset/Clear
tDVMV
(Notes 3 and 5)
(Note 2)
55
25
65
30
ns
ns
Address Input Valid to Address
Output Delay
tAVPV
NOTES: 1. Any input used to select an internal PSD8XXF function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
83
PSD8XXF Family
Preliminary Information
Microcontroller Interface – PSD8XXF AC/DC Parameters
(5V ± 10% Versions)
Port A Peripheral Data Mode Read Timing (5 V ± 10%)
-90
-15
Turbo
Off
Symbol
Parameter
Conditions
Min Max Min Max
Unit
tAVQV (PA)
tSLQV (PA)
Address Valid to Data Valid
CSI Valid to Data Valid
RD to Data Valid
(Note 3)
35
35
32
38
30
45
45
40
45
38
Add 10
Add 10
ns
ns
ns
ns
ns
ns
ns
ns
(Notes 1 and 4)
tRLQV (PA)
RD to Data Valid 8031 Mode
Data In to Data Out Valid
RD Data Hold Time
tDVQV (PA)
tQXRH (PA)
tRLRH (PA)
tRHQZ (PA)
0
0
RD Pulse Width
(Note 1)
(Note 1)
32
38
RD to Data High-Z
25
30
Port A Peripheral Data Mode Write Timing (5 V ± 10%)
-90
-15
Symbol
Parameter
Conditions
Min Max Min Max Unit
tWLQV (PA)
tDVQV (PA)
tWHQZ (PA)
WR to Data Propagation Delay
Data to Port A Data Propagation Delay
WR Invalid to Port A Tri-state
(Note 2)
(Note 5)
(Note 2)
35
30
25
40
38
33
ns
ns
ns
NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.
2. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral Mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
84
Preliminary Information
PSD8XXF Family
Microcontroller Interface – PSD8XXF AC/DC Parameters
(5V ± 10% Versions)
Power Down Timing (5 V ± 10%)
-90
-15
Symbol
Parameter
Conditions
Min Max
Min Max Unit
ALE Access Time from
Power Down
tLVDV
90
150
ns
µs
Maximum Delay from APD Enable
to Internal PDN Valid Signal
Using CLKIN Input
15 * tCLCL (Note 1)
tCLWH
NOTE: 1. tCLCL is the CLKIN clock period.
V
stbyon
Timing (5 V ± 10%)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
Vstby Detection to Vstbyon Output High
(Note 1)
20
µs
V
Off Detection to V
stbyon
stby
Output Low
tBXBL
(Note 1)
20
µs
NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.
Reset Pin Timing (5 V ± 10%)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tNLNH
Warm RESET Active Low Time (Note 1)
RESET High to Operational Device
Power On Reset Active Low Time
Warm Reset, will abort and reset Flash
150
ns
ns
tOPR
120
tNLNH-PO
1
ms
tNLNH-A
programming/erase cycles to Read mode.
For PSD8X4F only. (Note 2)
25
µs
NOTE: 1. RESET will not reset Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle.
85
PSD8XXF Family
Preliminary Information
Microcontroller Interface – PSD8XXF AC/DC Parameters
(5V ± 10% Versions)
Flash Program, Write and Erase Times (5 V ± 10%)
Symbol
Parameter
Flash Program
Min
Typ
Max
Unit
8.5
3
sec
sec
sec
sec
sec
µs
Flash Bulk Erase (Preprogrammed) (Note 1)
Flash Bulk Erase (Not Preprogrammed)
Sector Erase (Preprogrammed)
Sector Erase (Not Preprogrammed)
Byte Program
30
30
10
1
tWHQV3
tWHQV2
tWHQV1
2.2
14
1200
Program/Erase Cycles (Per Sector)
Sector Erase Time-Out
100,000
cycles
µs
tWHWLO
tQ7VQV
100
DQ7 Valid to Output (DQ7-0) Valid
(Data Polling) (Note 2)
30
ns
NOTE: 1. Programmed to all zeros before erase.
2. The polling status DQ7 is valid tQ7VQV ns before the data byte DQ0-7 is valid for reading.
ISC Timing (5 V ± 10%)
-90
-15
Symbol
Parameter
Conditions
Min Max
Min Max Unit
tISCCF
TCK Clock Frequency (except for PLD)
TCK Clock High Time
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
18
14
MHz
ns
tISCCH
26
26
2
31
31
tISCCL
TCK Clock Low Time
ns
tISCCF-P
tISCCH-P
tISCCL-P
tISCPSU
tISCPH
TCK Clock Frequency (for PLD only)
TCK Clock High Time(for PLD only)
TCK Clock Low Time(for PLD only)
ISC Port Set Up Time
2
MHz
ns
240
240
8
240
240
10
ns
ns
ISC Port Hold Up Time
5
5
ns
tISCPCO
tISCPZV
ISC Port Clock to Output
23
23
25
25
ns
ISC Port High-Impedance to Valid Output
ns
ISC Port Valid Output to
High-Impedance
tISCPVZ
23
25
ns
NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode.
2. For program or erase PLD only.
86
Preliminary Information
PSD8XXF Family
PSD813FV DC Characteristics (3.0 V to 3.6 V Versions) Advance Information
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
VIH
Supply Voltage
All Speeds
3.0
.7 VCC
–.5
3.6
VCC +.5
0.8
V
V
V
V
V
V
V
V
High Level Input Voltage
3.0 V < VCC < 3.6 V
3.0 V < VCC < 3.6 V
(Note 1)
VIL
Low Level Input Voltage
VIH1
VIL1
VHYS
VLKO
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
.8 VCC
–.5
VCC +.5
.2 VCC –.1
(Note 1)
0.3
VCC Min for Flash Erase and Program
1.5
2.2
0.1
I
OL = 20 µA, VCC = 3.0 V
IOL = 4 mA, VCC = 3.0 V
OH = –20 µA, VCC = 3.0 V
0.01
Output Low Voltage
VOL
0.15
2.99
0.45
V
V
I
2.9
VOH
Output High Voltage Except VSTBY On
IOH = –2 mA, VCC = 3.0 V
IOH1 = –1 µA
2.7
VSBY – 0.8
2.0
2.8
V
V
VOH
Output High Voltage VSTBY On
SRAM Standby Voltage
1
VSBY
ISBY
IIDLE
VDF
VCC
1
V
SRAM Standby Current (VSTBY Pin)
Idle Current (VSTBY Pin)
VCC = 0 V
0.5
µA
µA
V
VCC > VSBY
Only on VSTBY
–0.1
2
0.1
SRAM Data Retention Voltage
Standby Supply Current
for Power Down Mode
CSI >VCC –0.3 V
(Notes 2 and 3)
ISB
25
100
µA
ILI
Input Leakage Current
Output Leakage Current
VSS < VIN < VCC
0.45 < VIN < VCC
–1
±.1
±5
1
µA
µA
ILO
–10
10
ZPLD_TURBO = OFF,
f = 0 MHz (Note 3)
0
mA
µA/PT
mA
ZPLD Only
ZPLD_TURBO = ON,
f = 0 MHz
200
10
400
25
ICC (DC)
(Note 5)
Operating
Supply Current
FLASH
During FLASH or
EEPROM Write/Erase Only
Read Only, f = 0 MHz
f = 0 MHz
0
0
0
0
mA
mA
SRAM
ZPLD AC Adder
(Note 4)
Figure 31a
I
CC (AC)
FLASH
AC Adder
1.5
0.8
2.0
1.5
mA/MHz
mA/MHz
(Note 5)
SRAM AC Adder
NOTES: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC
2. CSI deselected or internal PD is active.
.
3. PLD is in non-turbo mode and none of the inputs are switching.
4. Refer to Figure 31a for PLD current calculation.
5. IOUT = 0 mA.
87
PSD8XXF Family
Preliminary Information
PSD8XXFV AC/DC Parameters – CPLD Timing Parameters
(3 V Versions)
CPLD Combinatorial Timing (3 V Versions)
-15
-20
Slew
PT
Min Max Min Max Aloc
TURBO Rate
Symbol
Parameter
Conditions
OFF (Note 1) Unit
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
tPD
45
45
45
43
50 Add 4 Add 20 Sub 6 ns
CPLD Input to CPLD Output
Enable
tEA
50
50
48
Add 20 Sub 6 ns
Add 20 Sub 6 ns
Add 20 Sub 6 ns
CPLD Input to CPLD Output
Disable
tER
CPLD Register Clear or
Preset Delay
tARP
CPLD Register Clear or
Preset Pulse Width
tARPW
tARD
30
35
Add 20
ns
ns
CPLD Array Delay
Any Micro Cell
29
33 Add 4
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
CPLD Micro Cell Synchronous Clock Mode Timing (3 V Versions)
-15
-20
Slew
TURBO Rate
OFF (Note 1) Unit
PT
Symbol
Parameter
Conditions
Min Max Min Max Aloc
Maximum Frequency
External Feedback
1/(tS+tCO
)
18.8
23.2
33.3
15.8
18.8
31.2
MHz
Maximum Frequency
Internal Feedback (fCNT
fMAX
1/(tS +tCO–10)
MHz
MHz
)
Maximum Frequency
Pipelined Data
1/(tCH+tCL
)
tS
Input Setup Time
Input Hold Time
25
0
30
0
Add 4 Add 20
ns
tH
ns
tCH
tCL
tCO
tARD
tMIN
Clock High Time
Clock Input
Clock Input
15
15
16
16
ns
Clock Low Time
ns
Sub 6 ns
ns
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
Clock Input
28
29
33
Any Micro Cell
33 Add 4
tCH+tCL(Note 2) 29
32
ns
NOTES: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
2. CLKIN tCLCL = tCH + tCL
.
88
Preliminary Information
PSD8XXF Family
PSD8XXFV AC/DC Parameters – CPLD Timing Parameters
(3 V Versions)
CPLD Micro Cell Asynchronous Clock Mode Timing (3 V Versions)
-15
-20
PT
Min Max Min Max Aloc
TURBO Slew
Symbol
Parameter
Conditions
OFF
Rate Unit
Maximum Frequency
External Feedback
1/(tSA+tCOA
)
19.2
23.8
27
16.9
20.4
24.4
MHz
Maximum Frequency
Internal Feedback (fCNTA
1/(tSA+tCOA–10)
1/(tCH A+tCLA
fMAXA
MHz
MHz
)
Maximum Frequency
Pipelined Data
)
tSA
Input Setup Time
Input Hold Time
12
15
22
15
13
17
25
16
Add 4 Add 20
ns
ns
ns
ns
tHA
tCHA
tCLA
tCOA
tARD
tMINA
Clock High Time
Add 20
Add 20
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
40
29
46
Add 20 Sub 6 ns
Any Micro Cell
1/fCNTA
33 Add 4
ns
ns
42
49
Input Micro Cell Timing (3 V Versions)
-15
-20
PT
TURBO
Symbol
Parameter
Conditions
Min Max Min Max
Aloc
OFF
Unit
tIS
Input Setup Time
Input Hold Time
(Note 1)
(Note 1)
(Note 1)
(Note 1)
0
0
ns
ns
ns
ns
tIH
25
13
13
30
15
15
Add 20
tINH
tINL
NIB Input High Time
NIB Input Low Time
NIB Input to Combinatorial
Delay
tINO
(Note 1)
62
70
Add 4
Add 20
ns
NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX
.
89
PSD8XXF Family
Preliminary Information
AC Symbols for PLD Timing.
Microcontroller
Interface –
PSD8XXFV
AC/DC
Example: tAVLX – Time from Address Valid to ALE Invalid.
Signal Letters
Parameters
(3 V Versions)
A – Address Input
C – CEout Output
D – Input Data
E – E Input
G – Internal WDOG_ON signal
I
– Interrupt Input
L – ALE Input
N – Reset Input or Output
P – Port Signal Output
Q – Output Data
R – WR, UDS, LDS, DS, IORD, PSEN Inputs
S – Chip Select Input
T – R/W Input
W – Internal PDN Signal
B – Vstby Output
M – Output Micro Cell
Signal Behavior
t
– Time
L
H
V
X
Z
– Logic Level Low or ALE
– Logic Level High
– Valid
– No Longer a Valid Logic Level
– Float
PW – Pulse Width
90
Preliminary Information
PSD8XXF Family
Microcontroller Interface – PSD8XXFV AC/DC Parameters
(3 V Versions)
Read Timing (3 V Versions)
-15
-20
Turbo
Symbol
tLVLX
Parameter
Conditions
Min Max Min Max
Off
Unit
ns
ns
ns
ns
ns
ns
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
26
10
12
30
12
14
tAVLX
tLXAX
tAVQV
tSLQV
(Note 3)
(Note 3)
(Note 3)
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid 8-Bit Bus
150
150
35
200 Add 20
200
40
(Note 5)
(Note 2)
(Note 1)
tRLQV
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251
50
55
45
ns
tRHQX
tRLRH
tRHQZ
tEHEL
tTHEH
tELTL
RD Data Hold Time
RD Pulse Width
0
0
ns
ns
ns
ns
ns
ns
40
45
RD to Data High-Z
(Note 1)
40
E Pulse Width
45
18
0
52
20
0
R/W Setup Time to Enable
R/W Hold Time After Enable
Address Input Valid to
Address Output Delay
tAVPV
(Note 4)
35
40
ns
NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD813F function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
91
PSD8XXF Family
Preliminary Information
Microcontroller Interface – PSD8XXFV AC/DC Parameters
(3 V Versions)
Write Timing (3 V Versions)
-15
-20
Symbol
tLVLX
Parameter
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Conditions
Min Max Min Max Unit
26
10
12
30
12
14
tAVLX
tLXAX
(Note 1)
(Note 1)
ns
ns
Address Valid to Leading
Edge of WR
tAVWL
(Notes 1 and 3)
20
25
ns
tSLWL
CS Valid to Leading Edge of WR
WR Data Setup Time
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
20
45
8
25
50
10
53
17
ns
ns
ns
ns
ns
tDVWH
tWHDX
tWLWH
tWHAX1
WR Data Hold Time
WR Pulse Width
48
12
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Input Invalid
tWHAX2
(Notes 3 and 6)
(Note 3)
0
0
ns
ns
ns
ns
ns
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
tWHPV
tWLMV
tDVMV
tAVPV
35
70
70
35
40
80
80
40
WR Valid to Port Output Valid Using
Micro Cell Register Preset/Clear
(Notes 3 and 4)
(Notes 3 and 5)
(Note 2)
Data Valid to Port Output Valid
Using Micro Cell Register Preset/Clear
Address Input Valid to Address
Output Delay
NOTES: 1. Any input used to select an internal PSD813F function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
92
Preliminary Information
PSD8XXF Family
Microcontroller Interface – PSD8XXFV AC/DC Parameters
(3 V Versions)
Port A Peripheral Data Mode Read Timing (3 V Versions)
-15
-20
Turbo
Off
Symbol
Parameter
Conditions
(Note 3)
Min Max Min Max
Unit
tAVQV (PA)
tSLQV (PA)
Address Valid to Data Valid
CSI Valid to Data Valid
RD to Data Valid
45
45
40
45
40
50 Add 20 ns
50 Add 20 ns
(Notes 1 and 4)
45
50
45
ns
ns
ns
ns
ns
ns
tRLQV (PA)
RD to Data Valid 8031 Mode
Data In to Data Out Valid
RD Data Hold Time
tDVQV (PA)
tQXRH (PA)
tRLRH (PA)
tRHQZ (PA)
0
0
RD Pulse Width
(Note 1)
(Note 1)
36
46
RD to Data High-Z
40
45
Port A Peripheral Data Mode Write Timing (3 V Versions)
-15
-20
Symbol
Parameter
Conditions
(Note 2)
Min Max Min Max Unit
tWLQV (PA)
WR to Data Propagation Delay
45
40
33
55
45
35
ns
ns
ns
Data to Port A Data Propagation
Delay
(Note 5)
(Note 2)
tDVQV (PA)
tWHQZ (PA)
WR Invalid to Port A Tri-state
NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.
2. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral Mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
93
PSD8XXF Family
Preliminary Information
Microcontroller Interface – PSD8XXFV AC/DC Parameters
(3 V Versions)
Power Down Timing (3 V Versions)
-15
-20
Symbol
Parameter
Conditions
Min Max
Min Max Unit
ALE Access Time from
Power Down
tLVDV
150
200
ns
µs
Maximum Delay from APD Enable
to Internal PDN Valid Signal
tCLWH
Using CLKIN Input
15 tCLCL (Note 1)
*
NOTE: 1. tCLCL is the CLKIN clock period.
V
stbyon
Timing (3 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
V
Detection to V
stbyon
Output
stby
(Note 1)
20
µs
High
tBXBL
V
Off Detection to V
stbyon
stby
(Note 1)
20
µs
Output Low
NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.
Reset Pin Timing (3 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tNLNH
Warm RESET Active Low Time (Note 1)
RESET High to Operational Device
Power On Reset Active Low Time
300
ns
ns
tOPR
300
tNLNH-PO
1
ms
Warm Reset, will abort and reset Flash
programming/erase cycles to Read
mode. For PSD8X4FV only.
tNLNH-A
25
µs
NOTE: 1. RESET will not reset Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle.
94
Preliminary Information
PSD8XXF Family
Microcontroller Interface – PSD8XXFV AC/DC Parameters
(3 V Versions)
Flash Program, Write and Erase Times (3 V Versions)
Symbol
Parameter
Flash Program
Min
Typ
Max
Unit
8.5
3
sec
sec
sec
sec
sec
µs
Flash Bulk Erase (Preprogrammed) (Note 1)
Flash Bulk Erase (Not Preprogrammed)
Sector Erase (Preprogrammed)
Sector Erase (Not Preprogrammed)
Byte Program
30
30
10
1
tWHQV3
tWHQV2
tWHQV1
2.2
14
1200
Program/Erase Cycles (Per Sector)
Sector Erase Time-Out
100,000
cycles
µs
tWHWLO
tQ7VQV
100
DQ7 Valid to Output (DQ7-0) Valid
(Data Polling) (Note 2)
30
ns
NOTES: 1. Programmed to all zeros before erase.
2. The polling status DQ7 is valid tQ7VQV ns before the data byte DQ0-7 is valid for reading.
ISC Timing (3 V Versions)
-15
-20
Symbol
Parameter
Conditions
Min Max
Min Max Unit
tISCCF
TCK Clock Frequency (except for PLD)
TCK Clock High Time
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
10
9
MHz
ns
tISCCH
45
45
2
51
51
tISCCL
TCK Clock Low Time
ns
tISCCF-P
tISCCH-P
tISCCL-P
tISCPSU
tISCPH
TCK Clock Frequency (for PLD only)
TCK Clock High Time (for PLD only)
TCK Clock Low Time (for PLD only)
ISC Port Set Up Time
2
MHz
ns
240
240
13
5
240
240
15
ns
ns
ISC Port Hold Up Time
5
ns
tISCPCO
tISCPZV
tISCPVZ
ISC Port Clock to Output
36
36
36
40
40
40
ns
ISC Port High-Impedance to Valid Output
ISC Port Valid Output to High-Impedance
ns
ns
NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode.
2. For program or erase PLD only.
95
PSD8XXF Family
Preliminary Information
Figure 32. Read Timing
t
t
AVLX
LXAX*
ALE/AS
t
LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
t
AVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
t
SLQV
CSI
t
t
RLQV
t
RHQX
RLRH
RD
(PSEN, DS)
tRHQZ
t
EHEL
E
t
THEH
t
ELTL
R/W
t
AVPV
ADDRESS OUT
*tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
96
Preliminary Information
PSD8XXF Family
Figure 33. Write Timing
t
t
LXAX
AVLX
ALE/AS
t
LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
t
AVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
t
SLWL
CSI
t
t
DVWH
WHDX
t
WR
WLWH
t
WHAX
(DS)
t
EHEL
E
t
t
THEH
ELTL
R/ W
t
WLMV
t
t
AVPV
WHPV
STANDARD
MCU I/O OUT
ADDRESS OUT
97
PSD8XXF Family
Preliminary Information
Figure 34. Peripheral I/O Read Timing
ALE/AS
ADDRESS
DATA VALID
A/D BUS
t
(PA)
(PA)
AVQV
t
SLQV
CSI
RD
t
t
(PA)
(PA)
RLQV
t
t
(PA)
(PA)
QXRH
RHQZ
RLRH
t
(PA)
DVQV
DATA ON PORT A
Figure 35. Peripheral I/O Write Timing
ALE/AS
ADDRESS
DATA OUT
A/D BUS
tWHQZ (PA)
tWLQV (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
98
Preliminary Information
PSD8XXF Family
Figure 36. Combinatorial Timing – PLD
CPLD INPUT
t
PD
CPLD
OUTPUT
Figure 37. Synchronous Clock Mode Timing – PLD
t
t
CL
CH
CLKIN
INPUT
t
S
t
H
t
CO
REGISTERED
OUTPUT
99
PSD8XXF Family
Preliminary Information
Figure38. Asynchronous Clock Mode Timing (Product-Term Clock)
tCHA
tCLA
CLOCK
INPUT
tSA
tHA
tCOA
REGISTERED
OUTPUT
Figure 39. Input Micro Cell Timing (Product-Term Clock)
t
t
INL
INH
PT CLOCK
t
t
IS
IH
INPUT
OUTPUT
t
INO
100
Preliminary Information
PSD8XXF Family
Figure 40. Input to Output Disable /Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
Figure 41. Asynchronous Reset /Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
Figure 42. ISC Timing
tISCCH
TCK
tISCCL
tISCPSU
tISCPH
TDI/TMS
t ISCPZV
tISCPCO
ISC OUTPUTS/TDO
tISCPVZ
ISC OUTPUTS/TDO
101
PSD8XXF Family
Preliminary Information
Figure 43. Reset Timing
OPERATING LEVEL
t
t
NLNH
NLNH-A
t
NLNH–PO
V
CC
RESET
t
t
OPR
OPR
WARM
RESET
POWER ON RESET
Figure 44. Key to Switching Waveforms
INPUTS
OUTPUTS
WAVEFORMS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
102
Preliminary Information
PSD8XXF Family
TA = 25 °C, f = 1 MHz
Pin Capacitance
Symbol
Parameter1
Conditions Typical2 Max Unit
CIN
Capacitance (for input pins only)
Capacitance (for input/output pins)
VIN = 0 V
VOUT = 0 V
VPP = 0 V
4
8
6
pF
pF
pF
COUT
CVPP
12
25
Capacitance (for CNTL2/VPP
)
18
NOTES: 1. These parameters are only sampled and are not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
Figure 45.
AC Testing
Input/Output
Waveform
3.0V
TEST POINT
1.5V
0V
Figure 46.
AC Testing
Load Circuit
2.01 V
195 Ω
DEVICE
UNDER TEST
CL = 30 pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
Upon delivery from WSI, the PSD8XXF device has all bits in the PLDs and memories in the
“1” or high state. The configuration bits are in the “0” or low state. The code, configuration,
and PLDs logic are loaded through the procedure of programming.
Programming
Information for programming the device is available directly from WSI. Please contact your
local sales representative. (See the last page.)
103
PSD8XXF Family
Preliminary Information
PSD8XXF
Pin
Assignments
52-Pin Plastic Leaded Chip Carrier (PLCC) (Package Type J)
Pin No.
Pin Assignments
Pin No.
Pin Assignments
1
GND
PB5
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PA2
PA1
2
3
PB4
PA0
4
PB3
AD0
5
PB2
AD1
6
PB1
AD2
7
PB0
AD3
8
PD2
AD4
9
PD1
AD5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PD0
AD6
PC7
AD7
PC6
VCC
PC5
AD8
PC4
AD9
VCC
AD10
AD11
AD12
AD13
AD14
AD15
CNTL0
RESET
CNTL2
CNTL1
PB7
GND
PC3
PC2 (VSTBY)
PC1
PC0
PA7
PA6
PA5
PA4
PA3
GND
PB6
104
Preliminary Information
PSD8XXF Family
PSD8XXF
Pin
Assignments
(cont.)
64-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U)
Pin No.
Pin Assignments
Pin No.
Pin Assignments
1
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
VCC
GND
GND
PC3
PC2
PC1
PC0
N/C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AD3
AD4
2
3
AD5
4
AD6
5
AD7
6
VCC
7
VCC
8
AD8
9
AD9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AD10
AD11
AD12
AD13
AD14
AD15
CNTL0
N/C
N/C
N/C
RESET
CNTL2
CNTL1
PB7
PA7
PA6
PA5
PA4
PA3
GND
GND
PA2
PA1
PA0
AD0
AD1
N/C
PB6
GND
GND
PB5
PB4
PB3
PB2
PB1
PB0
N/C
AD2
N/C
105
PSD8XXF Family
Preliminary Information
PSD8XXF
Pin
Assignments
(cont.)
52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
Pin No.
Pin Assignments
Pin No.
Pin Assignments
1
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
PA7
PA6
PA5
PA4
PA3
GND
PA2
PA1
PA0
AD0
AD1
AD2
AD3
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
AD4
AD5
2
3
AD6
4
AD7
5
VCC
AD8
6
7
AD9
8
AD10
AD11
AD12
AD13
AD14
AD15
CNTL0
RESET
CNTL2
CNTL1
PB7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PB6
GND
PB5
PB4
PB3
PB2
PB1
PB0
106
Preliminary Information
PSD8XXF Family
Figure 47. Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLCC)
(Package Type J)
PSD8XXF
Package
Information
7
6
5
4
3
2
52 51 50 49 48 47
1
8
PD2
PD1
46
45
AD15
9
AD14
AD13
AD12
10
11
12
13
14
15
16
17
18
PD0
PC7
44
43
PC6
PC5
PC4
42
41
40
39
38
37
36
35
34
AD11
AD10
AD9
AD8
V
CC
GND
PC3
V
CC
AD7
AD6
AD5
AD4
PC2 (VSTBY)
PC1
19
20
PC0
21 22 23 24 25 26 27 28 29 30 31 32 33
Figure 48. Drawing U4 – 64-Pin Plastic Thin Quad Flatpack (TQFP)
(Package Type U)
PD2
PD1
PD0
PC7
PC6
PC5
PC4
1
2
3
4
5
6
7
8
9
48 CNTL0
47 AD15
46 AD14
45 AD13
44 AD12
43 AD11
42 AD10
41 AD9
V
CC
V
40 AD8
CC
GND 10
GND 11
PC3 12
PC2 13
PC1 14
PC0 15
N/C 16
39 V
CC
38 V
CC
37 AD7
36 AD6
35 AD5
34 AD4
33 AD3
107
PSD8XXF Family
Preliminary Information
Figure 49. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP)
(Package Type M)
PSD8XXF
Package
Information
52 51 50 49 48 47 46 45 44 43 42 41 40
1
PD2
PD1
PD0
PC7
PC6
PC5
PC4
39
38
37
36
35
34
33
32
31
30
29
28
27
AD15
AD14
AD13
AD12
AD11
2
3
4
5
6
AD10
AD9
AD8
7
V
8
CC
V
GND
PC3
9
CC
10
11
12
AD7
AD6
AD5
AD4
PC2
PC1
PC0
13
14 15 16 17 18 19 20 21 22 23 24 25 26
108
Preliminary Information
PSD8XXF Family
Figure 47A.
Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J)
D
D1
3 2 1 52 51
E1
E
.025
.045
R
View A
C
B1
A2
View A
e1
B
D3
D2
E3
E2
A
A1
Family: Plastic Leaded Chip Carrier
Millimeters
Max
Inches
Symbol
A
Min
4.19
2.54
Notes
Min
Max
0.180
0.110
Notes
4.57
2.79
0.165
0.100
A1
A2
B
3.66
0.33
3.86
0.53
0.144
0.013
0.026
0.0097
0.785
0.750
0.690
0.152
0.021
0.032
0.0103
0.795
0.754
0.730
B1
C
0.66
0.81
0.246
19.94
19.05
17.53
0.261
20.19
19.15
18.54
D
D1
D2
D3
E
15.24
Reference
0.600
Reference
19.94
19.05
17.53
20.19
19.15
18.54
0.785
0.750
0.690
0.795
0.754
0.730
E1
E2
E3
e1
N
15.24
1.27
52
Reference
Reference
0.600
0.050
52
Reference
Reference
020197R1
109
PSD8XXF Family
Preliminary Information
Figure 48A.
Drawing U4 – 64-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U)
D
D1
D3
64
1
2
3
Index
Mark
E
E3
E1
Standoff: 0.05 mm Min.
C
A2
A
α
L
B
e1
Lead Coplanarity: 0.1mm Max.
Family: Plastic Thin Quad Flatpack (TQFP)
Millimeters
Inches
Symbol
Min
Max
Notes
Min
Max
Notes
α
0°
8°
0°
8°
A
–
1.60
1.45
–
0.063
0.057
0.016
0.007
0.632
0.553
A2
B
1.35
0.30
0.053
0.012
0.40
Reference
Reference
C
0.17
D
15.95
13.95
16.05
14.05
0.628
0.549
D1
D3
E
12.00
0.472
Reference
15.95
13.95
16.05
14.05
0.628
0.549
0.632
0.553
E1
E3
e1
L
12.00
0.80
Reference
Reference
0.472
0.031
Reference
Reference
0.50
0.75
0.019
0.030
N
64
64
060198R0
110
Preliminary Information
PSD8XXF Family
Figure 49A.
Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
D
D1
D3
52
1
2
3
Index
Mark
E
E3
E1
Standoff: 0.05 mm Min.
C
A2
A
α
L
B
e1
Lead Coplanarity: 0.1mm Max.
Family: Plastic Quad Flatpack (PQFP)
Millimeters
Max
Inches
Symbol
Min
Notes
Min
Max
Notes
α
0°
7°
0°
7°
A
–
2.35
2.10
–
0.093
0.083
0.015
0.009
0.522
0.396
A2
B
1.95
0.22
0.077
0.009
0.38
Reference
Reference
C
0.23
D
13.15
9.95
13.25
10.05
0.518
0.392
D1
D3
E
7.80
0.307
Reference
13.15
9.95
13.25
10.05
0.518
0.392
0.522
0.396
E1
E3
e1
L
7.80
0.65
Reference
Reference
0.307
0.026
Reference
Reference
0.73
1.03
0.029
0.041
N
52
52
060198R0
111
PSD8XXF Family
Preliminary Information
Selector Guide
112
Preliminary Information
PSD8XXF Family
Part Number
Construction
Flash PSD Part Number Construction
CHARACTER # 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PART
NUMBER
P
S
D
8
1
3
F
2
–
A
–
1
5
J
TEMP RANGE
"Blank" = 0°C to 70°C (Commercial)
PSD BRAND NAME
PSD = Standard Low
Power Device
+
+
I = –40°C to 85°C (Industrial)
FAMILY/SERIES
8 = Flash PSD for 8-bit MCUs
PACKAGE TYPE
J = PLCC
U = TQFP
M = PQFP
SRAM SIZE
0 = 0Kb
1 = 16Kb
2 = 32Kb
3 = 64Kb
SPEED
- 90 = 90ns
- 12 = 120ns
- 15 = 150ns
- 20 = 200ns
NVM SIZE
1 = 256Kb
2 = 512Kb
3 = 1Mb
REVISION
4 = 2Mb
"Blank" = no rev.
- A = Rev. A
- B = Rev. B
- C = Rev. C
I/O COUNT & OTHER
F = 27 I/O
G = 52 I/O
V
cc
VOLTAGE
2ND NVM TYPE, SIZE
& CONFIGURATION
"blank" = 5 Volt
V = 3.0 Volt
1 = EEPROM, 256Kb
2 = FLASH, 256Kb
3 = No 2nd Array
Ordering
Information
Operating
Temperature
Range
Speed
(ns)
Part Number
Package Type
PSD813F2-15J
PSD813F2-15JI
PSD813F2-15U
PSD813F2-15UI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F2-90J
PSD813F2-90U
90
90
52 Pin PLCC
64 Pin TQFP
Comm’l
Comm’l
PSD813F2-A-15J
PSD813F2-A-15JI
PSD813F2-A-15U
PSD813F2-A-15UI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F2-A-90J
PSD813F2-A-90JI
PSD813F2-A-90U
PSD813F2-A-90UI
90
90
90
90
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F2V-20J
PSD813F2V-20U
200
200
52 Pin PLCC
64 Pin TQFP
Comm’l
Comm’l
113
PSD8XXF Family
Preliminary Information
Ordering
Information
Operating
Temperature
Range
Speed
(ns)
Part Number
Package Type
PSD813F3-15J
PSD813F3-15JI
PSD813F3-15U
PSD813F3-15UI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F3-90J
PSD813F3-90U
90
90
52 Pin PLCC
64 Pin TQFP
Comm’l
Comm’l
PSD813F3-A-15J
PSD813F3-A-15JI
PSD813F3-A-15U
PSD813F3-A-15UI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F3-A-90J
PSD813F3-A-90JI
PSD813F3-A-90U
PSD813F3-A-90UI
90
90
90
90
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F3V-20J
PSD813F3V-20U
200
200
52 Pin PLCC
64 Pin TQFP
Comm’l
Comm’l
PSD813F4-15J
PSD813F4-15JI
PSD813F4-15U
PSD813F4-15UI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F4-90J
PSD813F4-90U
90
90
52 Pin PLCC
64 Pin TQFP
Comm’l
Comm’l
PSD813F4-A-15J
PSD813F4-A-15JI
PSD813F4-A-15U
PSD813F4-A-15UI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F4-A-90J
PSD813F4-A-90JI
PSD813F4-A-90U
PSD813F4-A-90UI
90
90
90
90
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F4V-20J
PSD813F4V-20U
200
200
52 Pin PLCC
64 Pin TQFP
Comm’l
Comm’l
114
Preliminary Information
PSD8XXF Family
Ordering
Information
Operating
Temperature
Range
Speed
(ns)
Part Number
Package Type
PSD813F5-15J
PSD813F5-15JI
PSD813F5-15U
PSD813F5-15UI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F5-90J
PSD813F5-90U
90
90
52 Pin PLCC
64 Pin TQFP
Comm’l
Comm’l
PSD813F5-A-15J
PSD813F5-A-15JI
PSD813F5-A-15U
PSD813F5-A-15UI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F5-A-90J
PSD813F5-A-90JI
PSD813F5-A-90U
PSD813F5-A-90UI
90
90
90
90
52 Pin PLCC
52 Pin PLCC
64 Pin TQFP
64 Pin TQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F5V-20J
PSD813F5V-20U
200
200
52 Pin PLCC
64 Pin TQFP
Comm’l
Comm’l
PSD833F2-15J
PSD833F2-15JI
PSD833F2-15M
PSD833F2-15MI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
52 Pin PQFP
52 Pin PQFP
Comm’l
Industrial
Comm’l
Industrial
PSD833F2-90J
PSD833F2-90M
90
90
52 Pin PLCC
52 Pin PQFP
Comm’l
Comm’l
PSD834F2-15J
PSD834F2-15JI
PSD834F2-15M
PSD834F2-15MI
150
150
150
150
52 Pin PLCC
52 Pin PLCC
52 Pin PQFP
52 Pin PQFP
Comm’l
Industrial
Comm’l
Industrial
PSD834F2-90J
PSD834F2-90M
90
90
52 Pin PLCC
52 Pin PQFP
Comm’l
Comm’l
115
PSD8XXF Family
Preliminary Information
Document
Revisions
Revision
Reason
Data Sheet
Changes
Date
15 Oct 99
PSD8XXF
–
Initial release
116
Preliminary Information
PSD8XXF Family
117
Waferscale Worldwide Sales, Service and Technical Support
KANSAS/NEBRASKA
Rush & West Associates
Tel: (913) 764-2700
Fax: (913) 764-0096
KENTUCKY
Victory Sales
Tel: (937) 436-1222
Fax: (937) 436-1224
PENNSYLVANIA
Victory Sales
Tel: (440) 498-7570
Fax: (440) 498-7574
BRAZIL
Colgil Comercial Ltda.
Tel: 011-55-11-3865-6001
Fax: 011-55-11-3666-9131
GERMANY
MEXICO
CompTech Sales
Tel: (915) 566-1022
REPRESENTATIVES
Atlantik Elektronik GmbH
Tel: 49-89-895050
Fax: 49-89-89505100
ALABAMA
Rep, Inc.
Tel: (256) 881-9270
Fax: (256) 882-6692
ARIZONA
Summit Sales
Tel: (480) 998-4850
Fax: (480) 998-5274
CALIFORNIA
SC Cubed
Fax: (52) 16-13-21-56
CHINA
BGR WYCK
Tel: (609) 727-1070
Fax: (609) 727-9633
PUERTO RICO
Waferscale Sales
Tel: (972) 418-2970
Fax: (972) 418-2971
SOUTH CAROLINA
Rep, Inc.
Tel: (919) 469-9997
Fax: (919) 481-3879
TENNESSEE
Rep, Inc.
Tel: (423) 475-9012
Fax: (423) 475-6340
Scantec GmbH
Tel: (49)-089 89 91 43-0
Fax: (49)-089 89 91 43-27
Tel: (52) 83-48-05-69
Fax: (52) 83-47-90-26
Lestina International Ltd.
Tel: 8610-849-9430/8888
Fax: 8610-849-9430
Tel: (52) 36-47-83-60
Fax: (52) 36-47-74-03
Topas Electronic GmbH
Tel: 49-511-968640
Fax: 49-511-9686464
GREECE
Radel S.A.
Tel: 301-921-3058
Fax: 301-924-2835
HONG KONG
Lestina International Ltd.
Tel: 852-2735-1736
Fax: 852-2730-5260
INDIA/PAKISTAN
Pamir Electronics Corp.
(USA Office)
MD/VA/DE/WV
Tel: 86811-531-5258
Fax: 86811-531-5258
Strategic Sales, Inc.
Tel: (410) 995-1900
Fax: (410) 964-3364
Tel: (52) 73-18-35-72
Fax: (52) 73-18-55-00
NETHERLANDS
Alcom Electronics bv
Tel: 31-10-288-2500
Fax: 31-10-288-2525
NEW ZEALAND
Apex Electronics
Tel: 644-3853404
Fax: 644-3853483
NORWAY
Henaco A/S
Tel: 47-22-917900
Fax: 47-22-917901
PHILIPPINES
In-Flux
Tel: 65-748-9959
Fax: 65-748-9979
REPUBLIC OF SOUTH
AFRICA
Components & System
Design
Tel: 2711-391-3062
Fax: 2711-391-5130
SINGAPORE
E-Smart Distribution
Pte, Ltd.
Tel: 65-299-7811
Fax: 65-294-1518
SPAIN, PORTUGAL
Matrix Electronica SL
Tel: 34-91-5602737
Fax: 34-91-5652863
Tel: 8620-380-7307/5688
Fax: 8620-380-7307
MASSACHUSETTS
Advanced Tech Sales, Inc.
Tel: (978) 664-0888
Fax: (978) 664-2526
MICHIGAN
Victory Sales
Tel: (313) 432-3151
Fax: (313) 432-3146
MINNESOTA
OHMS Technology, Inc.
Tel: (612) 932-2920
Fax: (612) 932-2918
Tel: (949) 598-3900
Fax: (949) 598-3918
Tel: 8625-449-1384
Fax: 8625-449-1384
Tel: (818) 865-6222
Fax: (818) 865-6223
P & S
Tel: (602) 633-0884
Fax: (602) 633-0885
Earle Assoc., Inc.
Tel: (619) 278-5441
Fax: (619) 278-5443
TEXAS
Tel: (86) 27 7493500/3506
Fax: (86) 27 7491166
CompTech Sales
Tel: (817) 640-8200
Fax: (817) 640-8204
RSVP Associates
Tel: (408) 467-1200
Fax: (408) 467-1250
Tel: 610-594-8337
Fax: 610-594-8559
Tel: (86) 10 62549897
Fax: (86) 10 62536518
UTAH
MISSOURI
Tel: (916) 567-0393
Fax: (916) 567-0393
Electrodyne, Inc.
Tel: (801) 264-8050
Fax: (801) 264-8065
In-Flux
Tel: 65-748-9959
Fax: 65-748-9979
INDONESIA
In-Flux
Tel: 65-748-9959
Fax: 65-748-9979
Rush & West Associates
Tel: (734) 965-3322
Fax: (734) 965-3529
Tel: (86) 21 64714208
Fax: (86) 21 64714208
Tel: (707) 586-1694
Fax: (707) 585-2617
CANADA
Intelatech, Inc.
WASHINGTON
I Squared, Inc.
Tel: (425) 822-9220
Fax: (425) 827-0350
WISCONSIN
Victory Sales
Tel: (86) 755 3245517
Fax: (86) 755 3353183
NEW JERSEY
Strategic Sales, Inc.
Tel: (201) 842-8960
Fax: (201) 842-0906
Tel: (86) 28 5575657
Fax: (86) 28 5563631
Tel: (905) 629-0082
Fax: (905) 629-1795
COLORADO
Waugaman Associates, Inc.
Tel: (303) 926-0002
Fax: (303) 926-0828
CONNECTICUT
Advanced Tech Sales
Tel: (203) 284-8247
Fax: (203) 284-8232
E-Smart Distribution
Pte, Ltd.
Tel: 65-299-7811
Fax: 65-294-1518
BGR WYCK
Tel: (856) 727-1070
Fax: (856) 727-9633
NEW MEXICO
Summit Sales
Tel: (480) 998-4850
Fax: (480) 998-5274
Tel: (86) 25 4508571
Fax: (86) 25 4526775
Tel: (414) 789-5770
Fax: (414) 789-5760
Tel: (852) 23142786
Fax: (852) 23142305
OHMS Technology, Inc.
Tel: (612) 932-2920
Fax: (612) 932-2918
WYOMING
Waugaman Associates,
Inc.
ISRAEL
Star-Tronics, Ltd.
Tel: 972-3-6960148
Fax: 972-3-6960255
Wuhan Liyuan Comp.
Tel: 86-27-7802986
Fax: 86-27-7802985
NEW YORK
ITALY
Strategic Sales, Inc.
Tel: (973) 237-9440
Fax: (973) 237-9445
FLORIDA
Comprel SPA
Tel: 39-3625781
Fax: 39-0362496800
DENMARK
Conley & Associates, Inc.
Tel: (407) 365-9347
Fax: (407) 365-1515
Tel: (303) 926-0002
Fax: (303) 926-0828
Jakob Hatteland A/S
Tel: 45-42-571000
Fax: 45-42-166199
SWEDEN
DipCom Electronics AB
Tel: 46-8-7522480
Fax: 46-8-7513649
Tri-Tech Electronics, Inc.
Tel: (716) 385-6500
Fax: (716) 385-7655
Silverstar
Tel: 39-2661251
Fax: 39-266101359
JAPAN
Internix, Inc.
DISTRIBUTORS
Arrow Electronics
Bell Micro Products
Wyle Electronics
Tel: (407) 365-3283
Fax: (407) 365-3727
EASTERN EUROPE
Elatec Vertriebs
Tel: 49-89-462-3070
Fax: 49-89-460-2403
ENGLAND
Micro Call, Ltd.
SWITZERLAND
Elbatex
Tel: 41-56-437-5111
Fax: 41-56-437-5188
Tel: (607) 722-3580
Fax: (607) 722-3774
NORTH CAROLINA
Rep, Inc.
Tel: (919) 469-9997
Fax: (919) 481-3879
OHIO
Victory Sales
Tel: (440) 498-7570
Fax: (440) 498-7574
Tel: (727) 572-8895
Fax: (727) 572-8896
GEORGIA
Rep, Inc.
Tel: (770) 938-4358
Fax: (770) 938-0194
IDAHO
Electrodyne, Inc.
Tel: (801) 264-8050
Fax: (801) 264-8065
ILLINOIS
Victory Sales
Tel: (630) 483-3417
Fax: (847) 963-2840
INDIANA
Victory Sales
Tel: (317) 581-0880
Fax: (317) 581-0882
IOWA
Zeus Electronics
Tel: 813-3-369-1105
Fax: 813-3-363-8486
WORLDWIDE
Laser & Electronic AG
Tel: 41-1-947-50-70
Fax: 41-1-947-50-80
TAlWAN
Ally, Inc.
Tel: 44-1296-330061
Fax: 44-1296-330065
Kyocera Corporation
Tel: 813-3-708-3111
Fax: 813-3-708-3372
AUSTRALIA
Zatek Components
Tel: 61-2-9-744-5711
Fax: 61-2-9-744-5527
Silicon Concepts, Ltd.
Tel: 44-1428-751-617
Fax: 44-1428-751-603
Nippon Imex Corporation
Tel: 813-3-321-8000
Fax: 813-3-325-0021
KOREA
Tel: 886-02-768-6399
Fax: 886-02-768-6390
Tel: 61-3-9574-9644
Fax: 61-3-9574-9661
AUSTRIA
Atlantic Elektronic GmbH
Tel: 43-1897-2637
Fax: 43-1897-2737
FINLAND
Tel: (937) 436-1222
Fax: (937) 436-1224
OKLAHOMA
CompTech
Tel: (918) 266-1966
Fax: (918) 266-1801
OREGON
I Squared, Inc.
Avnet Nortec OY
Tel: 358-0613181
Fax: 358-06922326
EPCO Technology Co. Ltd.
Tel: 886-02-8797-2627
Fax: 886-02-8797-2625
THAILAND
In-Flux
D & T
Tel: (822) 844-2668
Fax: (822) 844-2118
MALAYSIA
In-Flux
Tel: 65-748-9959
Fax: 65-748-9979
FRANCE
Microel
Tel: 33-1-69-07-08-24
Fax: 33-1-69-07-17-23
BELGIUM, LUX
Tel: 65-748-9959
Fax: 65-748-9979
Alcom Electronics nv/sa
Tel: 32-3-458-3033
Fax: 32-3-458-3126
Misil Technologies
Tel: 33-1-45-60-00-21
Fax: 33-1-45-60-01-86
Tel: (503) 670-0557
Fax: (503) 670-7646
E-Smart Distribution
Pte, Ltd.
Tel: 65-299-7811
Fax: 65-294-1518
Gassner & Clark Co.
Tel: (319) 393-5763
Fax: (319) 393-5799
E-Smart Distribution
Pte, Ltd.
Tel: 65-299-7811
Fax: 65-294-1518
REGIONAL SALES
EUROPE SALES
ASIA SALES
Northeast
Reading, MA
Tel: (781) 670-9313
Fax: (781) 670-9329
Midwest
Waferscale – Europe
2 Voie La Cardon
Waferscale – Taiwan
No. 31-5, Alley 65,
Lane 220, Sec. 2
Hsin-Long Road,
Taipei City,
Buffalo Grove, IL
Tel: (847) 215-2560
Fax: (847) 215-2702
91126 Palaiseau
Cedex, France
Tel: 33 (1) 69-32-01-20
Fax: 33 (1) 69-32-02-19
Corporate Headquarters
47280 Kato Road
Southeast
Dallas, TX
Tel: (972) 292-3285
Fax: (972) 292-3610
Western Area
Irvine, CA
Tel: (949) 453-5992
Fax: (949) 453-5995
Taiwan Roc
Tel: 886-2-8780-2340
Fax: 886-2-8780-6751
Fremont, California 94538-7333
Tel: 510-656-5400 Fax: 510-657-5916
800-TEAM-WSI (800-832-6974)
Web Site: http://www.waferscale.com
E-mail: info@waferscale.com
Waferscale – Asia, Ltd.
Korea Branch
Tel: 82-2-761-1281/2
Fax: 82-2-761-1283
Fremont, CA
Tel: (510) 498-1744
Fax: (510) 657-5916
4/10/00
118
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