PSD835G2-70UIT_技术文档

PSD835G2

Flash PSD, 5V Supply, for 8-bit MCUs

4 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

FEATURES SUMMARY

■

FLASH IN-SYSTEM PROGRAMMABLE (ISP)

PERIPHERAL FOR 8-BIT MCUS

Figure 1. Package

■

DUAL BANK FLASH MEMORIES

–

4 Mbits of Primary Flash Memory (8

uniform sectors, 64Kbyte)

256 Kbits of Secondary Flash Memory

with 4 sectors

Concurrent operation: READ from one

memory while erasing and writing the

other

■

64 KBIT OF BATTERY-BACKED SRAM

52 RECONFIGURABLE I/O PORTS

ENHANCED JTAG SERIAL PORT

PLD WITH MACROCELLS

TQFP80 (U)

–

Over 3000 Gates of PLD: CPLD and

DPLD

CPLD with 16 Output Macrocells (OMCs)

and 24 Input Macrocells (IMCs)

DPLD - user defined internal chip select

decoding

■

HIGH ENDURANCE:

–

100,000 Erase/WRITE Cycles of Flash

Memory

–

1,000 Erase/WRITE Cycles of PLD

15 Year Data Retention

■

52 INDIVIDUALLY CONFIGURABLE I/O

PORT PINS

They can be used for the following functions:

■

5V±10% SINGLE SUPPLY VOLTAGE

STANDBY CURRENT AS LOW AS 50µA

MEMORY SPEED

–

MCU I/Os

PLD I/Os

Latched MCU address output

Special function I/Os.

I/O ports may be configured as open-drain

outputs.

–

70ns Flash memory and SRAM access

time for V = 4.5V to 5.5V

CC

–

90ns Flash memory and SRAM access

time for V = 4.5V to 5.5V

CC

■

IN-SYSTEM PROGRAMMING (ISP) WITH

JTAG

–

Built-in JTAG compliant serial port allows

full-chip In-System Programmability

Efficient manufacturing allow easy

product testing and programming

Use low cost FlashLINK cable with PC

■

PAGE REGISTER

–

Internal page register that can be used to

expand the microcontroller address space

by a factor of 256

PROGRAMMABLE POWER MANAGEMENT

March 2004

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TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

First time programming.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Inventory build-up of pre-programmed devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Expensive sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Simultaneous READ and WRITE to Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Complex memory mapping.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Separate Program and Data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PSDsoft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. TQFP80 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. PSD Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2. PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. JTAG SIgnals on Port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

In-Application re-Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Methods of Programming Different Functional Blocks of the PSD . . . . . . . . . . . . . . . . . 17

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 4. PSDsoft Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PSD REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Register Address Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

REGISTER BIT DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Data-In Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Data-Out Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Direction Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Control Registers – Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Drive Registers – Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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Table 11. Drive Registers – Ports C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. Enable-Out Registers – Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. Input Macrocells – Ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 14. Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 15. Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 16. Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 17. Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 18. Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 19. Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 20. JTAG Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 21. Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 22. PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 23. PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 24. VM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 25. Memory_ID0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 26. Memory_ID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 27. Memory Block Size and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 25

Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Upper and Lower Block IN MAIN FLASH SECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5. Example for Flash Sector Chip Select FS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 6. Selecting the Upper or Lower Block in a Primary Flash Memory Sector. . . . . . . . . . . . . 26

Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 28. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Read the Erase/Program Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 29. Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Reset (RESET) Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 35

Figure 9. Priority Level of Memory and I/O Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 36

Separate Space Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 10.8031 Memory Modules – Separate Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11.8031 Memory Modules – Combined Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12.Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 30. DPLD and CPLD Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 13.PLD Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 14.DPLD Logic Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 15.Macrocell and I/O Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 31. Output Macrocell Port and Data Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 16.CPLD Output Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 17.Input Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 18.Handshaking Communication Using Input Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . 48

External Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 19.External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 32. MCUs and their Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 20.An Example of a Typical 8-bit Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . 51

PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 21.An Example of a Typical 8-bit Non-Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . 52

80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 22.Interfacing the PSD with an 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 33. 80C251 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 34. Interfacing the PSD with the 80C251, with One READ Input . . . . . . . . . . . . . . . . . . . . . 55

Figure 23.Interfacing the PSD with the 80C251, with RD and PSEN Inputs. . . . . . . . . . . . . . . . . . 56

80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 24.Interfacing the PSD with the 80C51X, 8-bit Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 25.Interfacing the PSD with a 68HC11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 26.General I/O Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 35. Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 36. Port Operating Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 37. I/O Port Latched Address Output Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 27.Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 38. Port Configuration Registers (PCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 39. Port Pin Direction Control, Output Enable P.T. Not Defined . . . . . . . . . . . . . . . . . . . . . . 64

Table 40. Port Pin Direction Control, Output Enable P.T. Defined . . . . . . . . . . . . . . . . . . . . . . . . . 64

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Table 41. Port Direction Assignment Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 42. Drive Register Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

OMC Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 43. Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Ports A,B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 28.Port A, B and C Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 29.Port D Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Port E – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Port G – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 30.Port E, F, G Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 44. Power-down Mode’s Effect on Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 31.APD Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 45. PSD Timing and Stand-by Current during Power-down Mode . . . . . . . . . . . . . . . . . . . . 71

Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

SRAM Standby Mode (Battery Backup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 32.Enable Power-down Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 46. APD Counter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Power-Up Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 33.Power-Up and Warm Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 47. Status During Power-Up Reset, Warm Reset and Power-down Mode . . . . . . . . . . . . . . 75

PROGRAMMING IN-CIRCUIT USING THE JTAG/ISP INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 76

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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Table 48. JTAG Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 34.PLD ICC /Frequency Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 49. Example of PSD Typical Power Calculation at V = 5.0V (with Turbo Mode On). . . . . 79

CC

Table 50. Example of PSD Typical Power Calculation at V = 5.0V (with Turbo Mode Off). . . . . 80

CC

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 51. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 52. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 53. AC Signal Letters for PLD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 54. AC Signal Behavior Symbols for PLD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 55. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 56. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 35.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 36.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 37.Switching Waveforms – Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 57. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 38.Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 39.Combinatorial Timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 58. CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 59. CPLD Macrocell Synchronous Clock Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 60. CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 40.Synchronous Clock Mode Timing – PLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 41.Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 42.Asynchronous Clock Mode Timing (Product Term Clock). . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 43.Input Macrocell Timing (Product Term Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 61. Input Macrocell Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 44.READ Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 62. READ Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 45.WRITE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 63. WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 46.Peripheral I/O Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 64. Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 47.Peripheral I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 65. Port F Peripheral Data Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 66. Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 67. Power-down Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 48.Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 68. Reset (Reset) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 69. V

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

STBYON

Figure 49.ISC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 70. ISC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 50.TQFP80 - 80 lead Thin, Quad, Flat Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 71. TQFP80 - 80 lead Thin, Quad, Flat Package Mechanical Data. . . . . . . . . . . . . . . . . . . . 98

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 72. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

APPENDIX A.PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 73. PSD835G2 TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 74. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8/102

PSD835G2

SUMMARY DESCRIPTION

The PSD family of memory systems for microcon-

trollers (MCUs) brings In-System-Programmability

(ISP) to Flash memory and programmable logic.

The result is a simple and flexible solution for em-

bedded designs. PSD devices combine many of

the peripheral functions found in MCU based ap-

plications.

The CPLD in the PSD devices features an opti-

mized macrocell logic architecture. The PSD mac-

rocell was created to address the unique

requirements of embedded system designs. It al-

lows direct connection between the system ad-

dress/data bus, and the internal PSD registers, to

simplify communication between the MCU and

other supporting devices.

In-Application Programming (IAP)

Two independent Flash memory arrays are includ-

ed so that the MCU can execute code from one

while erasing and programming the other. Robust

product firmware updates in the field are possible

over any communications channel (CAN, Ether-

net, UART, J1850, etc.) using this unique architec-

ture. Designers are relieved of these problems:

Simultaneous READ and WRITE to Flash mem-

ory. How can the MCU program the same memo-

ry from which it is executing code? It cannot. The

PSD allows the MCU to operate the two Flash

memory blocks concurrently, reading code from

one while erasing and programming the other dur-

ing IAP.

The PSD family offers two methods to program the

PSD Flash memory while the PSD is soldered to

the circuit board: In-System Programming (ISP)

via JTAG, and In-Application Programming (IAP).

Complex memory mapping. How can I map

these two memories efficiently? A programmable

Decode PLD (DPLD) is embedded in the PSD.

The concurrent PSD memories can be mapped

anywhere in MCU address space, segment by

segment with extremely high address resolution.

As an option, the secondary Flash memory can be

swapped out of the system memory map when

IAP is complete. A built-in page register breaks the

MCU address limit.

Separate Program and Data space. How can I

write to Flash memory while it resides in Program

space during field firmware updates? My 80C51

will not allow it. The PSD provides means to re-

classify Flash memory as Data space during IAP,

then back to Program space when complete.

In-System Programming (ISP) via JTAG

An IEEE 1149.1 compliant JTAG In-System Pro-

gramming (ISP) interface is included on the PSD

enabling the entire device (Flash memories, PLD,

configuration) to be rapidly programmed while sol-

dered to the circuit board. This requires no MCU

participation, which means the PSD can be pro-

grammed anytime, even when completely blank.

The innovative JTAG interface to Flash memories

is an industry first, solving key problems faced by

designers and manufacturing houses, such as:

First time programming. How do I get firmware

into the Flash memory the very first time? JTAG is

the answer. Program the blank PSD with no MCU

involvement.

Inventory build-up of pre-programmed devic-

es. How do I maintain an accurate count of pre-

programmed Flash memory and PLD devices

based on customer demand? How many and what

version? JTAG is the answer. Build your hardware

with blank PSDs soldered directly to the board and

then custom program just before they are shipped

to the customer. No more labels on chips, and no

more wasted inventory.

Expensive sockets. How do I eliminate the need

for expensive and unreliable sockets? JTAG is the

answer. Solder the PSD directly to the circuit

board. Program first time and subsequent times

with JTAG. No need to handle devices and bend

the fragile leads.

PSDsoft

PSDsoft, a software development tool from ST,

guides you through the design process step-by-

step making it possible to complete an embedded

MCU design capable of ISP/IAP in just hours. Se-

lect your MCU and PSDsoft takes you through the

remainder of the design with point and click entry,

covering PSD selection, pin definitions, program-

mable logic inputs and outputs, MCU memory map

definition, ANSI-C code generation for your MCU,

and merging your MCU firmware with the PSD de-

sign. When complete, two different device pro-

grammers are supported directly from PSDsoft:

FlashLINK (JTAG) and PSDpro.

9/102

PSD835G2

Figure 2. TQFP80 Connections

PD2

PD3

AD0

AD1

AD2

AD3

AD4

1

2

3

4

5

6

7

60 CNTL1

59 CNTL0

58 PA7

57 PA6

56 PA5

55 PA4

54 PA3

53 PA2

52 PA1

51 PA0

50 GND

49 GND

48 PC7

47 PC6

46 PC5

45 PC4

44 PC3

43 PC2

42 PC1

41 PC0

GND 8

V

9

CC

AD5 10

AD6 11

AD7 12

AD8 13

AD9 14

AD10 15

AD11 16

AD12 17

AD13 18

AD14 19

AD15 20

AI04943

10/102

PSD835G2

Table 1. Pin Description

Type

Description

Name

This is the lower Address/Data port. Connect your MCU address or address/data

bus according to the following rules:

If your MCU has a multiplexed address/data bus where the data is multiplexed with

the lower address bits, connect AD0-AD7 to this port.

If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this

port.

3-7-

10-12

ADIO0-7

I/O

If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this

port.

ALE or AS latches the address. The PSD drives data out only if the READ signal is

active and one of the PSD functional blocks was selected. The addresses on this

port are passed to the PLDs.

This is the upper Address/Data port. Connect your MCU address or address/data

bus according to the following rules:

If your MCU has a multiplexed address/data bus where the data is multiplexed with

the lower address bits, connect A8-A15 to this port.

If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this

port.

ADIO8-

15

13-20

I/O

If you are using an 80C251 in page mode, connect AD8-AD15 to this port.

If you are using an 80C51XA in burst mode, connect A12-A19 to this port.

ALE or AS latches the address. The PSD drives data out only if the READ signal is

active and one of the PSD functional blocks was selected. The addresses on this

port are passed to the PLDs.

The following control signals can be connected to this port, based on your MCU:

WR – active Low Write Strobe input.

CNTL0

59

I

R_W – active High READ/active Low WRITE input.

This port is connected to the PLDs. Therefore, these signals can be used in decode

and other logic equations.

The following control signals can be connected to this port, based on your MCU:

RD – active Low Read Strobe input.

E – E clock input.

DS – active Low Data Strobe input.

CNTL1

60

I

PSEN – connect PSEN to this port when it is being used as an active Low READ

signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is

actually the READ signal.

This port is connected to the PLDs. Therefore, these signals can be used in decode

and other logic equations.

This port can be used to input the PSEN (Program Select Enable) signal from any

MCU that uses this signal for code exclusively. If your MCU does not output a

Program Select Enable signal, this port can be used as a generic input. This port is

connected to the PLDs as input.

CNTL2

40

I

11/102

PSD835G2

Name

Type

Description

Active Low input. Resets I/O Ports, PLD macrocells and some of the Configuration

Registers and JTAG registers. Must be Low at Power-up. Reset also aborts the

Flash programming/erase cycle that is in progress.

Reset

39

I

These pins make up Port A. These port pins are configurable and can have the

following functions:

MCU I/O – write to or read from a standard output or input port.

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

58

57

56

55

54

53

52

51

I/O CMOS

or Open

Drain

CPLD macrocell (McellA0-7) outputs.

Inputs to the PLDs.

Latched, transparent or registered PLD input.

These pins make up Port B. These port pins are configurable and can have the

following functions:

MCU I/O – write to or read from a standard output or input port.

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

68

67

66

65

64

63

62

61

I/O CMOS

or Open

Drain

CPLD macrocell (McellB0-7) output.

Inputs to the PLDs.

Latched, transparent or registered PLD input.

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

48

47

46

45

44

43

42

41

These pins make up Port C. These port pins are configurable and can have the

following functions:

I/O CMOS MCU I/O – write to or read from a standard output or input port.

or Open

Drain

External Chip Select (ECS0-7) output.

Latched, transparent or registered PLD input.

PD0 pin of Port D. This port pin can be configured to have the following functions:

ALE/AS input latches addresses on ADIO0-ADIO15 pins.

I/O CMOS

or Open

Drain

AS input latches addresses on ADIO0-ADIO15 pins on the rising edge.

Input to the PLDs.

PD0

PD1

PD2

79

80

1

Transparent PLD input.

PD1 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

Input to the PLDs.

CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter,

and the CPLD AND Array.

PD2 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

Input to the PLDs.

PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory

and I/O. When High, the PSD memory blocks are disabled to conserve power. The

trailing edge of CSI can be used to get the PSD out of power-down mode.

12/102

PSD835G2

Name

Type

Description

PD3 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

PD3

PE0

2

Input to the PLDs.

PE0 pin of Port E. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

71

72

73

74

Latched address output.

TMS input for JTAG/ISP interface.

PE1 pin of Port E. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

PE1

PE2

PE3

Latched address output.

TCK input for JTAG/ISP interface (Schmidt Trigger).

PE2 pin of Port E. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

Latched address output.

TDI input for JTAG/ISP interface.

PE3 pin of Port E. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

Latched address output.

TDO input for JTAG/ISP interface.

PE4 pin of Port E. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

Latched address output.

PE4

75

TSTAT input for the ISP interface.

Ready/Busy for in-circuit Parallel Programming.

PE5 pin of Port E. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

PE5

PE6

76

77

Latched address output.

TERR active Low input for ISP interface.

PE6 pin of Port E. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

Latched address output.

V

STBY

SRAM standby voltage input for battery backup SRAM.

13/102

PSD835G2

Name

Type

Description

PE7 pin of Port E. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS

or Open

Drain

Latched address output.

PE7

78

V

battery backup indicator output. Goes High when power is drawn from an

BATON

external battery.

PF0 through PF7 pins of Port F. This port pins can be configured to have the

following functions:

MCU I/O – write to or read from a standard output or input port.

I/O CMOS Input to the PLDs.

or Open

PF0-PF7 31-38

Drain

Latched address outputs.

As address A0-A3 inputs in 80C51XA mode.

As data bus port (D07) in non-multiplexed bus configuration.

PG0 through PG7 pins of Port G. This port pins can be configured to have the

8, 30, I/O CMOS following functions:

PG0-

PG7

49,50,

or Open

MCU I/O – write to or read from a standard output or input port.

70

Drain

Latched address outputs.

9, 29,

69

V

Supply Voltage

Ground pins

CC

8, 30,

49,50,

70

GND

14/102

PSD835G2

Figure 3. PSD Block Diagram

AI05793b

15/102

PSD835G2

PSD ARCHITECTURAL OVERVIEW

PSD devices contain several major functional

blocks. Figure 3., page 15 shows the architecture

of the PSD device family. The functions of each

block are described briefly in the following sec-

tions. Many of the blocks perform multiple func-

tions and are user configurable.

and are differentiated by their output destinations,

number of product terms, and macrocells.

The PLDs consume minimal power by using Pow-

er-Management design techniques. The speed

and power consumption of the PLD is controlled

by the Turbo Bit in PMMR0 and other bits in the

PMMR2. These registers are set by the MCU at

run-time. There is a slight penalty to PLD propaga-

tion time when invoking the power management

features.

Memory

Each of the memory blocks is briefly discussed in

the following paragraphs. A more detailed discus-

sion can be found in the section entitled Memory

Blocks, page 24. The 4 Mbit (512K x 8) Flash

memory is the primary memory of the PSD. It is di-

vided into 8 equally-sized sectors that are individ-

ually selectable.

The 256 Kbit (32K x 8) secondary Flash memory

is divided into 4 equally-sized sectors. Each sector

is individually selectable.

I/O Ports

The PSD has 52 I/O pins distributed over the sev-

en ports (Port A, B, C, D, E, F and G). Each I/O pin

can be individually configured for different func-

tions. Ports can be configured as standard MCU I/

O ports, PLD I/O, or latched address outputs for

MCUs using multiplexed address/data buses.

The 64 Kbit SRAM is intended for use as a

scratch-pad memory or as an extension to the

MCU SRAM. If an external battery is connected to

The JTAG pins can be enabled on Port E for In-

System Programming (ISP). Ports F and G can

also be configured as data ports for a non-multi-

plexed bus.

Voltage Standby (V

, PC2), data is retained in

STBY

the event of power failure.

Ports A and B can also be configured as a data

port for a non-multiplexed bus.

MCU Bus Interface

PSD interfaces easily with most 8-bit MCUs that

have either multiplexed or non-multiplexed ad-

dress/data buses. The device is configured to re-

spond to the MCU’s control signals, which are also

used as inputs to the PLDs. For examples, please

see MCU Bus Interface Examples, page 52.

Each sector of memory can be located in a differ-

ent address space as defined by the user. The ac-

cess times for all memory types includes the

address latching and DPLD decoding time.

Page Register

The 8-bit Page Register expands the address

range of the MCU by up to 256 times. The paged

address can be used as part of the address space

to access external memory and peripherals, or in-

ternal memory and I/O. The Page Register can

also be used to change the address mapping of

sectors of the Flash memories into different mem-

ory spaces for IAP.

Table 2. PLD I/O

Product

Terms

Name

Inputs Outputs

PLDs

Decode PLD (DPLD)

Complex PLD (CPLD)

82

17

24

43

The device contains two PLDs, the Decode PLD

(DPLD) and the Complex PLD (CPLD), as shown

in Table 2, each optimized for a different function.

The functional partitioning of the PLDs reduces

power consumption, optimizes cost/performance,

and eases design entry.

The DPLD is used to decode addresses and to

generate Sector Select signals for the PSD inter-

nal memory and registers. The CPLD can imple-

ment user-defined logic functions. The DPLD has

combinatorial outputs. The CPLD has 16 Output

Macrocells (OMC) and 8 combinatorial outputs.

The PSD also has 24 Input Macrocells (IMC) that

can be configured as inputs to the PLDs. The

PLDs receive their inputs from the PLD Input Bus

150

Table 3. JTAG SIgnals on Port E

Port E Pins

PE0

JTAG Signal

TMS

TCK

PE1

PE2

TDI

PE3

TDO

TSTAT

TERR

PE4

PE5

16/102

PSD835G2

JTAG Port

Power Management Unit (PMU)

In-System Programming (ISP) can be performed

through the JTAG signals on Port E. This serial in-

terface allows complete programming of the entire

PSD device. A blank device can be completely

programmed. The JTAG signals (TMS, TCK,

TSTAT, TERR, TDI, TDO) can be multiplexed with

other functions on Port E. Table 3., page 16 indi-

cates the JTAG pin assignments.

The Power Management Unit (PMU) gives the

user control of the power consumption on selected

functional blocks based on system requirements.

The PMU includes an Automatic Power-down

(APD) Unit that turns off device functions during

MCU inactivity. The APD Unit has a Power-down

mode that helps reduce power consumption.

The PSD also has some bits that are configured at

run-time by the MCU to reduce power consump-

tion of the CPLD. The Turbo Bit in PMMR0 can be

reset to ’0’ and the CPLD latches its outputs and

goes to sleep until the next transition on its inputs.

In-System Programming (ISP)

Using the JTAG signals on Port E, the entire PSD

device (memory, logic, configuration) can be pro-

grammed or erased without the use of the MCU.

Additionally, bits in PMMR2 can be set by the

MCU to block signals from entering the CPLD to

reduce power consumption. Please see POWER

MANAGEMENT, page 70 for more details.

In-Application re-Programming (IAP)

The primary Flash memory can also be pro-

grammed in-system by the MCU executing the

programming algorithms out of the secondary

memory, or SRAM. Since this is a sizable separate

block, the application can also continue to operate.

The secondary memory can be programmed the

same way by executing out of the primary Flash

memory. The PLD or other PSD Configuration

blocks can be programmed through the JTAG port

or a device programmer. Table 4 indicates which

programming methods can program different func-

tional blocks of the PSD.

Table 4. Methods of Programming Different Functional Blocks of the PSD

Functional Block

Primary Flash Memory

JTAG/ISP

Device Programmer

IAP

Yes

No

Secondary Flash Memory

PLD Array (DPLD and CPLD)

PSD Configuration

No

17/102

PSD835G2

DEVELOPMENT SYSTEM

The PSD family is supported by PSDsoft, a Win-

dows-based (95, 98, NT) software development

tool. A PSD design is quickly and easily produced

in a point-and-click environment. The designer

does not need to enter Hardware Description Lan-

guage (HDL) equations, unless desired, to define

PSD pin functions and memory map information.

The general design flow is shown in Figure 4. PS-

Dsoft is available from our web site (the address is

given on the back page of this data sheet) or other

distribution channels.

PSDsoft directly supports two low cost device pro-

grammers form ST: PSDpro and FlashLINK

(JTAG). Both of these programmers may be pur-

chased through your local distributor/representa-

tive, or directly from our web site using a credit

card. The PSD is also supported by third party de-

vice programmers. See our web site for the current

list.

Figure 4. PSDsoft Development Tool

Choose MCU and PSD

Automatically Configures MCU

bus interface and other PSD

attributes.

Define PSD Pin and

Node Functions

Point-and-click definition of PSD

pin functions, internal nodes and

MCU system memory map

Define General Purpose

Logic in CPLD

C Code Generation

Point-and-click definition of

combinatorial and registered

logic in CPLD. Access to HDL is

available if needed.

GENERATE C CODE

SPECIFIC TO PSD

FUNCTIONS

Merge MCU Firmware

with PSD Configuration

USER'S CHOICE OF

MCU FIRMWARE

MICROCONTROLLER

A composite object file is created

containing MCU firmware and

PSD configuration

HEX OR S-RECORD

FORMAT

COMPILER/LINKER

*.OBJ FILE

ST PSD Programmer

*.OBJ

FILE AVAILABLE

FOR 3rd PARTY

PROGRAMMERS

(CONVENTIONAL or

JTAG/ISP)

PSDPro, or

FlashLINK (JTAG)

AI04918b

18/102

PSD835G2

PSD REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 5 shows the offset addresses to the PSD

registers relative to the CSIOP base address. The

CSIOP space is the 256 Bytes of address that is

allocated by the user to the internal PSD registers.

Table 5 provides brief descriptions of the registers

in CSIOP space. The following section gives a

more detailed description.

Table 5. Register Address Offset

Other

1

Port

A

Port

B

Port

C

Port

D

Port

E

Port

F

Port

G

Register Name

Description

Reads Port pin as input, MCU I/

O input mode

Data In

Control

00

01

10

11

30

32

34

36

40

42

44

46

41

43

45

47

Selects mode between MCU I/O

or Address Out

Stores data for output to Port

pins, MCU I/O output mode

Data Out

Direction

04

06

05

07

14

15

Configures Port pin as input or

output

Configures Port pins as either

CMOS or Open Drain on some

pins, while selecting high slew

rate on other pins.

Drive Select

08

09

18

19

38

48

49

Input Macrocell

Enable Out

0A

0C

0B

0D

1A

1B

Reads Input Macrocells

Reads the status of the output

enable to the I/O Port driver

1C

4C

READ – reads output of

macrocells A

WRITE – loads macrocell flip-

flops

Output

Macrocells A

20

READ – reads output of

macrocells B

WRITE – loads macrocell flip-

flops

Output

Macrocells B

21

23

Mask Macrocells

A

Blocks writing to the Output

Macrocells A

22

Mask Macrocells

B

Blocks writing to the Output

Macrocells B

Primary Flash

Protection

Read only – Primary Flash

Sector Protection

C0

C2

Secondary Flash

memory

Read only – PSD Security and

Secondary Flash memory

Sector Protection

Protection

JTAG Enable

PMMR0

PMMR2

Page

C7

B0

B4

E0

Enables JTAG Port

Power Management Register 0

Power Management Register 2

Page Register

Places PSD memory areas in

Program and/or Data space on

an individual basis.

VM

E2

Read only – Primary Flash

memory and SRAM size

Memory_ID0

Memory_ID1

F0

F1

Read only – Secondary Flash

memory type and size

Note: 1. Other registers that are not part of the I/O ports.

19/102

PSD835G2

REGISTER BIT DEFINITION

All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can

be found in the following sections.

Table 6. Data-In Registers – Ports A, B, C, D, E, F, G

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port pin 7

Port pin 6

Port pin 5

Port pin 4

Port pin 3

Port pin 2

Port pin 1

Port pin 0

Note: Bit Definitions (Read only registers):

Read Port pin status when Port is in MCU I/O input mode.

Table 7. Data-Out Registers – Ports A, B, C, D, E, F, G

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port pin 7

Port pin 6

Port pin 5

Port pin 4

Port pin 3

Port pin 2

Port pin 1

Port pin 0

Note: Bit Definitions:

Latched data for output to Port pin when pin is configured in MCU I/O output mode.

Table 8. Direction Registers – Ports A, B, C, D, E, F, G

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port pin 7

Port pin 6

Port pin 5

Port pin 4

Port pin 3

Port pin 2

Port pin 1

Port pin 0

Note: Bit Definitions:

Port pin 0 = Port pin is configured in Input mode (default).

Port pin 1 = Port pin is configured in Output mode.

Table 9. Control Registers – Ports E, F, G

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port pin 7

Port pin 6

Port pin 5

Port pin 4

Port pin 3

Port pin 2

Port pin 1

Port pin 0

Note: Bit Definitions:

Port pin 0 = Port pin is configured in MCU I/O mode (default).

Port pin 1 = Port pin is configured in Latched Address Out mode.

Table 10. Drive Registers – Ports A, B, D, E, G

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port pin 7

Port pin 6

Port pin 5

Port pin 4

Port pin 3

Port pin 2

Port pin 1

Port pin 0

Note: Bit Definitions:

Port pin 0 = Port pin is configured for CMOS Output driver (default).

Port pin 1 = Port pin is configured for Open Drain output driver.

Table 11. Drive Registers – Ports C, F

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port pin 7

Port pin 6

Port pin 5

Port pin 4

Port pin 3

Port pin 2

Port pin 1

Port pin 0

Note: Bit Definitions:

Port pin 0 = Port pin is configured for CMOS Output driver (default).

Port pin 1 = Port pin is configured in Slew Rate mode.

20/102

PSD835G2

Table 12. Enable-Out Registers – Ports A, B, C, F

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port pin 7

Port pin 6

Port pin 5

Port pin 4

Port pin 3

Port pin 2

Port pin 1

Port pin 0

Note: Bit Definitions (Read only registers):

Port pin 0 = Port pin is in tri-state driver (default).

Port pin 1 = Port pin is enabled.

Table 13. Input Macrocells – Ports A, B, C

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IMcell 7

IMcell 6

IMcell 5

IMcell 4

IMcell 3

IMcell 2

IMcell 1

IMcell 0

Note: Bit Definitions (Read only registers):

Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.

Table 14. Output Macrocells A Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mcella 7

Mcella 6

Mcella 5

Mcella 4

Mcella 3

Mcella 2

Mcella 1

Mcella 0

Note: Bit Definitions:

Write Register: Load MCellA7-MCellA0 with '0' or '1.'

Read Register: Read MCellA7-MCellA0 output status.

Table 15. Output Macrocells B Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mcellb 7

Mcellb 6

Mcellb 5

Mcellb 4

Mcellb 3

Mcellb 2

Mcellb 1

Mcellb 0

Note: Bit Definitions:

Write Register: Load MCellB7-MCellB0 with '0' or '1.'

Read Register: Read MCellB7-MCellB0 output status.

Table 16. Mask Macrocells A Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mcella 7

Mcella 6

Mcella 5

Mcella 4

Mcella 3

Mcella 2

Mcella 1

Mcella 0

Note: Bit Definitions:

McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).

McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.

Table 17. Mask Macrocells B Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mcellb 7

Mcellb 6

Mcellb 5

Mcellb 4

Mcellb 3

Mcellb 2

Mcellb 1

Mcellb 0

Note: Bit Definitions:

McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).

McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.

Table 18. Flash Memory Protection Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sec7_Prot

Sec6_Prot

Sec5_Prot

Sec4_Prot

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Note: Bit Definitions (Read only register):

Sec_Prot 1 = Primary Flash memory Sector is write protected.

Sec_Prot 0 = Primary Flash memory Sector is not write protected.

21/102

PSD835G2

Table 19. Flash Boot Protection Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Security_Bit not used

Note: Bit Definitions:

not used

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Sec_Prot 1 = Secondary Flash memory Sector is write protected.

Sec_Prot 0 = Secondary Flash memory Sector is not write protected.

Security_Bit 0 = Security Bit in device has not been set.

Security_Bit 1 = Security Bit in device has been set.

Table 20. JTAG Enable Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

not used

JTAGEnable

Note: Bit Definitions:

JTAG_Enable 1 = JTAG Port is enabled.

JTAG_Enable 0 = JTAG Port is disabled.

Table 21. Page Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PGR 7

PGR 6

PGR 5

PGR 4

PGR 3

PGR 2

PGR 1

PGR 0

Note: Bit Definitions:

Configure Page input to PLD. Default is PGR7-PGR0=00.

Table 22. PMMR0 Register

Bit 7

Bit 6

Bit 5

Bit 4

PLD

Bit 3

Bit 2

Bit 1

Bit 0

not used

PLD

not used

APD

not used

(set to ’0’)

MCells CLK Array CLK

Turbo

(set to ’0’)

Enable

(set to ’0’)

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.

2. Bit Definitions:

APD Enable0 = Automatic Power-down (APD) is disabled.

1 = Automatic Power-down (APD) is enabled.

PLD Turbo0 = PLD Turbo is on.

1 = PLD Turbo is off, saving power.

PLD Array CLK0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off.

1 = CLKIN to the PLD AND array is disconnected, saving power.

PLD MCells CLK0 = CLKIN to the PLD Macrocells is connected.

1 = CLKIN to the PLD Macrocells is disconnected, saving power.

Table 23. PMMR2 Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

not used

(set to ’0’)

PLD

Array WRH

PLD

Array ALE

PLD Array

CNTL2

PLD Array

CNTL1

PLD Array

CNTL0

not used

(set to ’0’)

PLD Array

Addr

Note: Bit Definitions:

PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.

1 = Address A7-A0 are blocked from the PLD array, saving power.

(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)

PLD Array CNTL20 = CNTL2 input to the PLD AND array is connected.

1 = CNTL2 input to the PLD AND array is disconnected, saving power.

PLD Array CNTL10 = CNTL1 input to the PLD AND array is connected.

1 = CNTL1 input to the PLD AND array is disconnected, saving power.

PLD Array CNTL00 = CNTL0 input to the PLD AND array is connected.

1 = CNTL0 input to the PLD AND array is disconnected, saving power.

PLD Array ALE 0 = ALE input to the PLD AND array is connected.

1 = ALE input to the PLD AND array is disconnected, saving power.

PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.

1 = WRH/DBE input to the PLD AND array is disconnected, saving power.

22/102

PSD835G2

Table 24. VM Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Peripheral

mode

not used

(set to ’0’)

not used

(set to ’0’)

FL_data

Boot_data

FL_code

Boot_code

SR_code

Note: 1. On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are always cleared on reset.

Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode.

2. Bit Definitions:

SR_code0 = PSEN cannot access SRAM in 80C51XA modes.

1 = PSEN can access SRAM in 80C51XA modes.

Boot_code0 = PSEN cannot access Secondary NVM in 80C51XA modes.

1 = PSEN can access Secondary NVM in 80C51XA modes.

FL_code0 = PSEN cannot access Primary Flash memory in 80C51XA modes.

1 = PSEN can access Primary Flash memory in 80C51XA modes.

Boot_data0 = RD cannot access Secondary NVM in 80C51XA modes.

1 = RD can access Secondary NVM in 80C51XA modes.

FL_data0 = RD cannot access Primary Flash memory in 80C51XA modes.

1 = RD can access Primary Flash memory in 80C51XA modes.

Peripheral mode0 = Peripheral mode of Port F is disabled.

1 = Peripheral mode of Port F is enabled.

Table 25. Memory_ID0 Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

S_size 3

S_size 2

S_size 1

S_size 0

F_size 3

F_size 2

F_size 1

F_size 0

Note: Bit Definitions:

F_size[3:0]

4h = Primary Flash memory size is 4 Mbit

5h = Primary Flash memory size is 8Mbit

0h = There is no SRAM

S_size[3:0]

1h = SRAM size is 16 Kbit

3h = SRAM size is 64 Kbit

Table 26. Memory_ID1 Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

not used

(set to ’0’)

not used

(set to ’0’)

B_type 1

B_type 0

B_size 3

B_size 2

B_size 1

B_size 0

Note: Bit Definitions:

B_size[3:0]

0h = There is no Secondary NVM

2h = Secondary NVM size is 256 Kbit

0h = Secondary NVM is Flash memory

1h = Secondary NVM is EEPROM

B_type[1:0]

23/102

PSD835G2

DETAILED OPERATION

As shown in Figure 3., page 15, the PSD consists

of six major types of functional blocks:

Memory Blocks

The PSD has the following memory blocks:

– Primary Flash memory

– Secondary Flash memory

– SRAM

■

Memory Blocks

PLD Blocks

MCU Bus Interface

I/O Ports

Power Management Unit (PMU)

JTAG/ISP Interface

The Memory Select signals for these blocks origi-

nate from the Decode PLD (DPLD) and are user-

defined in PSDsoft.

The functions of each block are described in the

following sections. Many of the blocks perform

multiple functions, and are user configurable.

Table 27. Memory Block Size and Organization

Primary Flash Memory

Secondary Flash Memory

SRAM

Sector

Number

Sector Size

(Bytes)

Sector Select

Signal

Sector Size

(Bytes)

Sector Select

Signal

SRAM Size

(Bytes)

SRAM Select

Signal

0

1

64K

512K

FS0

FS1

8K

CSBOOT0

CSBOOT1

CSBOOT2

CSBOOT3

16K

RS0

2

FS2

3

FS3

4

FS4

5

FS5

6

FS6

7

FS7

Total

8 Sectors

32K

4 Sectors

16K

24/102

PSD835G2

Primary Flash Memory and Secondary Flash

memory Description

Upper and Lower Block IN MAIN FLASH

SECTOR

The primary Flash memory is divided evenly into

eight equal sectors. The secondary Flash memory

is divided into four equal sectors of eight KBytes

each. Each sector of either memory block can be

separately protected from Program and Erase cy-

cles.

Flash memory may be erased on a sector-by-sec-

tor basis and programmed Word-by-Word. Flash

sector erasure may be suspended while data is

read from other sectors of the block and then re-

sumed after reading.

The PSD835G2’s main Flash memory has eight

64-KByte sectors. The 64-KByte sector size may

cause some difficulty in code mapping for an 8-bit

MCU with only 64-KByte address space. To re-

solve this mapping issue, the PSD835G2 provides

additional logic (see Figure 6., page 26) for the

user to split the 8 sectors such that each sector

has a lower and upper 32-KByte block, and the

two blocks can reside in different pages but in the

same address range.

If your design works with 64KB sectors, you don’t

need to configure this logic. If the design requires

32KB blocks in each sector, you need to define a

“FA15” PLD equation in PSDsoft as the A15 ad-

dress input to the main Flash module. FA15 con-

sists of 3 product terms and will control whether

the MCU is accessing the lower or upper 32KB in

the selected sector. Figure 4 shows an example

for Flash sector chip select FS0. A typical equation

is FA15 = pgr4 of the Page Register. When pgr4 is

0 (page 00), the lower 32KB is selected. When

pgr4 is switched to ’1’ by the user, the upper 32KB

is selected. PSDsoft will automatically generate

the PLD equations shown, based on your point

and click selections.

During a Program or Erase cycle in Flash memory,

the status can be output on Ready/Busy (PE4).

This pin is set up using PSDsoft.

Memory Block Select Signals

The DPLD generates the Select signals for all the

internal memory blocks (see PLDs, page 38).

Each of the eight sectors of the primary Flash

memory has a Select signal (FS0-FS7) which can

contain up to three product terms. Each of the four

sectors of the secondary Flash memory has a Se-

lect signal (CSBOOT0-CSBOOT3) which can con-

tain up to three product terms. Having three

product terms for each Select signal allows a given

sector to be mapped in different areas of system

memory. When using an MCU with separate Pro-

gram and Data space, these flexible Select signals

allow dynamic re-mapping of sectors from one

memory space to the other before and after IAP.

If no FA15 equation is defined in PSDsoft, the A15

that comes from the MCU address bus will be rout-

ed as input to the primary Flash memory instead of

FA15. The FA15 equation has no impact on the

Sector Erase operation.

Note: FA15 affects all eight sectors of the primary

Flash memory simultaneously. You cannot direct

FA15 to a particular Flash sector only.

Figure 5. Example for Flash Sector Chip Select FS0

page = [pgr7... pgr0]; “Page Register output

“Sector Chip Select Equation

FS0 = ((0000h <= address <= 7FFFh) & page = 00h) #

((0000h <= address <= 7FFFh) & page = 10h);

“select first 32KB block

“select second 32KB block

FA15 = pgr4;

“as address A15 input to the primary Flash memory

ai07652

25/102

PSD835G2

Figure 6. Selecting the Upper or Lower Block in a Primary Flash Memory Sector

FLASH MEMORY CHIP SELECT PINS FS0-FS7

DPLD

ARRAY

PRIMARY

FLASH

FA15

MEMORY

SECTOR

ADDR A15

MUX

A15

(1)

NVM CONTROL BIT

A14-A0

ai07653

Ready/Busy (PE4)

This signal can be used to output the Ready/Busy

status of the PSD. The output on Ready/Busy

(PE4) is a ’0’ (Busy) when Flash memory blocks

are being written to, or when the Flash memory

block is being erased. The output is a '1' (Ready)

when no WRITE or Erase cycle is in progress.

Typically, the MCU can read Flash memory using

READ operations, just as it would read a ROM de-

vice. However, Flash memory can only be altered

using specific Erase and Program instructions. For

example, the MCU cannot write a single byte di-

rectly to Flash memory as it would write a byte to

RAM. To program a byte into Flash memory, the

MCU must execute a Program instruction, then

test the status of the Program cycle. This status

test is achieved by a READ operation or polling

Ready/Busy (PE4).

Memory Operation

The primary Flash memory and secondary Flash

memory are addressed through the MCU Bus In-

terface. The MCU can access these memories in

one of two ways:

Flash memory can also be read by using special

instructions to retrieve particular Flash device in-

formation (sector protect status and ID).

–

The MCU can execute a typical bus WRITE or

READ operation just as it would if accessing a

RAM or ROM device using standard bus

cycles.

–

The MCU can execute a specific instruction

that consists of several WRITE and READ

operations. This involves writing specific data

patterns to special addresses within the Flash

memory to invoke an embedded algorithm.

These instructions are summarized in Table

Table 28., page 27.

26/102

PSD835G2

Table 28. Instructions

FS0-FS7 or

Instruction

CSBOOT0-

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5 Cycle 6 Cycle 7

CSBOOT3

“Read” RA

@ RD

(5)

1

Read

Read Primary

55h@

AAAh

90h@

555h

Read identifier

@X01h

AAh@ 555h

(6,13)

Flash ID

Read identifier

00h or 01h

@X02h

Read Sector

55h@

AAAh

90h@

555h

1

(6,8,13)

Protection

Program a Flash

55h@

AAAh

A0h@

555h

1

AAh@ 555h

PD@ PA

(13)

Byte

(7)

Flash Sector

55h@

AAAh

80h@

555h

55h@

AAAh

30h@

SA

30h

@

AAh@ 555h

(7)

Erase

next SA

55h@

AAAh

80h@

555h

55h@

AAAh

10h@

555h

Flash Bulk Erase

Suspend Sector

B0h@

XXXh

(11)

Erase

Resume Sector

1

30h@ XXXh

(12)

Erase

F0h@

any address

(6)

Reset

55h@

AAAh

20h@

555h

Unlock Bypass

AAh@ 555h

A0h@

XXXh

PD@ PA

(9)

Program

Unlock Bypass

00h@

XXXh

1

90h@ XXXh

(10)

Reset

Note: 1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label

2. All values are in hexadecimal:

X = Don’t Care.

RA = Address of the memory location to be read

RD = Data read from location RA during the READ cycle

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).

PA is an even address for PSD in word programming mode.

PD = Data to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)

SA = Address of the sector to be erased or verified. The Sector Select pins (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector or

whole memory to be erased, or verified, must be Active (High).

3. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft.

4. Only address Bits A11-A0 are used in instruction decoding. A15-A12 (or A16-A12) are don’t care.

5. No Unlock or instruction cycles are required when the device is in the READ mode

6. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector Protection Sta-

tus, or if the Error Flag Bit (DQ5/DQ13) goes High.

7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.

8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and

(A1,A0)=(1,0)

9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.

10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass

mode.

11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status

when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.

12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.

13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is

intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status

of the primary Flash memory.

27/102

PSD835G2

INSTRUCTIONS

An instruction consists of a sequence of specific

operations. Each received Byte is sequentially de-

coded by the PSD and not executed as a standard

WRITE operation. The instruction is executed

when the correct number of Bytes is properly re-

ceived and the time between two consecutive

Bytes is shorter than the time-out period. Some in-

structions are structured to include READ opera-

tions after the initial WRITE operations.

Power-up Mode

The PSD internal logic is reset upon Power-up to

the READ mode. Sector Select (FS0-FS7 and

CSBOOT0-CSBOOT3) must be held Low, and

Write Strobe (WR, CNTL0) High, during Power-up

for maximum security of the data contents and to

remove the possibility of a byte being written on

the first edge of Write Strobe (WR, CNTL0). Any

WRITE cycle initiation is locked when V

is be-

CC

The instruction must be followed exactly. Any in-

valid combination of instruction Bytes or time-out

between two consecutive bytes while addressing

Flash memory resets the device logic into READ

mode (Flash memory is read like a ROM device).

low V

READ

.

LKO

Under typical conditions, the MCU may read the

primary Flash memory or the secondary Flash

memory using READ operations just as it would a

ROM or RAM device. Alternately, the MCU may

use READ operations to obtain status information

about a Program or Erase cycle that is currently in

progress. Lastly, the MCU may use instructions to

read special data from these memory blocks. The

following sections describe these READ functions.

The PSD supports the instructions summarized in

Table 28., page 27:

Flash memory:

■

Erase memory by chip or sector

Suspend or resume sector erase

Program a Byte

Read Memory Contents

Reset to READ mode

Primary Flash memory and secondary Flash

memory are placed in the READ mode after Pow-

er-up, chip reset, or a Reset Flash instruction (see

Table 28). The MCU can read the memory con-

tents of the primary Flash memory or the second-

ary Flash memory by using READ operations any

time the READ operation is not part of an instruc-

tion.

Read primary Flash Identifier value

Read Sector Protection Status

Bypass

These instructions are detailed in Table 28. For ef-

ficient decoding of the instructions, the first two

Bytes of an instruction are the coded cycles and

are followed by an instruction Byte or a confirma-

tion Byte. The coded cycles consist in writing the

data AAh to address X555h during the first cycle

and data 55h to address XAAAh during the second

cycle unless the Bypass Instruction feature is

used). Address signals A15-A12 are Don’t Care

during the instruction WRITE cycles. However, the

Read Primary Flash Identifier

The primary Flash memory identifier is read with

an instruction composed of 4 operations: 3 specific

WRITE operations and a READ operation (see Ta-

ble 28., page 27). The identifier for the device is

E8h.

appropriate

CSBOOT0-CSBOOT3) must be selected.

Sector

Select

(FS0-FS7

or

Read Memory Sector Protection Status

The primary Flash memory Sector Protection Sta-

tus is read with an instruction composed of 4 oper-

ations: 3 specific WRITE operations and a READ

operation (see Table 28). The READ operation

produces 01h if the Flash memory sector is pro-

tected, or 00h if the sector is not protected.

The sector protection status for all NVM blocks

(primary Flash memory or secondary Flash mem-

ory) can also be read by the MCU accessing the

Flash Protection and Flash Boot Protection regis-

ters in PSD I/O space. See Flash Memory Sector

Protect, page 34 for register definitions.

The primary and secondary Flash memories have

the same instruction set (except for Read Primary

Flash Identifier). The Sector Select signals deter-

mine which Flash memory is to receive and exe-

cute the instruction. The primary Flash memory is

selected if any one of Sector Select (FS0-FS7) is

High, and the secondary Flash memory is selected

if any one of Sector Select (CSBOOT0-

CSBOOT3) is High.

28/102

PSD835G2

Read the Erase/Program Status Bits

The PSD provides several status bits to be used

by the MCU to confirm the completion of an Erase

or Program cycle of Flash memory. These status

bits minimize the time that the MCU spends per-

forming these tasks and are defined in Table 29.

The status bits can be read as many times as

needed.

For Flash memory, the MCU can perform a READ

operation to obtain these status bits while an

Erase or Program instruction is being executed by

the embedded algorithm. See PROGRAMMING

FLASH MEMORY, page 31 for details.

Table 29. Status Bit

FS0-FS7/CSBOOT0-

Functional Block

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

CSBOOT3

Erase

Time-

out

Data

Polling

Toggle Error

Flag Flag

V

Flash Memory

X

IH

Note: 1. X = Not guaranteed value, can be read either '1' or '0.'

2. DQ7-DQ0 represent the Data Bus Bits, D7-D0.

3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.

29/102

PSD835G2

Data Polling Flag (DQ7)

When erasing or programming in Flash memory,

the Data Polling Flag Bit (DQ7) outputs the com-

plement of the bit being entered for programming/

writing on the DQ7 Bit. Once the Program instruc-

tion or the WRITE operation is completed, the true

logic value is read on the Data Polling Flag Bit

(DQ7, in a READ operation).

–

The Toggle Flag Bit (DQ6) is effective after the

fourth WRITE pulse (for a Program instruction)

or after the sixth WRITE pulse (for an Erase

instruction).

If the Byte to be programmed belongs to a

protected Flash memory sector, the

instruction is ignored.

If all the Flash memory sectors selected for

erasure are protected, the Toggle Flag Bit

(DQ6) toggles to ’0’ for about 100µs and then

returns to the previous addressed Byte.

–

Data Polling is effective after the fourth WRITE

pulse (for a Program instruction) or after the

sixth WRITE pulse (for an Erase instruction). It

must be performed at the address being

programmed or at an address within the Flash

memory sector being erased.

Error Flag (DQ5)

During a normal Program or Erase cycle, the Error

Flag Bit (DQ5) is set to '0.' This bit is set to ’1’ when

there is a failure during Flash memory Byte Pro-

gram, Sector Erase, or Bulk Erase cycle.

In the case of Flash memory programming, the Er-

ror Flag Bit (DQ5) indicates the attempt to program

a Flash memory bit from the programmed state, 0,

to the erased state, 1, which is not valid. The Error

Flag Bit (DQ5) may also indicate a Time-out con-

dition while attempting to program a Byte.

In case of an error in a Flash memory Sector Erase

or Byte Program cycle, the Flash memory sector in

which the error occurred or to which the pro-

grammed Byte belongs must no longer be used.

Other Flash memory sectors may still be used.

The Error Flag Bit (DQ5) is reset after a Reset

Flash instruction.

–

During an Erase cycle, the Data Polling Flag

Bit (DQ7) outputs a '0.' After completion of the

cycle, the Data Polling Flag Bit (DQ7) outputs

the last bit programmed (it is a ’1’ after

erasing).

–

If the Byte to be programmed is in a protected

Flash memory sector, the instruction is

ignored.

If all the Flash memory sectors to be erased

are protected, the Data Polling Flag Bit (DQ7)

is reset to ’0’ for about 100µs, and then returns

to the previous addressed byte. No erasure is

performed.

Toggle Flag (DQ6)

The PSD offers another way for determining when

the Flash memory Program cycle is completed.

During the internal WRITE operation and when ei-

ther the FS0-FS7 or CSBOOT0-CSBOOT3 is true,

the Toggle Flag Bit (DQ6) toggles from '0' to '1' and

'1' to ’0’ on subsequent attempts to read any Byte

of the memory.

When the internal cycle is complete, the toggling

stops and the data read on the Data Bus D0-D7 is

the addressed memory Byte. The device is now

accessible for a new READ or WRITE operation.

The cycle is finished when two successive READs

yield the same output data.

Erase Time-out Flag (DQ3)

The Erase Time-out Flag Bit (DQ3) reflects the

time-out period allowed between two consecutive

Sector Erase instructions. The Erase Time-out

Flag Bit (DQ3) is reset to ’0’ after a Sector Erase

cycle for a time period of 100µs + 20% unless an

additional Sector Erase instruction is decoded. Af-

ter this time period, or when the additional Sector

Erase instruction is decoded, the Erase Time-out

Flag Bit (DQ3) is set to '1.'

30/102

PSD835G2

PROGRAMMING FLASH MEMORY

Flash memory must be erased prior to being pro-

grammed. The MCU may erase Flash memory all

at once or by-sector. A Flash memory sector is

erased to all 1s (FFh), and is programmed by set-

ting selected bits to '0.' Although Flash memory is

erased by-sector, it is programmed Word-by-

Word.

The primary and secondary Flash memories re-

quire the MCU to send an instruction to program a

Word or to erase sectors (see Table 28., page 27).

Once the MCU issues a Flash memory Program or

Erase instruction, it must check the status bits for

completion. The embedded algorithms that are in-

voked inside the PSD support several means to

provide status to the MCU. Status may be checked

using any of three methods: Data Polling, Data

Toggle, or the Ready/Busy (PE4) output pin.

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

ming algorithm has completed, to compare the

Byte that was written to the Flash memory with the

Byte that was intended to be written.

When using the Data Polling method after an

Erase cycle, Figure 7 still applies. However, the

Data Polling Flag Bit (DQ7) is '0' until the Erase cy-

cle is complete. A '1' on the Error Flag Bit (DQ5) in-

dicates a time-out condition on the Erase cycle; a

'0' indicates no error. The MCU can read any loca-

tion within the sector being erased to get the Data

Polling Flag Bit (DQ7) and the Error Flag Bit

(DQ5).

PSDsoft generates ANSI C code functions which

implement these Data Polling algorithms.

Data Polling

Figure 7. Data Polling Flowchart

Polling on the Data Polling Flag Bit (DQ7) is a

method of checking whether a Program or Erase

cycle is in progress or has completed. Figure 7

shows the Data Polling algorithm.

START

READ DQ5 & DQ7

at VALID ADDRESS

When the MCU issues a Program instruction, the

embedded algorithm within the PSD begins. The

MCU then reads the location of the Word to be

programmed in Flash memory to check status.

The Data Polling Flag Bit (DQ7) of this location be-

comes the complement of b7 of the original data

byte to be programmed. The MCU continues to

poll this location, comparing the Data Polling Flag

Bit (DQ7) and monitoring the Error Flag Bit (DQ5).

When the Data Polling Flag Bit (DQ7) matches b7

of the original data, and the Error Flag Bit (DQ5)

remains '0,' the embedded algorithm is complete.

If the Error Flag Bit (DQ5) is '1,' the MCU should

test the Data Polling Flag Bit (DQ7) again since

the Data Polling Flag Bit (DQ7) may have changed

simultaneously with the Error Flag Bit (DQ5, see

Figure 7).

DQ7

=

DATA

YES

NO

DQ5

= 1

YES

READ DQ7

DQ7

=

DATA

YES

The Error Flag Bit (DQ5) is set if either an internal

time-out occurred while the embedded algorithm

attempted to program the Byte or if the MCU at-

tempted to program a ’1’ to a bit that was not

erased (not erased is logic 0).

NO

FAIL

PASS

AI01369B

31/102

PSD835G2

Data Toggle

Checking the Toggle Flag Bit (DQ6) is a method of

determining whether a Program or Erase cycle is

in progress or has completed. Figure 8 shows the

Data Toggle algorithm.

The Flash memory then enters the Unlock Bypass

mode. A two-cycle Unlock Bypass Program in-

struction is all that is required to program in this

mode. The first cycle in this instruction contains

the Unlock Bypass Program code, A0h. The sec-

ond cycle contains the program address and data.

Additional data is programmed in the same man-

ner. These instructions dispense with the initial

two Unlock cycles required in the standard Pro-

gram instruction, resulting in faster total Flash

memory programming.

During the Unlock Bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset Flash

instructions are valid.

To exit the Unlock Bypass mode, the system must

issue the two-cycle Unlock Bypass Reset Flash in-

struction. The first cycle must contain the data

90h; the second cycle, the data 00h. Addresses

are Don’t Care for both cycles. The Flash memory

then returns to READ mode.

When the MCU issues a Program instruction, the

embedded algorithm within the PSD begins. The

MCU then reads the location of the byte to be pro-

grammed in Flash memory to check status. The

Toggle Flag Bit (DQ6) of this location toggles each

time the MCU reads this location until the embed-

ded algorithm is complete. The MCU continues to

read this location, checking the Toggle Flag Bit

(DQ6) and monitoring the Error Flag Bit (DQ5).

When the Toggle Flag Bit (DQ6) stops toggling

(two consecutive READs yield the same value),

and the Error Flag Bit (DQ5) remains '0,' the em-

bedded algorithm is complete. If the Error Flag Bit

(DQ5) is 1,' the MCU should test the Toggle Flag

Bit (DQ6) again, since the Toggle Flag Bit (DQ6)

may have changed simultaneously with the Error

Flag Bit (DQ5, see Figure 8).

The Error Flag Bit (DQ5) is set if either an internal

time-out occurred while the embedded algorithm

attempted to program the byte, or if the MCU at-

tempted to program a ’1’ to a bit that was not

erased (not erased is logic 0).

Figure 8. Data Toggle Flowchart

START

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

ming algorithm has completed, to compare the

Byte that was written to Flash memory with the

Byte that was intended to be written.

When using the Data Toggle method after an

Erase cycle, Figure 8 still applies. the Toggle Flag

Bit (DQ6) toggles until the Erase cycle is complete.

A 1 on the Error Flag Bit (DQ5) indicates a time-out

condition on the Erase cycle; a ’0’ indicates no er-

ror. The MCU can read any location within the sec-

tor being erased to get the Toggle Flag Bit (DQ6)

and the Error Flag Bit (DQ5).

READ

DQ5 & DQ6

DQ6

NO

=

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

PSDsoft generates ANSI C code functions which

implement these Data Toggling algorithms.

Unlock Bypass

DQ6

=

NO

The Unlock Bypass instructions allow the system

to program bytes to the Flash memories faster

than using the standard Program instruction. The

Unlock Bypass mode is entered by first initiating

two Unlock cycles. This is followed by a third

WRITE cycle containing the Unlock Bypass code,

20h (as shown in Table 28., page 27).

TOGGLE

YES

FAIL

PASS

AI01370B

32/102

PSD835G2

ERASING FLASH MEMORY

Flash Bulk Erase

The Flash Bulk Erase instruction uses six WRITE

operations followed by a READ operation of the

status register, as described in Table

28., page 27. If any byte of the Bulk Erase instruc-

tion is wrong, the Bulk Erase instruction aborts and

the device is reset to the Read Flash memory sta-

tus.

During execution of the Erase cycle, the Flash

memory accepts only Reset and Suspend Sector

Erase instructions. Erasure of one Flash memory

sector may be suspended, in order to read data

from another Flash memory sector, and then re-

sumed.

Suspend Sector Erase

During a Bulk Erase, the memory status may be

checked by reading the Error Flag Bit (DQ5), the

Toggle Flag Bit (DQ6), and the Data Polling Flag

Bit (DQ7), as detailed in “PROGRAMMING

FLASH MEMORY, page 31. The Error Flag Bit

(DQ5) returns a ’1’ if there has been an Erase Fail-

ure (maximum number of Erase cycles has been

executed).

When a Sector Erase cycle is in progress, the Sus-

pend Sector Erase instruction can be used to sus-

pend the cycle by writing 0B0h to any even

address when an appropriate Sector Select (FS0-

FS7 or CSBOOT0-CSBOOT3) is High. (See Table

28., page 27). This allows reading of data from an-

other Flash memory sector after the Erase cycle

has been suspended. Suspend Sector Erase is

accepted only during an Erase cycle and defaults

to READ mode. A Suspend Sector Erase instruc-

tion executed during an Erase time-out period, in

addition to suspending the Erase cycle, terminates

the time out period.

It is not necessary to program the memory with

00h because the PSD automatically does this be-

fore erasing to 0FFh.

During execution of the Bulk Erase instruction, the

Flash memory does not accept any instructions.

The Toggle Flag Bit (DQ6) stops toggling when the

PSD internal logic is suspended. The status of this

bit must be monitored at an address within the

Flash memory sector being erased. The Toggle

Flag Bit (DQ6) stops toggling between 0.1µs and

15µs after the Suspend Sector Erase instruction

has been executed. The PSD is then automatically

set to READ mode.

If a Suspend Sector Erase instruction was execut-

ed, the following rules apply:

– Attempting to read from a Flash memory sector

that was being erased outputs invalid data.

Flash Sector Erase

The Sector Erase instruction uses six WRITE op-

erations, as described in Table 28., page 27. Addi-

tional Flash Sector Erase codes and Flash

memory sector addresses can be written subse-

quently to erase other Flash memory sectors in

parallel, without further coded cycles, if the addi-

tional bytes are transmitted in a shorter time than

the time-out period of about 100µs. The input of a

new Sector Erase code restarts the time-out peri-

od.

The status of the internal timer can be monitored

through the level of the Erase Time-out Flag Bit

(DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,'

the Sector Erase instruction has been received

and the time-out period is counting. If the Erase

Time-out Flag Bit (DQ3) is '1,' the time-out period

has expired and the PSD is busy erasing the Flash

memory sector(s). Before and during Erase time-

out, any instruction other than Suspend Sector

Erase and Resume Sector Erase instructions

abort the cycle that is currently in progress, and re-

set the device to READ mode. It is not necessary

to program the Flash memory sector with 00h as

the PSD does this automatically before erasing

(Byte=FFh).

– Reading from a Flash sector that was not being

erased is valid.

– The Flash memory cannot be programmed, and

only responds to Resume Sector Erase and Re-

set Flash instructions (READ is an operation

and is allowed).

– If a Reset Flash instruction is received, data in

the Flash memory sector that was being erased

is invalid.

Resume Sector Erase

If a Suspend Sector Erase instruction was previ-

ously executed, the erase cycle may be resumed

with this instruction. The Resume Sector Erase in-

struction consists in writing 030h to any even ad-

dress while an appropriate Sector Select (FS0-

FS7 or CSBOOT0-CSBOOT3) is High. (See Table

28., page 27.)

During a Sector Erase, the memory status may be

checked by reading the Error Flag Bit (DQ5), the

Toggle Flag Bit (DQ6), and the Data Polling Flag

Bit (DQ7), as detailed in PROGRAMMING FLASH

MEMORY, page 31.

33/102

PSD835G2

SPECIFIC FEATURES

Flash Memory Sector Protect

Each primary and secondary Flash memory sector

can be separately protected against Program and

Erase cycles. Sector Protection provides addition-

al data security because it disables all Program or

Erase cycles. This mode can be activated through

the JTAG/ISP Port or a Device Programmer.

It must be executed after:

– Reading the Flash Protection Status or Flash ID

using the Flash instruction.

– An Error condition has occurred (and the device

has set the Error Flag Bit (DQ5) to ’1’) during a

Flash memory Program or Erase cycle.

Sector protection can be selected for each sector

using the PSDsoft program. This automatically

protects selected sectors when the device is pro-

grammed through the JTAG Port or a Device Pro-

grammer. Flash memory sectors can be

unprotected to allow updating of their contents us-

ing the JTAG Port or a Device Programmer. The

MCU can read (but cannot change) the sector pro-

tection bits.

Any attempt to program or erase a protected Flash

memory sector is ignored by the device. The Verify

operation results in a READ of the protected data.

The retention of the Protection status is thus en-

sured.

The Reset Flash instruction puts the Flash memo-

ry back into normal READ mode immediately. If an

Error condition has occurred (and the device has

set the Error Flag Bit (DQ5) to ’1’) the Flash mem-

ory is put back into normal READ mode within

25 µs of the Reset Flash instruction having been

issued. The Reset Flash instruction is ignored

when it is issued during a Program or Bulk Erase

cycle of the Flash memory. The Reset Flash in-

struction aborts any on-going Sector Erase cycle,

and returns the Flash memory to the normal READ

mode within 25µs.

Reset (RESET) Signal

A pulse on Reset (RESET) aborts any cycle that is

in progress, and resets the Flash memory to the

READ mode. When the reset occurs during a Pro-

gram or Erase cycle, the Flash memory takes up

to 25 µs to return to the READ mode. It is recom-

mended that the Reset (RESET) pulse (except for

the one described in Power-Up Reset, page 74)

be at least 25 µs so that the Flash memory is al-

ways ready for the MCU to fetch the bootstrap in-

structions after the Reset cycle is complete.

The sector protection status can be read by the

MCU through the primary and secondary Flash

memory protection registers (in the CSIOP block).

See Table 18., page 21 and Table 19., page 22.

Reset Flash

The Reset Flash instruction consists of one

WRITE cycle (see Table 28., page 27). It can also

be optionally preceded by the standard two

WRITE decoding cycles (writing AAh to AAAh and

55h to 554h).

SRAM

The SRAM is enabled when SRAM Select (RS0)

from the DPLD is High. SRAM Select (RS0) can

contain up to three product terms, allowing flexible

memory mapping.

The SRAM can be backed up using an external

battery. The external battery should be connected

PE7 can be configured as an output that indicates

when power is being drawn from the external bat-

tery. Battery-on Indicator (V

, PE7) is High

BATON

when the supply voltage falls below the battery

voltage and the battery on Voltage Stand-by

(V , PE6) is supplying power to the internal

STBY

SRAM.

to Voltage Stand-by (V

, PE6). If you have an

STBY

external battery connected to the PSD, the con-

tents of the SRAM are retained in the event of a

power loss. The contents of the SRAM are re-

tained so long as the battery voltage remains at

2 V or greater. If the supply voltage falls below the

battery voltage, an internal power switch-over to

the battery occurs.

SRAM Select (RS0), Voltage Stand-by (V

,

STBY

PC2) and Battery-on Indicator (V

, PC4) are

BATON

all configured using PSDsoft Express Configura-

tion.

The SRAM Select (RS0), V

and V

are

STBY

BATON

all configured using PSDsoft.

34/102

PSD835G2

SECTOR SELECT AND SRAM SELECT

Sector Select (FS0-FS7 for primary Flash memo-

ry, CSBOOT0-CSBOOT3 for secondary Flash

memory) and SRAM Select (RS0) are all outputs

of the DPLD. They are setup using PSDsoft. The

following rules apply to the equations for these sig-

nals:

Memory Select Configuration for MCUs with

Separate Program and Data Spaces

The 80C51 and compatible family of MCUs have

separate address spaces for Program memory

(selected using Program Select Enable (PSEN,

CNTL2)) and Data memory (selected using Read

Strobe (RD, CNTL1)). Any of the memories within

the PSD can reside in either space or both spaces.

This is controlled through manipulation of the VM

register that resides in the CSIOP space.

The VM register is set using PSDsoft to have an

initial value. It can subsequently be changed by

the MCU so that memory mapping can be

changed on-the-fly.

1. Primary Flash memory and secondary Flash

memory Sector Select signals must not be

larger than the physical sector size.

2. Any primary Flash memory sector must not be

mapped in the same memory space as

another primary Flash memory sector.

3. A secondary Flash memory sector must notbe

mapped in the same memory space as

another secondary Flash memory sector.

4. SRAM and I/O spaces must not overlap.

For example, you may wish to have SRAM and pri-

mary Flash memory in the Data space at Boot-up,

and secondary Flash memory in the Program

space at Boot-up, and later swap the primary and

secondary Flash memories. This is easily done

with the VM register by using PSDsoft to configure

it for Boot-up and having the MCU change it when

desired.

5. A secondary Flash memory sector may

overlap a primary Flash memory sector. In

case of overlap, priority is given to the

secondary Flash memory sector.

6. SRAM and I/O spaces may overlap any other

memory sector. Priority is given to the SRAM

and I/O.

Table 24., page 23 describes the VM Register.

Example

Figure 9. Priority Level of Memory and I/O

Components

FS0 is valid when the address is in the range of

8000h to BFFFh, CSBOOT0 is valid from 8000h to

9FFFh, and RS0 is valid from 8000h to 87FFh.

Any address in the range of RS0 always accesses

the SRAM. Any address in the range of CSBOOT0

greater than 87FFh (and less than 9FFFh) auto-

matically addresses secondary Flash memory

segment 0. Any address greater than 9FFFh ac-

cesses the primary Flash memory segment 0. You

can see that half of the primary Flash memory seg-

ment 0 and one-fourth of secondary Flash memory

segment 0 cannot be accessed in this example.

Also note that an equation that defined FS1 to any-

where in the range of 8000h to BFFFh would not

be valid.

Highest Priority

Level 1

SRAM, I/O, or

Peripheral I/O

Level 2

Secondary

Non-Volatile Memory

Level 3

Primary Flash Memory

Lowest Priority

AI02867D

Figure 9 shows the priority levels for all memory

components. Any component on a higher level can

overlap and has priority over any component on a

lower level. Components on the same level must

not overlap. Level one has the highest priority and

level 3 has the lowest.

35/102

PSD835G2

Configuration Modes for MCUs with Separate

Program and Data Spaces

Combined Space Modes. The Program and

Data spaces are combined into one memory

space that allows the primary Flash memory, sec-

ondary Flash memory, and SRAM to be accessed

by either Program Select Enable (PSEN, CNTL2)

or Read Strobe (RD, CNTL1). For example, to

configure the primary Flash memory in Combined

space, Bits b2 and b4 of the VM register are set to

’1’ (see Figure 11).

Separate Space Modes. Program space is sep-

arated from Data space. For example, Program

Select Enable (PSEN, CNTL2) is used to access

the program code from the primary Flash memory,

while Read Strobe (RD, CNTL1) is used to access

data from the secondary Flash memory, SRAM

and I/O Port blocks. This configuration requires

the VM register to be set to 0Ch (see Figure 10).

Figure 10. 8031 Memory Modules – Separate Space

Primary

Flash

Secondary

Flash

SRAM

DPLD

RS0

Memory

CSBOOT0-3

FS0-FS7

CS

OE

CS

OE

PSEN

RD

AI02869C

Figure 11. 8031 Memory Modules – Combined Space

Primary

Flash

Secondary

Flash

SRAM

DPLD

RS0

Memory

RD

CSBOOT0-3

FS0-FS7

CS

OE

CS

OE

VM REG BIT 3

VM REG BIT 4

PSEN

VM REG BIT 1

RD

VM REG BIT 2

VM REG BIT 0

AI02870C

36/102

PSD835G2

PAGE REGISTER

The 8-bit Page Register increases the addressing

capability of the MCU by a factor of up to 256. The

contents of the register can also be read by the

MCU. The outputs of the Page Register (PGR0-

PGR7) are inputs to the DPLD decoder and can be

included in the Sector Select (FS0-FS7,

CSBOOT0-CSBOOT3), and SRAM Select (RS0)

equations.

If memory paging is not needed, or if not all 8 page

register bits are needed for memory paging, then

these bits may be used in the CPLD for general

logic. See Application Note AN1154.

Figure 12 shows the Page Register. The eight flip-

flops in the register are connected to the internal

data bus D0-D7. The MCU can write to or read

from the Page Register. The Page Register can be

accessed at address location CSIOP + E0h.

Figure 12. Page Register

RESET

PGR0

INTERNAL

SELECTS

AND LOGIC

D0

D1

D2

D3

D4

D5

D6

D7

Q0

PGR1

Q1

Q2

Q3

Q4

Q5

Q6

Q7

PGR2

D0 - D7

DPLD

AND

CPLD

PGR3

PGR4

PGR5

PGR6

PGR7

R/W

PAGE

REGISTER

PLD

AI02871B

MEMORY ID REGISTERS

The 8-bit Read-only Memory Status Registers are

included in the CSIOP space. The user can deter-

mine the memory configuration of the PSD device

by reading the Memory ID0 and ID1 Registers.

The contents of the registers are defined in Table

25., page 23 and Table 26., page 23.

37/102

PSD835G2

PLDS

The PLDs bring programmable logic functionality

to the PSD. After specifying the logic for the PLDs

in PSDsoft, the logic is programmed into the de-

vice and available upon Power-up.

The PSD contains two PLDs: the Decode PLD

(DPLD), and the Complex PLD (CPLD). The PLDs

are briefly discussed in the next few paragraphs,

and in more detail in Decode PLD

(DPLD), page 40

(CPLD), page 41. Figure 13 shows the configura-

tion of the PLDs.

The DPLD performs address decoding for Select

signals for internal components, such as memory,

registers, and I/O ports.

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

chines, and encoding and decoding logic. These

logic functions can be constructed using the 16

Output Macrocells (OMC), 24 Input Macrocells

(IMC), and the AND Array. The CPLD can also be

used to generate External Chip Select (ECS0-

ECS2) signals.

The AND Array is used to form product terms.

These product terms are specified using PSDsoft.

An Input Bus consisting of 82 signals is connected

to the PLDs. The signals are shown in Table 30.

This reduces power consumption and can be used

only when these MCU control signals are not used

in PLD logic equations.

Each of the two PLDs has unique characteristics

suited for its applications. They are described in

the following sections.

Table 30. DPLD and CPLD Inputs

Number

and

Complex

PLD

Input Source

Input Name

of

Signals

1

A15-A0

CNTL2-CNTL0

RST

16

3

MCU Address Bus

MCU Control Signals

Reset

1

Power-down

PDN

1

Port A Input

Macrocells

PA7-PA0

PB7-PB0

PC7-PC0

8

Port B Input

Macrocells

Port C Input

Macrocells

Port D Inputs

Port F Inputs

Page Register

PD3-PD0

PF7-PF0

4

8

The Turbo Bit in PSD

The PLDs in the PSD can minimize power con-

sumption by switching to standby when inputs re-

main unchanged for an extended time of about

70ns. Resetting the Turbo Bit to ’0’ (Bit 3 of

PMMR0) automatically places the PLDs into

standby if no inputs are changing. Turning the Tur-

bo mode off increases propagation delays while

reducing power consumption. See POWER

MANAGEMENT, page 70, on how to set the Tur-

bo Bit.

PGR7-PGR0

Macrocell A Feedback MCELLA.FB7-FB0

Macrocell B Feedback MCELLB.FB7-FB0

Secondary Flash

memory Program

Status Bit

Ready/Busy

1

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

Additionally, five bits are available in PMMR2 to

block MCU control signals from entering the PLDs.

38/102

PSD835G2

Figure 13. PLD Diagram

I / O P O R T S

P L D I N P U T B U S

39/102

PSD835G2

Decode PLD (DPLD)

The DPLD, shown in Figure 14, is used for decod-

ing the address for internal and external compo-

nents. The DPLD can be used to generate the

following decode signals:

–

1 internal SRAM Select (RS0) signal (three

product terms)

1 internal CSIOP Select (PSD Configuration

Register) signal

1 JTAG Select signal (enables JTAG/ISP on

Port E)

2 internal Peripheral Select signals

(Peripheral I/O mode).

–

8 Sector Select (FS0-FS7) signals for the

primary Flash memory (three product terms

each)

–

4 Sector Select (CSBOOT0-CSBOOT3)

signals for the secondary Flash memory (three

product terms each)

Figure 14. DPLD Logic Array

CSBOOT 0

CSBOOT 1

CSBOOT 2

CSBOOT 3

3

(INPUTS)

(32)

3

FS0

I/O PORTS (PORT A,B,C,F)

FS1

FS2

(8)

MCELLA.FB7-FB0 (FEEDBACKS)

MCELLB.FB7-FB0 (FEEDBACKS)

(8)

FS3

8 PRIMARY FLASH

MEMORY SECTOR

SELECTS

PGR0 -PGR7

FS4

FS5

(16)

(4)

(1,2)

A15-A0

PD3-PD0 (ALE,CLKIN,CSI)

PDN (APD OUTPUT)

FS6

FS7

(1)

(

(3)

(1)

CNTRL2-CNTRL0 READ/WRITE CONTROL SIGNALS)

RESET

RS0

3

SRAM SELECT

RD_BSY

CSIOP

I/O DECODER

SELECT

PSEL0

PERIPHERAL I/O

MODE SELECT

PSEL1

JTAGSEL

AI02873E

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

2. Additional address lines can be brought into PSD via Port A, B, C, D or F.

40/102

PSD835G2

Complex PLD (CPLD)

The CPLD can be used to implement system logic

functions, such as loadable counters and shift reg-

isters, system mailboxes, handshaking protocols,

state machines, and random logic. The CPLD can

also be used to generate three External Chip Se-

lect (ECS0-ECS2), routed to Port D.

Although External Chip Select (ECS0-ECS2) can

be produced by any Output Macrocell (OMC),

these three External Chip Select (ECS0-ECS2) on

Port D do not consume any Output Macrocells

(OMC).

■

Product Term Allocator

AND Array capable of generating up to 137

product terms

■

Four I/O Ports.

Each of the blocks are described in the sections

that follow.

The Input Macrocells (IMC) and Output Macrocells

(OMC) are connected to the PSD internal data bus

and can be directly accessed by the MCU. This

enables the MCU software to load data into the

Output Macrocells (OMC) or read data from both

the Input and Output Macrocells (IMC and OMC).

This feature allows efficient implementation of sys-

tem logic and eliminates the need to connect the

data bus to the AND Array as required in most

standard PLD macrocell architectures.

As shown in Figure 13., page 39, the CPLD has

the following blocks:

■

24 Input Macrocells (IMC)

16 Output Macrocells (OMC)

Macrocell Allocator

41/102

PSD835G2

Figure 15. Macrocell and I/O Port

U X M

M U X

A N D A R R A Y

P L D I N P U T B U S

42/102

PSD835G2

Output Macrocell (OMC)

Eight of the Output Macrocells (OMC) are con-

nected to Port A pins and are named as McellA0-

McellA7. The other eight macrocells are connect-

ed to Port B pins and are named as McellB0-

McellB7.

The Output Macrocell (OMC) architecture is

shown in Figure 16., page 45. As shown in the fig-

ure, there are native product terms available from

the AND Array, and borrowed product terms avail-

able (if unused) from other Output Macrocells

(OMC). The polarity of the product term is con-

trolled by the XOR gate. The Output Macrocell

(OMC) can implement either sequential logic, us-

ing the flip-flop element, or combinatorial logic.

The multiplexer selects between the sequential or

combinatorial logic outputs. The multiplexer output

can drive a port pin and has a feedback path to the

AND Array inputs.

The flip-flop in the Output Macrocell (OMC) block

can be configured as a D, T, JK, or SR type in the

PSDsoft program. The flip-flop’s clock, preset, and

clear inputs may be driven from a product term of

the AND Array. Alternatively, CLKIN (PD1) can be

used for the clock input to the flip-flop. The flip-flop

is clocked to the rising edge of CLKIN (PD1). The

preset and clear are active High inputs. Each clear

input can use up to two product terms.

Table 31. Output Macrocell Port and Data Bit Assignments

Output

Macrocell

Port

Assignment

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

Native Product Terms

McellA0

McellA1

McellA2

McellA3

McellA4

McellA5

McellA6

McellA7

McellB0

McellB1

McellB2

McellB3

McellB4

McellB5

McellB6

McellB7

Port A0

Port A1

Port A2

Port A3

Port A4

Port A5

Port A6

Port A7

Port B0

Port B1

Port B2

Port B3

Port B4

Port B5

Port B6

Port B7

3

4

6

5

6

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

43/102

PSD835G2

Product Term Allocator

The CPLD has a Product Term Allocator. The PSD

uses the Product Term Allocator to borrow and

place product terms from one macrocell to anoth-

er. The following list summarizes how product

terms are allocated:

Data can be loaded to the Output Macrocells

(OMC) on the trailing edge of the Write Strobe

(WR, CNTL0) signal.

The OMC Mask Register

There is one Mask Register for each of the two

groups of eight Output Macrocells (OMC). The

Mask Registers can be used to block the loading

of data to individual Output Macrocells (OMC).

The default value for the Mask Registers is 00h,

which allows loading of the Output Macrocells

(OMC). When a given bit in a Mask Register is set

to a '1,' the MCU is blocked from writing to the as-

sociated Output Macrocells (OMC). For example,

suppose McellA0-McellA3 are being used for a

state machine. You would not want a MCU WRITE

to McellA to overwrite the state machine registers.

Therefore, you would want to load the Mask Reg-

ister for McellA (Mask Macrocell AB) with the value

0Fh.

–

McellA0-McellA7 all have three native product

terms and may borrow up to six more

McellB0-McellB3 all have four native product

terms and may borrow up to five more

McellB4-McellB7 all have four native product

terms and may borrow up to six more.

Each macrocell may only borrow product terms

from certain other macrocells. Product terms al-

ready in use by one macrocell are not available for

another macrocell.

If an equation requires more product terms than

are available to it, then “external” product terms

are required that consume other Output Macro-

cells (OMC). If external product terms are used,

extra delay is added for the equation that required

the extra product terms.

This is called product term expansion. PSDsoft

performs this expansion as needed.

Loading and Reading the Output Macrocells

(OMC)

The Output Macrocells (OMC) block occupies a

memory location in the MCU address space, as

defined by the CSIOP block (see I/O

PORTS, page 59). The flip-flops in each of the 16

Output Macrocells (OMC) can be loaded from the

data bus by a MCU. Loading the Output Macro-

cells (OMC) with data from the MCU takes priority

over internal functions. As such, the preset, clear,

and clock inputs to the flip-flop can be overridden

by the MCU. The ability to load the flip-flops and

read them back is useful in such applications as

loadable counters and shift registers, mailboxes,

and handshaking protocols.

The Output Enable of the OMC

The Output Macrocells (OMC) block can be con-

nected to an I/O port pin as a PLD output. The out-

put enable of each port pin driver is controlled by

a single product term from the AND Array, ORed

with the Direction Register output. The pin is en-

abled upon Power-up if no output enable equation

is defined and if the pin is declared as a PLD out-

put in PSDsoft.

If the Output Macrocell (OMC) output is declared

as an internal node and not as a port pin output in

the PSDabel file, the port pin can be used for other

I/O functions. The internal node feedback can be

routed as an input to the AND Array.

44/102

PSD835G2

Figure 16. CPLD Output Macrocell

A N D A R R A Y

P L D I N P U T B U S

45/102

PSD835G2

Input Macrocells (IMC)

The CPLD has 24 Input Macrocells (IMC), one for

each pin on Ports A, B, and C. The architecture of

the Input Macrocells (IMC) is shown in Figure

17., page 47. The Input Macrocells (IMC) are indi-

vidually configurable, and can be used as a latch,

register, or to pass incoming Port signals prior to

driving them onto the PLD input bus. The outputs

of the Input Macrocells (IMC) can be read by the

MCU through the internal data bus.

Input Macrocells (IMC) can use Address Strobe

(ALE/AS, PD0) to latch address bits higher than

A15. Any latched addresses are routed to the

PLDs as inputs.

Input Macrocells (IMC) are particularly useful with

handshaking communication applications where

two processors pass data back and forth through

a common mailbox. Figure 18., page 48 shows a

typical configuration where the Master MCU writes

to the Port A Data Out Register. This, in turn, can

be read by the Slave MCU via the activation of the

“Slave-Read” output enable product term.

The Slave can also write to the Port A Input Mac-

rocells (IMC) and the Master can then read the In-

put Macrocells (IMC) directly.

Note that the “Slave-Read” and “Slave-Wr” signals

are product terms that are derived from the Slave

MCU inputs Read Strobe (RD, CNTL1), Write

Strobe (WR, CNTL0), and Slave_CS.

The enable for the latch and clock for the register

are driven by a multiplexer whose inputs are a

product term from the CPLD AND Array or the

MCU Address Strobe (ALE/AS). Each product

term output is used to latch or clock four Input

Macrocells (IMC). Port inputs 3-0 can be con-

trolled by one product term and 7-4 by another.

Configurations for the Input Macrocells (IMC) are

specified by PSDsoft. Outputs of the Input Macro-

cells (IMC) can be read by the MCU via the IMC

buffer. See I/O PORTS, page 59.

46/102

PSD835G2

Figure 17. Input Macrocell

A N D A R R A Y

P L D I N P U T B U S

47/102

PSD835G2

Figure 18. Handshaking Communication Using Input Macrocells

48/102

PSD835G2

External Chip

The CPLD also provides eight Chip Select outputs

that can be used to select external devices. The

Chip Selects can be routed to either Port C or Port

F, depending on the pin declaration in the PSD-

soft. Each Chip Select (ECS0-ECS7) consists of

one product term that can be configured active

High or Low.

The Output Enable of the pin is controlled by either

the Output Enable product term or the Direction

Register (See Figure 19).

Figure 19. External Chip Select

ENABLE (.OE) PT

DIRECTION

REGISTER

ECS TO

PORT C OR F

PD0 PIN

ECS PT

POLARITY

BIT

PORT C OR PORT F

AI07654

49/102

PSD835G2

MCU BUS INTERFACE

The “no-glue logic” MCU Bus Interface block can

be directly connected to most popular MCUs and

their control signals. Key 8-bit MCUs, with their

bus types and control signals, are shown in Table

32. The interface type is specified using the PSD-

soft.

Table 32. MCUs and their Control Signals

2

MCU

8031/8051

80C51XA

80C251

80198

Data Bus Width CNTL0 CNTL1 CNTL2

PC7

ADIO0 PA3-PA0 PA7-PA4

PD0

ALE

AS

1

8

WR

R/W

WR

R/W

WR

R/W

RD

PSEN

RD

E

PSEN

A0

A4

A0

(Note )

1

PSEN

A3-A0

(Note )

1

(Note ) (Note )

(Note )

1

PSEN

(Note )

1

(Note ) (Note )

(Note )

1

68HC11

68HC05C0

68HC912

Z80

(Note ) (Note )

(Note )

1

RD

E

AS

(Note ) (Note )

(Note )

1

DBE

AS

(Note )

1

RD

DS

E

D3-D0

D7-D4

(Note ) (Note ) (Note )

1

Z8

AS

(Note ) (Note )

(Note )

1

68330

(Note ) (Note )

(Note )

1

M37702M2

ALE

D3-D0

D7-D4

(Note ) (Note )

Note: 1. Unused CNTL2 pin can be configured as PLD input. Other unused pins (PD3-PD0, PA3-PA0) can be configured for other I/O func-

tions.

2. ALE/AS input is optional for MCUs with a non-multiplexed bus

50/102

PSD835G2

PSD Interface to a Multiplexed 8-Bit Bus

Figure 20 shows an example of a system using a

MCU with an 8-bit multiplexed bus and a PSD. The

ADIO port on the PSD is connected directly to the

MCU address/data bus. Address Strobe (ALE/AS,

PD0) latches the address signals internally.

Latched addresses can be brought out to Port E,

For G. The PSD drives the ADIO data bus only

when one of its internal resources is accessed and

Read Strobe (RD, CNTL1) is active. Should the

system address bus exceed sixteen bits, Ports A,

B, C, or F may be used as additional address in-

puts.

Figure 20. An Example of a Typical 8-bit Multiplexed Bus Interface

MCU

PSD

AD7-AD0

A15-A8

A7-A0

PORT

F

(

)

OPTIONAL

ADIO

PORT

A15-A8

PORT

G

OPTIONAL

(

)

WR

RD

WR CNTRL0

(

)

RD CNTRL1

A23-A16

PORT

A, B

or C

(

)

BHE

BHE CNTRL2

(OPTIONAL)

RST

ALE

(

)

ALE PD0

PORT D

RESET

AI02878D

51/102

PSD835G2

PSD Interface to a Non-Multiplexed 8-Bit Bus

MCU Bus Interface Examples

Figure 21 shows an example of a system using a

MCU with an 8-bit non-multiplexed bus and a

PSD. The address bus is connected to the ADIO

Port, and the data bus is connected to Port F. Port

F is in tri-state mode when the PSD is not access-

ed by the MCU. Should the system address bus

exceed sixteen bits, Ports A, B or C may be used

for additional address inputs.

Figures 22 through 25 show examples of the basic

connections between the PSD and some popular

MCUs. The PSD Control input pins are labeled as

to the MCU function for which they are configured.

The MCU bus interface is specified using the PS-

Dsoft.

Figure 21. An Example of a Typical 8-bit Non-Multiplexed Bus Interface

PSD

MCU

D7-D0

PORT

F

ADIO

PORT

A15-A0

PORT

G

(

)

WR

RD

WR CNTRL0

(

)

RD CNTRL1

PORT

A, B

or C

A23-A16

(OPTIONAL)

(

)

BHE

BHE CNTRL2

RST

ALE

(

)

ALE PD0

PORT D

RESET

AI02879D

52/102

PSD835G2

80C31

Figure 22 shows the bus interface for the 80C31,

which has an 8-bit multiplexed address/data bus.

The lower address byte is multiplexed with the

data bus. The MCU control signals Program Se-

lect Enable (PSEN, CNTL2), Read Strobe (RD,

CNTL1), and Write Strobe (WR, CNTL0) may be

used for accessing the internal memory and I/O

Ports blocks. Address Strobe (ALE/AS, PD0)

latches the address.

Figure 22. Interfacing the PSD with an 80C31

A15-A8

[15

AD :8

]

AD7-AD0

[

]

AD 7:0

V

CC

PSD

80C31

V

CC CC CC

19

39

38

37

36

35

34

33

32

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

31

32

33

34

35

36

37

38

3

4

5

6

X1

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

ADIO0

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

CRYSTAL

RESET

18

9

X2

7

10

11

12

RESET

12

13

14

15

INT0

INT1

T0

21

22

23

24

25

26

27

21

22

23

24

25

26

27

28

A8

A9

13

14

15

16

17

18

19

20

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

ADIO8

ADIO9

T1

A10

A11

A12

A13

A14

A15

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

1

2

3

4

5

6

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

28

16

17

WR

59

60

51

52

53

54

55

56

57

58

7

8

WR

RD

CNTL0(WR)

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

RD

CNTL1(RD)

CNTL2(PSEN)

29

30

PSEN

ALE

40

PSEN

ALE/P

10

11

79

RXD

TXD

PD0 (ALE)

PD1 (CLKIN)

PD2 (CS)

PD3

80

1

2

31

EA/VP

39

61

62

63

64

65

66

67

RESET

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

71

72

73

74

75

76

77

78

PE0 (TMS)

PE1 (TCK/ST)

PE2 (TDI)

PE3 (TDO)

PE4 (TSTAT/RDY)

PE5 (TERR)

PE6 (VSTBY)

RESET

68

41

42

43

44

45

46

47

48

PE7 (VBATON)

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

GND GND GND GND GND

30 49 50 70

8

AI02880D

53/102

PSD835G2

80C251

The Intel 80C251 MCU features a user-config-

urable bus interface with four possible bus config-

urations, as shown in Table 33.

The 80C251 has two major operating modes:

Page mode and Non-page mode. In Non-page

mode, the data is multiplexed with the lower ad-

dress byte, and Address Strobe (ALE/AS, PD0) is

active in every bus cycle. In Page mode, data (D7-

D0) is multiplexed with address (A15-A8). In a bus

cycle where there is a Page hit, Address Strobe

(ALE/AS, PD0) is not active and only addresses

(A7-A0) are changing. The PSD supports both

modes. In Page Mode, the PSD bus timing is iden-

tical to Non-Page Mode except the address hold

time and setup time with respect to Address

Strobe (ALE/AS, PD0) is not required. The PSD

access time is measured from address (A7-A0)

valid to data in valid.

The first configuration is 80C31 compatible, and

the bus interface to the PSD is identical to that

shown in Figure 22., page 53. The second and

third configurations have the same bus connection

as shown in Table 34., page 55. There is only one

Read Strobe (PSEN) connected to CNTL1 on the

PSD. The A16 connection to PA0 allows for a larg-

er address input to the PSD. The fourth configura-

tion is shown in Figure 23., page 56. Read Strobe

(RD) is connected to CNTL1 and Program Select

Enable (PSEN) is connected to CNTL2.

Table 33. 80C251 Configurations

80C251 READ/WRITE

Configuration

Connecting to PSD Pins

Page Mode

Pins

WR

RD

PSEN

CNTL0

CNTL1

CNTL2

Non-Page Mode, 80C31

compatible A7-A0 multiplex with

D7-D0

1

WR

PSEN only

CNTL0

CNTL1

Non-Page Mode

A7-A0 multiplex with D7-D0

2

3

WR

PSEN only

CNTL0

CNTL1

Page Mode

A15-A8 multiplex with D7-D0

WR

RD

PSEN

CNTL0

CNTL1

CNTL2

Page Mode

A15-A8 multiplex with D7-D0

4

54/102

PSD835G2

Table 34. Interfacing the PSD with the 80C251, with One READ Input

A17-A8

[15

AD :8

]

A17

AD7-AD0

[

]

AD 7:0

V

CC

U1

PSD

80C31

V

CC CC CC

(2)

(1)

2

3

4

5

6

43

42

41

40

39

38

37

36

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

31 A16

3

4

5

6

P1.0

P0.0

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

32 A17

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

33

34

35

36

37

38

7

8

9

10

11

12

21

22

23

24

25

26

27

24

25

26

27

28

29

30

31

A8

A9

13

14

15

16

17

18

19

20

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

ADIO8

ADIO9

21

20

X1

X2

A10

A11

A12

A13

A14

A15

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

CRYSTAL

28

18

19

WR

59

60

40

79

51

52

53

54

55

56

57

58

WR

RD/A16

PSEN

CNTL0(WR)

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

A16

CNTL1(RD)

CNTL2(PSEN)

32

RD

ALE

10

PD0 (ALE)

PD1 (CLKIN)

PD2 (CS)

PD3

RESET

EA

RESET

80

1

2

33

ALE

35

39

61

62

63

64

65

66

67

RESET

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

71

72

73

74

75

76

77

78

PE0 (TMS)

PE1 (TCK/ST)

PE2 (TDI)

PE3 (TDO)

PE4 (TSTAT/RDY)

PE5 (TERR)

PE6 (VSTBY)

RESET

68

41

42

43

44

45

46

47

48

PE7 (VBATON)

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

GND GND GND GND GND

30 49 50 70

8

AI02881D

Note: 1. The A16 and A17 connections are optional.

2. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.

55/102

PSD835G2

Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs

A15-A8

[

]

AD 15:8

AD7-AD0

[

]

AD 7:0

V

CC

PSD

80C31

V

CC CC CC

(2)

2

3

4

5

6

43

42

41

40

39

38

37

36

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

31

32

33

34

35

36

37

38

3

4

5

6

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P0.0

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

7

8

9

10

11

12

21

22

23

24

25

26

27

24

25

26

27

28

29

30

31

A8

A9

13

14

15

16

17

18

19

20

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

ADIO8

ADIO9

21

20

X1

X2

A10

A11

A12

A13

A14

A15

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

CRYSTAL

28

18

19

32

WR

RD

59

60

40

51

52

53

54

55

56

57

58

WR

RD/A16

PSEN

CNTL0(WR)

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

CNTL1(RD)

CNTL2(PSEN)

PSEN

10

RESET

EA

RESET

33

79

ALE

PD0 (ALE)

PD1 (CLKIN)

PD2 (CS)

PD3

ALE

80

1

2

35

61

62

63

64

65

66

67

39

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

RESET

71

PE0 (TMS)

72

73

74

75

76

77

78

PE1 (TCK/ST)

PE2 (TDI)

PE3 (TDO)

PE4 (TSTAT/RDY)

PE5 (TERR)

PE6 (VSTBY)

RESET

68

41

42

43

44

45

46

47

48

PE7 (VBATON)

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

GND GND GND GND GND

30 49 50 70

8

AI02882D

56/102

PSD835G2

80C51XA

The Philips 80C51XA MCU family supports an 8-

or 16-bit multiplexed bus that can have burst cy-

cles. Address bits (A3-A0) are not multiplexed,

while (A19-A4) are multiplexed with data bits

(D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4)

are multiplexed with data bits (D7-D0).

The 80C51XA can be configured to operate in

eight-bit data mode (as shown in Figure 24).

The 80C51XA improves bus throughput and per-

formance by executing burst cycles for code fetch-

es. In Burst Mode, address A19-A4 are latched

internally by the PSD, while the 80C51XA changes

the A3-A0 signals to fetch up to 16 bytes of code.

The PSD access time is then measured from ad-

dress A3-A0 valid to data in valid. The PSD bus

timing requirement in Burst Mode is identical to the

normal bus cycle, except the address setup and

hold time with respect to Address Strobe (ALE/AS,

PD0) does not apply.

Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus

[

]

A 19:12 D[7:0]

[3

A :0

]

V

CC

PSD

9

29 69

80C31

V

CC CC CC

(2)

43

42

41

40

39

38

37

36

21

20

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

31

32

33

34

35

36

37

38

3

4

5

6

XTAL1

XTAL2

A4D0

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

A5D1

A6D2

A7D3

A8D4

A9D5

A10D6

A11D7

CRYSTAL

7

10

11

12

11

13

6

RXD0

TXD0

RXD1

TXD1

7

21

22

23

24

25

26

27

24

25

26

27

28

29

30

31

A8

A9

13

14

15

16

17

18

19

20

A12D8

A13D9

A14D10

A15D11

A16D12

A17D13

A18D14

A19D15

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

ADIO8

ADIO9

9

8

A10

A11

A12

A13

A14

A15

T2EX

T2

T0

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

16

28

5

4

3

2

A3

A2

A1

A0

A3

A2

A1

51

52

53

54

55

56

57

58

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

WR

RD

59

60

40

CNTL0(WR)

RESET

10

RESET

CNTL1(RD)

CNTL2(PSEN)

A0/WRH

WRL

18

14

15

INT0

INT1

19

RD

V

35

CC

EA/WAIT

79

PD0 (ALE)

PD1 (CLKIN)

PD2 (CS)

PD3

32

33

PSEN

ALE

80

1

2

61

62

63

64

65

66

67

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

ALE

39

RESET

71

PE0 (TMS)

72

73

74

75

76

77

78

PE1 (TCK/ST)

PE2 (TDI)

PE3 (TDO)

PE4 (TSTAT/RDY)

PE5 (TERR)

PE6 (VSTBY)

RESET

68

41

42

43

44

45

46

47

48

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PE7 (VBATON)

GND GND GND GND GND

30 49 50 70

8

AI02883D

57/102

PSD835G2

68HC11

Figure 25 shows a bus interface to a 68HC11

where the PSD is configured in 8-bit multiplexed

mode with E and R/W settings. The DPLD can be

used to generate the READ and WR signals for

external devices.

Figure 25. Interfacing the PSD with a 68HC11

A15-A8

[

A 15:8]

AD7-AD0

[3

A :0

]

V

CC

PSD

9

29 69

80C31

V

CC CC CC

(2)

34

33

32

31

30

29

28

27

9

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

31

32

33

34

35

36

37

38

3

4

5

6

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

10

11

12

13

7

10

11

12

14

15

16

21

22

23

24

25

26

27

A8

A9

8

13

14

15

16

17

18

19

20

42

41

40

39

38

37

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

XT

EX

ADIO8

ADIO9

CRYSTAL

A10

A11

A12

A13

A14

A15

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

7

19

IRQ

XIRQ

18

36

35

28

20

21

22

23

24

25

PD0

PD1

PD2

PD3

PD4

PD5

51

52

53

54

55

56

57

58

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

6

5

R/W

E

59

60

CNTL0(R/W)

CNTL1(RD)

R/W

E

40

4

CNTL2(E)

AS

43

44

45

46

47

48

49

50

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

AS

79

PD0 (AS)

PD1 (CLKIN)

PD2 (CS)

PD3

RESET

80

1

2

61

62

63

64

65

66

67

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

RESET

39

RESET

71

PE0 (TMS)

52

51

VRH

VRL

72

73

74

75

76

77

78

PE1 (TCK/ST)

PE2 (TDI)

PE3 (TDO)

PE4 (TSTAT/RDY)

PE5 (TERR)

PE6 (VSTBY)

68

2

3

MODB

MODA

41

42

43

44

45

46

47

48

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

RESET

PE7 (VBATON)

RESET

GND GND GND GND GND

30 49 50 70

8

AI02884D

58/102

PSD835G2

I/O PORTS

There are seven programmable I/O ports: Ports A,

B, C, D, E and F. Each of the ports is eight bits ex-

cept for Port D, which is 4 bits. Each port pin is in-

dividually user-configurable, thus allowing multiple

functions per port. The ports are configured using

PSDsoft or by the MCU writing to on-chip registers

in the CSIOP space.

The Port pin’s tri-state output driver enable is con-

trolled by a two input OR gate whose inputs come

from the CPLD AND Array enable product term

and the Direction Register. If the enable product

term of any of the Array outputs is not defined and

that port pin is not defined as a CPLD output in the

PSDabel file, then the Direction Register has sole

control of the buffer that drives the port pin.

The topics discussed in this section are:

The contents of these registers can be altered by

the MCU. The Port Data Buffer (PDB) feedback

path allows the MCU to check the contents of the

registers.

Ports A, B, and C have embedded Input Macro-

cells (IMC). The Input Macrocells (IMC) can be

configured as latches, registers, or direct inputs to

the PLDs. The latches and registers are clocked

by Address Strobe (ALE/AS, PD0) or a product

term from the PLD AND Array. The outputs from

the Input Macrocells (IMC) drive the PLD input bus

and can be read by the MCU. See Input Macro-

cells (IMC), page 46.

■

General Port architecture

Port operating modes

Port Configuration Registers (PCR)

Port Data Registers

Individual Port functionality.

General Port Architecture

The general architecture of the I/O Port block is

shown in Figure 26., page 60. Individual Port ar-

chitectures are shown in Figure 28., page 66 to

Figure 30., page 69. In general, once the purpose

for a port pin has been defined, that pin is no long-

er available for other purposes. Exceptions are

noted.

Port Operating Modes

The I/O Ports have several modes of operation.

Some modes can be defined using PSDabel,

some by the MCU writing to the Registers in

CSIOP space, and some by both. The modes that

can only be defined using PSDsoft must be pro-

grammed into the device and cannot be changed

unless the device is reprogrammed. The modes

that can be changed by the MCU can be done so

dynamically at run-time. The PLD I/O, Data Port,

Address Input, Peripheral I/O and MCU Reset

modes are the only modes that must be defined

before programming the device. All other modes

can be changed by the MCU at run-time.

As shown in Figure 26., page 60, the ports contain

an output multiplexer whose select signals are

driven by the configuration bits in the Control Reg-

isters (Ports E, F and G only) and PSDsoft Config-

uration. Inputs to the multiplexer include the

following:

–

Output data from the Data Out register

Latched address outputs

CPLD macrocell output

External Chip Select (ECS0-ECS2) from the

CPLD.

The Port Data Buffer (PDB) is a tri-state buffer that

allows only one source at a time to be read. The

Port Data Buffer (PDB) is connected to the Internal

Data Bus for feedback and can be read by the

MCU. The Data Out and macrocell outputs, Direc-

tion and Control Registers, and port pin input are

all connected to the Port Data Buffer (PDB).

Table 35., page 61 summarizes which modes are

available on each port. Table 38., page 64 shows

how and where the different modes are config-

ured. Each of the port operating modes are de-

scribed in the following sections.

59/102

PSD835G2

Figure 26. General I/O Port Architecture

DATA OUT

REG.

DATA OUT

ADDRESS

D

Q

WR

ADDRESS

ALE

PORT PIN

D

G

Q

OUTPUT

MUX

MACROCELL OUTPUTS

EXT CS

READ MUX

P

D

B

OUTPUT

SELECT

DATA IN

CONTROL REG.

ENABLE OUT

D

Q

WR

DIR REG.

D

Q

(

)

ENABLE PRODUCT TERM .OE

INPUT

MACROCELL

CPLD-INPUT

AI02885

60/102

PSD835G2

MCU I/O Mode

In the MCU I/O mode, the MCU uses the I/O Ports

block to expand its own I/O ports. By setting up the

CSIOP space, the ports on the PSD are mapped

into the MCU address space. The addresses of

the ports are listed in Table 5., page 19.

A port pin can be put into MCU I/O mode by writing

a ’0’ to the corresponding bit in the Control Regis-

ter (Ports E, F and G). The MCU I/O direction may

be changed by writing to the corresponding bit in

the Direction Register, or by the output enable

product term. See Direction Register, page 64.

When the pin is configured as an output, the con-

tent of the Data Out Register drives the pin. When

configured as an input, the MCU can read the port

input through the Data In buffer. See Figure

26., page 60.

by a product term from the PLD, or by resetting the

corresponding bit in the Direction Register to '0.'

The corresponding bit in the Direction Register

must not be set to ’1’ if the pin is defined as a PLD

input pin in PSDsoft. The PLD I/O mode is speci-

fied in PSDsoft by declaring the port pins, and then

specifying an equation in PSDsoft.

Address Out Mode

For MCUs with a multiplexed address/data bus,

Address Out Mode can be used to drive latched

addresses on to the port pins. These port pins can,

in turn, drive external devices. Either the output

enable or the corresponding bits of both the Direc-

tion Register and Control Register must be set to

a ’1’ for pins to use Address Out Mode. This must

be done by the MCU at run-time. See Table

37., page 62 for the address output pin assign-

ments on Ports E, F and G for various MCUs.

Note: Do not drive address signals with Address

Out Mode to an external memory device if it is in-

tended for the MCU to Boot from the external de-

vice. The MCU must first Boot from PSD memory

so the Direction and Control register bits can be

set.

Ports A, B and C do not have Control Registers,

and are in MCU I/O mode by default. They can be

used for PLD I/O if they are specified in PSDsoft.

PLD I/O Mode

The PLD I/O Mode uses a port as an input to the

CPLD’s Input Macrocells (IMC), and/or as an out-

put from the CPLD’s Output Macrocells (OMC).

The output can be tri-stated with a control signal.

This output enable control signal can be defined

Table 35. Port Operating Modes

Port Mode

MCU I/O

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Yes

PLD I/O

McellA Outputs

McellB Outputs

Additional Ext. CS Outputs

PLD Inputs

Yes

No

Yes

No

Yes

No

Yes

No

Yes

Yes (A7-A0)

or (A15-A8)

Address Out

No

Yes (A7-A0) Yes (A7-A0)

Address In

Data Port

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Peripheral I/O

1

JTAG ISP

No

Yes

Note: 1. Can be multiplexed with other I/O functions.

61/102

PSD835G2

Table 36. Port Operating Mode Settings

Control

Register

Setting

Direction

Register

Setting

VM Register

Setting

Mode

Defined in PSDsoft

JTAG Enable

1 = output,

0 = input

4

MCU I/O

Declare pins only

N/A

0 (Note )

2

(Note )

Declare pins and logic

equations

2

PLD I/O

N/A

1

N/A

(Note )

Selected for MCU with

non-mux bus

Data Port (Port F)

N/A

Address Out

(Port E, F, G)

2

Declare pins only

1 (Note )

Declare pins or logic

equations for Input

Macrocells

Address In

(Port A,B,C,D, F)

N/A

Peripheral I/O

(Port F)

Logic equations

(PSEL0 & 1)

N/A

PIO Bit = 1

N/A

3

Declare pins only

JTAG_Enable

JTAG ISP (Note )

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

3. Any of these three methods enables the JTAG pins on Port E.

4. Control Register setting is not applicable to Ports A, B and C.

Table 37. I/O Port Latched Address Output Assignments

Port E

(PE3-PE0)

Port E

(PE7-PE4)

Port F

(PF3-PF0)

Port F

(PF7-PF4)

Port G

(PG3-PG0)

Port G

(PG7-PG4)

MCU

Address

(A7-A4)

Address

(A7-A4)

Address

(A11-A8)

Address

(A15-A12)

1

8051XA

80C251

N/A

Address

(A11-A8)

Address

(A7-A4)

N/A

(Page Mode)

All Other

8-Bit Multiplexed

Address

(A3-A0)

Address

(A7-A4)

Address

(A3-A0)

Address

(A7-A4)

Address

(A3-A0)

Address

(A7-A4)

8-Bit

Address

(A3-A0)

Address

(A7-A4)

N/A

Non-Multiplexed Bus

Note: 1. N/A = Not Applicable.

62/102

PSD835G2

Address In Mode

For MCUs that have more than 16 address sig-

nals, the higher addresses can be connected to

Port A, B, C, D or F and are routed as inputs to the

PLDs. The address input can be latched in the In-

put Macrocell (IMC) by Address Strobe (ALE/AS,

PD0). Any input that is included in the DPLD equa-

tions for the SRAM, or primary or secondary Flash

memory is considered to be an address input.

Mode is automatically configured in PSDsoft when

a non-multiplexed bus MCU is selected.

Peripheral I/O Mode

Peripheral I/O mode can be used to interface with

external 8-bit peripherals. In this mode, all of Port

F serves as a tri-state, bi-directional data buffer for

the MCU. Peripheral I/O Mode is enabled by set-

ting Bit 7 of the VM Register to a '1.' Figure 27

shows how Port A acts as a bi-directional buffer for

the MCU data bus if Peripheral I/O Mode is en-

abled. An equation for PSEL0 and/or PSEL1 must

be written in PSDsoft. The buffer is tri-stated when

PSEL0 or PSEL1 is not active.

Data Port Mode

Port F can be used as a data bus port for an MCU

with a non-multiplexed address/data bus. The

Data Port is connected to the data bus of the MCU.

The general I/O functions are disabled in Port F if

the port is configured as a Data Port. Data Port

Figure 27. Peripheral I/O Mode

RD

PSEL0

PSEL

PSEL1

D0-D7

VM REGISTER BIT 7

PF0-PF7

DATA BUS

WR

AI02886b

63/102

PSD835G2

JTAG In-System Programming (ISP)

Drive Select Register

Port E is JTAG compliant, and can be used for In-

System Programming (ISP). You can multiplex

JTAG operations with other functions on Port E

because In-System Programming (ISP) is not per-

formed in normal Operating mode. For more infor-

mation on the JTAG Port, see PROGRAMMING

The Drive Select Register configures the pin driver

as Open Drain or CMOS for some port pins, and

controls the slew rate for the other port pins. An

external pull-up resistor should be used for pins

configured as Open Drain.

A pin can be configured as Open Drain if its corre-

sponding bit in the Drive Select Register is set to a

'1.' The default pin drive is CMOS.

Note that the slew rate is a measurement of the

rise and fall times of an output. A higher slew rate

means a faster output response and may create

more electrical noise. A pin operates at a high slew

rate when the corresponding bit in the Drive Reg-

ister is set to '1.' The default rate is slow slew.

IN-CIRCUIT

INTERFACE, page 76.

Port Configuration Registers (PCR)

USING

THE

JTAG/ISP

Each Port has a set of Port Configuration Regis-

ters (PCR) used for configuration. The contents of

the registers can be accessed by the MCU through

normal READ/WRITE bus cycles at the addresses

given in Table 5., page 19. The addresses in Ta-

ble 5 are the offsets in hexadecimal from the base

of the CSIOP register.

The pins of a port are individually configurable and

each bit in the register controls its respective pin.

For example, Bit 0 in a register refers to Bit 0 of its

port. The three Port Configuration Registers

(PCR), shown in Table 38, are used for setting the

Port configurations. The default Power-up state for

each register in Table 38 is 00h.

Table 42., page 65 shows the Drive Register for

Ports A, B, C, D, E and F. It summarizes which

pins can be configured as Open Drain outputs and

which pins the slew rate can be set for.

Table 38. Port Configuration Registers (PCR)

Register Name

Control

Port

E, F, G

MCU Access

WRITE/READ

Control Register

Direction

A,B,C,D, E, F, G WRITE/READ

Any bit reset to ’0’ in the Control Register sets the

corresponding port pin to MCU I/O Mode, and a ’1’

sets it to Address Out Mode. The default mode is

MCU I/O. Only Ports E, F and G have an associat-

ed Control Register.

1

Drive Select

Note: 1. See Table 42., page 65 for Drive Register bit definition.

Table 39. Port Pin Direction Control, Output

Enable P.T. Not Defined

Direction Register

The Direction Register, in conjunction with the out-

put enable (except for Port D), controls the direc-

tion of data flow in the I/O Ports. Any bit set to ’1’

in the Direction Register causes the correspond-

ing pin to be an output, and any bit set to ’0’ causes

it to be an input. The default mode for all port pins

is input.

Figure 28., page 66 and Figure 29., page 67 show

the Port Architecture diagrams for Ports A/B/C and

E/F/G, respectively. The direction of data flow for

Ports A, B, C and F are controlled not only by the

direction register, but also by the output enable

product term from the PLD AND Array. If the out-

put enable product term is not active, the Direction

Register has sole control of a given pin’s direction.

Direction Register Bit

Port Pin Mode

Input

0

1

Output

Table 40. Port Pin Direction Control, Output

Enable P.T. Defined

Direction

Register Bit

Output Enable

P.T.

Port Pin Mode

0

1

0

1

0

1

Input

Output

An example of a configuration for a Port with the

three least significant bits set to output and the re-

mainder set to input is shown in Table 41. Since

Port D only contains four pins (shown in Figure

29., page 67), the Direction Register for Port D

has only the four least significant bits active.

Table 41. Port Direction Assignment Example

Bit 7 Bit6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0

0

1

64/102

PSD835G2

Table 42. Drive Register Pin Assignment

Drive Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Port A

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Port B

Port C

Port D

Slew

Rate

Slew

Rate

Slew

Rate

Slew

Rate

Slew

Rate

Slew

Rate

Slew

Rate

Slew

Rate

Open

Drain

Open

Drain

Open

Drain

Open

Drain

1

NA

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Port E

Port F

Port G

Slew Rate Slew Rate Slew Rate Slew Rate Slew Rate Slew Rate Slew Rate Slew Rate

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Note: 1. NA = Not Applicable.

Port Data Registers

The Port Data Registers, shown in Table 43, are

used by the MCU to write data to or read data from

the ports. Table 43 shows the register name, the

ports having each register type, and MCU access

for each register type. The registers are described

below.

contents of the register can also be read back by

the MCU.

Output Macrocells (OMC)

The CPLD Output Macrocells (OMC) occupy a lo-

cation in the MCU’s address space. The MCU can

read the output of the Output Macrocells (OMC). If

the OMC Mask Register bits are not set, writing to

the macrocell loads data to the macrocell flip-flops.

See PLDs, page 38.

Data In

Port pins are connected directly to the Data In buff-

er. In MCU I/O input mode, the pin input is read

through the Data In buffer.

OMC Mask Register

Data Out Register

Each OMC Mask Register bit corresponds to an

Output Macrocell (OMC) flip-flop. When the OMC

Mask Register bit is set to a '1,' loading data into

the Output Macrocell (OMC) flip-flop is blocked.

The default value is 0 or unblocked.

Stores output data written by the MCU in the MCU

I/O output mode. The contents of the Register are

driven out to the pins if the Direction Register or

the output enable product term is set to '1.' The

Table 43. Port Data Registers

Register Name

Port

MCU Access

Data In

A, B, C, D, E, F, G READ – input on pin

A, B, C, D, E, F, G WRITE/READ

Data Out

READ – outputs of macrocells

WRITE – loading macrocell flip-flops

Output Macrocell

Mask Macrocell

A, B

WRITE/READ – prevents loading into a given

macrocell

Input Macrocell

Enable Out

A, B, C

READ – outputs of the Input Macrocells

A, B, C, F

READ – the output enable control of the port driver

65/102

PSD835G2

Input Macrocells (IMC)

The Input Macrocells (IMC) can be used to latch or

store external inputs. The outputs of the Input

Macrocells (IMC) are routed to the PLD input bus,

and can be read by the MCU. See PLDs, page 38.

–

MCU I/O Mode

CPLD Output – Macrocells McellA7-McellA0

can be connected to Port A, McellB7-McellB0

can be connected to Port B, External Chip

Select ECS7-ECS0 can be connected to Port

C.

Enable Out

The Enable Out register can be read by the MCU.

It contains the output enable values for a given

port. A ‘1’ indicates the driver is in output mode. A

‘0’ indicates the driver is in tri-state and the pin is

in input mode.

–

CPLD Input – Via the Input Macrocells (IMC).

Address In – Additional high address inputs

using the Input Macrocells (IMC).

Open Drain/Slew Rate – pins PC7-PC0 can be

configured to fast slew rate, pins PA7-PA0 and

PB7-PB0 can be configured to Open Drain

Mode.

–

Ports A,B and C – Functionality and Structure

Ports A and B have similar functionality and struc-

ture, as shown in Figure 28.

The two ports can be configured to perform one or

more of the following functions:

Figure 28. Port A, B and C Structure

DATA OUT

REG.

DATA OUT

D

Q

WR

PORT PIN

OUTPUT

MUX

MCELLA7-MCELLA0 (PORT A)

MCELLB7-MCELLB0 (PORT B)

EXT.CS (PORT C)

READ MUX

P

D

B

OUTPUT

SELECT

DATA IN

ENABLE OUT

DIR REG.

D

Q

WR

(

)

ENABLE PRODUCT TERM .OE

CPLD-INPUT

INPUT

MACROCELL

AI02887b

66/102

PSD835G2

Port D – Functionality and Structure

Port D has four I/O pins. It can be configured to

program one or more of the following functions

(see Figure 29):

Port D pins can be configured in PSDsoft as input

pins for other dedicated functions:

–

PD0 – ALE, as Address Strobe input.

PD1 – CLKIN, as Clock input to the Macrocell

flip-flops and APD counter.

–

MCU I/O Mode

CPLD Input – direct input to CPLD, no Input

Macrocell (IMC).

–

PD2 – CSI, as active Low Chip Select input. A

High input will disable the Flash/SRAM

memories and the CSIOP.

PD3 – as DBE input from 68HC912.

Figure 29. Port D Structure

DATA OUT

REG.

DATA OUT

D

Q

WR

PORT D PIN

OUTPUT

MUX

READ MUX

P

D

B

OUTPUT

SELECT

DATA IN

DIR REG.

D

Q

WR

CPLD-INPUT

AI02888C

67/102

PSD835G2

Port E – Functionality and Structure

Port E can be configured to perform one or more

of the following functions:

–

CPLD Input – as direct input of the CPLD

array.

Address In – addition high address inputs.

Direct input to the CPLD array, no Input

Macrocell (IMC) latching is available.

Latched Address Out – Provide latched

address out per Table 47., page 75.

Slew Rate – pins can be set up for fast slew

rate.

–

MCU I/O Mode

In-System Programming – JTAG port can be

enabled for programming/erase of the PSD

device. Refer to PROGRAMMING IN-CIR-

CUIT USING THE JTAG/ISP

–

INTERFACE, page 76 for more information.

–

Open Drain – Port E pins can be configured in

Open Drain Mode.

Battery Backup features – PE6 can be

Data Port – connected to D7-D0 when Port F

is configured as Data Port for a non-

multiplexed bus.

configured as a Battery Input (V

) pin. PE7

STBY

can be configured as a Battery On Indicator

output pin, indicating when V is less than

–

Peripheral I/O Mode.

CC

Port G – Functionality and Structure

Port G can be configured to perform one or more

of the following functions:

–

V

BAT

.

–

Latched Address Output – Provided latched

address (A7-A0) output.

Port F – Functionality and Structure

Port F can be configured to perform one or more

of the following functions:

MCU I/O Mode

Latched Address Out – Provide latched

address out per Table 47., page 75.

Open Drain – pins can be configured in Open

Drain Mode.

–

MCU I/O Mode

CPLD Output – External Chip Select ECS7-

ECS0 can be connected to Port F (or Port C).

68/102

PSD835G2

Figure 30. Port E, F, G Structure

DATA OUT

REG.

DATA OUT

D

Q

WR

PORT

E, F OR G PIN

ADDRESS

ALE

ADDRESS

A7-A0 OR A15-A8

D

G

Q

OUTPUT

MUX

EXT.CS (PORT F)

READ MUX

P

D

B

OUTPUT

SELECT

DATA IN

CONTROL REG.

ENABLE OUT

D

Q

WR

DIR REG.

D

Q

(

)

ENABLE PRODUCT TERM .OE

CPLD-INPUT

ISP OR BATTERY BACK-UP (PORT E)

CONFIGURATION

BIT

AI02889b

69/102

PSD835G2

POWER MANAGEMENT

The PSD835G2 offers configurable power saving

options. These options may be used individually or

in combinations, as follows:

externally (noise, other devices on the MCU

bus, etc.). Keep in mind that any unblocked

PLD input signals that are changing states

keep the PLD out of Stand-by mode, but not

the memories.

PSD Chip Select Input (CSI, PD2) can be

used to disable the internal memories, placing

them in standby mode even if inputs are

changing. This feature does not block any

internal signals or disable the PLDs. This is a

good alternative to using the APD Unit. There

is a slight penalty in memory access time

when PSD Chip Select Input (CSI, PD2)

makes its initial transition from deselected to

selected.

The PMMRs can be written by the MCU at run-

time to manage power. All PSD devices

support “blocking bits” in these registers that

are set to block designated signals from

reaching both PLDs. Current consumption of

the PLDs is directly related to the composite

frequency of the changes on their inputs (see

Figure 34., page 78). Significant power

savings can be achieved by blocking signals

that are not used in PLD logic equations at

run-time. PSDsoft creates a fuse map that

automatically blocks the low address Byte

(A7-A0) or the Control signals (CNTL0-

CNTL2, ALE and WRH/DBE) if none of these

signals are used in PLD logic equations.

PSD devices have a Turbo Bit in PMMR0. This

bit can be set to turn the Turbo mode off (the

default is with Turbo mode turned on). While

Turbo mode is off, the PLDs can achieve

standby current when no PLD inputs are

changing (zero DC current). Even when inputs

do change, significant power can be saved at

lower frequencies (AC current), compared to

when Turbo mode is on. When the Turbo

mode is on, there is a significant DC current

component and the AC component is higher.

–

All memory blocks in a PSD (primary and

secondary Flash memory, and SRAM) are

built with Power Management technology. In

addition to using special silicon design

methodology, power management technology

puts the memories into standby mode when

address/data inputs are not changing (zero

DC current). As soon as a transition occurs on

an input, the affected memory “wakes up”,

changes and latches its outputs, then goes

back to standby. The designer does not have

to do anything special to achieve memory

standby mode when no inputs are changing—

it happens automatically.

–

The PLD sections can also achieve Stand-by

mode when its inputs are not changing, as

described in the sections on the Power

Management Mode Registers (PMMR).

–

As with the Power Management mode, the

Automatic Power Down (APD) unit allows the

PSD to reduce to standby current

automatically. The APD Unit can also block

MCU address/data signals from reaching the

memories and PLDs. This feature is available

on all the devices of the PSD family. The APD

Unit is described in more detail in Automatic

Power-down (APD) Unit and Power-down

Mode, page 71.

Built-in logic monitors the Address Strobe of

the MCU for activity. If there is no activity for a

certain time period (MCU is asleep), the APD

Unit initiates Power-down mode (if enabled).

Once in Power-down mode, all address/data

signals are blocked from reaching PSD

memory and PLDs, and the memories are

deselected internally. This allows the memory

and PLDs to remain in standby mode even if

the address/data signals are changing state

70/102

PSD835G2

Automatic Power-down (APD) Unit and Power-down Mode

The APD Unit, shown in Figure 31, puts the PSD

into Power-down mode by monitoring the activity

of Address Strobe (ALE/AS, PD0). If the APD Unit

is enabled, as soon as activity on Address Strobe

(ALE/AS, PD0) stops, a four-bit counter starts

counting. If Address Strobe (ALE/AS, PD0) re-

mains inactive for fifteen clock periods of CLKIN

(PD1), Power-down (PDN) goes High, and the

PSD enters Power-down mode, as discussed

next.

Power-down Mode. By default, if you enable the

APD Unit, Power-down mode is automatically en-

abled. The device enters Power-down mode if Ad-

dress Strobe (ALE/AS, PD0) remains inactive for

fifteen periods of CLKIN (PD1).

registers. The blocked signals include MCU

control signals and the common CLKIN (PD1).

Note that blocking CLKIN (PD1) from the

PLDs does not block CLKIN (PD1) from the

APD Unit.

All PSD memories enter Standby mode and

are drawing standby current. However, the

PLD and I/O ports blocks do not go into

Standby Mode because you don’t want to

have to wait for the logic and I/O to “wake-up”

before their outputs can change. See Table 44

for Power-down mode effects on PSD ports.

–

Typical standby current is of the order of

microamperes. These standby current values

assume that there are no transitions on any

PLD input.

The following should be kept in mind when the

PSD is in Power-down mode:

–

If Address Strobe (ALE/AS, PD0) starts

pulsing again, the PSD returns to normal

Operating mode. The PSD also returns to

normal Operating mode if either PSD Chip

Select Input (CSI, PD2) is Low or the Reset

(RESET) input is High.

The MCU address/data bus is blocked from all

memories and PLDs.

Various signals can be blocked (prior to

Power-down mode) from entering the PLDs by

setting the appropriate bits in the PMMR

Table 44. Power-down Mode’s Effect on Ports

Port Function

MCU I/O

Pin Level

No Change

Undefined

Tri-State

PLD Out

–

Address Out

Data Port

Peripheral I/O

Tri-State

Figure 31. APD Unit

APD EN

PMMR0 BIT 1=1

TRANSITION

DETECTION

DISABLE BUS

INTERFACE

ALE

PD

CLR

APD

SECONDARY FLASH SELECT

PRIMARY FLASH SELECT

COUNTER

RESET

EDGE

DETECT

PD

CSI

PLD

SRAM SELECT

POWER DOWN

CLKIN

(

)

PDN SELECT

DISABLE PRIMARY AND

SECONDARY FLASH/SRAM MEMORIES

AI02891b

Table 45. PSD Timing and Stand-by Current during Power-down Mode

5V V

PLD Propagation

Delay

Memory

Access Time

Access Recovery Time to

Normal Access

CC

Mode

Typical Standby Current

1

2

t

Power-down

No Access

Normal t (Note )

LVDV

50µA (Note )

PD

Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.

2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is '0.'

71/102

PSD835G2

Other Power Saving Options

The PSD offers other reduced power saving op-

tions that are independent of the Power-down

mode. Except for the SRAM Standby and Chip Se-

lect Input (CSI, PD2) features, they are enabled by

setting bits in the PMMR0 and PMMR2 registers

(see Table 22., page 22 and Table 23., page 22

for a bit definition of the two registers).

secondary Flash memory, and SRAM, and reduc-

es the PSD power consumption. However, the

PLD and I/O signals remain operational when PSD

Chip Select Input (CSI, PD2) is High.

There may be a timing penalty when using PSD

Chip Select Input (CSI, PD2) depending on the

speed grade of the PSD that you are using. See

PLD Power Management

the timing parameter t

in Table 64., page 93.

SLQV

The power and speed of the PLDs are controlled

by the Turbo Bit (Bit 3) in PMMR0. By setting the

bit to '1,' the Turbo mode is off and the PLDs con-

sume the specified standby current when the in-

puts are not switching for an extended time of

70ns. The propagation delay time is increased af-

ter the Turbo Bit is set to ’1’ (turned off) when the

inputs change at a composite frequency of less

than 15 MHz. When the Turbo Bit is reset to ’0’

(turned on), the PLDs run at full power and speed.

The Turbo Bit affects the PLD’s DC power, AC

power, and propagation delay. Refer to MAXI-

MUM RATING, page 81 for PLD timings.

Input Clock

The PSD provides the option to turn off CLKIN

(PD1) to the PLD to save AC power consumption.

CLKIN (PD1) is an input to the PLD AND Array and

the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is

not being used as part of the PLD logic equation,

the clock should be disabled to save AC power.

CLKIN (PD1) is disconnected from the PLD AND

Array or the Macrocells block by setting Bits 4 or 5

to a ’1’ in PMMR0.

Figure 32. Enable Power-down Flow Chart

Blocking MCU control signals with the bits of

PMMR2 can further reduce PLD AC power con-

sumption.

RESET

SRAM Standby Mode (Battery Backup). The

PSD supports a battery backup mode in which the

contents of the SRAM are retained in the event of

a power loss. The SRAM has a Voltage Standby

Enable APD

Set PMMR0 Bit 1 = 1

pin (V

, PC2) that can be connected to an ex-

STBY

ternal battery. When V

becomes lower than

CC

OPTIONAL

V

then the PSD automatically connects to

STBY

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bit 0.

Voltage Stand-by (V

to the SRAM. The SRAM Standby Current (I

, PC2) as a power source

STBY

)

STBY

is typically 0.5µA. The SRAM data retention volt-

age is 2 V minimum. The Battery-on Indicator

(V

BATON

cates when the V has dropped below V

the SRAM is running on battery power.

PSD Chip Select Input (CSI, PD2)

ALE/AS idle

for 15 CLKIN

clocks?

No

PD2 of Port D can be configured in PSDsoft as the

PSD Chip Select Input (CSI). When Low, the sig-

nal selects and enables the internal (primary)

Flash memory, secondary Flash memory, SRAM,

and I/O blocks for READ or WRITE operations in-

volving the PSD. A High on PSD Chip Select Input

(CSI, PD2) disables the primary Flash memory,

Yes

PSD in Power

Down Mode

AI02892B

72/102

PSD835G2

Input Control Signals

The PSD provides the option to turn off the ad-

dress input (A7-A0) and input control signals

(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/

AS, PD0) and DBE) to the PLD to save AC power

consumption. These signals are inputs to the PLD

AND Array. During Power-down mode, or, if any of

them are not being used as part of the PLD logic

equation, these signals should be disabled to save

AC power. They are disconnected from the PLD

AND Array by setting Bits 0, 2, 3, 4, 5, and 6 to a

‘1’ in PMMR2.

Table 46. APD Counter Operation

APD Enable Bit ALE PD Polarity

ALE Level

APD Counter

Not Counting

0

1

X

1

0

X

Pulsing

Not Counting

1

0

Counting (Generates PDN after 15 Clocks)

73/102

PSD835G2

RESET TIMING AND DEVICE STATUS AT RESET

Power-Up Reset

Upon Power-up, the PSD requires a Reset (RE-

SET) pulse of duration t (1ms minimum)

warm reset. Figure 33 shows the timing of the

Power-up and warm reset.

NLNH-PO

after V

is steady. During this period, the device

CC

I/O Pin, Register and PLD Status at Reset

loads internal configurations, clears some of the

registers and sets the Flash memory into Operat-

ing mode. After the rising edge of Reset (RESET),

the PSD remains in the Reset mode for an addi-

tional period, t

first memory access is allowed.

Table 47., page 75 shows the I/O pin, register and

PLD status during Power-Up Reset, warm reset

and Power-down mode. PLD outputs are always

valid during warm reset, and they are valid in Pow-

er-Up Reset once the internal PSD Configuration

bits are loaded. This loading of PSD is completed

(120ns maximum), before the

OPR

The Flash memory is reset to the READ mode

upon Power-up. Sector Select (FS0-FS7 and

CSBOOT0-CSBOOT3) must all be Low, Write

Strobe (WR, CNTL0) High, during Power-Up Re-

set for maximum security of the data contents and

to remove the possibility of a byte being written on

the first edge of Write Strobe (WR, CNTL0). Any

Flash memory WRITE cycle initiation is prevented

typically long before V

ramps up to operating

CC

level. Once the PLD is active, the state of the out-

puts are determined by the equations specified in

PSDsoft.

Reset of Flash Memory Erase and Program

Cycles

A Reset (RESET) also resets the internal Flash

memory state machine. During a Flash memory

Program or Erase cycle, Reset (RESET) termi-

nates the cycle and returns the Flash memory to

automatically when V is below V

.

CC

LKO

Warm Reset

Once the device is up and running, the device can

be reset with a pulse of a much shorter duration,

the READ mode within a period of t

minimum).

(25µs

NLNH-A

t

(150ns minimum). The same t

period is

NLNH

OPR

needed before the device is operational after

Figure 33. Power-Up and Warm Reset (RESET) Timing

V_CC(min)

V

CC

t

NLNH

t

OPR

t

OPR

NLNH-PO

Power-On Reset

NLNH-A

Warm Reset

RESET

AI02866b

74/102

PSD835G2

Table 47. Status During Power-Up Reset, Warm Reset and Power-down Mode

Port Configuration

MCU I/O

Power-Up Reset

Input mode

Warm Reset

Input mode

Power-down Mode

Unchanged

Valid after internal PSD

configuration bits are

loaded

Depends on inputs to PLD

(addresses are blocked in

PD mode)

PLD Output

Valid

Address Out

Data Port

Tri-stated

Not defined

Tri-stated

Peripheral I/O

Register

Power-Un Reset

Warm Reset

Power-down Mode

PMMR0 and PMMR2

Cleared to ’0’

Unchanged

Cleared to ’0’ by internal

Power-Up Reset

Depends on .re and .pr

equations

Depends on .re and .pr

equations

Macrocells flip-flop status

Initialized, based on the

selection in PSDsoft

Configuration menu

Initialized, based on the

selection in PSDsoft

Configuration menu

1

Unchanged

VM Register

All other registers

Cleared to ’0’

Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to ’0’ on Power-Up Reset or Warm Reset.

75/102

PSD835G2

PROGRAMMING IN-CIRCUIT USING THE JTAG/ISP INTERFACE

The JTAG/ISP Interface block can be enabled on

Port E (see Table 48., page 77). All memory

blocks (primary and secondary Flash memory),

PLD logic, and PSD Configuration Register bits

may be programmed through the JTAG/ISP Inter-

face block. A blank device can be mounted on a

printed circuit board and programmed using

JTAG/ISP.

The standard JTAG signals (IEEE 1149.1) are

TMS, TCK, TDI, and TDO. Two additional signals,

TSTAT and TERR, are optional JTAG extensions

used to speed up Program and Erase cycles.

By default, on a blank PSD (as shipped from the

factory or after erasure), four pins on Port E are

enabled for the basic JTAG signals TMS, TCK,

TDI, and TDO.

See Application Note AN1153 for more details on

JTAG In-System Programming (ISP).

JTAG_ON is false, the four pins can be used for

general PSD I/O.

JTAG_ON = PSDsoft_enabled +

/* An NVM configuration bit inside

the PSD is set by the designer in

the

PSDsoft

Configuration

utility. This dedicates the pins

for JTAG at all times (compliant

with IEEE 1149.1 */

Microcontroller_enabled +

/* The microcontroller can set a

bit at run-time by writing to the

PSD register, JTAG Enable. This

register is located at address

CSIOP + offset C7h. Setting the

JTAG_ENABLE bit in this register

will enable the pins for JTAG use.

This bit is cleared by a PSD reset

or the microcontroller. See Table

20., page 22 for bit definition.

*/

Standard JTAG Signals

PSD_product_term_enabled;

The standard JTAG signals (TMS, TCK, TDI, and

TDO) can be enabled by any of three different con-

ditions that are logically ORed. When enabled,

TDI, TDO, TCK, and TMS are inputs, waiting for a

JTAG serial command from an external JTAG con-

troller device (such as FlashLINK or Automated

Test Equipment). When the enabling command is

received, TDO becomes an output and the JTAG

channel is fully functional inside the PSD. The

same command that enables the JTAG channel

may optionally enable the two additional JTAG sig-

nals, TSTAT and TERR.

The following symbolic logic equation specifies the

conditions enabling the four basic JTAG signals

(TMS, TCK, TDI, and TDO) on their respective

Port E pins. For purposes of discussion, the logic

label JTAG_ON is used. When JTAG_ON is true,

the four pins are enabled for JTAG. When

/* A dedicated product term (PT)

inside the PSD can be used to

enable the JTAG pins. This PT has

the reserved name JTAGSEL. Once

defined as a node in PSDabel, the

designer can write an equation for

JTAGSEL. This method is used when

the Port E JTAG pins are

multiplexed with other I/O

signals. It is recommended to

logically tie the node JTAGSEL to

the JEN\ signal on the Flashlink

cable when multiplexing JTAG

signals. See Application Note 1153

for details. */

The PSD supports JTAG/ISP commands, but not

Boundary Scan. The PSDsoft software tool and

FlashLINK JTAG programming cable implement

the JTAG/ISP commands.

76/102

PSD835G2

JTAG Extensions

Security and Flash memory Protection

TSTAT and TERR are two JTAG extension signals

enabled by an JTAG command received over the

four standard JTAG signals (TMS, TCK, TDI, and

TDO). They are used to speed Program and Erase

cycles by indicating status on PSD signals instead

of having to scan the status out serially using the

standard JTAG channel. See Application Note

AN1153.

When the Security Bit is set, the device cannot be

read on a Device Programmer or through the

JTAG Port. When using the JTAG Port, only a Full

Chip Erase command is allowed.

All other Program, Erase and Verify commands

are blocked. Full Chip Erase returns the part to a

non-secured blank state. The Security Bit can be

set in PSDsoft.

TERR indicates if an error has occurred when

erasing a sector or programming a Byte in Flash

memory. This signal goes Low (active) when an

Error condition occurs, and stays Low until a spe-

cial JTAG command is executed or a chip Reset

All primary and secondary Flash memory sectors

can individually be sector protected against era-

sures. The Sector Protect Bits can be set in PSD-

soft.

(RESET)

“ISC_DISABLE” command.

pulse

is

received

after

an

Table 48. JTAG Port Signals

Port E Pin

PE0

JTAG Signals

TMS

Description

Mode Select

TSTAT behaves the same as Ready/Busy de-

scribed in the section entitled Ready/Busy

(PE4), page 26. TSTAT is High when the PSD de-

vice is in READ mode (primary and secondary

Flash memory contents can be read). TSTAT is

Low when Flash memory Program or Erase cycles

are in progress, and also when data is being writ-

ten to the secondary Flash memory.

PE1

PE2

PE3

PE4

PE5

TCK

Clock

TDI

Serial Data In

Serial Data Out

Status

TDO

TSTAT

TERR

TSTAT and TERR can be configured as open-

drain type signals during a JTAG command.

Error Flag

77/102

PSD835G2

AC/DC PARAMETERS

The tables provided below describe the AD and

DC parameters of the PSD:

The following are issues concerning the parame-

ters presented:

■ DC Electrical Specification

■ AC Timing Specification

–

In the DC specification the supply current is

given for different modes of operation. Before

calculating the total power consumption,

determine the percentage of time that the PSD

is in each mode. Also, the supply power is

considerably different if the Turbo Bit is '0.'

The AC power component gives the PLD,

Flash memory, and SRAM mA/MHz

specification. Figure 34 show the PLD mA/

MHz as a function of the number of Product

Terms (PT) used.

■

PLD Timing

–

Combinatorial Timing

Synchronous Clock Mode

Asynchronous Clock Mode

Input Macrocell Timing

–

■

MCU Timing

–

READ Timing

WRITE Timing

Peripheral Mode Timing

Power-down and Reset Timing

In the PLD timing parameters, add the

required delay when Turbo Bit is '0.'

Figure 34. PLD I /Frequency Consumption

CC

110

100

90

V

= 5V

CC

80

70

60

50

40

30

20

10

0

PT 100%

PT 25%

0

5

10

15

20

25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

AI02894

78/102

PSD835G2

Table 49. Example of PSD Typical Power Calculation at V = 5.0V (with Turbo Mode On)

CC

Conditions

Highest Composite PLD input frequency

(Freq PLD)

= 8 MHz

= 4 MHz

MCU ALE frequency (Freq ALE)

% Flash memory Access = 80%

% SRAM access

% I/O access

= 15%

= 5% (no additional power above base)

Operational Modes

% Normal

% Power-down Mode

Number of product terms used

(from fitter report)

= 10%

= 90%

= 45 PT

% of total product terms = 45/193 = 23.3%

Turbo Mode

= ON

Calculation (using typical values)

= Ipwrdown x %pwrdown + %normal x (I (ac) + I (dc))

I

total

CC

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE

+ %SRAM x 1.5mA/MHz x Freq ALE

+ % PLD x 2mA/MHz x Freq PLD

+ #PT x 400µA/PT)

= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz

+ 0.15 x 1.5mA/MHz x 4 MHz

+ 2mA/MHz x 8 MHz

+ 45 x 0.4mA/PT)

= 45µA + 0.1 x (8 + 0.9 + 16 + 18mA)

= 45µA + 0.1 x 42.9

= 45µA + 4.29mA

= 4.34mA

This is the operating power with no Flash memory WRITE or Erase cycles in progress.

Calculation is based on I = 0mA.

OUT

79/102

PSD835G2

Table 50. Example of PSD Typical Power Calculation at V = 5.0V (with Turbo Mode Off)

CC

Conditions

Highest Composite PLD input frequency

(Freq PLD)

= 8 MHz

= 4 MHz

MCU ALE frequency (Freq ALE)

% Flash memory Access = 80%

% SRAM access

% I/O access

= 15%

= 5% (no additional power above base)

Operational Modes

% Normal

% Power-down Mode

Number of product terms used

(from fitter report)

= 10%

= 90%

= 45 PT

% of total product terms = 45/193 = 23.3%

Turbo Mode

= Off

Calculation (using typical values)

= Ipwrdown x %pwrdown + %normal x (I (ac) + I (dc))

I

total

CC

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE

+ %SRAM x 1.5mA/MHz x Freq ALE

+ % PLD x (from graph using Freq PLD))

= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz

+ 0.15 x 1.5mA/MHz x 4 MHz

+ 24mA)

= 45µA + 0.1 x (8 + 0.9 + 24)

= 45µA + 0.1 x 32.9

= 45µA + 3.29mA

= 3.34mA

This is the operating power with no Flash memory WRITE or Erase cycles in progress.

Calculation is based on I = 0mA.

OUT

80/102

PSD835G2

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings” table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 51. Absolute Maximum Ratings

Symbol

Parameter

Min.

Max.

125

235

7.0

Unit

°C

V

T

Storage Temperature

Lead Temperature during Soldering (20 seconds max.)

–65

STG

1

T

LEAD

V

IO

Input and Output Voltage (Q = V

Supply Voltage

or Hi-Z)

OH

–0.6

V

CC

7.0

V

Device Programmer Supply Voltage

Electrostatic Discharge Voltage (Human Body model)

–0.6

14.0

2000

V

PP

2

V

ESD

–2000

V

Note: 1. IPC/JEDEC J-STD-020A

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

81/102

PSD835G2

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Designers should check that the operating

conditions in their circuit match the measurement

conditions when relying on the quoted parame-

ters.

Table 52. Operating Conditions

Symbol

Parameter

Min.

4.5

–40

0

Max.

5.5

85

Unit

V

CC

Supply Voltage

Ambient Operating Temperature (industrial)

Ambient Operating Temperature (commercial)

°C

T

A

70

Table 53. AC Signal Letters for PLD Timing

Table 54. AC Signal Behavior Symbols for PLD

Timing

A

C

D

E

I

Address Input

CEout Output

Input Data

t

Time

L

Logic Level Low or ALE

Logic Level High

Valid

H

V

X

Z

E Input

Interrupt Input

ALE Input

No Longer a Valid Logic Level

Float

L

N

P

Q

R

S

T

RESET Input or Output

Port Signal Output

Output Data

PW

Pulse Width

Note: Example: t

= Time from Address Valid to ALE Invalid.

AVLX

UDS, LDS, DS, RD, PSEN Inputs

Chip Select Input

R/W Input

W

B

WR Input

V

STBY

Output

M

Output Macrocell

Note: Example: t

= Time from Address Valid to ALE Invalid.

AVLX

Table 55. AC Measurement Conditions

Symbol

Parameter

Min.

Max.

Unit

C

Load Capacitance

30

pF

L

Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.

Table 56. Capacitance

2

Symbol

Parameter

Test Condition

Max.

Unit

pF

Typ.

C

V

= 0V

Input Capacitance (for input pins)

4

8

6

IN

Output Capacitance (for input/

output pins)

pF

C

V

OUT

12

25

OUT

C

Capacitance (for CNTL2/V

)

PP

V = 0V

PP

pF

18

VPP

Note: 1. Sampled only, not 100% tested.

2. Typical values are for T = 25°C and nominal supply voltages.

A

82/102

PSD835G2

Figure 35. AC Measurement I/O Waveform

Figure 36. AC Measurement Load Circuit

2.01 V

3.0V

195 Ω

Test Point

1.5V

Device

Under Test

0V

C_L= 30 pF

(Including Scope and

AI03103b

Jig Capacitance)

AI03104b

Figure 37. Switching Waveforms – Key

INPUTS

OUTPUTS

WAVEFORMS

STEADY INPUT

STEADY OUTPUT

MAY CHANGE FROM

HI TO LO

WILL BE CHANGING

FROM HI TO LO

MAY CHANGE FROM

LO TO HI

WILL BE CHANGING

LO TO HI

DON'T CARE

CHANGING, STATE

UNKNOWN

OUTPUTS ONLY

CENTER LINE IS

TRI-STATE

AI03102

83/102

PSD835G2

Table 57. DC Characteristics

Test Condition

(in addition to those in

Table 52., page 82)

Symbol

Parameter

Min.

Typ.

Max.

+0.5

Unit

V

4.5V < V < 5.5V

V

Input High Voltage

2

V

IH

CC

V

4.5V < V < 5.5V

Input Low Voltage

–0.5

0.8

+ 0.5

IL

CC

1

0.8V

Reset High Level Input Voltage

IH1

CC

(Note )

1

0.2V –0.1

Reset Low Level Input Voltage

Reset Pin Hysteresis

–0.5

0.3

V

IL1

CC

(Note )

HYS

V

(min) for Flash Erase and

CC

V

2.5

4.2

V

LKO

OL

Program

I

= 20µA, V = 4.5V

0.01

0.25

4.49

3.9

0.1

V

OL

CC

Output Low Voltage

I

= 8mA, V = 4.5V

0.45

OL

CC

I

= –20µA, V = 4.5V

4.4

2.4

V

OH

CC

Output High Voltage Except

V

OH

V

STBY

On

I

= –2mA, V = 4.5V

V

OH

CC

V

I

Output High Voltage V

On

I

= –1µA

V

– 0.8

STBY

V

OH1

STBY

OH1

V

SRAM Stand-by Voltage

SRAM Stand-by Current

2.0

V

STBY

CC

V

= 0V

0.5

1

µA

V

STBY

IDLE

CC

I

Idle Current (V

input)

V

> V

CC STBY

–0.1

2

0.1

STBY

V

I

Only on V

STBY

SRAM Data Retention Voltage

DF

CSI > V – 0.3V

CC

Stand-by Supply Current

for Power-down Mode

100

200

µA

SB

2,3,5

(Notes

)

I

V

< V < V

SS IN CC

Input Leakage Current

Output Leakage Current

–1

±0.1

±5

1

µA

LI

0.45 < V < V

CC

–10

10

LO

IN

PLD_TURBO = Off,

0

µA/PT

mA

3

f = 0 MHz (Note )

PLD Only

PLD_TURBO = On,

f = 0 MHz

400

15

700

30

Operating

Supply

Current

I

(DC)

5

CC

During Flash memory

WRITE/Erase Only

(Note )

Flash memory

Read only, f = 0 MHz

f = 0 MHz

0

mA

SRAM

Figure 34

PLD AC Base

4

(note )

I

(AC)

5

CC

mA/

MHz

Flash memory AC Adder

SRAM AC Adder

2.5

1.5

3.5

3.0

(Note )

mA/

MHz

Note: 1. Reset (Reset) has hysteresis. V is valid at or below 0.2V –0.1. V

is valid at or above 0.8V

.

IL1

CC

IH1

CC

2. CSI deselected or internal Power-down mode is active.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Please see Figure 34 for the PLD current calculation.

5. I

= 0mA

OUT

84/102

PSD835G2

Figure 38. Input to Output Disable / Enable

INPUT

tER

tEA

INPUT TO

OUTPUT

ENABLE/DISABLE

AI02863

Figure 39. Combinatorial Timing – PLD

CPLD INPUT

tPD

CPLD OUTPUT

AI07655

Table 58. CPLD Combinatorial Timing

-70

-90

Slew

PT

Aloc

Turbo

Off

Symbol

Parameter

Conditions

Unit

1

rate

Min Max Min Max

CPLD Input Pin/Feedback to

CPLD Combinatorial Output

t

20

21

25

26

+ 2

+ 12

– 2

ns

PD

CPLD Input to CPLD Output

Enable

t

EA

CPLD Input to CPLD Output

Disable

ER

CPLD Register Clear or

Preset Delay

ARP

CPLD Register Clear or

Preset Pulse Width

t

10

20

ns

ARPW

ARD

CPLD Array Delay

Any macrocell

11

16

+ 2

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

85/102

PSD835G2

Table 59. CPLD Macrocell Synchronous Clock Mode Timing

-70

-90

Max

Slew

PT

Aloc

Turbo

Off

Symbol

Parameter

Conditions

Unit

1

rate

Min Max Min

Maximum Frequency

External Feedback

1/(t +t

)

34.4

30.30

43.48

50.00

MHz

S

CO

Maximum Frequency

f

1/(t +t –10)

S CO

52.6

83.3

MAX

Internal Feedback (f

)

CNT

Maximum Frequency

Pipelined Data

1/(t +t

)

CH CL

t

Input Setup Time

Input Hold Time

14

0

15

0

+ 2

+ 12

ns

S

H

Clock High Time

Clock Low Time

Clock Input

Any macrocell

6

10

CH

CL

CO

ARD

MIN

6

Clock to Output Delay

CPLD Array Delay

15

11

18

16

– 2

+ 2

2

t +t

CH CL

12

20

Minimum Clock Period

Note: 1. Fast Slew Rate output available on Ports C and F.

2. CLKIN (PD1) t = t + t

.

CL

CLCL

CH

Table 60. CPLD Macrocell Asynchronous Clock Mode Timing

-70

-90

PT

Aloc

Turbo Slew

Symbol

Parameter

Conditions

Unit

Off

Rate

Min

Max Min

Max

Maximum

1/(t +t

)

Frequency

38.4

26.32

MHz

SA COA

External Feedback

Maximum

Frequency

Internal Feedback

f

1/(t +t

–10)

62.5

47.6

35.71

37.3

MHz

MAXA

SA COA

(f

)

CNTA

Maximum

Frequency

Pipelined Data

1/(t

+t

)

CHA CLA

t

Input Setup Time

Input Hold Time

6

7

8

+ 2

+ 12

ns

SA

HA

12

Clock Input High

Time

t

9

12

15

+ 12

ns

CHA

CLA

Clock Input Low

Time

12

Clock to Output

Delay

t

21

11

28

30

16

– 2

ns

COA

CPLD Array Delay

Any macrocell

+ 2

ARDA

MINA

Minimum Clock

Period

1/f

CNTA

16

86/102

PSD835G2

Figure 40. Synchronous Clock Mode Timing – PLD

t

CL

CH

CLKIN

INPUT

t

S

t

H

t

CO

REGISTERED

OUTPUT

AI02860

Figure 41. Asynchronous Reset / Preset

tARPW

RESET/PRESET

INPUT

tARP

REGISTER

OUTPUT

AI02864

Figure 42. Asynchronous Clock Mode Timing (Product Term Clock)

tCHA

tCLA

CLOCK

INPUT

tSA

tHA

tCOA

REGISTERED

OUTPUT

AI02859

87/102

PSD835G2

Figure 43. Input Macrocell Timing (Product Term Clock)

t

INL

INH

PT CLOCK

INPUT

t

IH

IS

OUTPUT

t

INO

AI03101

Table 61. Input Macrocell Timing

-70

-90

PT

Aloc

Turbo

Off

Symbol

Parameter

Input Setup Time

Conditions

Unit

Min Max Min Max

1

t

0

15

9

0

ns

IS

(Note )

1

Input Hold Time

20

12

+ 12

IH

(Note )

1

NIB Input High Time

NIB Input Low Time

INH

INL

(Note )

1

9

(Note )

NIB Input to Combinatorial

Delay

1

t

34

46

+ 2

+ 12

ns

INO

(Note )

Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t

and t

.

LXAX

AVLX

88/102

PSD835G2

Figure 44. READ Timing

1

t

LXAX

t

AVLX

ALE/AS

t

LVLX

A/D

MULTIPLEXED

BUS

ADDRESS

VALID

DATA

VALID

t

AVQV

ADDRESS

NON-MULTIPLEXED

BUS

ADDRESS

VALID

DATA

NON-MULTIPLEXED

BUS

DATA

VALID

t

SLQV

CSI

t

RLQV

t

RHQX

RLRH

RD

(PSEN, DS)

tRHQZ

t

EHEL

E

t

THEH

t

ELTL

R/W

t

AVPV

ADDRESS OUT

AI02895

Note: 1. t

and t

are not required for 80C51XA in Burst Mode.

LXAX

AVLX

89/102

PSD835G2

Table 62. READ Timing

Symbol

-70

-90

Turbo

Off

Parameter

Conditions

Unit

Min Max Min Max

t

ALE or AS Pulse Width

15

4

20

6

ns

LVLX

AVLX

LXAX

AVQV

SLQV

3

Address Setup Time

(Note )

3

Address Hold Time

7

8

(Note )

3

Address Valid to Data Valid

CS Valid to Data Valid

RD to Data Valid 8-Bit Bus

70

75

24

90

100

32

+ 12

(Note )

5

(Note )

t

RLQV

RD or PSEN to Data Valid

8-Bit Bus, 8031, 80251

2

31

38

ns

(Note )

1

t

RD Data Hold Time

RD Pulse Width

0

ns

RHQX

RLRH

(Note )

1

27

32

(Note )

1

t

RD to Data High-Z

20

25

ns

RHQZ

EHEL

THEH

ELTL

(Note )

E Pulse Width

27

6

32

10

0

R/W Setup Time to Enable

R/W Hold Time After Enable

0

Address Input Valid to

Address Output Delay

4

t

20

25

ns

AVPV

(Note )

Note: 1. RD timing has the same timing as DS and PSEN signals.

2. RD and PSEN have the same timing.

3. Any input used to select an internal PSD function.

4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.

5. RD timing has the same timing as DS signal.

90/102

PSD835G2

Figure 45. WRITE Timing

t

LXAX

AVLX

ALE/AS

t

LVLX

A/D

MULTIPLEXED

BUS

ADDRESS

VALID

DATA

VALID

t

AVWL

ADDRESS

NON-MULTIPLEXED

BUS

ADDRESS

VALID

DATA

NON-MULTIPLEXED

BUS

DATA

VALID

t

SLWL

CSI

t

DVWH

WHDX

t

WR

WLWH

t

WHAX

(DS)

t

EHEL

E

t

THEH

ELTL

R/ W

t

WLMV

t

AVPV

WHPV

STANDARD

MCU I/O OUT

ADDRESS OUT

AI02896

91/102

PSD835G2

Table 63. WRITE Timing

Symbol

-70

-90

Parameter

Conditions

Unit

Min Max Min Max

t

ALE or AS Pulse Width

15

4

20

6

ns

LVLX

AVLX

LXAX

1

Address Setup Time

Address Hold Time

(Note )

1

7

8

(Note )

Address Valid to Leading

Edge of WR

1,3

t

8

15

ns

AVWL

(Notes

)

3

t

CS Valid to Leading Edge of WR

WR Data Setup Time

12

25

4

15

35

5

ns

SLWL

(Note )

3

DVWH

WHDX

WLWH

WHAX1

(Note )

3,7

WR Data Hold Time

(Note

)

3

WR Pulse Width

28

6

35

8

(Note )

3

Trailing Edge of WR to Address Invalid

(Note )

Trailing Edge of WR to DPLD Address

Invalid

3,6

t

0

ns

WHAX2

WHPV

(Note

)

Trailing Edge of WR to Port Output

Valid Using I/O Port Data Register

3

27

42

30

55

(Note )

Data Valid to Port Output Valid

Using Macrocell Register

Preset/Clear

3,5

t

ns

DVMV

(Notes

)

Address Input Valid to Address

Output Delay

2

t

20

48

25

55

ns

AVPV

(Note )

WR Valid to Port Output Valid Using

Macrocell Register Preset/Clear

3,4

WLMV

(Notes

)

Note: 1. Any input used to select an internal PSD function.

2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.

3. WR has the same timing as E and DS signals.

4. Assuming data is stable before active WRITE signal.

5. Assuming WRITE is active before data becomes valid.

6. t

7. t

is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

WHAX2

is 6ns when writing to Output Macrocell Registers AB and BC.

WHDX

92/102

PSD835G2

Figure 46. Peripheral I/O Read Timing

ALE/AS

ADDRESS

DATA VALID

A/D BUS

t

(PF)

AVQV

t

SLQV

CSI

RD

t

(PF)

RLQV

t

(PF)

QXRH

RHQZ

RLRH

t

(PF)

DVQV

DATA ON PORT F

AI02897b

Table 64. Port F Peripheral Data Mode Read Timing

-70

-90

Turbo

Off

Symbol

Parameter

Conditions

Unit

Min Max Min Max

Address Valid to Data

Valid

3

t

30

35

+ 12

ns

AVQV–PF

(Note )

CSI Valid to Data Valid

RD to Data Valid

25

21

31

22

35

32

38

30

ns

SLQV–PF

RLQV–PF

1,4

(Notes

)

t

RD to Data Valid 8031 Mode

Data In to Data Out Valid

RD Data Hold Time

RD Pulse Width

t

DVQV–PF

QXRH–PF

RLRH–PF

0

1

27

32

(Note )

1

t

RD to Data High-Z

23

25

ns

RHQZ–PF

(Note )

93/102

PSD835G2

Figure 47. Peripheral I/O Write Timing

ALE/AS

ADDRESS

DATA OUT

A/D BUS

tWHQZ (PF)

tWLQV (PF)

WR

tDVQV (PF)

PORT F

DATA OUT

AI02898B

Table 65. Port F Peripheral Data Mode Write Timing

-70

-90

Symbol

Parameter

Conditions

Unit

Min Max Min Max

2

t

WR to Data Propagation Delay

Data to Port A Data Propagation Delay

WR Invalid to Port A Tri-state

25

22

20

35

30

25

ns

WLQV–PF

DVQV–PF

WHQZ–PF

(Note )

5

(Note )

2

(Note )

Note: 1. RD has the same timing as DS and PSEN.

2. WR has the same timing as the E and DS signals.

3. Any input used to select Port F Data Peripheral mode.

4. Data is already stable on Port F.

5. Data stable on ADIO pins to data on Port F.

Table 66. Program, Write and Erase Times

Symbol

Parameter

Min.

Typ.

Max.

30

Unit

Flash Program

8.5

3

s

1

s

Flash Bulk Erase (pre-programmed to “00”)

Flash Bulk Erase (not pre-programmed)

Sector Erase (pre-programmed)

Sector Erase (not pre-programmed to “00”)

Byte Program

10

1

t

30

s

WHQV3

WHQV2

WHQV1

2.2

14

s

1200

µs

cycles

µs

ns

Program / Erase Cycles (per Sector)

Sector Erase Time-Out

100,000

t

100

WHWLO

Q7VQV

2

30

DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

Note: 1. Programmed to all zero before erase.

2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

94/102

PSD835G2

Table 67. Power-down Timing

-70

-90

Symbol

Parameter

Conditions

Unit

Min Max Min Max

t

ALE Access Time from Power-down

80

90

ns

µs

LVDV

Maximum Delay from

APD Enable to Internal PDN Valid Signal

1

Using CLKIN (PD1)

CLWH

15 * t

CLCL

Note: 1. t

is the period of CLKIN (PD1).

CLCL

Figure 48. Reset (RESET) Timing

V_CC(min)

V

CC

t

NLNH

t

OPR

t

OPR

NLNH-PO

NLNH-A

Power-On Reset

Warm Reset

RESET

AI02866b

Table 68. Reset (Reset) Timing

Symbol

Parameter

Conditions

Min

150

1

Max

Unit

ns

1

t

NLNH

RESET Active Low Time

Power On Reset Active Low Time

ms

µs

NLNH–PO

NLNH–A

OPR

2

25

Warm Reset

RESET High to Operational Device

120

ns

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ mode.

Table 69. V

Symbol

Timing

STBYON

Parameter

Detection to V Output High

STBYON

Conditions

Min

Typ

20

Max

Unit

µs

1

t

V

STBY

BVBH

(Note )

1

t

V

STBY

Off Detection to V

Output Low

STBYON

20

µs

BXBL

(Note )

Note: 1. V

timing is measured at V ramp rate of 2 ms.

CC

STBYON

95/102

PSD835G2

Figure 49. ISC Timing

t_ISCCH

TCK

t_ISCCL

t_ISCPSU

t_ISCPH

TDI/TMS

t _ISCPZV

t_ISCPCO

ISC OUTPUTS/TDO

t_ISCPVZ

ISC OUTPUTS/TDO

AI02865

Table 70. ISC Timing

Symbol

-70

-90

Parameter

Conditions

Unit

Min Max Min Max

1

t

Clock (TCK, PC1) Frequency (except for PLD)

Clock (TCK, PC1) High Time (except for PLD)

Clock (TCK, PC1) Low Time (except for PLD)

Clock (TCK, PC1) Frequency (PLD only)

Clock (TCK, PC1) High Time (PLD only)

20

18

MHz

ns

ISCCF

(Note )

1

23

26

ISCCH

ISCCL

(Note )

1

ns

(Note )

2

MHz

ns

ISCCFP

ISCCHP

(Note )

2

240

(Note )

2

t

Clock (TCK, PC1) Low Time (PLD only)

ISC Port Set Up Time

240

6

240

8

ns

ISCCLP

ISCPSU

ISCPH

(Note )

ISC Port Hold Up Time

5

ISC Port Clock to Output

21

23

ISCPCO

ISCPZV

ISC Port High-Impedance to Valid Output

ISC Port Valid Output to

High-Impedance

t

21

23

ns

ISCPVZ

Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

2. For Program or Erase PLD only.

96/102

PSD835G2

PACKAGE MECHANICAL

Figure 50. TQFP80 - 80 lead Thin, Quad, Flat Package Outline

D

D1

D2

A2

e

b

Ne

E2 E1 E

N

1

Nd

A

CP

L1

c

A1

α

L

QFP-A

Note: Drawing is not to scale.

97/102

PSD835G2

Table 71. TQFP80 - 80 lead Thin, Quad, Flat Package Mechanical Data

mm

inches

Min.

Symb.

Typ.

Min.

Max.

1.20

0.15

1.05

0.27

0.20

Typ.

Max.

0.047

0.006

0.041

0.011

0.008

A

A1

A2

b

0.05

0.95

0.17

0.09

0.002

0.037

0.007

0.004

0.22

0.009

c

D

14.00

12.00

9.50

14.00

12.00

9.50

0.50

0.60

1.00

0.08

3.5°

0.551

0.472

0.374

0.551

0.472

0.374

0.020

0.024

0.039

0.003

3.5°

D1

D2

E

—

E1

E2

e

—

L

0.45

0.75

0.018

0.030

L1

CP

α

0.0°

80

7.0°

0.0°

80

7.0°

N

Nd

Ne

20

98/102

PSD835G2

PART NUMBERING

Table 72. Ordering Information Scheme

Example:

PSD8

3

5

G

2

–

90

U

I

T

Device Type

PSD8 = 8-bit PSD with Register Logic

SRAM Size

3 = 64 Kbit

Flash Memory Size

5 = 4 Mbit (512 Kb x8)

I/O Count

G = 52 I/O

2nd Flash Memory

2 = 256 Kbit (32 Kb x8) Flash Memory

Operating Voltage

blank = V = 4.5 to 5.5V

CC

(1)

V

= V = 3.0 to 3.6V

CC

Speed

70 = 70ns

90 = 90ns

Package

U = TQFP80

Temperature Range

blank = 0 to 70°C (Commercial)

I = –40 to 85°C (Industrial)

Shipping Option

T = Tape & Reel Packing

Note: 1. The 3.3V ±10% devices are not covered by this datasheet, but by the PSD835G2V datasheet.

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

99/102

PSD835G2

APPENDIX A. PIN ASSIGNMENTS

Table 73. PSD835G2 TQFP80

Pin No. Assignments

1

2

PD2

PD3

AD0

AD1

AD2

AD3

AD4

GND

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

GND

PA0

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

3

4

5

6

7

8

V

CC

V

CC

V

CC

9

10

11

12

13

14

15

16

17

18

19

20

AD5

AD6

GND

PF0

GND

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PD0

PD1

AD7

PF1

PA1

AD8

PF2

PA2

AD9

PF3

PA3

AD10

AD11

AD12

AD13

AD14

AD15

PF4

PA4

PF5

PA5

PF6

PA6

PF7

PA7

RESET

CNTL2

CNTL0

CNTL1

100/102

PSD835G2

REVISION HISTORY

Table 74. Document Revision History

Date

Version

Description of Revision

01-Mar-2000

1.0

PSD835G2: Document written in the WSI format. Initial release.

Turbo Off changed from +10 to +12 in Table 58, CPLD Combinatorial Timing, Table 59,

CPLD Macrocell Synchronous Clock Mode Timing, Table 60, CPLD Macrocell

Asynchronous Clock Mode Timing, Table 61, Input Macrocell Timing, Table 62, Read

Timing, Table 64, Port F Peripheral Data Mode Read Timing.

t

max for 70ns speed class changed from 13 to 15 in Table 59.

CO

t

min and t min for 70ns speed class changed from 5 to 7 and 9 to 12, respectively

CLA

30-Nov-2000

1.1

HA

and t

min for 90ns speed class changed from 12 to 15 in Table 60.

CLA

t

min changed for 70ns speed class changed from 5 to 7 in Table 62.

LXAX

min changed for 70ns speed class changed from 5 to 7, t

min for 70ns speed

LXAX

DVWH

class changed from 12 to 25, t

Table 63.

min for 70ns speed class changed from 25 to 28 in

WLWH

PSD835G2: Configurable Memory System on a Chip for 8-bit Microcontrollers.

Front page and back two pages in ST format added to the PDF file.

Any references to Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST,

Flash+PSD and PSDsoft.

31-Jan-2002

1.2

11-Sep-2002

03-Mar-04

2.0

3.0

Document reformatted. No parameters changed.

Document reformatted; mechanical dimensions corrected (Table 71)

101/102

PSD835G2

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequ

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is g

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are s

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products a

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectron

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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102/102


型号：	PSD835G2-70UIT
厂家：	ST
描述：	Flash PSD, 5V Supply, for 8-bit MCUs 4 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM 闪存PSD ， 5V电源， 8位MCU的4兆位+ 256千双快闪记忆体和64 Kbit的SRAM 闪存静态存储器
文件：	总102页 (文件大小：1452K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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