RHFL6000AKP02V [STMICROELECTRONICS]
2 A rad-hard adjustable positive voltage regulator;
| 型号： | RHFL6000AKP02V |
| 厂家： | 
ST |
| 描述： | 2 A rad-hard adjustable positive voltage regulator |
| 文件： | 总31页 (文件大小：1158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RHFL6000A
2 A rad-hard adjustable positive voltage regulator
Datasheet - preliminary data
Rad-hard: guaranteed up to 300 krad MIL-
STD-883J Method 1019.9 high dose rate
and 0.01 rad/s in ELDRS conditions
Radiation environment (SET/SEL/SEB):
- SEL free @ LET=120 MeV*cm2/mg
- SET: less than 3.3% of VOUT @ 120 MeV
Heavy Ions SET dedicated internal circuitry
implemented for absorbing output transient
Operating junction temperature range: -55
°C to 125 °C
Description
The RHFL6000A high-performance adjustable
positive voltage regulator provides exceptional
radiation performance. It is tested in accordance
with MIL-STD-883J Method 1019.9, in ELDRS
conditions. The device is available in the FLAT-
16P, a hermetic ceramic package, and the QML-
V die is specifically designed for space and harsh
radiation environments. A dedicated internal
circuitry is implemented for absorbing output
transients during SET events. The operating
input voltage goes from 2.5 V to 12 V.
Features
Input voltage range from 2.5 V to 12 V
2 A guaranteed output current
Low dropout voltage: 0.3 V typ. @ 0.4 A
Embedded overtemperature and overcurrent
protection
Adjustable overcurrent limitation
Output overload monitoring/signalling
Adjustable output voltage
Internal control loop accessible via an
external pin, optional
Inhibit (ON/OFF) TTL compatible control
Programmable output short-circuit current
Remote sensing operation
Table 1: Device summary
Quality level EPPL
Device
Package
Lead finish
Gold
Mass (g)
RHFL6000AKP1
RHFL6000AKP01V (1)
RHFL6000AKP02V (1)
Engineering model
QML-V Flight
-
Target
Target
FLAT-16P
0.70
QML-V Flight
Tin
Notes:
(1)Qualification ongoing.
Contact ST sales office for information about the specific conditions for products in die form and other quality
levels.
October 2015
DocID028379 Rev 2
1/31
www.st.com
This is preliminary information on a new product now in development
or undergoing evaluation. Details are subject to change without notice.
Contents
RHFL6000A
Contents
1
2
3
4
5
6
Diagram............................................................................................5
Pin configuration.............................................................................6
Maximum ratings.............................................................................8
Electrical characteristics ................................................................9
Typical application diagram .........................................................12
Radiations......................................................................................13
6.1
6.2
Total ionizing dose (MIL-STD-883 test method 1019).....................13
Heavy Ions ......................................................................................14
7
8
Additional guidelines for SET mitigation.....................................16
7.1
7.2
Ground connections........................................................................16
Capacitor selection..........................................................................16
Device description.........................................................................17
8.1
8.2
8.3
8.4
8.5
8.6
8.7
ADJ pin ...........................................................................................17
Inhibit ON-OFF control....................................................................17
Overtemperature protection ............................................................17
Overcurrent protection ....................................................................17
OCM pin..........................................................................................17
STAB pin.........................................................................................18
FILT C pin .......................................................................................18
9
Application information ................................................................19
9.1
9.2
Notes on the 16-pin hermetic flat package......................................20
FPGA supply...................................................................................20
10 Typical performance characteristics ...........................................21
11 Package information .....................................................................26
11.1
FLAT-16P package information.......................................................26
12 Ordering information.....................................................................28
12.1
12.3
Traceability information...................................................................28
Documentation................................................................................29
13 Revision history ............................................................................30
2/31
DocID028379 Rev 2
RHFL6000A
List of tables
List of tables
Table 1: Device summary...........................................................................................................................1
Table 2: Pin description ..............................................................................................................................7
Table 3: Absolute maximum ratings ...........................................................................................................8
Table 4: Thermal data.................................................................................................................................8
Table 5: Electrical characteristics ...............................................................................................................9
Table 6: TID tests results..........................................................................................................................13
Table 7: Heavy ions results ......................................................................................................................14
Table 8: Bias configurations .....................................................................................................................15
Table 9: Test configurations .....................................................................................................................15
Table 10: Flat-16P package mechanical data ..........................................................................................27
Table 11: Order code................................................................................................................................28
Table 12: Date codes................................................................................................................................28
Table 13: Table of documentation by product ..........................................................................................29
Table 14: Document revision history ........................................................................................................30
DocID028379 Rev 2
3/31
List of figures
RHFL6000A
List of figures
Figure 1: Block diagram..............................................................................................................................5
Figure 2: Pin configuration (top view) .........................................................................................................6
Figure 3: Typical application diagram.......................................................................................................12
Figure 4: Heavy Ions test configuration ....................................................................................................14
Figure 5: Output voltage vs temperature ..................................................................................................21
Figure 6: Output voltage vs temperature ..................................................................................................21
Figure 7: Output voltage vs temperature ..................................................................................................21
Figure 8: Output voltage vs temperature ..................................................................................................21
Figure 9: Line regulation vs temperature..................................................................................................22
Figure 10: Load regulation vs temperature (IOUT = 5 mA to 400 mA) .......................................................22
Figure 11: Load regulation vs temperature (IOUT = 5 mA to 1 A, VIN = 2.5 V............................................22
Figure 12: Dropout voltage vs. temperature (IOUT = 0.4 A) .......................................................................22
Figure 13: Dropout voltage vs temperature (IOUT = 1 A) ...........................................................................23
Figure 14: Dropout voltage vs temperature (IOUT = 2 A) ...........................................................................23
Figure 15: Quiescent current (OFF mode)................................................................................................23
Figure 16: Quiescent current (ON mode, IOUT = 5 mA).............................................................................23
Figure 17: Quiescent current (ON mode, IOUT = 1 A)................................................................................24
Figure 18: Quiescent current (ON mode, IOUT = 2 A)................................................................................24
Figure 19: Short circuit current vs RSHORT .................................................................................................24
Figure 20: SVR vs frequency....................................................................................................................24
Figure 21: SVR vs frequency (T = 90 °C).................................................................................................24
Figure 22: Turn on transient .....................................................................................................................24
Figure 23: Turn off transient .....................................................................................................................25
Figure 24: Line transient (IOUT = 0.8 A, VOUT = 3 V) ..................................................................................25
Figure 25: Line transient (IOUT = 2 A, VOUT = 2.5 V) ..................................................................................25
Figure 26: Load transient..........................................................................................................................25
Figure 27: Stability area for ceramic capacitor .........................................................................................25
Figure 28: Stability area for tantalum capacitor ........................................................................................25
Figure 29: Flat-16P package outline.........................................................................................................26
4/31
DocID028379 Rev 2
RHFL6000A
Diagram
1
Diagram
Figure 1: Block diagram
V
I
A
B
start-up/
curr.gen.
FILT _C
error
bandgap
V
O
am pl.
d rive r
INHIBIT
ON-OFF
control
STAB
R2 (ext.)
I
SC
A
B
overload prot.
ADJ
thermal
shutdown
R1 (ext.)
OCM
overcurrent
monitoring
antisaturating
stage
GIPD250620151147MT
DocID028379 Rev 2
5/31
Pin configuration
RHFL6000A
2
Pin configuration
Figure 2: Pin configuration (top view)
GIPD250620151148MT
The upper metallic package lid is connected to ground. The bottom metallization
is electrically floating.
6/31
DocID028379 Rev 2
RHFL6000A
Pin configuration
Table 2: Pin description
Pin description
Pin
name
FLAT-16P
(1)
VO
1, 2, 6, 7
3, 4, 5
Output port of the regulator.
VI(2)
Input port of the regulator.
Ground.
GND
12, 13
Current limit setting pin. Connect a resistor between this pin and VI to set
the current limit threshold.
ISC
8
Overcurrent monitor flag. Open collector, internally pulled up.
OCM
10
The signal on this pin goes to low logic level when the current limit
activates.
Device Inhibit pin. Internally pulled-down.
INHIBIT
ADJ
14
15
9
The regulator is off when this pin is set at high logic level.
Feedback pin. Connect to external resistor divider for output voltage
setting.
Filter capacitor pin. An optional capacitor can be connected between this
pin and GND.
FILT C
An optional R-C network can be connected between this pin and GND to
tune the internal control loop.
STAB
NC
11
16
Not internally connected.
Notes:
(1)All the output pins must be connected together on the PCB.
(2)All of input pins must be connected together on the PCB.
The upper metallic package lid is connected to ground. The bottom metallization
is electrically floating.
DocID028379 Rev 2
7/31
Maximum ratings
RHFL6000A
3
Maximum ratings
Table 3: Absolute maximum ratings
Symbol
VI
Parameter
Value
Unit
DC input voltage, VI-VGROUND
-0.3 to 12
V
VO
DC output voltage range
-0.3 to (VI + 0.3)
-0.3 to (VO + 0.3)
2
V
V
VADJ
IO
Adjustable pin voltage
Continuous output current
Over current monitor pin voltage vs GND
Current limit pin voltage vs GND
Inhibit pin voltage
A
VOCM
VISC
-0.3 to 12
-0.3 to 12
-0.3 to 12
-0.3 to 2.5
-0.3 to 1.3
-65 to +150
-55 to +125
2
V
V
INHIBIT
STAB
FILT C
TSTG
TOP
V
Stability capacitor pin voltage
Filter capacitor pin voltage
Storage temperature range
Operating junction temperature range
Human body model (HBM)
Machine model (MM)
V
V
°C
°C
kV
V
ESD
200
Charged device model (CDM)
500
V
Absolute maximum ratings are those values beyond which damage to the device
may occur. Functional operation under these condition is not implied.
Table 4: Thermal data
Symbol
RthJC
Parameter
Thermal resistance junction-case, FLAT-16P
Maximum soldering temperature, 10 s
Value
8.3
Unit
°C/W
°C
TSOLD
300
8/31
DocID028379 Rev 2
RHFL6000A
Electrical characteristics
4
Electrical characteristics
TJ = 25 °C, VI = 2.5 V, VO = VADJ, CI = CO = 10 µF (tantalum), unless otherwise specified.
Table 5: Electrical characteristics
Symbol
Parameter
Operating
Test conditions
Min.
Typ.
Max.
Unit
VI
IO = 1 A, TJ = -55 to 125 °C
2.5
12
V
input voltage
IO = 5 mA to 1 A, VO = Vadj
,
Reference
voltage
VADJ
1.205 1.245 1.285
V
A
TJ = -55 to 125 °C
Output current
limit (1)
ISHORT
Adjustable by external resistor
1
3
VI = 2.5 V to 12 V, IO = 5 mA,
TJ = +25 °C
0.1
0.4
0.5
0.35
0.4
0.5
0.3
0.5
0.6
0.6
VI = 2.5 V to 12 V, IO = 5 mA,
TJ = -55 °C
∆VO/∆VI Line regulation
0.2
%
VI = 2.5 V to 12 V, IO = 5 mA,
TJ = +125 °C
0.08
0.02
0.2
VI = 2.5 V, IO = 5 to 400 mA,
TJ = +25 °C
VI = 2.5 V, IO = 5 to 400 mA,
TJ = -55 °C
VI = 2.5 V, IO = 5 to 400 mA,
TJ = +125 °C
0.03
0.3
VI = 2.5 V, IO = 5 mA to 1 A,
TJ = +25 °C
∆VO/ ∆IO Load regulation
%
VI = 2.5 V, IO = 5 mA to 1 A,
TJ = -55 °C
0.3
VI = 2.5 V, IO = 5 mA to 1 A,
TJ = +125 °C
0.3
VI = 2.5 V, IO = 5 mA to 2 A,
TJ = -55 to 125 °C
0.6
Output
ZOUT
IO = 100 mA DC and 20 mA rms
100
mΩ
impedance
VI = 2.5 V to 12 V, IO = 5 mA,
TJ = +25 °C
7
7
VI = 2.5 V to 12 V, IO = 30 mA,
TJ = +25 °C
Quiescent
VI = 2.5 V to 12 V, IO = 300 mA,
TJ = +25 °C
current (2)
Iq
30
60
7
mA
ON mode
VI = 2.5 V to 12 V, IO = 1 A,
TJ = +25 °C
VI = 2.5 V to 12 V, IO = 30 mA,
TJ = -55 °C
DocID028379 Rev 2
9/31
Electrical characteristics
RHFL6000A
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VI = 2.5 V to 12 V, IO = 300 mA,
TJ = -55 °C
35
80
7
VI = 2.5 V to 12 V, IO = 1 A,
TJ = -55 °C
VI = 2.5 V to 12 V, IO = 30 mA,
TJ = +125 °C
VI = 2.5 V to 12 V, IO = 300 mA,
TJ = +125 °C
30
60
VI = 2.5 V to 12 V, IO = 1 A,
TJ = +125 °C
Quiescent
current
VI = 2.5 V, VINH = 2.4 V, OFF mode,
TJ = -55 to +125 °C
IqOFF
0.2
1
mA
OFF mode
IO = 400 mA, VO = 2.5 to 9 V,
(+25 °C)
300
250
350
450
400
550
IO = 400 mA, VO = 2.5 to 9 V,
(-55 °C)
IO = 400 mA, VO = 2.5 to 9 V,
(+125 °C)
Vd
Dropout voltage
mV
IO = 1 A, VO = 2.5 to 9 V, (+25 °C)
IO = 1 A, VO = 2.5 to 9 V, (-55 °C)
IO = 1 A, VO = 2.5 to 9 V, (+125 °C)
IO = 2 A, VO = 2.5 to 9 V, (+25 °C)
IO = 2 A, VO = 2.5 to 9 V, (-55 °C)
IO = 2 A, VO = 2.5 to 9 V, (+125 °C)
IO = 5 mA, TJ = -55 to +125 °C
IO = 5 mA, TJ = -55 to +125 °C
570
470
700
550
500
700
800
700
900
VINH(ON) Inhibit voltage
VINH(OFF) Inhibit voltage
0.8
V
2.4
60
f = 120 Hz
70
40
VI = VO + 2.5 V ± 0.5
Supply voltage
SVR
V,
dB
rejection (3)
f = 33 Hz
VO = 3 V IO = 5 mA
30
Shutdown input
current
ISH
VINH = 5 V
15
µA
V
VOCM
OCM pin voltage Sinked IOCM = 24 mA active low
VI = VO + 2.5 V,
0.38
VINH = from 0 V to 2.4 V,
IO = 400 mA ,
Inhibit
tPLH
propagation
30
µs
delay, turn-off (3)
VO = 3 V, CI = CO = 10 µF
10/31
DocID028379 Rev 2
RHFL6000A
Electrical characteristics
Symbol
Parameter
Test conditions
VI = VO + 2.5 V,
Min.
Typ.
Max.
Unit
VINH = from 2.4 V to 0 V,
IO = 400 mA , VO = 3 V,
CI = CO = 10 µF
Inhibit
propagation
delay, turn-on (3)
tPHL
100
µs
B = 10 Hz to 100 kHz,
IO = 5 mA to 2 A
Output noise
voltage (3)
eN
40
µVrms
Notes:
(1)These values are guaranteed by design. For each application it is strongly recommended to comply with the
maximum current limit of the package used.
(2)See Table 6: "Tid tests results".
(3)These values are guaranteed by design.
DocID028379 Rev 2
11/31
Typical application diagram
RHFL6000A
5
Typical application diagram
Figure 3: Typical application diagram
12/31
DocID028379 Rev 2
RHFL6000A
Radiations
6
Radiations
6.1
Total ionizing dose (MIL-STD-883 test method 1019)
The products that are guaranteed in radiation within RHA QML-V system, fully comply with
the MIL-STD-883 test method 1019 specification. The RHFL6000A is being RHA QML-V
qualified, tested and characterized in full compliance with the MIL-STD-883 specification,
both below 10 mrad/s (low dose rate) and between 50 and 300 rad/s (high dose rate).
Testing is performed in accordance with MIL-prf-38535 and the test method 1019 of
the MIL-STD-883 for total ionizing dose (TID).
ELDRS characterization is performed in qualification only on both biased and
unbiased parts, on a sample of ten units from two different wafer lots.
Each wafer lot is tested at high dose rate only, in the worst bias case condition, based
on the results obtained during the initial qualification.
Table 6: TID tests results
Type
Conditions
Value
300
Unit
50 rad(Si)/s high dose rate up to
10 mrad(Si)/s low dose rate up to (1)
ELDRS free up to (1)
TID
100
krad
100
From 0 krad to 300 krad at 50 rad/s ,
MIL-STD-883J method 1019.9
Output voltage radiation drift
<1.1
<15
ppm/krad
mA
From 0 krad to 300 krad at 50 rad/s ,
MIL-STD-883J method 1019.9
VI = 2.5 V to 12 V, IO = 5 to 30 mA,
TJ = -55 to +125 °C
Quiescent current
(ON state)
Notes:
(1)300 krad low dose rate test ongoing.
DocID028379 Rev 2
13/31
Radiations
RHFL6000A
6.2
Heavy Ions
The heavy ions trials are performed on qualification lots only. No additional test is
performed. Table 7 summarizes the results of heavy ions tests.
Table 7: Heavy ions results
Feature
Conditions
LET = 120 MeV*cm2/mg
Value
Unit
SEL/B performance
No latchup/burnout
-
VI = 12 V
LET = 32 MeV*cm2/mg
Saturated cross-section = 6.18*10-5 cm²
VIN up to 9 V
± 15% max over less
than 300 ns
VI - VO ≤ 7.5 V
IOUT < 300 mA
LET = 120 MeV*cm2/mg
VIN up to 12 V
SET performance
during events
% of VO
No SET above ± 3%
No SET above ± 3.3%
VI - VO < 3.0 V
IOUT < 300 mA
LET = 120 MeV*cm2/mg
VIN up to 4 V
VI - VO < 1.5 V
IOUT < 1 A
SEL and SET performances described here below are related to the circuit configuration
and bias conditions shown in Figure 4: "Heavy Ion test configuration" and Table 8: "Bias
configurations" and Table 9: "Test configurations".
Figure 4: Heavy Ions test configuration
14/31
DocID028379 Rev 2
RHFL6000A
Radiations
Table 8: Bias configurations
Bias condition
Test mode
SEL
VIN = 12 V, VOUT = 9 V, VINHIBIT = 0 V, IOUT = 5 mA
VIN = 3 V, VOUT = 1.5 V, VINHIBIT = 0 V, IOUT = 1 mA
VIN = 9 V, VOUT = 0 V, VINHIBIT = 9 V, IOUT = 0 mA
VIN = 4 V, VOUT = 2.5 V, VINHIBIT = 0 V, IOUT = 1 A
VIN = 7 V, VOUT = 5 V, VINHIBIT = 0 V, IOUT = 300 mA
VIN = 12 V, VOUT = 9 V, VINHIBIT = 0 V, IOUT = 300 mA
SET
Table 9: Test configurations
Test configuration
Test mode
CIN1 = 100 µF
COUT1 = COUT2 = 47 µF
CIN2 = COUT4 = COUT5 = 100 nF
SEL
Sel configuration
Cbyp = 47 nF
Cfilt = 22 nF
RISC = 8.2 kΩ
Rload = 1.8 kΩ
CIN1 = 100 µF
COUT1 = COUT2 = 47 µF
CIN2 = COUT4 = COUT5 = 100 nF
Cbyp = 47 nF
SET 1
Cfilt = 22 nF
RISC = 8.2 kΩ
Rload = depending on bias conditions
CIN1 = COUT1 = 220 µF
COUT5 = COUT2 = not connected
CIN2 = COUT4 = 100 nF
Cbyp = 47 nF
SET
SET 2
Cfilt = 22 nF
RISC = 8.2 kΩ
Rload = depending on bias conditions
DocID028379 Rev 2
15/31
Additional guidelines for SET mitigation
RHFL6000A
7
Additional guidelines for SET mitigation
This section provides detailed design guidelines necessary to obtain the required
performance against SET. In this respect, we can identify two main areas for intervention:
ground connection and external components selection.
7.1
Ground connections
To achieve the best performance in terms of output voltage accuracy, noise immunity and
robustness against single event effects, it is recommended to implement a proper PCB
layout by following the suggestions described below.
According to qualitative simulations of single events, some very short SET (i.e., a duration
in the 100 ns range) are strongly dependent on the stray inductances versus GND. The
best solution to reduce the parasitic inductance is the adoption of a GND plane (with
separate power and sense paths where possible). By minimizing the stray GND
impedance, this approach is of great assistance in controlling the amplitude of the SET
events near the load.
If this solution is not applicable, we suggest using a star-bus topology, where the PCB
reference GND connection is close to the GND pin of the regulator.
To achieve a good GND sense, it is necessary to comply with the following rules:
connect the regulator GND pin and load GND node both to the sense and power GND
traces on the PCB using vias to minimize the path;
an array of multiple via structures works better than a single large one;
for GND connectors/plugs: use separate plugs for power supply and testing probes;
connect input/output capacitors GND terminals to GND sense on the PCB.
7.2
Capacitor selection
With reference to Figure 4: "Heavy Ion test configuration", a combination of capacitors must
be present on the input and output ports. For the INPUT terminals, this may consist of a
100 µF bulk capacitor (CIN1) in parallel with a polyester 100 nF one (CIN2) used for
decoupling purposes.
For each of the two OUTPUT connections (pins 1, 2 and 6, 7) we suggest using a
combination of a 47µF bulk capacitor (COUT1, COUT2,) in parallel with a polyester 100 nF one
(COUT4, COUT5) for decoupling purposes.
Regarding parts selection, for the 100 nF elements we suggest low-ESL and low ESR
capacitors.
Concerning the selection of the three bulk capacitors, we suggest:
using tantalum SMD;
selecting size and ESL as small as possible;
placing capacitors as close as possible to the input/output terminals;
using an array of capacitors in parallel, where possible. This works better than a single
capacitor against the short events.
16/31
DocID028379 Rev 2
RHFL6000A
Device description
8
Device description
The RHFL6000A adjustable voltage regulator contains a PNP type power element
controlled by a signal resulting from an amplified comparison between the internal
temperature-compensated band-gap and the fraction of the desired output voltage value
obtained from an external resistor divider bridge. The device is protected by several
functional blocks.
8.1
ADJ pin
The feedback voltage necessary for the loop regulation comes from the load through an
external resistor divider (R1, R2 as in Figure 3: "Typical application diagram") whose mid
point is connected to the ADJ pin (allowing all possible output voltage settings as per user
requirements).
8.2
8.3
Inhibit ON-OFF control
By setting the INHIBIT pin to TTL high level , the device switches off. The device is in ON
state when the INHIBIT pin is set low. Since the INHIBIT pin is pulled down internally, it can
be left floating whenever the inhibit function is not used.
Overtemperature protection
A temperature detector internally monitors the power element junction temperature. The
device turns off when a temperature of approximately 175 °C is reached, returning to ON
mode when the temperature decreases down to approximately 135 °C.
It should be noted that when the internal temperature detector reaches 175 °C, the active
power element can be as high as 225 °C. Prolonged operation under these conditions may
exceed the maximum operating ratings and device reliability cannot be guaranteed.
8.4
Overcurrent protection
An default internal costant current limit is set at ISHORT = 3 A (when VO is at 0 V).
This value can be decreased via an external resistor (RSHORT) connected between the ISC
and VI pins, with a typical value range of 10 kΩ to 200 kΩ.
To maintain optimal regulation, it is necessary to set ISHORT 1.6 times greater than the
desired maximum operating current (IO ). When IO reaches ISHORT–300 mA, the current
limiter intervenes, VO starts to drop and the OCM flag is raised. When no current limitation
adjustment is required, the ISC pin must be left unbiased.
The combination of overcurrent and overtemperature circuits provides RHFL6000A with a
high level of protection against destructive junction temperature excursions in all load
conditions.
8.5
OCM pin
The OCM pin is an open collector flag normally pulled up at VI by a 5 kΩ resistor.
It goes to low state when the current limit becomes active. It is buffered and can sink 10
mA.
DocID028379 Rev 2
17/31
Device description
RHFL6000A
8.6
STAB pin
The STAB pin gives user direct access to regulator internal control loop stability
adjustment. Its usage is optional and it should be left unconnected when not used.
8.7
FILT C pin
The FILT C pin helps reduce SET rate when bypassed to GND through a 22 nF ceramic
capacitor. Its usage is optional and it should be left unconnected when not used.
18/31
DocID028379 Rev 2
RHFL6000A
Application information
9
Application information
To adjust the output voltage, the R2 resistor must be connected between the VO and ADJ
pins. The R1 resistor must be connected between ADJ and ground. Resistor values can be
derived from the following formula:
VO = VADJ (R1+ R2) / R1
where
= 1.248 V typ.
VADJ
The minimum output voltage is therefore VADJ and minimum input voltage is 2.5 V.
The RHFL6000A operates correctly when the VI - VO voltage difference is slightly above
the power element saturation voltage (Vd, dropout voltage).
A minimum load current of 0.5 mA must be set to ensure proper regulation under no-load
condition. It is advisable to make this current flow into the resistor divider.
For this reason, we suggest selecting an R1 value not higher than 10 k Ω.
The RHFL6000 flat16 package offers multiple input and output pins.
All of the available VI pins should always be externally interconnected. The same must be
applied to all the available VO pins, otherwise the stability and reliability of the device
cannot be guaranteed.
The inhibit function switches off the output current very quickly. According to Lenz’s Law,
external circuitry reacts with LdI/dt terms which can be of high amplitude in case of serial
inductive elements or large stray PCB inductance. Large transient voltage would develop
on both device terminals. It is advisable to protect the device output with Schottky diodes to
prevent negative voltage excursions. A14 V Zener diode could protect the device input.
The input and output capacitors must be connected as close as possible to the device
terminals.
Since the RHFL6000A voltage regulator is manufactured with very high speed bipolar
technology (6 GHz fT transistors), the PCB layout must be designed with exceptional care,
with very low inductance and low mutually coupling lines. Otherwise, high frequency
parasitic signals may be picked up by the device resulting in system self-oscillation.
On the other hand, the benefit of this technology is SVR performance extended to high
frequencies.
DocID028379 Rev 2
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Application information
RHFL6000A
9.1
9.2
Notes on the 16-pin hermetic flat package
The RHFL6000A adjustable voltage regulator is available in a high thermal dissipation 16-
pin hermetic Flat package, whose bottom flange is metallized to allow direct soldering or
glueing to a heat sink (efficient thermal conductivity). The upper metallic package lid is
connected to ground. The bottom metallization is electrically floating.
FPGA supply
FPGA devices are very sensitive to VDD transients beyond a few % of their nominal supply
voltage (usually 1.5 V).
The RHFL6000A includes specific integrated circuitry designed to absorb the output
transients under heavy ion beams, rendering it suitable for safe FPGA supply operation.
20/31
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RHFL6000A
Typical performance characteristics
10
Typical performance characteristics
(CIN = COUT = 10 µF tantalum, unless otherwise specified)
Figure 5: Output voltage vs temperature
(VIN = 2.5 V, IOUT = 5 mA)
Figure 6: Output voltage vs temperature
(VIN = 2.5 V, IOUT = 400 mA)
1.28
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.19
1.18
-55
-40
-25
0
25
55
85
125
-55
-40
-25
0
25
55
85
125
Temperature ºC
Temperature ºC
GIPD240620151216MT
GIPD240620151357MT
Figure 7: Output voltage vs temperature
(VIN = 2.5 V IOUT = 1 A)
Figure 8: Output voltage vs temperature
(VIN = 2.5 V IOUT = 2 A)
1.28
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.19
1.18
-55
-40
-25
0
25
55
85
125
-55
-40
-25
0
25
55
85
125
Temperature ºC
Temperature ºC
GIPD240620151148MT
GIPD240620151155MT
DocID028379 Rev 2
21/31
Typical performance characteristics
RHFL6000A
Figure 10: Load regulation vs temperature
Figure 9: Line regulation vs temperature
(IOUT = 5 mA to 400 mA)
Figure 12: Dropout voltage vs. temperature
(IOUT = 0.4 A)
Figure 11: Load regulation vs temperature
(IOUT = 5 mA to 1 A, VIN = 2.5 V
600
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Vout=9V
Vout=2.5V
500
400
300
200
100
0
0
-80
-55
25
125
100
120
140
-60
-20
0
20
40
60
-40
80
Temperature ºC
Temperature ºC
GIPD240620151125MT
GIPD290620151104MT
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DocID028379 Rev 2
RHFL6000A
Figure 13: Dropout voltage vs temperature
(IOUT = 1 A)
Typical performance characteristics
Figure 14: Dropout voltage vs temperature
(IOUT = 2 A)
1600
1000
900
Vout=9V
1500
Vout=2.5V
Vout=9V
1400
Vout=2.5V
800
700
600
500
400
300
200
100
1300
1200
1100
1000
900
800
700
600
500
400
-80
0
-80
100
120
100
120
-60
-20
0
20
40
60
80
140
-60
-20
0
20
40
60
80
140
-40
-40
Temperature ºC
Temperature ºC
GIPD240620151103MT
GIPD230620151454MT
Figure 16: Quiescent current (ON mode,
IOUT = 5 mA)
Figure 15: Quiescent current (OFF mode)
V
= 2.5 V, V = 2.4 V
INH
IN
V
= 2.5 V
IN
1000
900
800
700
600
500
0.008
0.007
0.006
0.005
0.004
0.003
400
300
200
0.002
100
0
0.001
0
100
120
-80
-60
-20
0
20
40
60
140
-40
80
100
120
0
20
40
140
-80
-60
-20
60
-40
80
Temperature ºC
Temperature ºC
GIPD230620151442MT
GIPD230620151432MT
DocID028379 Rev 2
23/31
Typical performance characteristics
RHFL6000A
Figure 17: Quiescent current (ON mode, IOUT = 1 A)
Figure 18: Quiescent current (ON mode, IOUT = 2 A)
V
= 2.5 V
V
= 2.5 V
IN
IN
0.006
0.12
0.11
0.1
0.005
0.004
0.09
0.08
0.07
0.06
0.003
0.002
0.05
0.04
0.03
0.02
0.01
0
0.001
0
125
125
-55
-25
0
25
55
85
-55
-25
0
25
55
85
Temperature ºC
Temperature ºC
GIPD260620151051MT
GIPD230620151152MT
Figure 19: Short circuit current vs RSHORT
Figure 20: SVR vs frequency
V
to Gnd, C =C
=1µF, V =6V, Vout in short circuit condition
IN
V
IN
= from 5 to 6V, V
=3V, I
=5mA, C =C =1µF tantalum
IN OUT
EN
IN OUT
OUT
OUT
100
4
90
80
3.5
3
70
2.5
2
60
50
40
1.5
1
30
20
10
0.5
0
0
100
1000
0
10 20 30 40 50 60
10000
70 80 90 100 110 120 130 140
100000
150
Frequency[Hz]
R
[Kohm]
SH
GIPD230620151129MT
GIPD230620151141MT
Figure 21: SVR vs frequency (T = 90 °C)
Figure 22: Turn on transient
V
= from 3.5 to 4.5V, C =C
=1µF tantalum,T=90°C, V
=2.5V
IN
IN OUT
OUT
100
90
80
Iout=5mA
Iout=1A
70
60
50
40
30
20
10
0
100
1000
10000
100000
Frequency[Hz]
GIPD230620151047MT
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RHFL6000A
Typical performance characteristics
Figure 23: Turn off transient
Figure 24: Line transient (IOUT = 0.8 A, VOUT = 3 V)
Figure 25: Line transient (IOUT = 2 A, VOUT = 2.5 V)
Figure 26: Load transient
Figure 28: Stability area for tantalum capacitor
Figure 27: Stability area for ceramic capacitor
DocID028379 Rev 2
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Package information
RHFL6000A
11
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
11.1
FLAT-16P package information
Figure 29: Flat-16P package outline
8241681_4
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DocID028379 Rev 2
RHFL6000A
Package information
Table 10: Flat-16P package mechanical data
mm
inch
Dim.
Min.
0.095
0.015
0.004
0.382
0.264
0.130
0.030
Typ.
Max.
0.113
0.019
0.007
0.398
0.280
0.142
Min.
2.42
0.38
0.10
9.71
6.71
3.30
0.76
Typ.
Max.
2.88
0.48
0.18
10.11
7.11
3.60
A
b
c
D
E
0.136
0.050
E2
E3
e
3.45
1.27
0.250
0.026
0.005
0.290
0.045
L
6.35
0.66
0.13
7.36
1.14
Q
S1
DocID028379 Rev 2
27/31
Ordering information
RHFL6000A
12
Ordering information
Table 11: Order code
Lead
finish
CPN
Quality level
Engineering model
QML-V flight
EPPL
Package
Marking (1)
Packing
Strip
pack
RHFL6000AKP1
-
FLAT-16P
Gold RHFL6000KPA1
Strip
pack
RHFL6000AKP01V (2)
RHFL6000AKP02V (2)
Target FLAT-16P
Target FLAT-16P
Gold
Tin
TBD
TBD
Strip
pack
QML-V flight
Notes:
(1)Specific marking only. The full marking includes in addition: - for the engineering models : ST logo, date code,
country of origin (FR) - for QML flight parts : ST logo, date code, country of origin (FR), manufacturer code
(CSTM), serial number of the part within the assembly lot.
(2)Qualification ongoing.
Contact ST sales office for information about the specific conditions for :
1) Products in die form
2) Other quality levels
3) Tape & reel packing
12.1
Traceability information
Date code in formation is structured as described below:
Table 12: Date codes
Model
Datecode
EM
3yywwN
yywwN
QML flight
where:
yy = year
ww = week number
N = lot index in the week
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DocID028379 Rev 2
RHFL6000A
Ordering information
12.3
Documentation
The table below gives a summary of the documentation provided with each type of
products:
Table 13: Table of documentation by product
Quality level
Documentation
Engineering model
-
Certificate of conformance (including group C & D reference)
Precap report (100% high & low magnification)
SEM report
QML-V flight
Screening summary
Group A summary (quality conformance inspection of electrical tests)
Group B summary (quality conformance inspection of mechanical tests)
Group E (quality conformance inspection of wafer lot radiation verification test)
DocID028379 Rev 2
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Revision history
RHFL6000A
13
Revision history
Table 14: Document revision history
Changes
Date
Revision
21-Sep-2015
1
First release.
Updated Table 7: "Heavy ions results".
12-Oct-2015
2
Minor text changes.
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RHFL6000A
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
DocID028379 Rev 2
31/31
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