RHRXH162374K-01V [STMICROELECTRONICS]

Rad hard low voltage CMOS 16-bit D-type Flip-Flop with 3.6V tolerant inputs and outputs; 抗辐射低电压CMOS 16位D型触发器与宽容3.6V的输入和输出


型号：	RHRXH162374K-01V
厂家：	ST
描述：	Rad hard low voltage CMOS 16-bit D-type Flip-Flop with 3.6V tolerant inputs and outputs 抗辐射低电压CMOS 16位D型触发器与宽容3.6V的输入和输出触发器
文件：	总17页 (文件大小：513K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

54VCXH162374

Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state)

with 3.6V tolerant inputs and outputs

Features

■ 1.65 to 3.6V inputs and outputs

■ High speed:

– t = 3.4ns (Max) at V = 3.0 to 3.6V

– t = 4.8ns (Max) at V = 2.3 to 2.7V

■ Symmetrical impedance outputs:

– |I | = I = 12mA (Min) at V = 3.0V

Flat-48

– |I | = I = 8mA (Min) at V = 2.3V

Description

■ Power down protection on inputs and outputs

■ 26Ω serie resistors in outputs

The 54VCXH162374 is a low voltage CMOS 16

bit d-type Flip-Flop with 3 state outputs non

inverting fabricated with sub-micron silicon gate

■ Operating voltage range:

– V (Opr) = 1.65V to 3.6V

and five-layer metal wiring C MOS technology. It

■ Pin and function compatible with 54 SERIES

is ideal for low power and very high speed 1.65 to

3.6V applications; it can be interfaced to 3.6V

signal environment for both inputs and outputs.

H162374

■ Bus hold provided on both sides

■ Cold spare function

These 16 bit D-TYPE flip-flops are controlled by

two clock inputs (nCK) and two output enable

inputs (nOE).

■ Latch-up performance exceeds

300mA (JESD 17)

■ ESD performance:

On the positive transition of the (nCK), the nQ

outputs will be set to the logic state that were

setup at the nD inputs.

– HBM > 2000V

(MIL STD 883 method 3015); MM > 200V

■ 300KRad Mil1019.6 Condition A, (RHA QML

While the (nOE) input is low, the 8 outputs (nQ)

will be in a normal state (HIGH or LOW logic level)

and while high level the outputs will be in a high

impedance state.

qualification extension undergone)

■ No SEL, no SEU under 72 Mev/cm2/mg LET

heavy ions irradiation

Any output control does not affect the internal

operation of flip flops; that is, the old data can be

retained or the new data can be entered even

while the outputs are OFF.

■ QML qualified product

■ Device fully compliant with

DSCC SMD 5962-05212

July 2007

Rev 4

1/17

www.st.com

Contents

54VCXH162374

Contents

Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

2.3

Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2/17

54VCXH162374

Logic symbols and I/O equivalent circuit

Figure 1. IEC logic symbols

Figure 2. Input and output equivalent circuit

3/17

Logic symbols and I/O equivalent circuit

Figure 3. Logic diagram

54VCXH162374

Note:

This logic diagram has not to be used to estimate propagation delays

4/17

54VCXH162374

Pin settings

2.1

Pin connection

Figure 4. Pin connection (top through view)

5/17

Pin settings

54VCXH162374

2.2

Pin description

Table 1. Pin description

Pin N°

Symbol

Name and function

1OE

3 state output enable input (Active

LOW)

2, 3, 5, 6, 8, 9, 11, 12

13, 14, 16, 17, 19, 20, 22, 23

1Q0 to 1Q7

2Q0 to 2Q7

2OE

3-state outputs

3 state output enable input (Active

LOW)

2CK

2D0 to 2D7

1D0 to 1D7

1CK

Clock input

36, 35, 33, 32, 30, 29, 27, 26

47, 46, 44, 43, 41, 40, 38, 37

Data inputs

Clock input

4, 10, 15, 21, 28, 34, 39, 45

7, 18, 31, 42

GND

Ground (0V)

Positive supply voltage

V_CC

2.3

Truth table

Table 2. Truth table

Inputs

Output

No change ⁽¹⁾

1. Q outputs are latched at the time when the LE input is taken low logic level.

Note:

X = Do not care; Z = High Impedance

6/17

54VCXH162374

Maximum rating

Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 3. Absolute maximum ratings

Symbol

Parameter

Value

Unit

V_CC

Supply voltage

-0.5 to +4.6

-0.5 to V_CC+ 0.5

V_I

V_O

I_IK

DC input voltage

DC output voltage (OFF State)

DC output voltage (High or Low State) ⁽¹⁾

DC input diode current

- 50

± 50

DC output diode current ⁽²⁾

DC output current

I_OK

I_O

I_CCor

I_GND

DC V_CCor ground current per supply pin

± 100

P_D

T_stg

T_L

Power dissipation

400

-65 to +150

260

°C

Storage temperature

Lead temperature (10 sec)

°C

1. I_Oabsolute maximum rating must be observed

2. V_O< GND, V_O> V_CC

3.1

Recommended operating conditions

Table 4. Recommended operating conditions

Symbol

Parameter

Value

Unit

V_CC

Supply voltage

1.8 to 3.6

V_I

Input voltage

-0.3 to 3.6

0 to 3.6

0 to V_CC

± 12

V_O

Output voltage (OFF state)

Output voltage (High or Low State)

I_OH, I_OLHigh or low level output current (V_CC= 3.0 to 3.6V)

_OH, I_OLHigh or low level output current (V_CC= 2.3 to 2.7V)

°C

± 8

T_op

Operating temperature

-55 to 125

0 to 10

Input rise and fall time ⁽¹⁾

dt/dv

ns/V

1. V_INfrom 0.8V to 2V at V_CC= 3.0V

7/17

Electrical characteristics

54VCXH162374

Electrical characteristics

Table 5. DC specifications (2.7V < V < 3.6V unless otherwise specified)

Test condition

Value

-55 to 125°C

Symbol

Parameter

Unit

V_CC

(V)

Min

Max

V_IH

V_IL

High level input voltage

Low level input voltage

2.0

2.7 to 3.6

0.8

I_O=-100 µA

V_CC-0.2

2.2

2.7 to 3.6

2.7

I_O=-6 mA

I_O=-8 mA

I_O=-12 mA

I_O=100 µA

I_O=6 mA

High level output

voltage

V_OH

2.4

3.0

2.2

2.7 to 3.6

2.7

0.2

0.4

Low level output

voltage

V_OL

I_O=8 mA

0.55

0.8

3.0

2.7 to 3.6

3.0

I_O=12 mA

V_I= 0 to 3.6V

V_I= 0.8V

I_I

Input leakage current

Input hold current

± 5

µA

I_I(HOLD)

V_I= 2V

-75

V_I= 0 to 3.6V

3.6

± 500

Power Off leakage

current

I_off

V_Ior V_O= 0 to 3.6V

µA

V_I= V_IHor V_IL

V_O= 0 to 3.6V

High impedance output

leakage current

I_OZ

2.7 to 3.6

± 10

V_I= V_CCor GND

V_Ior V_O= V_CCto 3.6V

V_IH= V_CC- 0.6V

Quiescent supply

current

I_CC

2.7 to 3.6

µA

± 20

750

∆I_CC

I_CCincr. per Input

8/17

54VCXH162374

Electrical characteristics

Table 6. DC specifications (2.3V < V < 2.7V unless otherwise specified)

Test condition

Value

Symbol

Parameter

-55 to 125 °C

Unit

V_CC

(V)

Min

Max

V_IH

V_IL

High level input voltage

Low level input voltage

1.6

2.3 to 2.7

0.7

I_O=-100 µA

V_CC-0.2

2.0

I_O=-4 mA

I_O=-6 mA

V_OH

High level output voltage

2.3

1.8

I_O=-8 mA

1.7

I_O=100 µA

I_O=6 mA

2.3 to 2.7

2.3

0.2

0.4

0.6

± 5

V_OL

Low level output voltage

I_O=8 mA

I_I

V_I= V_CCor GND

V_I= 0.7V

Input leakage current

Input hold current

2.3 to 2.7

2.3

µA

I_I(HOLD)

V_I= 1.7V

-45

Power Off leakage

current

I_off

V_Ior V_O= 0 to 3.6V

µA

V_I= V_IHor V_IL

V_O= 0 to 3.6V

High impedance output

leakage current

I_OZ

2.3 to 2.7

± 10

V_I= V_CCor GND

I_CC

Quixent

2.3 to 2.7

µA

V_Ior V_O= V_CCto 3.6V

± 20

Table 7. Dynamic switching characteristics

(T = 25°C, Input t = t = 2.0ns, C = 30pF, R = 500Ω)

Test condition

Value

T_A= 25 °C

Symbol

Parameter

Unit

V_CC

(V)

Min

Typ

0.25

0.35

-0.25

-0.35

2.05

2.65

Max

2.5

3.3

2.5

3.3

2.5

3.3

_IL= 0V

Dynamic valley low voltage

quiet output ^{(1) (2)}

V_OLV

V_OHV

V_IH= V_CC

V_IL= 0V

V_IH= V_CC

Dynamic valley high voltage

quiet output ^{(2) (3)}

V_IL= 0V

V_IH= V_CC

Dynamic valley high voltage

quiet output ^{(2) (3)}

1. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to

HIGH. The remaining output is measured in the LOW state.

2. Parameters guaranteed by design.

3. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to

HIGH. The remaining output is measured in the HIGH state.

9/17

Electrical characteristics

54VCXH162374

Table 8. AC electrical characteristics (C = 30pF, R = 500Ω, Input t = t = 2.0ns)

Test condition

Value

Symbol

Parameter

-55 to 125 °C

Unit

V_CC

(V)

Min

1.0

0.8

1.0

0.8

1.0

0.8

1.0

1.5

190

235

Max

5.5

4.5

6.2

4.5

5.1

4.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

Propagation delay

time Dn to Qn

t_PLHt_PHL

Propagation delay

time LE to Qn

t_{PLH PHL}

t_{PZL PZH}

Output enable time

Output disable time

t_{PLZ PHZ}

Setup tIme, HIGH or

LOW level Dn to LE

t_s

t_h

t_w

Hold time High or

LOW level Dn to LE

LE pulse width, HIGH

0.5

Output to output skew

time ^{(1) (2)}

t_{OSLH OSHL}

1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

outputs of the same device switching in the same direction, either HIGH or LOW (t_OSLH= | t_PLHm- t_PLHn|,

t_OSHL= | t_PHLm- t_PHLn|)

2. Parameter guaranteed by design

Table 9. Capacitive characteristics

Test condition

V_CC

Value

T_A= 25 °C

Symbol

Parameter

Unit

(V)

Min

Typ

Max

C_IN

V_IN= 0 or V_CC

Input capacitance

Output capacitance

2.5 or 3.3

C_OUT

f_IN= 10MHz

V_IN= 0 or V_CC

Power dissipation

capacitance ⁽¹⁾

C_PD

2.5 or 3.3

1. C_PDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the

operating current consumption without load. (Refer to Test Circuit). Average operating current can be

obtained by the following equation. I_CC(opr)= C_PDx V_CCx f_IN+ I_CC/16 (per circuit)

10/17

54VCXH162374

Test circuit

Figure 5. Test circuit

Table 10. Test circuit

Test

Switch

t_PLH, t_PHL

Open

_PZL, t_PLZ(V_CC= 3.0 to 3.6V)

_PZL, t_PLZ(V_CC= 2.3 to 2.7V)

2V_CC

GND

t_PZH, t_PHZ

C = 30pF or equivalent (includes jig and probe capacitance)

R = R = 500Ω or equivalent

R = Z

of pulse generator (typically 50Ω)

OUT

11/17

Waveforms

54VCXH162374

Waveforms

Table 11. Waveform symbol value

Symbol

V_CC

3.0 to 3.6V

2.3 to 2.7V

V_IH

V_M

V_X

V_Y

2.7V

V_CC

1.5V

V_CC/2

V_OL+0.3V

V_OH-0.3V

V_OL+0.15V

V_OH-0.15V

Figure 6. Waveform - nCK TO Qn propagation delays, nCK maximum frequency, Dn

TO nCK setup and hold times (f = 1MHz; 50% duty cycle)

12/17

54VCXH162374

Waveforms

Figure 7. Waveform - output enable and disable time (f = 1MHz; 50% duty cycle)

Figure 8. Waveform - nCK minimum pulse width (f = 1MHz; 50% duty cycle)

13/17

Package mechanical data

54VCXH162374

Package mechanical data

54VCXH162374 Products are supplied into ceramic body / metal lid hermetic Flat 48-pin

space package

Table 12. Flat-48 (MIL-STD-1835) mechanical data

inch

Typ

Dim.

Min

2.18

0.20

0.12

15.57

9.52

6.22

1.52

Typ

Max

2.72

0.30

0.18

15.92

9.78

6.48

1.78

Min

Max

2.47

0.254

0.15

15.75

9.65

6.35

1.65

0.635

0.20

8.38

0.79

0.43

0.086

0.008

0.005

0.613

0.375

0.245

0.060

0.097

0.010

0.006

0.620

0.380

0.250

0.065

0.025

0.008

0.330

0.031

0.017

0.107

0.012

0.007

0.627

0.385

0.255

0.070

6.85

0.66

0.25

9.40

0.92

0.61

0.270

0.026

0.010

0.370

0.036

0.024

Figure 9. Package dimension

7330585B

14/17

54VCXH162374

Order code

Table 13. Order code

Flight model

Engineering

Package Lead finish Radiation level

model

QML-V

RHFXH162374K-01V

QML-Q

Gold

300kRad

100kRad

RHFXH162374K-01Q

RHRXH162374K1

Flat-48

RHRXH162374K-01V RHRXH162374K-01Q RHRXH162374 K1

RHRXH162374K-02V RHRXH162374K-02Q Use the above one

Solder dip

15/17

Revision history

54VCXH162374

Revision history

Table 14. Revision history

Date

Revision

Changes

09-Jul-2004

17-May-2005

19-Jun-2006

30-Jul-2007

First release.

SMD qualified.

300Krad bullet updated, new template, mechanical data updated

Typo in Table 12 on page 14.

16/17

54VCXH162374

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17/17

RHRXH162374K-01V [STMICROELECTRONICS]

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