SPC560P54L5_技术文档

SPC56AP60x, SPC56AP54x

SPC560P60x, SPC560P54x

32-bit Power Architecture^®based MCU with 1088 KB Flash memory

and 80 KB RAM for automotive chassis and safety applications

Datasheet  production data

Features

■ 64 MHz, dual issue, 32-bit CPU core complex

(e200z0h)

– Compliant with Power Architecture

LQFP100

14 x 14 mm

LQFP144

20 x 20 mm

®

embedded category

■ Communications interfaces

– Variable Length Encoding (VLE)

– 2 LINFlex modules (LIN 2.1,

■ Memory organizazion

1 × Master/Slave, 1 × Master Only)

– Up to 1024 KB on-chip code Flash memory

– 5 DSPI modules with automatic chip select

with additional 64 KB for EEPROM

generation

emulation (data flash), with ECC, with

– 2 FlexCAN interfaces (2.0B Active) with 32

erase/program controller

message buffers

– Up to 80 KB on-chip SRAM with ECC

– 1 Safety port based on FlexCAN; usable as

■ Fail safe protection

third CAN when not used as safety port

– ECC protection on system SRAM and

Flash

– Safety port

– 1 FlexRay™ module (V2.1) with dual or

single channel, 64 message buffers and up

to 10 Mbit/s

– SWT with servicing sequence pseudo-

random generator

– Power management

■ 2 CRC units with three contexts and 3

hardwired polynomials(CRC8,CRC32 and

CRC-16-CCITT)

– Non-maskable interrupt for both cores

– Fault collection and control unit (FCCU)

– Safe mode of system-on-chip (SoC)

– Register protection scheme

■ 10-bit A/D converter

– 27 input channels and pre-sampling feature

– Conversion time < 1 µs including sampling

time at full precision

■ Nexus^®L2+ interface

– Programmable cross triggering unit (CTU)

– 4 analog watchdog with interrupt capability

■ Single 3.3 V or 5 V supply for I/Os and ADC

■ 2 on-platform peripherals set with 2 INTC

■ On-chip CAN/UART Bootstrap loader with boot

assist module (BAM)

■ 16-channel eDMA controller with multiple

■ Ambient temperature ranges: –40 to 125 °C or

transfer request sources

–40 to 105 °C

■ General purpose I/Os (80 GPIO + 26 GPI on

LQFP144; 49 GPIO + 16 GPI on LQFP100)

Table 1.

Package

Device summary

Part number

■ 2 general purpose eTimer units

– 6 timers, each with up/down count

capabilities

768 KB Flash

1 MB Flash

– 16-bit resolution, cascadable counters

– Quadrature decode with rotation direction

flag

SPC560P54L5

SPC56AP54L5

SPC560P60L5

SPC56AP60L5

LQFP144

LQFP100

SPC560P54L3

SPC56AP54L3

SPC560P60L3

SPC56AP60L3

– Double buffer input capture and output

compare

May 2012

Doc ID 18340 Rev 3

1/104

This is information on a product in full production.

www.st.com

1

Contents

SPC56xP54x, SPC56xP60x

Contents

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

1.2

1.3

1.4

1.5

Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.1

1.5.2

1.5.3

1.5.4

1.5.5

1.5.6

1.5.7

1.5.8

1.5.9

High performance e200z0h core processor . . . . . . . . . . . . . . . . . . . . . . 13

Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 14

On-chip flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Frequency modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 16

Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.10 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.11 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.12 System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.5.13 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.14 Fault collection and control unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.15 System integration unit (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.16 Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5.17 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.18 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.19 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.5.20 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.5.21 Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 21

1.5.22 Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 22

1.5.23 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.5.24 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.5.25 Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.5.26 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.5.27 Nexus development interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.5.28 IEEE 1149.1 (JTAG) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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SPC56xP54x, SPC56xP60x

Contents

1.5.29 On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2

Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 27

2.1

2.2

Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.2.1

2.2.2

2.2.3

Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 29

System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.1

3.2

3.3

3.4

3.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.5.1

General notes for specifications at maximum junction temperature . . . 56

3.6

3.7

3.8

Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 58

Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 58

Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 58

3.8.1

3.8.2

Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 58

Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60

3.9

Power Up/Down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.10 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.10.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.11 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.11.1 DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.11.2 DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.11.3 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.12 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.14 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 74

3.15 Analog-to-Digital converter (ADC) electrical characteristics . . . . . . . . . . 74

3.15.1 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.15.2 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.16 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Doc ID 18340 Rev 3

3/104

Contents

SPC56xP54x, SPC56xP60x

3.17 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.17.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.18 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.18.1 RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.18.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.18.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.18.4 External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.18.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.1

4.2

ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.2.1

4.2.2

LQFP144 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 97

LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5

6

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPC56xP54/60 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SPC56xP54/60 device configuration difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SPC56xP54/60 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Thermal characteristics for 144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Thermal characteristics for 100-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Approved NPN ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . . . . . . . . . . 64

Supply current (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . . . . . . . . . . 67

Supply current (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Peripherals supply current (5 V and 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . 72

Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . 72

Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

PLLMRFM electrical specifications

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

(V

= 1.08 V to 1.32 V, V = V

= 0 V, TA = TL to TH)‘ . . . . . . . . . . . . . . . . . . . 73

DDPLL

SS

SSPLL

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

16 MHz RC oscillator electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Nexus debug port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

DSPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Doc ID 18340 Rev 3

5/104

List of figures

SPC56xP54x, SPC56xP60x

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

SPC56xP54/60 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

LQFP176 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

LQFP144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

LQFP100 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Power supplies constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Power supplies constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Voltage regulator configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 10. Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 11. Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 12. Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 13. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 14. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 15. ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 16. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 17. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 18. Transient behavior during sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 19. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 20. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 21. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 22. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 23. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 24. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 25. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 26. Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 27. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 28. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 29. DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 30. DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 31. DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 32. DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 33. DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 34. DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 35. DSPI modified transfer format timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 36. DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 37. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 38. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 39. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 40. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

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Introduction

1

Introduction

1.1

Document overview

This document provides electrical specifications, pin assignments, and package diagrams

for the SPC56xP54/60 series of microcontroller units (MCUs). It also describes the device

features and highlights important electrical and physical characteristics. For functional

characteristics, refer to the device reference manual.

1.2

Description

This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement

in integrated automotive application controllers. It belongs to an expanding range of

automotive-focused products designed to address chassis applications specifically the

airbag application.

This family is one of a series of next-generation integrated automotive microcontrollers

based on the Power Architecture technology.

The advanced and cost-efficient host processor core of this automotive controller family

complies with the Power Architecture embedded category. It operates up to 64 MHz and

offers high performance processing optimized for low power consumption. It capitalizes on

the available development infrastructure of current Power Architecture devices and is

supported with software drivers, operating systems and configuration code to assist with

users implementations.

1.3

Device comparison

Table 2 provides a summary of different members of the SPC56xP54/60 family and their

features—relative to Full-featured version—to enable a comparison among the family

members and an understanding of the range of functionality offered within this family.

Table 2.

SPC56xP54/60 device comparison

Feature

SPC560P54

SPC560P60

SPC56AP54

SPC56AP60

Code Flash memory (with ECC)

Data Flash / EE (with ECC)

SRAM (with ECC)

768 KB

1 MB

768 KB

1 MB

64 KB

80 KB

64 KB

80 KB

Processor core

32-bit e200z0h

32-bit Dual e200z0h

Instruction set

VLE

CPU performance

0-64 MHz

FMPLL (frequency-modulated phase-

locked loop) modules

1

INTC (interrupt controller) channels

PIT (periodic interrupt timer)

148

1 (includes four 32-bit timers)

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Table 2.

SPC56xP54x, SPC56xP60x

SPC56xP54/60 device comparison (continued)

Feature SPC560P54 SPC560P60

SPC56AP54

SPC56AP60

Enhanced DMA (direct memory

access) channels

16

FlexRay

Yes (64 message buffer)

FlexCAN (controller area network)

Safety port

3^(1),(2)

Yes (via third FlexCAN module)

FCCU (fault collection and control unit)

CTU (cross triggering unit)

eTimer channels

Yes⁽³⁾

Yes

2 × 6

FlexPWM (pulse-width modulation)

channels

No

Analog-to-digital converters (ADC)

LINFlex modules

One (10-bit, 27-channel)⁽⁴⁾

2 (1 × Master/Slave, 1 × Master only)

DSPI (deserial serial peripheral

interface) modules

5⁽⁵⁾

CRC (cyclic redundancy check) units

JTAG interface

2⁽⁶⁾

Yes

Nexus port controller (NPC)

Digital power supply⁽⁸⁾

Yes (Level 2+)⁽⁷⁾

3.3 V or 5 V single supply with external transistor

Analog power supply

Supply

3.3 V or 5 V

16 MHz

Internal RC oscillator

External crystal oscillator

Packages

4–40 MHz

LQFP100

LQFP144

LQFP176 ⁽⁹⁾

Standard ambient

Temperature

–40 to 125 °C

temperature

1. Each FlexCAN module has 32 message buffers.

2. One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.

3. Enhanced FCCU version

4. Same amount of ADC channels as on SPC560P44/50 not considering the internally connected ones. 26 channels on

LQFP144 and 16 channels on LQFP100.

5. Increased number of CS for DSPI_1

6. Upgraded specification with addition of 8-bits polynomial (CRC-8 VDA CAN) support and 3rd context

7. Improved debugging capability with data trace capability and increased Nexus throughput available on emulation package

8. 3.3 V range and 5 V range correspond to different orderable parts.

9. Software development package only. Not available for production.

SPC56xP54/60 is present on the market in two different options enabling different features:

Full-featured, and Airbag configuration. Table 3 shows the main differences between the two

versions.

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Introduction

Airbag

Table 3.

SPC56xP54/60 device configuration difference

Feature

Full-featured

CTU (cross triggering unit)

Yes

No

4

FlexRay

Yes (64 message buffer)

DSPI (deserial serial peripheral interface) modules

CRC (cyclic redundancy check) unit

5

2

1

1.4

Block diagram

Figure 1 shows a top-level block diagram of the SPC56xP54/60 MCU. Table 4 summarizes

the functions of the blocks.

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Introduction

Figure 1.

SPC56xP54x, SPC56xP60x

SPC56xP54/60 block diagram

e200z0 Core

32-bit

general

purpose

Variable

length

encoded

32-bit

general

purpose

Variable

length

encoded

PMU

INTC_0

SWT_0

STM_0

Exception

handler

Exception

handler

registers instructions

INTC_1

SWT_1

Special

Instruction

purpose

unit

Integer

execution

unit

Special

Instruction

purpose

unit

Integer

execution

unit

registers

Branch

STM_1

Load/Store

prediction

unit

Load/Store

prediction

unit

JTAG

unit

ECSM_0

SEMA4_0

ECSM_1

SEMA4_1

Nexus

port

controller

Nexus 2+

DMAMUX_0

DMA_0

INSTR

M0

DATA

INSTR

M5

DATA

M2

M3

M1

M6

Cross Bar Switch (XBAR, AMBA 2.0 v6 AHB) XBAR_0

Memory protection unit MPU_0

S2

Memory protection unit MPU_1

S7

S0

S1

S3

S6

NASPS_0

NASPS_1

P0

P1

PBRIDGE_0

PFLASHC_0

PBRIDGE_1

SRAMC_0

SRAMC_1

48KB

SRAM

with ECC

1024KB

code flash

with ECC

4x16KB

data flash

with ECC

32KB

SRAM

with ECC

Peripheral Bus (IPS)

26

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Introduction

Table 4.

SPC56xP54/60 series block summary

Block

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Function

Block of read-only memory containing VLE code which is executed according to

the boot mode of the device

Boot assist module (BAM)

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Controller area network

(FlexCAN)

Supports the standard CAN communications protocol

Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Cross triggering unit (CTU)

Crossbar switch (XBAR)

Supports simultaneous connections between two master ports and three slave

ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus

width.

Is dedicated to the computation of CRC off-loading the CPU. Each context has

a separate CRC computation engine in order to allow the concurrent

computation of the CRC of multiple data streams.

Cyclic redundancy checker

(CRC) unit

Deserial serial peripheral

interface (DSPI)

Provides a synchronous serial interface for communication with external

devices

Enhanced direct memory access Performs complex data transfers with minimal intervention from a host

(eDMA)

processor via “n” programmable channels

Enhanced timer (eTimer)

Provides enhanced programmable up/down modulo counting

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

Error correction status module

(ECSM)

Provides an output clock used as input reference for FMPLL_0 or as reference

clock for specific modules depending on system needs

External oscillator (XOSC)

Fault collection and control unit

(FCCU)

Provides functional safety to the device

Flash memory

Provides non-volatile storage for program code, constants and variables

Provides high-speed distributed control for advanced automotive applications

FlexRay (FlexRay communication

controller)

Frequency-modulated phase-

locked loop (FMPLL)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC)

JTAG controller

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

LINFlex controller

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control

unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Mode entry module (MC_ME)

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Introduction

Table 4.

SPC56xP54x, SPC56xP60x

SPC56xP54/60 series block summary (continued)

Block Function

Is the interface between the system bus and on-chip peripherals

Peripheral bridge (PBRIDGE)

Periodic interrupt timer (PIT)

Produces periodic interrupts and triggers

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Power control unit (MC_PCU)

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the

device

Provides the hardware support needed in multi-core systems for implementing

semaphores and provide a simple mechanism to achieve lock/unlock

operations via a single write access

Semaphore unit (SEMA4)

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

Provides control over all the electrical pad controls and up 32 ports with 16 bits

System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

Provides system configuration and status data (such as memory size and

System status and configuration

status, device mode and security status), device identification data, debug

module (SSCM)

status port enable and selection, and bus and peripheral abort enable/disable

Provides a set of output compare events to support AUTOSAR⁽¹⁾and operating

System timer module (STM)

system tasks

System watchdog timer (SWT)

Provides protection from runaway code

Supports up to 18 external sources that can generate interrupts or wakeup

events, of which 1 can cause non-maskable interrupt requests or wakeup

events.

Wakeup unit (WKPU)

1. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)

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Introduction

1.5

Feature details

1.5.1

High performance e200z0h core processor

The e200z0h Power Architecture core provides the following features:

●

High performance e200z0 core processor for managing peripherals and interrupts

Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

Harvard architecture

Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions

–

Results in smaller code size footprint

Minimizes impact on performance

●

Branch processing acceleration using lookahead instruction buffer

Load/store unit

–

1-cycle load latency

Misaligned access support

No load-to-use pipeline bubbles

●

Thirty-two 32-bit general purpose registers (GPRs)

Separate instruction bus and load/store bus Harvard architecture

Hardware vectored interrupt support

Reservation instructions for implementing read-modify-write constructs

Long cycle time instructions, except for guarded loads, do not increase interrupt latency

Extensive system development support through Nexus debug port

Non maskable Interrupt support

1.5.2

Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between six

master ports and six slave ports. The crossbar supports a 32-bit address bus width and a

32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any

slave port; but one of those transfers must be an instruction fetch from internal flash

memory. If a slave port is simultaneously requested by more than one master port,

arbitration logic selects the higher priority master and grant it ownership of the slave port. All

other masters requesting that slave port are stalled until the higher priority master

completes its transactions. Requesting masters are treated with equal priority and will be

granted access to a slave port in round-robin fashion, based upon the ID of the last master

to be granted access.

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The crossbar provides the following features:

6 master ports:

●

–

2 e200z0 core complex Instruction ports

2 e200z0 core complex Load/Store Data ports

eDMA

FlexRay

●

6 slave ports:

–

2 Flash memory (code flash and data flash)

2 SRAM (48 KB + 32 KB)

2 PBRIDGE

●

32-bit internal address, 32-bit internal data paths

Fixed Priority Arbitration based on Port Master

Temporary dynamic priority elevation of masters

1.5.3

Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module

capable of performing complex data movements via 16 programmable channels, with

minimal intervention from the host processor. The hardware micro architecture includes a

DMA engine which performs source and destination address calculations, and the actual

data movement operations, along with an SRAM-based memory containing the transfer

control descriptors (TCD) for the channels. This implementation is utilized to minimize the

overall block size.

The eDMA module provides the following features:

●

16 channels support independent 8, 16 or 32-bit single value or block transfers

Supports variable sized queues and circular queues

Source and destination address registers are independently configured to post-

increment or remain constant

●

Each transfer is initiated by a peripheral, CPU, or eDMA channel request

Each eDMA channel can optionally send an interrupt request to the CPU on completion

of a single value or block transfer

●

DMA transfers possible between system memories, DSPIs, ADC, eTimer and CTU

Programmable DMA Channel Multiplexer for assignment of any DMA source to any

available DMA channel with up to 30 potential request sources

●

eDMA abort operation through software

1.5.4

On-chip flash memory with ECC

The SPC56xP54/60 provides up to 1024 KB of programmable, non-volatile, flash memory.

The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash

memory module interfaces the system bus to a dedicated flash memory array controller. It

supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to

flash memory. The module contains a four-entry, 4x128-bit prefetch buffers. Prefetch buffer

hits allow no-wait responses. Normal flash memory array accesses are registered and are

forwarded to the system bus on the following cycle, incurring 2 wait states.

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Introduction

The flash memory module provides the following features:

●

Up to 1024 KB flash memory

–

14 blocks (2×16 KB + 2×32 KB + 2×16 KB + 2×64 KB + 6×128 KB) code flash

4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash

Full Read While Write (RWW) capability between code and data flash

●

Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch

buffers can be configured to prefetch code or data or both)

Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page

buffer miss at 64 MHz

●

Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

Hardware and software configurable read and write access protections on a per-master

basis.

●

Configurable access timing allowing use in a wide range of system frequencies.

Multiple-mapping support and mapping-based block access timing (0–31 additional

cycles) allowing use for emulation of other memory types.

●

Software programmable block program/erase restriction control.

Erase of selected block(s)

Read page size of 128 bits (4 words)

64-bit ECC with single-bit correction, double-bit detection for data integrity

Embedded hardware program and erase algorithm

Erase suspend, program suspend and erase-suspended program

Censorship protection scheme to prevent flash memory content visibility

Hardware support for EEPROM emulation

1.5.5

On-chip SRAM with ECC

The SPC56xP54/60 SRAM module provides a general-purpose memory of up to 80 KB.

The SRAM module provides the following features:

●

Supports read/write accesses mapped to the SRAM memory from any master

Up to 80 KB general purpose RAM

●

–

2 blocks (48 KB + 32 KB)

●

Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of

memory

Typical SRAM access time: 0 wait state for reads and 32-bit writes; 1 wait state for 8-

and 16-bit writes if back to back with a read to same memory block

1.5.6

Interrupt controller (INTC)

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt

requests, suitable for statically scheduled hard real-time systems.

For high priority interrupt requests, the time from the assertion of the interrupt request from

the peripheral to when the processor is executing the interrupt service routine (ISR) has

been minimized. The INTC provides a unique vector for each interrupt request source for

quick determination of which ISR needs to be executed. It also provides an ample number of

priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To

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Introduction

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allow the appropriate priorities for each source of interrupt request, the priority of each

interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be

supported. The INTC supports the priority ceiling protocol for coherent accesses. By

providing a modifiable priority mask, the priority can be raised temporarily so that all tasks

which share the resource can not preempt each other.

The INTC provides the following features:

●

Unique 9-bit vector for each separate interrupt source

8 software triggerable interrupt sources

●

16 priority levels with fixed hardware arbitration within priority levels for each interrupt

source

●

Ability to modify the ISR or task priority.

–

Modifying the priority can be used to implement the Priority Ceiling Protocol for

accessing shared resources.

2 external high priority interrupts directly accessing the main core and IOP critical

interrupt mechanism

The INTC module is replicated for each processor.

1.5.7

System clocks and clock generation

The following list summarizes the system clock and clock generation on the SPC56xP54/60:

●

Lock detect circuitry continuously monitors lock status

Loss of clock (LOC) detection for PLL outputs

Programmable output clock divider (1, 2, 4, 8)

Programmable output clock divider (1, 2, 3 to 256)

eTimer module running at the same frequency as the e200z0h core

On-chip oscillator with automatic level control

Internal 16 MHz RC oscillator for rapid start-up and safe mode

–

Supports frequency trimming by user application

1.5.8

Frequency modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz

input clock. Further, the FMPLL supports programmable frequency modulation of the

system clock. The FMPLL multiplication factor, output clock divider ratio are all software

configurable.

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Introduction

The FMPLL has the following major features:

●

Input clock frequency from 4 MHz to 40 MHz

Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

●

Modulation enabled/disabled through software

Triangle wave modulation

Programmable modulation depth ( 0.25% to 4% deviation from center frequency)

–

Programmable modulation frequency dependent on reference frequency

●

Self-clocked mode (SCM) operation

1.5.9

Main oscillator

The main oscillator provides these features:

●

Input frequency range 4 MHz to 40 MHz

Crystal input mode or Oscillator input mode

PLL reference

1.5.10

Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current

charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap

reference voltage.

The RC Oscillator provides these features:

●

Nominal frequency 16 MHz

6% variation over voltage and temperature after process trim

Clock output of the RC oscillator serves as system clock source in case loss of lock or

loss of clock is detected by the PLL

●

RC oscillator is used as the default system clock during startup

1.5.11

1.5.12

Periodic interrupt timer (PIT)

The PIT module implements these features:

●

Up to four general purpose interrupt timers

32-bit counter resolution

Clocked by system clock frequency

Each channel can be used as trigger for a DMA request

System timer module (STM)

The STM module implements these features:

●

32-bit up counter with 8-bit prescaler

Four 32-bit compare channels

Independent interrupt source for each channel

Counter can be stopped in debug mode

The STM module is replicated for each processor.

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1.5.13

Software watchdog timer (SWT)

The SWT has the following features:

●

Fault tolerant output

●

Safe internal RC oscillator as reference clock

Windowed watchdog

Program flow control monitor with 16-bit pseudorandom key generation

The SWT module is replicated for each processor.

1.5.14

Fault collection and control unit (FCCU)

The FCCU provides an independent fault reporting mechanism even if the CPU is exhibiting

unstable behaviors. The FCCU module has the following features:

●

Redundant collection of hardware checker results

●

Redundant collection of error information and latch of faults from critical modules on

the device

●

Collection of self-test results

Configurable and graded fault control

–

Internal reactions (no internal reaction, IRQ)

External reaction (failure is reported to the external/surrounding system via

configurable output pins)

1.5.15

System integration unit (SIUL)

The SPC56xP54/60 SIUL controls MCU pad configuration, external interrupts, general

purpose I/O (GPIO) pin configuration, and internal peripheral multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The

GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The SIUL provides the following features:

●

Centralized general purpose input output (GPIO) control of input/output pins and

analog input-only pads (package dependent)

●

All GPIO pins can be independently configured to support pull-up, pull down, or no pull

Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

All peripheral pins (except ADC channels) can be alternatively configured as both

general purpose input or output pins

●

ADC channels support alternative configuration as general purpose inputs

Direct readback of the pin value is supported on all pins through the SIU

Configurable digital input filter that can be applied to some general purpose input pins

for noise elimination

–

Up to 4 internal functions can be multiplexed onto one pin

1.5.16

Boot and censorship

Different booting modes are available in the SPC56xP54/60:

●

From internal flash memory

Via a serial link

●

18/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Introduction

The default booting scheme is the one which uses the internal flash memory (an internal

pull-down is used to select this mode). The alternate option allows the user to boot via

FlexCAN or LINFlex (using the boot assist module software).

A censorship scheme is provided to protect the contents of the flash memory and offer

increased security for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile

memory.

Boot assist module (BAM)

The BAM is a block of read-only one-time programmed memory and is identical for all

SPC56xP54/60 devices that are based on the e200z0h core. The BAM program is executed

every time the device is powered on if the alternate boot mode has been selected by the

user.

The BAM provides the following features:

●

Serial bootloading via FlexCAN or LINFlex.

●

BAM can accept a password via the used serial communication channel to grant the

legitimate user access to the non-volatile memory.

1.5.17

1.5.18

Error correction status module (ECSM)

The ECSM on this device features the following:

●

Platform configuration and revision

ECC error reporting for flash memory and SRAM

ECC error injection for SRAM

The ECSM module is replicated for each processor.

FlexCAN

The FlexCAN module is a communication controller implementing the CAN protocol

according to Bosch Specification version 2.0B. The CAN protocol was designed to be used

primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-

time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness

and required bandwidth. FlexCAN module contains 32 message buffers.

Doc ID 18340 Rev 3

19/104

Introduction

SPC56xP54x, SPC56xP60x

The FlexCAN module provides the following features:

Full implementation of the CAN protocol specification, Version 2.0B

●

–

Standard data and remote frames

Extended data and remote frames

0 to 8 bytes data length

Programmable bit rate as fast as 1 Mbit/s

●

32 message buffers of 0 to 8 bytes data length

Each message buffer configurable as Rx or Tx, all supporting standard and extended

messages

●

Programmable loop-back mode supporting self-test operation

3 programmable mask registers

Programmable transmit-first scheme: lowest ID or lowest buffer number

Time stamp based on 16-bit free-running timer

Global network time, synchronized by a specific message

Maskable interrupts

Independent of the transmission medium (an external transceiver is assumed)

High immunity to EMI

Short latency time due to an arbitration scheme for high-priority messages

Transmit features

–

Supports configuration of multiple mailboxes to form message queues of scalable

depth

–

Arbitration scheme according to message ID or message buffer number

Internal arbitration to guarantee no inner or outer priority inversion

Transmit abort procedure and notification

●

Receive features

–

Individual programmable filters for each mailbox

8 mailboxes configurable as a six-entry receive FIFO

8 programmable acceptance filters for receive FIFO

Programmable clock source

–

System clock

Direct oscillator clock to avoid PLL jitter

1.5.19

Safety port (FlexCAN)

The SPC56xP54/60 MCU has a second CAN controller synthesized to run at high bit rates

to be used as a safety port. The CAN module of the safety port provides the following

features:

●

Identical to the FlexCAN module

●

Bit rate as fast as 7.5 Mb at 60 MHz CPU clock using direct connection between CAN

modules (no physical transceiver required)

●

32 Message buffers of 0 to 8 bytes data length

Can be used as a third independent CAN module

20/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Introduction

1.5.20

FlexRay

The FlexRay module provides the following features:

●

Full implementation of FlexRay Protocol Specification 2.1

64 configurable message buffers can be handled

Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate

Message buffers configurable as Tx, Rx or RxFIFO

Message buffer size configurable

Message filtering for all message buffers based on FrameID, cycle count and message

ID

●

Programmable acceptance filters for RxFIFO message buffers

1.5.21

Serial communication interface module (LINFlex)

The LINFlex on the SPC56xP54/60 features the following:

●

Supports LIN Master mode (on both modules), LIN Slave mode (on one module) and

UART mode

●

LIN state machine compliant to LIN1.3, 2.0, and 2.1 Specifications

Handles LIN frame transmission and reception without CPU intervention

LIN features

–

Autonomous LIN frame handling

Message buffer to store Identifier and up to 8 data bytes

Supports message length as long as 64 bytes

Detection and flagging of LIN errors: Sync field; Delimiter; ID parity; Bit; Framing;

Checksum and Time-out errors

–

Classic or extended checksum calculation

Configurable Break duration as long as 36-bit times

Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)

Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

Interrupt-driven operation with 16 interrupt sources

●

LIN slave mode features

–

Autonomous LIN header handling

Autonomous LIN response handling

UART mode

–

Full-duplex operation

Standard non return-to-zero (NRZ) mark/space format

Data buffers with 4-byte receive, 4-byte transmit

Configurable word length (8-bit or 9-bit words)

Error detection and flagging

Parity, Noise and Framing errors

Interrupt-driven operation with four interrupt sources

Separate transmitter and receiver CPU interrupt sources

16-bit programmable baud-rate modulus counter and 16-bit fractional

2 receiver wake-up methods

Doc ID 18340 Rev 3

21/104

Introduction

SPC56xP54x, SPC56xP60x

1.5.22

Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial

interface for communication between the SPC56xP54/60 MCU and external devices.

The DSPI modules provide these features:

●

Full duplex, synchronous transfers

Master or slave operation

●

Programmable master bit rates

Programmable clock polarity and phase

End-of-transmission interrupt flag

Programmable transfer baud rate

Programmable data frames from 4 to 16 bits

Up to 28 chip select lines available

–

8 each on DSPI_0 and DSPI_1

4 each on DSPI_2, DSPI_3, and DSPI_4

●

8 clock and transfer attributes registers

Chip select strobe available as alternate function on one of the chip select pins for

deglitching

●

FIFOs for buffering up to 5 transfers on the transmit and receive side

Queueing operation possible through use of the eDMA

General purpose I/O functionality on pins when not used for SPI

1.5.23

eTimer

Two eTimer modules are provided, each with six 16-bit general purpose up/down

timer/counter per module. The following features are implemented:

●

Individual channel capability

–

Input capture trigger

Output compare

Double buffer (to capture rising edge and falling edge)

Separate prescaler for each counter

Selectable clock source

0% to 100% pulse measurement

Rotation direction flag (Quad decoder mode)

●

Maximum count rate

–

Equals peripheral clock/2 — for external event counting

Equals peripheral clock — for internal clock counting

●

Cascadeable counters

Programmable count modulo

Quadrature decode capabilities

Counters can share available input pins

Count once or repeatedly

Preloadable counters

Pins available as GPIO when timer functionality not in use

22/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Introduction

1.5.24

Analog-to-digital converter (ADC)

The ADC module provides the following features:

Analog part:

●

1 on-chip analog-to-digital converter

10-bit AD resolution

1 sample and hold unit per ADC

Conversion time, including sampling time, less than 1 s (at full precision)

Typical sampling time is 150 ns min. (at full precision)

Differential non-linearity error (DNL) 1 LSB

Integral non-linearity error (INL) 1.5 LSB

Total unadjusted error (TUE) <3 LSB

Single-ended input signal range from 0 to 3.3 V / 5.0 V

ADC and its reference can be supplied with a voltage independent from V

DDIO

ADC supply can be equal or higher than V

DDIO

ADC supply and the ADC reference are not independent from each other (they are

internally bonded to the same pad)

●

Sample times of 2 (default), 8, 64, or 128 ADC clock cycles

Digital part:

●

27 input channels (26 + 1 internally connected)

●

4 analog watchdogs to compare ADC results against predefined levels (low, high,

range) before results are stored

●

2 operating modes: Normal mode and CTU control mode

Normal mode features

–

Register-based interface with the CPU: control register, status register, 1 result

register per channel

–

ADC state machine managing 3 request flows: regular command, hardware

injected command, and software injected command

–

Selectable priority between software and hardware injected commands

DMA compatible interface

●

CTU control mode features

–

Triggered mode only

4 independent result queues (2 × 16 entries, 2 × 4 entries)

Result alignment circuitry (left justified; right justified)

32-bit read mode allows to have channel ID on one of the 16-bit part

DMA compatible interfaces

1.5.25

Cross triggering unit (CTU)

The Cross Triggering Unit (CTU) allows automatic generation of ADC conversion requests

on user selected conditions with minimized CPU load for dynamic configuration.

Doc ID 18340 Rev 3

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Introduction

SPC56xP54x, SPC56xP60x

It implements the following features:

●

Double buffered trigger generation unit with up to eight independent triggers generated

from external triggers

●

Trigger generation unit configurable in sequential mode or in triggered mode

Each Trigger can be appropriately delayed to compensate the delay of external low

pass filter

●

Double buffered global trigger unit allowing eTimer synchronization and/or ADC

command generation

●

Double buffered ADC command list pointers to minimize ADC-trigger unit update

Double buffered ADC conversion command list with up to 24 ADC commands

Each trigger has the capability to generate consecutive commands

ADC conversion command allows to control ADC channel from each ADC, single or

synchronous sampling, independent result queue selection

1.5.26

Cyclic redundancy check (CRC)

●

3 contexts for the concurrent CRC computation

Separate CRC engine for each context

Zero-wait states during the CRC computation (pipeline scheme)

3 hard-wired polynomials (CRC-8 VDA CAN, CRC-32 ethernet and CRC-16-CCITT)

Support for byte/half-word/word width of the input data stream

Support for expected and actual CRC comparison

1.5.27

Nexus development interface (NDI)

The NDI block provides real-time development support capabilities for the SPC56xP54/60

Power Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard.

This development support is supplied for MCUs without requiring external address and data

pins for internal visibility. The NDI block is an integration of several individual Nexus blocks

that are selected to provide the development support interface for this device. The NDI block

interfaces to the host processor and internal buses to provide development support as per

the IEEE-ISTO 5001-2003 Class 2+ standard. The development support provided includes

access to the MCU’s internal memory map and access to the processor’s internal registers

during run time.

24/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Introduction

The Nexus Interface provides the following features:

●

Configured via the IEEE 1149.1

All Nexus port pins operate at V

Nexus 2+ features supported

(no dedicated power supply)

DDIO

–

Static debug

Watchpoint messaging

Ownership trace messaging

Program trace messaging

Real time read/write of any internally memory mapped resources through JTAG

pins

–

Overrun control, which selects whether to stall before Nexus overruns or keep

executing and allow overwrite of information

–

Watchpoint triggering, watchpoint triggers program tracing

DDR

●

Auxiliary Output Port

–

4 MDO (Message Data Out) pins

MCKO (Message Clock Out) pin

2 MSEO (Message Start/End Out) pins

EVTO (Event Out) pin

●

Auxiliary Input Port

EVTI (Event In) pin

–

1.5.28

IEEE 1149.1 (JTAG) controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and

connectivity while remaining transparent to system logic when not in test mode. All data

input to and output from the JTAGC block is communicated in serial format. The JTAGC

block is compliant with the IEEE standard.

The JTAG controller provides the following features:

●

IEEE Test Access Port (TAP) interface with four pins (TDI, TMS, TCK, TDO)

Selectable modes of operation include JTAGC/debug or normal system operation.

A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

–

BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD

●

A 5-bit instruction register that supports the additional following public instructions:

–

ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_CORE0,

ACCESS_AUX_TAP_CORE1, ACCESS_AUX_TAP_NASPS_0,

ACCESS_AUX_TAP_NASPS_1

●

Three test data registers: a bypass register, a boundary scan register, and a device

identification register.

A TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry.

Doc ID 18340 Rev 3

25/104

Introduction

SPC56xP54x, SPC56xP60x

1.5.29

On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

●

Uses external NPN transistor

●

Regulates external 3.3 V to 5.0 V down to 1.2 V for the core logic

Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

26/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

2

Package pinouts and signal descriptions

2.1

Package pinouts

The LQFP pinouts are shown in the following figures.

(a)

Figure 2.

LQFP176 pinout (top view)

NMI

1

PA[4]

V

PF[12]

PD[14]

PG[3]

PC[14]

PG[2]

PC[13]

PG[4]

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

PA[6]

2

PP_TEST

PD[1]

3

PF[4]

4

V

5

DD_HV_IO5

SS_HV_IO5

MDO4

V

6

7

MDO5

MDO6

NC

8

9

PD[12]

PG[6]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

NC

V

DD_HV_FL

SS_HV_FL

PF[5]

V

PD[13]

DD_HV_IO0

SS_HV_IO0

PF[6]

V

SS_LV_COR1

DD_LV_COR1

MDO0

PA[7]

PC[4]

PA[8]

PC[5]

PA[5]

PC[7]

PC[3]

PA[3]

V

DD_HV_IO2

SS_HV_IO2

NC

MDO9

MDO8

MDO7

LQFP176

V

SS_HV_IO6

DD_HV_IO6

V

SS_LV_COR0

TDO

DD_LV_COR0

PF[7]

TCK

PF[8]

TMS

V

TDI

DD_HV_IO1

SS_HV_IO1

PF[9]

PF[10]

PF[11]

PD[9]

DD_HV_OSC

SS_HV_OSC

XTAL

EXTAL

RESET

PD[8]

PG[5]

PA[2]

PG[7]

PC[12]

NC

V

NC

98

PG[8]

PC[11]

PG[9]

PD[11]

PG[10]

PD[10]

PG[11]

PA[1]

PA[0]

97

96

95

94

93

PD[5]

PD[6]

SS_LV_COR3

DD_LV_COR3

92

91

V

90

89

a. Software development package only. Not available for production.

Doc ID 18340 Rev 3

27/104

Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

(b)

Figure 3.

LQFP144 pinout (top view)

NMI

PA[6]

PD[1]

PF[4]

PF[5]

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

PA[4]

V

PP_TEST

PF[12]

PD[14]

PG[3]

PC[14]

PG[2]

PC[13]

PG[4]

PD[12]

PG[6]

V

DD_HV_IO0

SS_HV_IO0

PF[6]

MDO

PA[7]

PC[4]

PA[8]

PC[5]

PA[5]

PC[7]

PC[3]

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

V

DD_HV_FL

SS_HV_FL

PD[13]

V

SS_LV_COR1

DD_LV_COR1

V

SS_LV_COR0

DD_LV_COR0

PF[7]

PA[3]

V

DD_HV_IO2

LQFP144

SS_HV_IO2

TDO

TCK

TMS

TDI

PG[5]

PA[2]

PG[7]

PC[12]

PG[8]

PC[11]

PG[9]

PD[11]

PG[10]

PD[10]

PG[11]

PA[1]

PF[8]

V

DD_HV_IO1

SS_HV_IO1

PF[9]

PF[10]

PF[11]

PD[9]

V

DD_HV_OSC

SS_HV_OSC

XTAL

EXTAL

RESET

PD[8]

PD[5]

PD[6]

V

SS_LV_COR3

DD_LV_COR3

PA[0]

V

b. Availability of port pin alternate functions depends on product selection

Doc ID 18340 Rev 3

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SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

(c)

Figure 4.

LQFP100 pinout (top view)

75

74

73

72

71

70

69

68

67

66

65

PA[4]

V

PD[14]

PC[14]

PC[13]

PD[12]

NMI

PA[6]

PD[1]

PA[7]

PC[4]

PA[8]

PC[5]

PA[5]

PC[7]

PC[3]

1

2

PP TEST

3

4

5

6

V

7

DD_HV_FL

SS_HV_FL

V

8

PD[13]

9

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SS_LV_COR1

DD_LV_COR1

V

SS_LV_COR0

DD_LV_COR0

DD_HV_IO1

64 PA[3]

63

62

V

DD_HV_IO2

SS_HV_IO2

LQFP100

SS_HV_IO1

61 TDO

PD[9]

TCK

V

60

59

58

57

56

55

54

53

52

51

DD_HV_OSC

SS_HV_OSC

XTAL

EXTAL

RESET

PD[8]

PD[5]

PD[6]

TMS

TDI

PA[2]

PC[12]

PC[11]

PD[11]

PD[10]

PA[1]

PA[0]

V

SS_LV_COR3

DD_LV_COR3

2.2

Pin descriptions

The following sections provide signal descriptions and related information about the

functionality and configuration of the SPC56xP54/60 devices.

2.2.1

Power supply and reference voltage pins

Table 5 lists the power supply and reference voltage for the SPC56xP54/60 devices.

Table 5.

Supply pins

Supply

LQFP LQFP LQFP

Symbol

Description

100

144

176⁽¹⁾

VREG control and power supply pins

BCTRL

Voltage regulator external NPN Ballast base control pin

47

50

69

72

81

86

V_{DD_HV_REG}(3.3 V or

5.0 V)

Voltage regulator supply voltage

c. Availability of port pin alternate functions depends on product selection

Doc ID 18340 Rev 3

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Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

Table 5.

Supply pins (continued)

Supply

LQFP LQFP LQFP

Symbol

Description

100

144

176⁽¹⁾

1.2 V decoupling⁽²⁾pins for core logic supply and voltage

regulator feedback. Decoupling capacitor must be connected

between this pins and V_{SS_LV_REGCOR.}

V_{DD_LV_REGCOR}

48

70

82

1.2 V decoupling⁽²⁾pins for core logic GND and voltage regulator

feedback. Decoupling capacitor must be connected between this

pins and V_{DD_LV_REGCOR.}

V_{SS_LV_REGCOR}

49

71

85

ADC0 reference and supply voltage

ADC supply and high reference voltage

ADC ground and low reference voltage

Power supply pins (3.3 V or 5.0 V)

Input/Output supply voltage

Input/Output ground

V_{DD_HV_AD}

V_{SS_HV_AD}

39

40

56

57

64

65

V_{DD_HV_IO0}

V_{SS_HV_IO0}

V_{DD_HV_IO1}

V_{SS_HV_IO1}

V_{DD_HV_IO2}

V_{SS_HV_IO2}

V_{DD_HV_IO3}

V_{SS_HV_IO3}

V_{DD_HV_IO4}

V_{SS_HV_IO4}

V_{DD_HV_IO5}

V_{SS_HV_IO5}

V_{DD_HV_IO6}

V_{SS_HV_IO6}

V_{DD_HV_FL}

V_{SS_HV_FL}

V_{DD_HV_OSC}

V_{SS_HV_OSC}

—

13

14

63

62

87

88

—

69

68

16

17

6

7

14

15

Input/Output supply voltage

Input/Output ground

21

22

91

90

126

127

—

29

30

Input/Output supply voltage

Input/Output ground

115

114

150

151

169

170

5

Input/Output supply voltage

Input/Output ground

Input/Output supply voltage

Input/Output ground

—

Input/Output supply voltage

Input/Output ground

—

6

Input/Output supply voltage

Input/Output ground

—

108

109

121

120

35

—

Code and data flash supply voltage

Code and data flash supply ground

Crystal oscillator amplifier supply voltage

Crystal oscillator amplifier ground

Power supply pins (1.2 V)

97

96

27

28

36

1.2 V Decoupling pins for core logic supply. Decoupling capacitor

must be connected between these pins and the nearest

V_{SS_LV_COR0}pin.

V_{DD_LV_COR0}

12

11

18

17

26

25

1.2 V Decoupling pins for core logic GND. Decoupling capacitor

must be connected between these pins and the nearest

V_{DD_LV_COR0}pin_.

V_{SS_LV_COR0}

30/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

Table 5.

Supply pins (continued)

Supply

LQFP LQFP LQFP

Symbol

Description

100

144

176⁽¹⁾

1.2 V Decoupling pins for core logic supply. Decoupling capacitor

must be connected between these pins and the nearest

V_{SS_LV_COR1}pin.

V_{DD_LV_COR1}

V_{SS_LV_COR1}

V_{DD_LV_COR2}

V_{SS_LV_COR2}

V_{DD_LV_COR3}

V_{SS_LV_COR3}

65

93

117

1.2 V Decoupling pins for core logic GND. Decoupling capacitor

must be connected between these pins and the nearest

V_{DD_LV_COR1}pin.

66

92

93

25

24

94

131

132

36

118

155

156

44

1.2 V Decoupling pins for core logic supply. Decoupling capacitor

must be connected between these pins and the nearest

V_{SS_LV_COR2}pin.

1.2 V Decoupling pins for core logic GND. Decoupling capacitor

must be connected between these pins and the nearest

V_{DD_LV_COR 2}pin.

1.2 V Decoupling pins for core logic supply. Decoupling capacitor

must be connected between these pins and the nearest

V_{SS_LV_COR3}pin.

1.2 V Decoupling pins for core logic GND. Decoupling capacitor

must be connected between these pins and the nearest

V_{DD_LV_COR 3}pin.

35

43

1. LQFP176 available only as development package.

2. See datasheet Voltage Regulator Electrical Characteristics section for more details.

2.2.2

System pins

Table 6 and Table 7 contain information on pin functions for the SPC56xP54/60 devices. The

pins listed in Table 6 are single-function pins. The pins shown in Table 7 are multi-function

pins, programmable via their respective Pad Configuration Register (PCR) values.

Table 6.

System pins

Pad Speed⁽¹⁾

Symbol

Description

Direction

LQFP LQFP LQFP

100

SRC=0 SRC=1

144 176⁽²⁾

Dedicated pins

Output

Only

MDO0

MDO4

MDO5

MDO6

Nexus Message Data Output—line 0

Nexus Message Data Output—line 4

Nexus Message Data Output—line 5

Nexus Message Data Output—line 6

Fast

—

9

17

7

Output

Only

—

Output

Only

8

Output

Only

9

Doc ID 18340 Rev 3

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Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

Table 6.

System pins (continued)

Description

Pad Speed⁽¹⁾

Symbol

Direction

LQFP LQFP LQFP

100

SRC=0 SRC=1

144 176⁽²⁾

Output

Only

MDO7

MDO8

MDO9

MDO10

MDO11

Nexus Message Data Output—line 7

Nexus Message Data Output—line 8

Nexus Message Data Output—line 9

Nexus Message Data Output—line 10

Nexus Message Data Output—line 11

Fast

—

110

111

112

166

171

Output

Only

—

Output

Only

Output

Only

Output

Only

Output

Only

RDY

NMI

Nexus ready output

—

1

—

1

172

1

Non-Maskable Interrupt

Input Only

Analog output of the oscillator amplifier

circuit. Needs to be grounded if oscillator is

used in bypass mode.

XTAL

—

18

29

37

Analog input of the oscillator amplifier

circuit, when the oscillator is not in bypass

mode.

EXTAL

—

19

30

38

Analog input for the clock generator when

the oscillator is in bypass mode.

TMS⁽³⁾

TCK⁽³⁾

TDI⁽³⁾

JTAG state machine control

JTAG clock

Input Only

—

59

60

58

87

88

86

105

106

104

JTAG data input

Output

Only

TDO⁽³⁾

JTAG data output

—

61

89

107

Reset pin

Bidirectional reset with Schmitt trigger

characteristics and

Bidirec-

tional

RESET⁽⁴⁾

Medium

—

20

31

39

noise filter

Test pin

Pin for testing purpose only. To be tied to

ground in normal operating mode.

V_{PP TEST}

—

74

34

107

51

131

59

Pin for testing purpose only. To be tied to

ground in normal operating mode.

V_{REG_BYPASS}

1. SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

2. LQFP176 available only as development package.

3. In this pin there is an internal pull, refer to JTAGC chapter in the device reference manual for pull direction.

4. Its configuration can be set up by the PCR[108] register inside the SIU module. See SIUL chapter in the device reference

manual.

32/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

2.2.3

Pin muxing

Table 7 defines the pin list and muxing for the SPC56xP54/60 devices relative to Full-

featured version.

Each row of Table 7 shows all the possible ways of configuring each pin, via “alternate

functions”. The default function assigned to each pin after reset is the ALT0 function.

Pins marked as external interrupt capable can also be used to resume from STOP and

HALT mode.

SPC56xP54/60 devices provide four main I/O pad types depending on the associated

functions:

●

Slow pads are the most common, providing a compromise between transition time and

low electromagnetic emission.

Medium pads provide fast enough transition for serial communication channels with

controlled current to reduce electromagnetic emission.

Fast pads provide maximum speed. They are used for improved NEXUS debugging

capability.

Symmetric pads are designed to meet FlexRay requirements.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at

the cost of reducing AC performance.

(1)

Table 7.

Pin muxing

Pad speed⁽⁶⁾

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

SRC = 0 SRC = 1

100

144 176⁽⁷⁾

Port A

ALT0

ALT1

ALT2

ALT3

—

GPIO[0]

ETC[0]

SCK_2

F[0]

SIUL

eTimer_0

DSPI_2

FCCU

I/O

O

A[0]

A[1]

PCR[0]

PCR[1]

Slow

Medium

51

73

74

89

90

EIRQ[0]

SIUL

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[1]

ETC[1]

SOUT_2

F[1]

SIUL

eTimer_0

DSPI_2

FCCU

I/O

O

52

57

O

EIRQ[1]

SIUL

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[2]

ETC[2]

CS3

SIUL

eTimer_0

DSPI_4

—

I/O

O

—

I

A[2]⁽⁸⁾PCR[2]

—

Slow

Medium

84

102

SIN_2

ABS[0]

EIRQ[2]

DSPI_2

MC_RGM

SIUL

—

I

—

I

Doc ID 18340 Rev 3

33/104

Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

SRC = 0 SRC = 1

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[3]

ETC[3]

CS0_2

—

SIUL

eTimer_0

DSPI_2

—

I/O

—

I

A[3]⁽⁸⁾PCR[3]

Slow

Medium

64

92

116

132

ABS[1]

EIRQ[3]

MC_RGM

SIUL

—

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[4]

ETC[0]

CS1_2

ETC[4]

FAB

SIUL

eTimer_1

DSPI_2

eTimer_0

MC_RGM

SIUL

I/O

O

A[4]⁽⁸⁾PCR[4]

75

108

I/O

I

—

EIRQ[4]

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[5]

CS0_1

ETC[5]

CS7_0

EIRQ[5]

SIUL

DSPI_1

eTimer_1

DSPI_0

SIUL

I/O

O

A[5]

A[6]

A[7]

PCR[5]

PCR[6]

PCR[7]

Slow

Medium

8

2

4

14

22

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[6]

SCK_1

CS2_4

—

SIUL

DSPI_1

DSPI_4

—

I/O

—

I

2

EIRQ[6]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[7]

SOUT_1

CS1_4

—

SIUL

DSPI_1

DSPI_4

—

I/O

O

I/O

—

I

10

18

EIRQ[7]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[8]

—

SIUL

—

I/O

—

I/O

—

I

CS0_4

—

DSPI_4

—

A[8]

A[9]

PCR[8]

PCR[9]

Slow

Medium

6

12

20

SIN_1

EIRQ[8]

DSPI_1

SIUL

—

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[9]

CS1_2

—

SIUL

DSPI_2

—

I/O

O

—

I

94

134

158

—

SIN_4

DSPI_4

34/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

SRC = 0 SRC = 1

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[10]

CS0_2

—

SIUL

DSPI_2

—

I/O

—

I

A[10] PCR[10]

A[11] PCR[11]

A[12] PCR[12]

Slow

Medium

81

118

120

122

142

144

146

—

EIRQ[9]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[11]

SCK_2

—

SIUL

DSPI_2

—

I/O

—

I

82

83

—

EIRQ[10]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[12]

SOUT_2

—

SIUL

DSPI_2

—

I/O

O

—

I

—

EIRQ[11]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[13]

CS4_1

—

SIUL

DSPI_1

—

I/O

—

I

A[13] PCR[13]

A[14] PCR[14]

A[15] PCR[15]

Slow

Medium

95

99

136

143

144

160

175

176

—

SIN_2

EIRQ[12]

DSPI_2

SIUL

—

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[14]

TXD

SIUL

Safety Port

eTimer_1

DSPI_1

SIUL

I/O

O

ETC[4]

CS5_1

EIRQ[13]

I/O

O

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[15]

CS6_1

ETC[5]

—

SIUL

DSPI_1

eTimer_1

—

I/O

O

I/O

—

I

Medium 100

RXD

Safety Port

SIUL

—

EIRQ[14]

I

Port B

ALT0

ALT1

ALT2

ALT3

—

GPIO[16]

TXD

SIUL

FlexCAN_0

eTimer_1

SSCM

I/O

O

B[0] PCR[16]

ETC[2]

I/O

—

I

Slow

Medium

76

109

133

DEBUG[0]

EIRQ[15]

SIUL

Doc ID 18340 Rev 3

35/104

Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

SRC = 0 SRC = 1

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[17]

CS7_1

SIUL

DSPI_1

eTimer_1

SSCM

I/O

O

I/O

—

I

ETC[3]

B[1] PCR[17]

Slow

Medium

77

110

134

DEBUG[1]

RXD

FlexCAN_0

SIUL

—

EIRQ[16]

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[18]

TXD

SIUL

LINFlex_0

DSPI_4

SSCM

I/O

O

B[2] PCR[18]

B[3] PCR[19]

SOUT_4

DEBUG[2]

EIRQ[17]

I/O

—

I

Slow

Medium

79

80

114

116

138

140

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[19]

—

SIUL

—

I/O

—

I/O

—

I

SCK_4

DEBUG[3]

RXD

DSPI_4

SSCM

LINFlex_0

ALT0

ALT1

ALT2

ALT3

SIUL

I/O

O

GPIO[22]

clk_out

MC_CGL

DSPI_2

MC_CGL

O

B[6] PCR[22]

CS2_2

Slow

Medium

96

29

138

162

O

clk_out_div256

EIRQ[18]

—

SIUL

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[23]

—

SIUL

—

B[7] PCR[23]

Input Only

—

43

51

—

AN[0]

RXD

ADC_0

LINFlex_0

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[24]

—

SIUL

—

B[8] PCR[24]

Input Only

—

31

35

47

52

55

60

—

AN[1]

ETC[5]

ADC_0

eTimer_0

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[25]

—

SIUL

—

B[9] PCR[25]

—

AN[11]

ADC_0

36/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

SRC = 0 SRC = 1

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[26]

—

SIUL

—

B[10] PCR[26]

B[11] PCR[27]

B[12] PCR[28]

—

Input Only

—

36

53

54

55

61

62

63

—

AN[12]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[27]

—

SIUL

—

37

38

—

AN[13]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[28]

—

SIUL

—

AN[14]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[29]

—

SIUL

—

B[13] PCR[29]

B[14] PCR[30]

B[15] PCR[31]

Input Only

—

42

44

43

60

64

62

68

76

70

—

AN[16]

RXD

ADC_0

LINFlex_1

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[30]

—

SIUL

—

AN[17]

ETC[4]

EIRQ[19]

ADC_0

eTimer_0

SIUL

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[31]

—

SIUL

—

AN[18]

EIRQ[20]

ADC_0

SIUL

—

Port C

ALT0

ALT1

ALT2

ALT3

—

GPIO[32]

—

SIUL

—

C[0] PCR[32]

—

Input Only

—

45

66

78

—

AN[19]

ADC_0

Doc ID 18340 Rev 3

37/104

Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

SRC = 0 SRC = 1

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[33]

SIUL

—

C[1] PCR[33]

C[2] PCR[34]

C[3] PCR[35]

C[4] PCR[36]

C[5] PCR[37]

C[6] PCR[38]

—

Input Only

—

28

41

45

49

53

—

AN[2]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[34]

SIUL

—

30

10

5

—

AN[3]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[35]

CS1_0

ETC[4]

TXD

SIUL

DSPI_0

eTimer_1

LINFlex_1

SIUL

I/O

O

I/O

O

Slow

Medium

16

24

EIRQ[21]

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[36]

CS0_0

SIUL

DSPI_0

—

I/O

—

I

—

11

19

DEBUG[4]

EIRQ[22]

SSCM

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[37]

SCK_0

SIUL

DSPI_0

DSPI_4

SSCM

SIUL

I/O

—

I

SCK_4

7

13

21

DEBUG[5]

EIRQ[23]

ALT0

ALT1

ALT2

ALT3

—

GPIO[38]

SOUT_0

—

SIUL

DSPI_0

—

I/O

O

—

I

98

142

174

DEBUG[6]

EIRQ[24]

SSCM

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[39]

—

SIUL

—

I/O

—

I

—

C[7] PCR[39]

C[8] PCR[40]

Slow

Medium

9

15

23

DEBUG[7]

SIN_0

SIN_4

SSCM

DSPI_0

DSPI_4

—

I

ALT0

ALT1

ALT2

ALT3

GPIO[40]

CS1_1

CS1_4

CS6_0

SIUL

I/O

O

DSPI_1

DSPI_4

DSPI_0

91

130

154

O

38/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

SRC = 0 SRC = 1

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

GPIO[41]

CS3_2

CS0_4

—

SIUL

DSPI_2

DSPI_4

—

I/O

O

C[9] PCR[41]

C[10] PCR[42]

C[11] PCR[43]

C[12] PCR[44]

Slow

Medium

84

123

111

80

147

135

96

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[42]

CS2_2

CS2_4

—

SIUL

DSPI_2

DSPI_4

—

I/O

O

78

55

56

O

—

ALT0

ALT1

ALT2

ALT3

GPIO[43]

ETC[4]

CS2_2

CS0_3

SIUL

I/O

O

eTimer_0

DSPI_2

DSPI_3

I/O

ALT0

ALT1

ALT2

ALT3

GPIO[44]

ETC[5]

CS3_2

CS1_3

SIUL

I/O

O

eTimer_0

DSPI_2

DSPI_3

82

100

O

ALT0

ALT1

ALT2

ALT3

—

GPIO[45]

ETC[1]

—

SIUL

eTimer_1

—

I/O

—

I

C[13] PCR[45]

Slow

Medium

71

101

125

—

EXT_IN

RXD

CTU_0

FlexCAN_1

—

I

ALT0

ALT1

ALT2

ALT3

GPIO[46]

ETC[2]

SIUL

I/O

O

eTimer_1

CTU_0

C[14] PCR[46]

C[15] PCR[47]

Slow

72

85

103

124

127

148

EXT_TGR

TXD

FlexCAN_1

O

ALT0

ALT1

ALT2

ALT3

—

GPIO[47]

CA_TR_EN

ETC[0]

SIUL

FlexRay_0

eTimer_1

—

I/O

O

Symmet-

ric

I/O

—

I

—

EXT_IN

CTU_0

Port D

ALT0

ALT1

ALT2

ALT3

GPIO[48]

CA_TX

ETC[1]

—

SIUL

FlexRay_0

eTimer_1

—

I/O

O

Symmet-

ric

D[0] PCR[48]

Slow

86

125

149

I/O

—

Doc ID 18340 Rev 3

39/104

Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

SRC = 0 SRC = 1

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[49]

CS4_1

SIUL

DSPI_1

I/O

O

D[1] PCR[49]

D[2] PCR[50]

ETC[2]

eTimer_1

CTU_0

I/O

O

Slow

Medium

3

EXT_TRG

CA_RX

FlexRay_0

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[50]

CS5_1

ETC[3]

—

SIUL

DSPI_1

eTimer_1

—

I/O

O

I/O

—

I

97

140

168

CB_RX

FlexRay_0

ALT0

ALT1

ALT2

ALT3

GPIO[51]

CB_TX

ETC[4]

—

SIUL

FlexRay_0

eTimer_1

—

I/O

O

Symmet-

ric

D[3] PCR[51]

D[4] PCR[52]

D[5] PCR[53]

D[6] PCR[54]

Slow

89

90

22

23

128

129

33

152

153

41

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[52]

CB_TR_EN

ETC[5]

SIUL

FlexRay_0

eTimer_1

—

I/O

O

Symmet-

ric

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[53]

CS3_0

—

SIUL

DSPI_0

—

I/O

O

Medium

—

O

SOUT_3

DSPI_3

ALT0

ALT1

ALT2

ALT3

GPIO[54]

CS2_0

SIUL

I/O

O

DSPI_0

DSPI_3

DSPI_4

34

42

SCK_3

I/O

O

SOUT_4

ALT0

ALT1

ALT2

ALT3

—

GPIO[55]

CS3_1

—

SIUL

DSPI_1

—

I/O

O

—

O

I

D[7] PCR[55]

Slow

Medium

26

37

45

CS4_0

SIN_3

DSPI_0

DSPI_3

ALT0

ALT1

ALT2

ALT3

GPIO[56]

CS2_1

RDY

SIUL

I/O

O

DSPI_1

nexus_0

DSPI_0

D[8] PCR[56]

D[9] PCR[57]

Slow

Medium

21

15

32

26

40

34

O

CS5_0

O

ALT0

ALT1

ALT2

ALT3

GPIO[57]

—

SIUL

—

I/O

—

O

TXD

LINFlex_1

DSPI_1

CS6_1

O

40/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

SRC = 0 SRC = 1

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

GPIO[58]

—

SIUL

—

I/O

—

D[10] PCR[58]

D[11] PCR[59]

Slow

Medium

53

76

78

92

94

CS0_3

—

DSPI_3

—

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[59]

—

SIUL

—

I/O

—

54

70

67

73

CS1_3

SCK_3

DSPI_3

O

I/O

ALT0

ALT1

ALT2

ALT3

—

GPIO[60]

—

SIUL

—

I/O

—

O

D[12] PCR[60]

D[13] PCR[61]

D[14] PCR[62]

—

Slow

Medium

99

95

123

119

129

DS7_1

RXD

DSPI_1

LINFlex_1

I

ALT0

ALT1

ALT2

ALT3

GPIO[61]

—

SIUL

—

I/O

—

O

CS2_3

SOUT_3

DSPI_3

O

ALT0

ALT1

ALT2

ALT3

—

GPIO[62]

—

SIUL

—

I/O

—

O

CS3_3

—

DSPI_3

—

105

—

I

SIN_3

DSPI_3

ALT0

ALT1

ALT2

ALT3

—

GPIO[63]

—

SIUL

—

D[15] PCR[63]

—

Input Only

—

41

58

66

—

AN[20]

ADC_0

Port E

ALT0

ALT1

ALT2

ALT3

—

GPIO[64]

—

SIUL

—

E[0] PCR[64]

E[1] PCR[65]

—

Input Only

—

46

27

68

39

80

47

—

AN[21]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[65]

SIUL

—

AN[4]

ADC_0

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Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

SRC = 0 SRC = 1

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[66]

SIUL

—

E[2] PCR[66]

E[3] PCR[67]

E[4] PCR[68]

E[5] PCR[69]

E[6] PCR[70]

E[7] PCR[71]

E[8] PCR[72]

E[9] PCR[73]

—

Input Only

—

32

49

40

42

44

46

48

59

61

57

48

50

52

54

56

67

69

—

AN[5]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[67]

SIUL

—

AN[6]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[68]

SIUL

—

AN[7]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[69]

SIUL

—

AN[8]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[70]

SIUL

—

AN[9]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[71]

—

SIUL

—

AN[10]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[72]

—

SIUL

—

AN[22]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[73]

—

SIUL

—

AN[23]

ADC_0

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SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

SRC = 0 SRC = 1

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[74]

—

SIUL

—

E[10] PCR[74]

E[11] PCR[75]

E[12] PCR[76]

E[13] PCR[77]

E[14] PCR[78]

—

Input Only

—

63

65

75

77

—

AN[24]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[75]

—

SIUL

—

AN[25]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[76]

—

SIUL

—

67

79

—

AN[26]

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[77]

SCK_3

—

SIUL

DSPI_3

—

I/O

—

I

Slow

Medium

117

119

141

143

—

EIRQ[25]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[78]

SOUT_3

—

SIUL

DSPI_3

—

I/O

O

—

I

—

EIRQ[26]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[79]

—

SIUL

—

I/O

—

I

—

E[15] PCR[79]

Slow

Medium

—

121

133

145

157

—

SIN_3

EIRQ[27]

DSPI_3

SIUL

—

I

Port F

ALT0

ALT1

ALT2

ALT3

—

GPIO[80]

DBG_0

CS3_3

—

SIUL

FlexRay_0

DSPI_3

—

I/O

O

—

I

F[0] PCR[80]

EIRQ[28]

SIUL

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Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

SRC = 0 SRC = 1

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[81]

DBG_1

CS2_3

—

SIUL

FlexRay_0

DSPI_3

—

I/O

O

—

I

F[1] PCR[81]

Slow

Medium

—

135

159

EIRQ[29]

SIUL

ALT0

ALT1

ALT2

ALT3

GPIO[82]

DBG_2

CS1_3

—

SIUL

FlexRay_0

DSPI_3

—

I/O

O

F[2] PCR[82]

F[3] PCR[83]

F[4] PCR[84]

F[5] PCR[85]

F[6] PCR[86]

F[7] PCR[87]

F[8] PCR[88]

F[9] PCR[89]

Slow

Medium

Fast

—

137

139

4

161

167

4

O

—

ALT0

ALT1

ALT2

ALT3

GPIO[83]

DBG_3

CS0_3

—

SIUL

FlexRay_0

DSPI_3

—

I/O

O

I/O

—

ALT0

ALT1

ALT2

ALT3

—

MDO[3]

—

nexus_0

—

O

—

ALT0

ALT1

ALT2

ALT3

—

Fast

5

13

16

27

28

31

MDO[2]

—

nexus_0

—

O

—

ALT0

ALT1

ALT2

ALT3

GPIO[86]

—

SIUL

—

I/O

—

Fast

8

MDO[1]

—

nexus_0

—

O

—

ALT0

ALT1

ALT2

ALT3

GPIO[87]

—

SIUL

—

I/O

—

Fast

19

20

23

MCKO

—

nexus_0

—

O

—

ALT0

ALT1

ALT2

ALT3

GPIO[88]

—

SIUL

—

I/O

—

Fast

MSEO1

—

nexus_0

—

O

—

ALT0

ALT1

ALT2

ALT3

GPIO[89]

—

SIUL

—

I/O

—

Fast

MSEO0

—

nexus_0

—

O

—

44/104

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SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

SRC = 0 SRC = 1

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

GPIO[90]

—

SIUL

—

I/O

—

O

F[10] PCR[90]

F[11] PCR[91]

F[12] PCR[92]

F[13] PCR[93]

F[14] PCR[94]

Slow

Fast

—

24

25

32

33

EVTO

—

nexus_0

—

ALT0

ALT1

ALT2

ALT3

GPIO[91]

EVTI

—

SIUL

nexus_0

—

I/O

I

Medium

—

ALT0

ALT1

ALT2

ALT3

GPIO[92]

ETC[3]

—

SIUL

eTimer_1

—

I/O

—

106

112

115

130

136

139

—

ALT0

ALT1

ALT2

ALT3

GPIO[93]

ETC[4]

—

SIUL

eTimer_1

—

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[94]

TXD

—

SIUL

LINFlex_1

—

I/O

O

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[95]

SIUL

I/O

—

I

—

F[15] PCR[95]

Slow

Medium

—

113

137

—

RXD

LINFlex_1

Port G

ALT0

ALT1

ALT2

ALT3

—

GPIO[96]

F[0]

SIUL

FCCU

—

I/O

O

G[0] PCR[96]

G[1] PCR[97]

—

I

Slow

Medium

—

38

46

—

EIRQ[30]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[97]

F[1]

SIUL

FCCU

—

I/O

O

—

I

141

173

—

EIRQ[31]

SIUL

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Package pinouts and signal descriptions

SPC56xP54x, SPC56xP60x

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

SRC = 0 SRC = 1

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

—

GPIO[98]

—

SIUL

—

I/O

—

I

G[2] PCR[98]

—

Slow

Medium

—

102

126

—

SIN_4

DSPI_4

ALT0

ALT1

ALT2

ALT3

GPIO[99]

—

SIUL

—

I/O

—

O

G[3] PCR[99]

G[4] PCR[100]

G[5] PCR[101]

G[6] PCR[102]

G[7] PCR[103]

Slow

Medium

—

104

100

85

128

124

103

122

101

SOUT_4

—

DSPI_4

—

ALT0

ALT1

ALT2

ALT3

GPIO[100]

—

SIUL

—

I/O

—

SCK_4

—

DSPI_4

—

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[101]

—

SIUL

—

I/O

—

CS0_4

—

DSPI_4

—

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[102]

—

SIUL

—

I/O

—

O

98

CS1_4

—

DSPI_4

—

ALT0

ALT1

ALT2

ALT3

GPIO[103]

—

SIUL

—

I/O

—

O

83

CS2_4

—

DSPI_4

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[104]

—

SIUL

—

I/O

—

O

G[8] PCR[104]

G[9] PCR[105]

Slow

Medium

—

81

79

97

95

CS3_4

—

DSPI_4

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[105]

SIUL

I/O

—

I

—

RXD

FlexCAN_1

46/104

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SPC56xP54x, SPC56xP60x

Package pinouts and signal descriptions

(1)

Table 7.

Pin muxing (continued)

Pad speed⁽⁶⁾

Alternate

I/O

Port

PCR

register

Peripheral

function

Functions

direction

(4)

LQFP LQFP LQFP

(2),(3)

(5)

SRC = 0 SRC = 1

100

144 176⁽⁷⁾

ALT0

ALT1

ALT2

ALT3

GPIO[106]

SIUL

I/O

—

O

—

TXD

—

FlexCAN_1

—

G[10] PCR[106]

G[11] PCR[107]

Slow

Medium

—

77

75

93

91

—

ALT0

ALT1

ALT2

ALT3

GPIO[107]

SIUL

—

I/O

—

1. This table concerns Full-featured version. Please refer to “SPC56xP54/60 device configuration difference” table for

difference between Full-featured, and Airbag configuration.

2. ALT0 is the primary (default) function for each port after reset.

3. Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.

PCR[PA] = 00  ALT0; PCR[PA] = 01  ALT1; PCR[PA] = 10  ALT2; PCR[PA] = 11  ALT3. This is intended to select

the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values

selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”.

4. Module included on the MCU.

5. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the

values of the PSMI[PADSELx] bitfields inside the SIUL module.

6. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

7. LQFP176 available only as development package.

8. Weak pull down during reset.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

3

Electrical characteristics

3.1

Introduction

This section contains electrical characteristics of the device as well as temperature and

power considerations.

This product contains devices to protect the inputs against damage due to high static

voltages. However, it is advisable to take precautions to avoid application of any voltage

higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V

DD

or V ). This can be done by the internal pull-up or pull-down, which is provided by the

SS

product for most general purpose pins.

The parameters listed in the following tables represent the characteristics of the device and

its demands on the system.

In the tables where the device logic provides signals with their respective timing

characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol

column.

In the tables where the external system must provide signals with their respective timing

characteristics to the device, the symbol “SR” for System Requirement is included in the

Symbol column.

Caution:

All of the following parameter values can vary depending on the application and must be

confirmed during silicon validation, silicon characterization or silicon reliability trial.

3.2

Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To

give the customer a better understanding, the classifications listed in Table 8 are used and

the parameters are tagged accordingly in the tables where appropriate.

Table 8.

Parameter classifications

Classification tag

Tag description

P

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

C

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical

column are within this category.

T

D

Those parameters are derived mainly from simulations.

Note:

The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

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Electrical characteristics

3.3

Absolute maximum ratings

(1)

Table 9.

Absolute maximum ratings

Parameter

SR Digital ground

Symbol

V_{SS_HV}

Conditions

Min

Max⁽²⁾

Unit

—

0

V

3.3 V / 5.0 V input/output supply

SR voltage with respect to ground

(3)

V_{DD_HV_IOx}

—

–0.3

6.0

V

(V_{SS_HV}

)

Input/output ground voltage with

respect to ground (V_{SS_HV}

V_{SS_HV_IOx}

V_{DD_HV_FL}

V_{SS_HV_FL}

SR

—

–0.1

–0.3

0.1

6.0

)

3.3 V / 5.0 V code and data flash

SR memory supply voltage with respect

to ground (V_{SS_HV}

V

Relative to

V_{DD_HV_IOx}

0.3

+

)

Code and data flash memory ground

with respect to ground (V_{SS_HV}

SR

—

–0.1

–0.3

0.1

6.0

)

3.3 V / 5.0 V crystal oscillator

V_{DD_HV_OSC}SR amplifier supply voltage with respect

to ground (V_{SS_HV}

Relative to

V_{DD_HV_IOx}

0.3

)

3.3 V / 5.0 V crystal oscillator

V_{SS_HV_OSC}

SR amplifier reference voltage with

—

–0.1

0.1

V

respect to ground (V_{SS_HV}

)

—

– 0.3

6.0

3.3 V / 5.0 V voltage regulator supply

V_{DD_HV_REG}SR voltage with respect to ground

(V_{SS_HV}

Relative to

V_{DD_HV_IOx}

0.3

+

)

V_{DD_HV_REG}

< 2.7 V

V_{DD_HV_REG}

+ 0.3

– 0.3

3.3 V / 5.0 V ADC supply and high

SR reference voltage with respect to

V_{DD_HV_AD}

V

V_{DD_HV_REG}

> 2.7 V

ground (V_{SS_HV}

)

6.0

0.1

ADC ground and low reference

SR voltage with respect to ground

V_{SS_HV_AD}

—

–0.1

0.25

V

(V_{SS_HV}

)

Slope characteristics on all V_DD

(4)

TV_DD

SR during power up⁽⁵⁾with respect to

—

250

6.0

V/ms

ground (V_{SS_HV}

)

–0.3

Voltage on any pin with respect to

SR ground (V_{SS_HV_IOx}) with respect to

V_IN

V

Relative to

V_{DD_HV_IOx}

0.3

+

ground (V_{SS_HV}

)

V_{DD_HV_REG}V_{SS_HV_AD} V_{DD_HV_AD}

V

< 2.7 V

0.3

V_{DD_HV_AD}

10

V_INAN

SR Analog input voltage

V_{DD_HV_REG}

> 2.7 V

V_{SS_HV_AD}

Injected input current on any pin

SR

I_INJPAD

—

–10

mA

during overload condition

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Electrical characteristics

SPC56xP54x, SPC56xP60x

(1)

Table 9.

Absolute maximum ratings (continued)

Symbol

Parameter

Conditions

Min

Max⁽²⁾

Unit

Absolute sum of all injected input

currents during overload condition

I_INJSUM

SR

—

–50

50

mA

Low voltage static current sink

through V_{DD_LV}

I_{VDD_LV}

—

155

mA

T_STG

T_J

SR Storage temperature

—

–55

–40

150

°C

SR Junction temperature under bias

1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings

only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device

reliability or cause permanent damage to the device.

2. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress

have not yet been determined.

3. The difference between each couple of voltage supplies must be less than 300 mV, |V_{DD_HV_IOy}– V_{DD_HV_IOx}| < 300 mV.

4. Ensure a monotonic supply ramp starting at ground level

5. Guaranteed by device validation

Figure 5 shows the constraints of the different power supplies.

Figure 5.

Power supplies constraints

VDD_HV_xxx

6.0V

-0.3V

VDD_HV_IOx

-0.3V

6.0V

The SPC56xP54/60 supply architecture provides an ADC supply that is managed

independently of standard V

supply.

supply. Figure 6 shows the constraints of the ADC power

DD_HV

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SPC56xP54x, SPC56xP60x

Electrical characteristics

(d)

Figure 6.

Independent ADC supply

VDD_HV_AD

6.0V

-0.3V

VDD_HV_REG

6.0V

-0.3V

2.7V

3.4

Recommended operating conditions

Table 10. Recommended operating conditions (5.0 V)

Symbol

V_{SS_HV}

Parameter

SR Digital ground

Conditions

Min

Max⁽¹⁾

Unit

—

0

V

5.0 V input/output supply

voltage

(2)

V_{DD_HV_IOx}

V_{SS_HV_IOx}

SR

—

4.5

5.5

V

SR Input/output ground voltage

—

0

4.5

5.5

5.0 V code and data flash

SR

V_{DD_HV_FL}

V

Relative to

V_{DD_HV_IOx}

memory supply voltage

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

Code and data flash

SR

V_{SS_HV_FL}

V_{DD_HV_OSC}

V_{SS_HV_OSC}

—

0

memory ground

4.5

5.5

5.0 V crystal oscillator

SR

Relative to

V_{DD_HV_IOx}

amplifier supply voltage

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

5.0 V crystal oscillator

SR

—

0

amplifier reference voltage

d. Device design targets the removal of this conditions. To be confirmed by design during device validation.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Table 10. Recommended operating conditions (5.0 V) (continued)

Symbol

Parameter

Conditions

Min

Max⁽¹⁾

Unit

—

4.5

5.5

5.0 V voltage regulator

supply voltage

V_{DD_HV_REG}

SR

V

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

—

4.5

5.5

—

5.0 V ADC supply and high

reference voltage

V_{DD_HV_AD}

SR

V

Relative to

V_{DD_HV_REG}

V_{DD_HV_REG}– 0.1

ADC ground and low

reference voltage

V_{SS_HV_AD}

—

0

(3),(4)

V_{DD_LV_REGCOR}

SR Internal supply voltage

SR Internal reference voltage

SR Internal supply voltage

SR Internal reference voltage

—

0

—

0

V

(3)

V_{SS_LV_REGCOR}

(3),(4)

V_{DD_LV_CORx}

—

0

—

0

(3)

V_{SS_LV_CORx}

T_A

Ambient temperature under

SR

—

–40

125

°C

bias

1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.

In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.

2. The difference between each couple of voltage supplies must be less than 100 mV, |V_{DD_HV_IOy}– V_{DD_HV_IOx}| < 100 mV.

3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an

on-chip voltage regulator—but for the device to function properly the low voltage grounds (V_{SS_LV_xxx}) must be shorted to

high voltage grounds (V_{SS_HV_xxx}) and the low voltage supply pins (V_{DD_LV_xxx}) must be connected to the external ballast

emitter.

4. The low voltage supplies (V_{DD_LV_xxx}) are not all independent.

V_{DD_LV_COR1}and V_{DD_LV_COR2}are shorted internally via double bonding connections with lines that provide the low

voltage supply to the data flash memory module. Similarly, V_{SS_LV_COR1}and V_{SS_LV_COR2}are internally shorted.

V_{DD_LV_REGCOR}and V_{DD_LV_REGCORx}are physically shorted internally, as are V_{SS_LV_REGCOR}and V_{SS_LV_CORx}

.

Table 11.

Recommended operating conditions (3.3 V)

Parameter Conditions

SR Digital ground

Symbol

Min

Max⁽¹⁾

Unit

V_{SS_HV}

—

0

V

3.3 V input/output supply

voltage

(2)

V_{DD_HV_IOx}

SR

3.0

3.6

V

V_{SS_HV_IOx}

SR Input/output ground voltage

—

0

3.0

3.6

3.3 V code and data flash

SR

V_{DD_HV_FL}

V

Relative to

V_{DD_HV_IOx}

memory supply voltage

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

Code and data flash

SR

V_{SS_HV_FL}

V_{DD_HV_OSC}

V_{SS_HV_OSC}

—

0

memory ground

3.0

3.6

3.3 V crystal oscillator

SR

Relative to

V_{DD_HV_IOx}

amplifier supply voltage

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

3.3 V crystal oscillator

SR

—

0

amplifier reference voltage

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Electrical characteristics

Table 11.

Recommended operating conditions (3.3 V) (continued)

Symbol

Parameter

Conditions

Min

Max⁽¹⁾

Unit

—

3.0

3.6

3.3 V voltage regulator

supply voltage

V_{DD_HV_REG}

SR

V

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

—

3.0

5.5

3.3 V ADC supply and high

reference voltage

V_{DD_HV_AD}

SR

V

Relative to

V_{DD_HV_REG}

V_{DD_HV_REG}– 0.1

ADC ground and low

reference voltage

V_{SS_HV_AD}

—

0

(3),(4)

V_{DD_LV_REGCOR}

SR Internal supply voltage

SR Internal reference voltage

SR Internal supply voltage

SR Internal reference voltage

—

0

—

0

V

(3)

V_{SS_LV_REGCOR}

(3),(4)

V_{DD_LV_CORx}

—

0

—

0

(3)

V_{SS_LV_CORx}

T_A

Ambient temperature under

SR

—

–40

125

°C

bias

1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.

In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.

2. The difference between each couple of voltage supplies must be less than 100 mV, |V_{DD_HV_IOy}– V_{DD_HV_IOx}| < 100 mV.

3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an

on-chip voltage regulator—but for the device to function properly the low voltage grounds (V_{SS_LV_xxx}) must be shorted to

high voltage grounds (V_{SS_HV_xxx}) and the low voltage supply pins (V_{DD_LV_xxx}) must be connected to the external ballast

emitter.

4. The low voltage supplies (V_{DD_LV_xxx}) are not all independent.

V_{DD_LV_COR1}and V_{DD_LV_COR2}are shorted internally via double bonding connections with lines that provide the low

voltage supply to the data flash memory module. Similarly, V_{SS_LV_COR1}and V_{SS_LV_COR2}are internally shorted.

V_{DD_LV_REGCOR}and V_{DD_LV_REGCORx}are physically shorted internally, as are V_{SS_LV_REGCOR}and V_{SS_LV_CORx}

.

Figure 7 shows the constraints of the different power supplies.

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Electrical characteristics

Figure 7.

SPC56xP54x, SPC56xP60x

(e)

Power supplies constraints

VDD_HV_xxx

5.5V

3.3V

3.2V

VDD_HV_IOx

5.5V

3.2V

3.3V

The SPC56xP54/60 supply architecture provides an ADC supply that is managed

independently of standard V

supply.

supply. Figure 8 shows the constraints of the ADC power

DD_HV

e. IO AC and DC characteristics are guaranteed only in the range 3.0V–3.6V when PAD3V5V is low, and in the

range 4.5V–5.5V when PAD3V5V is high.

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Electrical characteristics

Figure 8.

Independent ADC supply

VDD_HV_AD

5.5V

3.0V

VDD_HV_REG

5.5V

3.0V

3.5

Thermal characteristics

Table 12. Thermal characteristics for 144-pin LQFP

Symbol

Parameter

Conditions

Typical value Unit

D

Single layer board—1s

Four layer board—2s2p

Single layer board—1s

Operating conditions

53.4

43.9

29.6

9.3

°C/W

Thermal resistance junction-to-ambient,

natural convection⁽¹⁾

R_JA

R_JB

R_JCtop

_JB

Thermal resistance junction-to-board⁽²⁾

Thermal resistance junction-to-case (top)⁽³⁾

Junction-to-board, natural convection⁽⁴⁾

Junction-to-case, natural convection⁽⁵⁾

29.8

1.3

_JC

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification

for this package.

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package.

3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.

5. Thermal characterization parameter indicating the temperature difference between the case and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JC.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Table 13. Thermal characteristics for 100-pin LQFP

Symbol

Parameter

Conditions

Typical value Unit

D

Single layer board—1s

Four layer board—2s2p

47.3

35.6

19.1

9.1

°C/W

Thermal resistance junction-to-ambient,

natural convection⁽¹⁾

R_JA

R_JB

R_JCtop

_JB

Thermal resistance junction-to-board⁽²⁾

Thermal resistance junction-to-case (top)⁽³⁾Single layer board—1s

Junction-to-board, natural convection⁽⁴⁾

Junction-to-case, natural convection⁽⁵⁾

Operating conditions

19.1

1.1

_JC

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification

for this package.

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package.

3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.

5. Thermal characterization parameter indicating the temperature difference between the case and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JC.

3.5.1

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T , can be obtained from Equation 1:

J

Equation 1

T = T + (R

× P )

J

A

JA D

where:

o

T

= ambient temperature for the package ( C)

A

o

R

= junction to ambient thermal resistance ( C/W)

JA

P

= power dissipation in the package (W)

D

The junction to ambient thermal resistance is an industry standard value that provides a

quick and easy estimation of thermal performance. Unfortunately, there are two values in

common usage: the value determined on a single layer board and the value obtained on a

board with two planes. For packages such as the PBGA, these values can be different by a

factor of two. Which value is closer to the application depends on the power dissipated by

other components on the board. The value obtained on a single layer board is appropriate

for the tightly packed printed circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low power dissipation and the components are

well separated.

When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a

junction to case thermal resistance and a case to ambient thermal resistance:

Equation 2

R

= R

+ R

JA

JC CA

where:

R

= junction to ambient thermal resistance (°C/W)

= junction to case thermal resistance (°C/W)

= case to ambient thermal resistance (°C/W)

JA

JC

CA

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SPC56xP54x, SPC56xP60x

Electrical characteristics

R

is device related and cannot be influenced by the user. The user controls the thermal

JC

environment to change the case to ambient thermal resistance, R

. For instance, the user

CA

can change the size of the heat sink, the air flow around the device, the interface material,

the mounting arrangement on printed circuit board, or change the thermal dissipation on the

printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are

not used, the Thermal Characterization Parameter ( ) can be used to determine the

JT

junction temperature with a measurement of the temperature at the top center of the

package case using Equation 3:

Equation 3

T = T + ( × P )

J T JT D

where:

T

= thermocouple temperature on top of the package (°C)

= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

T



JT

P

D

The thermal characterization parameter is measured per JESD51-2 specification using a 40

gauge type T thermocouple epoxied to the top center of the package case. The

thermocouple should be positioned so that the thermocouple junction rests on the package.

A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of

wire extending from the junction. The thermocouple wire is placed flat against the package

case to avoid measurement errors caused by cooling effects of the thermocouple wire.

References

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134

(408) 943-6900

U.S.A.

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering

Documents at 800-854-7179 or 303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998, pp.

47-54.

2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled

Applications, Electronic Packaging and Production, pp. 53-58, March 1998.

3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal

Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San

Diego, 1999, pp. 212-220.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

3.6

Electromagnetic interference (EMI) characteristics

Table 14. EMI testing specifications

Level

(Max)

Parameter

Symbol

Conditions

f_OSC/f_BUS

Frequency

Unit

V_DD= 5 V;

8 MHz crystal

64 MHz bus

150 kHz–150 MHz

150–1000 MHz

18

12

dBV

—

T_A= 25 °C

NoPLLfrequency

modulation

IEC Level

M

150 kHz–30 MHz

RBW 9 kHz, Step

Size 5 kHz

Radiated

150 kHz–150 MHz

150–1000 MHz

18

12

V_{RE_TEM}

emissions,

8 MHz crystal

64 MHz bus

dBV

electric field

2% PLL

frequency

modulation

30 MHz–1 GHz

RBW 120 kHz,

Step Size 80 kHz

IEC Level

M

—

3.7

Electrostatic discharge (ESD) characteristics

(1),(2)

Table 15. ESD ratings

Symbol

Parameter

Conditions

Value

Unit

V_ESD(HBM)

V_ESD(CDM)

SR Electrostatic discharge (Human Body Model)

SR Electrostatic discharge (Charged Device Model)

—

2000

V

750 (corners)

500 (other)

—

V

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification

requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at

room temperature followed by hot temperature, unless specified otherwise in the device specification

3.8

Power management electrical characteristics

3.8.1

Voltage regulator electrical characteristics

The internal voltage regulator requires an external NPN ballast to be connected as shown in

Figure 9. Table 16 contains all approved NPN ballast components. Capacitances should be

placed on the board as near as possible to the associated pins. Care should also be taken

to limit the serial inductance of the V

, BCTRL and V

pins to less than

DD_HV_REG

DD_LV_CORx

L

, see Table 17.

Reg

Note:

The voltage regulator output cannot be used to drive external circuits. Output pins are used

only for decoupling capacitances.

V

must be generated using internal regulator and external NPN transistor. It is not

DD_LV_COR

possible to provide V

through external regulator.

DD_LV_COR

For the SPC56xP54/60 microcontroller, capacitors, with total values not below C

,

DEC1

should be placed between V

/V

close to external ballast transistor

DD_LV_CORx SS_LV_CORx

emitter. 4 capacitors, with total values not below C

, should be placed close to

DEC2

microcontroller pins between each V

/V

supply pairs and the

DD_LV_CORx SS_LV_CORx

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Electrical characteristics

V

/V

pair . Additionally, capacitors with total values not below

DD_LV_REGCOR SS_LV_REGCOR

C

, should be placed between the V

/V

pins close to ballast

DEC3

DD_HV_REG SS_HV_REG

collector. Capacitors values have to take into account capacitor accuracy, aging and

variation versus temperature.

All reported information are valid for voltage and temperature ranges described in

recommended operating condition, Table 10 and Table 11.

Figure 9.

Voltage regulator configuration

VDD_HV_REG

C_DEC3

SPC56xP54/60

BJT⁽¹⁾

BCTRL

VDD_LV_COR

C_DEC2

C_DEC1

1. Refer to Table 16.

Table 16. Approved NPN ballast components

Part

Manufacturer

Approved derivatives⁽¹⁾

ON Semi

NXP

BCP68

BCP68-25

BCP68

Infineon

NXP

BCP68-25

BCX68

BC868

BCX68-10;BCX68-16;BCX68-25

BC868

Infineon

NXP

BC817-16;BC817-25;BC817SU;

BC817-16;BC817-25

BCP56-16

BC817

ST

Infineon

ON Semi

NXP

BCP56-10;BCP56-16

BCP56-10

BCP56

BCP56-10;BCP56-16

1. For automotive applications please check with the appropriate transistor vendor for automotive grade

certification

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Table 17. Voltage regulator electrical characteristics

Value

Unit

Symbol

C

Parameter

Conditions

Min Typ Max

Output voltage under

maximum load run supply

current configuration

V_{DD_LV_REGCOR}CC

P

Post-trimming

1.15

—

1.32

—

V

BJT from Table 16. 3

capacitances (i.e. X7R or

X8R capacitors) with nominal

value of 10 µF

19.5 30

14.3 22

µF

External decoupling/stability

ceramic capacitor

C_DEC1

SR —

BJT BC817, one capacitance

of 22 µF

BJT from Table 16. 3x10 µF.

Absolute maximum value

between 100 kHz and

10 MHz

Resulting ESR of all three

capacitors of C_DEC1

—

50 m

40 m

R_REG

SR —

BJT BC817, 1x 22 µF.

Absolute maximum value

between 100 kHz and

10 MHz

Resulting ESR of the unique

capacitor C_DEC1

10

4 capacitances (i.e. X7R or

X8R capacitors) with nominal 1200 1760

value of 440 nF

External decoupling/stability

ceramic capacitor

C_DEC2

SR —

—

nF

µF

3 capacitances (i.e. X7R or

X8R capacitors) with nominal

value of 10 µF; C_DEC3has to 19.5 30

be equal or greater than

C_DEC1

External decoupling/stability

C_DEC3

SR — ceramic capacitor on

V_{DD_HV_REG}

Resulting ESL of V_{DD_HV_REG}

BCTRL and V_{DD_LV_CORx}pins

,

L_Reg

SR —

—

15 nH

3.8.2

Voltage monitor electrical characteristics

The device implements a Power On Reset module to ensure correct power-up initialization,

as well as three low voltage detectors to monitor the V and the V

voltage while

DD

DD_LV

device is supplied:

●

POR monitors V during the power-up phase to ensure device is maintained in a safe

DD

reset state

●

LVDHV3 monitors V to ensure device reset below minimum functional supply

DD

LVDHV5 monitors V when application uses device in the 5.0V 10% range

DD

LVDLVCOR monitors low voltage digital power domain

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Electrical characteristics

Value

Table 18. Low voltage monitor electrical characteristics

Symbol

Parameter

Conditions⁽¹⁾

Unit

Min

Max

V_PORH

T

P

Power-on reset threshold

—

1.5

1.0

—

2.7

—

V

V_PORUP

Supply for functional POR module

T_A= 25°C

V_{REGLVDMOK_H}

V_{REGLVDMOK_L}

V_{FLLVDMOK_H}

V_{FLLVDMOK_L}

V_{IOLVDMOK_H}

V_{IOLVDMOK_L}

V_{IOLVDM5OK_H}

V_{IOLVDM5OK_L}

V_{MLVDDOK_H}

V_{MLVDDOK_L}

Regulator low voltage detector high threshold

Regulator low voltage detector low threshold

Flash memory low voltage detector high threshold

Flash memory low voltage detector low threshold

I/O low voltage detector high threshold

I/O low voltage detector low threshold

—

2.95

—

2.6

—

2.95

—

2.6

—

2.95

—

2.6

—

I/O 5V low voltage detector high threshold

I/O 5V low voltage detector low threshold

Digital supply low voltage detector high

Digital supply low voltage detector low

4.4

—

3.8

—

1.15

—

1.08

1. V_DD= 3.3V 10% / 5.0V 10%, T_A= –40 °C to T_{A MAX}, unless otherwise specified

3.9

Power Up/Down sequencing

To prevent an overstress event or a malfunction within and outside the device, the

SPC56xP54/60 implements the following sequence to ensure each module is started only

when all conditions for switching it ON are available:

1. A POWER_ON module working on voltage regulator supply controls the correct start-

up of the regulator. This is a key module ensuring safe configuration for all voltage

regulator functionality when supply is below 1.5V. Associated POWER_ON (or POR)

signal is active low.

–

Several low voltage detectors, working on voltage regulator supply monitor the

voltage of the critical modules (voltage regulator, I/Os, flash memory and low

voltage domain). LVDs are gated low when POWER_ON is active.

–

A POWER_OK signal is generated when all critical supplies monitored by the LVD

are available. This signal is active high and released to all modules including I/Os,

flash memory and RC16 oscillator needed during power-up phase and reset

phase. When POWER_OK is low the associated modules are set into a safe state.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Figure 10. Power-up typical sequence

V_LVDHV3H

V_PORH

3.3V

VDD_HV_REG

V_{POR_UP}

0V

3.3V

POWER_ON

LVDM (HV)

0V

3.3V

0V

V_{MLVDOK_H}

VDD_LV_REGCOR

1.2V

0V

3.3V

LVDD (LV)

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

~1us

1.2V

0V

Internal Reset Generation Module

FSM

P0

P1

Figure 11. Power-down typical sequence

V_LVDHV3L

3.3V

V_PORH

VDD_HV_REG

0V

3.3V

LVDM (HV)

POWER_ON

0V

3.3V

0V

1.2V

0V

VDD_LV_REGCOR

LVDD (LV)

3.3V

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

Internal Reset Generation Module

FSM

1.2V

0V

IDLE

P0

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Electrical characteristics

Figure 12. Brown-out typical sequence

V_LVDHV3H

V_LVDHV3L

3.3V

VDD_HV_REG

0V

3.3V

LVDM (HV)

POWER_ON

0V

3.3V

0V

1.2V

0V

VDD_LV_REGCOR

LVDD (LV)

3.3V

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

~1us

Internal Reset Generation Module

1.2V

0V

FSM

IDLE

P0

P1

3.10

NVUSRO register

Portions of the device configuration, such as high voltage supply, and watchdog

enable/disable after reset are controlled via bit values in the non-volatile user options

register (NVUSRO) register.

For a detailed description of the NVUSRO register, please refer to the device reference

manual.

3.10.1

NVUSRO[PAD3V5V] field description

Table 19 shows how NVUSRO[PAD3V5V] controls the device configuration.

(1)

Table 19. PAD3V5V field description

Value⁽²⁾

Description

0

1

High voltage supply is 5.0 V

High voltage supply is 3.3 V

1. See the device reference manual for more information on the NVUSRO register.

2. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.

The DC electrical characteristics are dependent on the PAD3V5V bit value.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

3.11

DC electrical characteristics

3.11.1

DC electrical characteristics (5 V)

Table 20 gives the DC electrical characteristics at 5 V (4.5 V < V

NVUSRO[PAD3V5V]=0) as described in Figure 13.

< 5.5 V,

DD_HV_IOx

Figure 13. I/O input DC electrical characteristics definition

V

IN

V

DD

V

IH

V

HYS

V

IL

PDIx = ‘1’

(GPDI register of SIUL)

PDIx = ‘0’

Table 20. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)

Symbol

Parameter

Conditions

Min

Max

Unit

V_IL

D Minimum low level input voltage

P Maximum level input voltage

P Minimum high level input voltage

D Maximum high level input voltage

T Schmitt trigger hysteresis

—

–0.1⁽¹⁾

—

V

—

0.65 V_{DD_HV_IOx}

—

0.35 V_{DD_HV_IOx}

V_IH

—

V_IH

V_{DD_HV_IOx}+ 0.1⁽¹⁾

V_HYS

0.1 V_{DD_HV_IOx}

—

0.8V_{DD_HV_IOx}

—

0.8 V_{DD_HV_IOx}

—

V_{OL_S}P Slow, low level output voltage

V_{OH_S}P Slow, high level output voltage

V_{OL_M}P Medium, low level output voltage

I_OL= 3 mA

0.1 V_{DD_HV_IOx}

I_OH= –3 mA

I_OL= 3 mA

—

0.1 V_{DD_HV_IOx}

V_{OH_M}P Medium, high level output voltage I_OH= –3 mA

—

0.1 V_{DD_HV_IOx}

—

V_{OL_F}P Fast, low level output voltage

V_{OH_F}P Fast, high level output voltage

Symmetric, low level output

I_OL= 3 mA

I_OH= –3 mA

0.8 V_{DD_HV_IOx}

V_{OL_SYM}

P

I_OL= 3 mA

—

0.1 V_{DD_HV_IOx}

—

V

voltage

Symmetric, high level output

voltage

V_{OH_SYM}

P

I_OH= –3 mA

0.8 V_{DD_HV_IOx}

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Electrical characteristics

Table 20. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) (continued)

Symbol

Parameter

Conditions

_IN= V_IL

V_IN= V_IH

_IN= V_IL

Min

Max

Unit

V

–130

—

–10

—

I_PU

P Equivalent pull-up current

µA

V

10

I_PD

P Equivalent pull-down current

µA

V_IN= V_IH

—

130

Input leakage current

P

I_IL

T_A= –40 to 125 °C

–1

1

(all bidirectional ports)

Input leakage current

P

I_IL

T_A= –40 to 125 °C

—

–0.5

0.5

µA

pF

(all ADC input-only ports)

C_IN

D Input capacitance

—

–130

—

10

—

V_IN= V_IL

I_PU

D RESET, equivalent pull-up current

µA

V_IN= V_IH

V_IN= V_IL

V_IN= V_IH

–10

—

10

RESET, equivalent pull-down

current

I_PD

D

—

130

1. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Table 21. Supply current (5.0 V, NVUSRO[PAD3V5V]=0)

Value

Unit

Symbol

Parameter

Conditions

Typ Max

V_{DD_LV_CORE}

externally forced at 1.3 V

ADC Freq = 32 MHz

RUN — Maximum Mode⁽¹⁾

64 MHz 90

120

PLL Freq = 64 MHz

16 MHz 21

40 MHz 35

64 MHz 48

16 MHz 24

40 MHz 42

64 MHz 58

37

55

72

41

64

85

RUN - Platform consumption,

single core⁽²⁾

T

VDD_LV_CORE

externally forced to 1.3V

I_{DD_LV_CORE}

RUN - Platform consumption,

dual core⁽³⁾

V_{DD_LV_CORE}

RUN — Maximum Mode⁽⁴⁾

HALT Mode⁽⁵⁾

64 MHz 85

113

15

Supply

current

externally forced at 1.3 V

mA

V_{DD_LV_CORE}

P

T

—

5.5

4.5

—

externally forced at 1.3 V

V_{DD_LV_CORE}

STOP Mode⁽⁶⁾

13

externally forced at 1.3 V

Flash memory supply current

during read

V_{DD_HV_FL}at 5.0 V

14

I_{DD_FLASH}

Flash memory supply current

during erase operation on 1

flash memory module

V_{DD_HV_FL}at 5.0 V

—

42

V_{DD_HV_AD}at 5.0 V

ADC Freq = 16 MHz

ADC supply current —

Maximum Mode

I_{DD_ADC}

I_{DD_OSC}

T

—

3

4

OSC supply current

V_{DD_OSC}at 5.0 V

8 MHz

2.6

3.2

1. Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM

enabled. I/O supply current excluded.

2. RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz

on, PLL64MHz OFF(except for code running at 64MHz).

Code is performing continous data transfet from Flash to RAM.

3. RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,

PLL64MHz OFF(except for code running at 64MHz).

Code is performing continous data transfet from Flash to RAM.

4. Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM

enabled. I/O supply current excluded.

5. HALT mode configuration, only for the “P” classification: Code Flash memory in low power mode, data Flash memory in

power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

6. STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL

are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

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SPC56xP54x, SPC56xP60x

Electrical characteristics

3.11.2

DC electrical characteristics (3.3 V)

Table 22 gives the DC electrical characteristics at 3.3 V (3.0 V < V

NVUSRO[PAD3V5V]=1) as described in Figure 14.

< 3.6 V,

DD_HV_IOx

Figure 14. I/O input DC electrical characteristics definition

V

IN

V

DD

V

IH

V

HYS

V

IL

PDIx = ‘1’

(GPDI register of SIUL)

PDIx = ‘0’

(1)

Table 22. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)

Symbol

Parameter

Conditions

Min

Max

Unit

V_IL

D Minimum low level input voltage

P Maximum low level input voltage

P Minimum high level input voltage

D Maximum high level input voltage

T Schmitt trigger hysteresis

—

–0.1⁽²⁾

—

V

—

0.35 V_{DD_HV_IOx}

V_IH

—

0.65 V_{DD_HV_IOx}

—

V_IH

—

0.1 V_{DD_HV_IOx}

—

V_{DD_HV_IOx}+ 0.1⁽²⁾

V_HYS

—

0.5

—

V_{OL_S}P Slow, low level output voltage

V_{OH_S}P Slow, high level output voltage

I_OL= 1.5 mA

I_OH= –1.5 mA

V_{DD_HV_IOx}– 0.8

—

V_{DD_HV_IOx}– 0.8

—

V_{OL_M}P Medium, low level output voltage I_OL= 2 mA

V_{OH_M}P Medium, high level output voltage I_OH= –2 mA

0.5

—

V_{OL_F}P Fast, high level output voltage

V_{OH_F}P Fast, high level output voltage

Symmetric, high level output

I_OL= 1.5 mA

0.5

—

I_OH= –1.5 mA

V_{DD_HV_IOx}– 0.8

V_{OL_SYM}

P

I_OL= 1.5 mA

—

0.5

—

V

voltage

Symmetric, high level output

voltage

V_{OH_SYM}

P

I_OH= –1.5 mA

V_{DD_HV_IOx}– 0.8

V

_IN= V_IL

–130

—

I_PU

P Equivalent pull-up current

µA

V_IN= V_IH

–10

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Electrical characteristics

SPC56xP54x, SPC56xP60x

(1)

Table 22. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) (continued)

Symbol

Parameter

Conditions

_IN= V_IL

Min

Max

Unit

V

10

—

I_PD

P Equivalent pull-down current

µA

V_IN= V_IH

130

Input leakage current

P

I_IL

T_A= –40 to 125 °C

—

1

µA

(all bidirectional ports)

Input leakage current

P

I_IL

T_A= –40 to 125 °C

—

0.5

µA

pF

(all ADC input-only ports)

C_IN

D Input capacitance

—

–130

—

10

—

V_IN= V_IL

I_PU

D RESET, equivalent pull-up current

µA

V_IN= V_IH

V_IN= V_IL

V_IN= V_IH

–10

—

10

RESET, equivalent pull-down

current

I_PD

D

—

130

1. These specifications are design targets and subject to change per device characterization.

2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.

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SPC56xP54x, SPC56xP60x

Electrical characteristics

Table 23. Supply current (3.3 V, NVUSRO[PAD3V5V]=1)

Value

Unit

Symbol

Parameter

Conditions

Typ Max

V_{DD_LV_CORE}

externally forced at

1.3 V

RUN — Maximum Mode⁽¹⁾

64 MHz 90

120

ADC Freq = 32 MHz

PLL Freq = 64 MHz

16 MHz 21

40 MHz 35

64 MHz 48

16 MHz 24

40 MHz 42

64 MHz 58

37

55

72

41

64

85

T

RUN - Platform consumption,

single core⁽²⁾

VDD_LV_CORE

externally forced to 1.3V

RUN - Platform consumption,

dual core⁽³⁾

I_{DD_LV_CORE}

V_{DD_LV_CORE}

RUN — Maximum Mode⁽⁴⁾

HALT Mode⁽⁵⁾

64 MHz 85

113

15

externally forced at

1.3 V

Supply

current

mA

V_{DD_LV_CORE}

P

—

5.5

externally forced at

1.3 V

V_{DD_LV_CORE}

STOP Mode⁽⁶⁾

—

4.5

—

3

13

14

42

externally forced at

1.3 V

Flash memory supply current

during read

V

_{DD_HV_FL}at 3.3 V

I_{DD_FLASH}

D

Flash memory supply current

during erase operation on 1

flash memory module

V_{DD_HV_FL}at 3.3 V

V_{DD_HV_AD}at 3.3 V

ADC Freq = 16 MHz

ADC supply current —

Maximum Mode

I_{DD_ADC}

I_{DD_OSC}

T

4

3

OSC supply current

V_{DD_OSC}at 3.3 V

8 MHz 2.4

1. Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM

enabled. I/O supply current excluded.

2. RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz

on, PLL64MHz OFF(except for code running at 64MHz).

Code is performing continous data transfet from Flash to RAM.

3. RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,

PLL64MHz OFF(except for code running at 64MHz).

Code is performing continous data transfet from Flash to RAM.

4. Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM

enabled. I/O supply current excluded.

5. HALT mode configuration, only for the “P” classification: Code Flash memory in low power mode, data Flash memory in

power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

6. STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL

are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

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SPC56xP54x, SPC56xP60x

Electrical characteristics

3.11.3

I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is

associated to a V /V supply pair as described in Table 25.

DD SS

Table 25. I/O supply segment

Supply segment

4

Package

1

2

3

5

6

7

pin23 –

pin38

pin39 –

pin55

pin58 –

pin68

pin73 –

pin89

pin92 –

pin125

pin128 –

pin5

LQFP144 pin8 – pin20

pin15 –

LQFP100

pin27 –

pin38

pin41 –

pin46

pin51 –

pin61

pin64 –

pin86

pin89 – pin10

—

pin26

Table 26. I/O consumption

Value

Min Typ Max

Symbol

C

Parameter

Conditions⁽¹⁾

Unit

V

_DD= 5.0 V 10%,

—

20

16

Dynamic I/O current

CC D for SLOW

configuration

PAD3V5V = 0

(2)

I_SWTSLW

C_L= 25 pF

mA

V_DD= 3.3 V 10%,

PAD3V5V = 1

V_DD= 5.0 V 10%,

29

Dynamic I/O current

CC D for MEDIUM

configuration

PAD3V5V = 0

(2)

I_SWTMED

mA

V_DD= 3.3 V 10%,

PAD3V5V = 1

17

V_DD= 5.0 V 10%,

110

50

Dynamic I/O current

CC D for FAST

configuration

PAD3V5V = 0

(2)

I_SWTFST

V_DD= 3.3 V 10%,

PAD3V5V = 1

C_L= 25 pF, 2 MHz

C_L= 25 pF, 4 MHz

C_L= 100 pF, 2 MHz

C_L= 25 pF, 2 MHz

C_L= 25 pF, 4 MHz

C_L= 100 pF, 2 MHz

C_L= 25 pF, 13 MHz

C_L= 25 pF, 40 MHz

C_L= 100 pF, 13 MHz

C_L= 25 pF, 13 MHz

C_L= 25 pF, 40 MHz

C_L= 100 pF, 13 MHz

—

2.3

3.2

6.6

1.6

2.3

4.7

6.6

13.4

18.3

5

V_DD= 5.0 V 10%,

PAD3V5V = 0

Root medium square

CC D I/O current for SLOW

configuration

I_RMSSLW

mA

V_DD= 3.3 V 10%,

PAD3V5V = 1

V_DD= 5.0 V 10%,

PAD3V5V = 0

Root medium square

I/O current for

MEDIUM

I_RMSMEDCC D

mA

configuration

V_DD= 3.3 V 10%,

PAD3V5V = 1

8.5

11

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Table 26. I/O consumption (continued)

Value

Unit

Symbol

C

Parameter

Conditions⁽¹⁾

Min Typ Max

C_L= 25 pF, 40 MHz

—

22

33

56

14

20

35

70

V

_DD= 5.0 V 10%,

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

C_L= 25 pF, 40 MHz

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

PAD3V5V = 0

Root medium square

I_RMSFST

CC D I/O current for FAST

configuration

mA

V_DD= 3.3 V 10%,

PAD3V5V = 1

Sum of all the static

SR D I/O current within a

supply segment

V_DD= 5.0 V 10%, PAD3V5V = 0

I_AVGSEG

V_DD= 3.3 V 10%, PAD3V5V = 1

—

65

1. V_DD= 3.3 V 10% / 5.0 V 10%, T_A= –40 to 125 °C, unless otherwise specified

2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

3.12

Main oscillator electrical characteristics

The SPC56xP54/60 provides an oscillator/resonator driver.

Table 27. Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)

Symbol

f_OSC

Parameter

Min

Max

Unit

SR Oscillator frequency

4

6.5

1

40

25

—

MHz

mA/V

V

g_m

P

T

Transconductance

V_OSC

t_OSCSU

Oscillation amplitude on EXTAL pin

Start-up time^(1),(2)

8

ms

1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive

capacitive loads can cause long start-up time.

2. Value captured when amplitude reaches 90% of EXTAL

Table 28. Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)

Symbol

f_OSC

Parameter

Min

Max

Unit

SR Oscillator frequency

4

1

8

40

20

—

MHz

mA/V

V

g_m

P

T

Transconductance

V_OSC

t_OSCSU

Oscillation amplitude on EXTAL pin

Start-up time^(1),(2)

ms

1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive

capacitive loads can cause long start-up time.

2. Value captured when amplitude reaches 90% of EXTAL

72/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Electrical characteristics

Table 29. Input clock characteristics

Symbol Parameter

Oscillator frequency

Min

Typ

Max

Unit

f_OSC

SR

4

—

50

40

64

MHz

ns

f_CLK

t_rCLK

t_DC

Frequency in bypass

Rise/fall time in bypass

Duty cycle

—

1

47.5

52.5

%

3.13

FMPLL electrical characteristics

Table 30. PLLMRFM electrical specifications

(V

= 1.08 V to 1.32 V, V = V

= 0 V, T = T to T )

DDPLL

SS

SSPLL

A

L

H

Value

Symbol

Parameter

Conditions

Unit

min

max

f_{ref_crystal}

f_{ref_ext}

D

PLL reference frequency range⁽¹⁾

Crystal reference

4

40

MHz

Phase detector input frequency range

(after pre-divider)

f_{pll_in}

D

—

4

16

MHz

f_FMPLLOUT

Clock frequency range in normal mode

120

Measured using

clock division —

typically /16

f_FREE

P

Free running frequency

20

150

64

MHz

f_sys

D

On-chip PLL frequency

System clock period

—

16

—

MHz

ns

t_CYC

1 / f_sys

3.7

56

Lower limit

Upper limit

—

1.6

24

20

–4

f_LORL

f_LORH

D

Loss of reference frequency window⁽²⁾

MHz

f_SCM

Self-clocked mode frequency^(3),(4)

Short-term jitter⁽⁹⁾

150

4

f_SYSmaximum

% f_CLKOUT

CLKOUT

period

f

_PLLIN= 16 MHz

C_JITTER

T

Long-term jitter (avg. (resonator),

jitter^{(5),(6),(7),(8)}

—

10

ns

over 2 ms interval)

f_PLLCLKat 64 MHz,

4000 cycles

t_lpll

t_dc

f_LCK

f_UL

f_CS

f_DS

D

PLL lock time ^{(10), (11)}

—

40

200

60

µs

%

Duty cycle of reference

Frequency LOCK range

Frequency un-LOCK range

—

–6

6

% f_sys

–18

0.25

–0.5

—

18

Center spread

Down Spread

—

4.0⁽¹²⁾

–8.0

70

D

Modulation Depth

%f_sys

kHz

f_MOD

Modulation frequency⁽¹³⁾

1. Considering operation with PLL not bypassed.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

2. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.

3. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f_LOR

window.

4. f_VCOself clock range is 20–150 MHz. f_SCMrepresents f_SYSafter PLL output divider (ERFD) of 2 through 16 in enhanced

mode.

5. This value is determined by the crystal manufacturer and board design.

6. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_SYS

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via V_DDPLLand V_SSPLLand variation in crystal oscillator frequency increase the C_JITTER

percentage for a given interval.

7. Proper PC board layout procedures must be followed to achieve specifications.

8. Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C_JITTER

and either f_CSor f_DS(depending on whether center spread or down spread modulation is enabled).

9. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.

10. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

PLL, load capacitors should not exceed these limits.

11. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR).

12. This value is true when operating at frequencies above 60 MHz, otherwise f_CSis 2% (above 64 MHz).

13. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

3.14

16 MHz RC oscillator electrical characteristics

Table 31. 16 MHz RC oscillator electrical characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

f_RC

P

RC oscillator frequency

T_A= 25 °C

—

16

—

MHz

Fast internal RC oscillator variation

over temperature and

_RCMVAR

—

–6

—

6

%

supply with respect to f_RCat TA = 25 °C

in high-frequency configuration

Post Trim Accuracy: The variation of

the PTF⁽¹⁾from the 16 MHz

_RCMTRIM

_RCMSTEP

T

T_A= 25 °C

–1

—

1

%

Fast internal RC oscillator trimming

step

1.6

—

1. PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and

temperature

3.15

Analog-to-Digital converter (ADC) electrical characteristics

The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital

Converter.

74/104

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SPC56xP54x, SPC56xP60x

Electrical characteristics

Figure 15. ADC characteristics and error definitions

Offset Error OSE

Gain Error GE

1023

1022

1021

1020

1019

1 LSB ideal = V

/ 1024

DD_ADC

1018

(2)

code out

7

(1)

6

(1) Example of an actual transfer curve

(2) The ideal transfer curve

5

(5)

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

4

(4)

3

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

1017 1018 1019 1020 1021 1022 1023

(LSB

V

)

ideal

in(A)

Offset Error OSE

3.15.1

Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have

low AC impedance. Placing a capacitor with good high-frequency characteristics at the input

pin of the device can be effective: the capacitor should be as large as possible, ideally

infinite. This capacitor contributes to attenuate the noise present on the input pin; further, it

sources charge during the sampling phase, when the analog signal source is a high-

impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the

input pin (simple RC filter). The RC filtering may be limited according to the source

impedance value of the transducer or circuit supplying the analog signal to be measured.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

The filter at the input pins must be designed taking into account the dynamic characteristics

of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the

sampling capacitance: being C and C substantially two switched capacitances, with a

S

P2

frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground.

For instance, assuming a conversion rate of 1 MHz, with C + C equal to 3 pF, a

S

P2

resistance of 330 k is obtained (R = 1 / (fc × (C + C )), where fc represents the

EQ

S

P2

conversion rate at the considered channel). To minimize the error induced by the voltage

partitioning between this resistance (sampled voltage on C + C ) and the sum of R + R

F

S

P2

S

, the external circuit must be designed to respect the Equation 4:

Equation 4

R

+ R

F

1

2

S

R

--------------------- --

LSB

V





A

EQ

Equation 4 generates a constraint for external network design, in particular on resistive

path. Internal switch resistances (R

resistances.

and R ) can be neglected with respect to external

SW

AD

Figure 16. Input equivalent circuit (precise channels)

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Sampling

Selection

Source

Filter

Current Limiter

R

AD

S

F

L

SW1

V

C

S

A

F

P1

P2

R

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance

Sampling Switch Impedance

Pin Capacitance (two contributions, C and C

P1

Sampling Capacitance

S

F

L

R

C

R

C

SW1

AD

P

)

P2

S

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Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Electrical characteristics

Figure 17. Input equivalent circuit (extended channels)

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Selection

Extended

Switch

Sampling

Source

R

Filter

Current Limiter

R

L

R

AD

SW2

S

F

SW1

C

S

C

V

C

P2

A

F

P1

P3

R : Source impedance

S

R : Filter resistance

F

C : Filter capacitance

F

R : Current limiter resistance

L

R

: Channel selection switch impedance (two contributions, R

: Sampling switch impedance

and R

)

SW1

SW2

AD

C : Pin capacitance (two contributions, C , C and C )

P3

P

P1

P2

C : Sampling capacitance

S

A second aspect involving the capacitance network shall be considered. Assuming the three

capacitances C , C and C are initially charged at the source voltage V (refer to the

F

P1

P2

A

equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when

the sampling phase is started (A/D switch close).

Figure 18. Transient behavior during sampling phase

Voltage Transient on C_S

V

CS

V

A

V <0.5 LSB

V

A2

1

2

₁< (R_SW+ R_AD) C_S<< T_S

V

A1

₂= R_L(C_S+ C_P1+ C_P2)

T

t

S

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Electrical characteristics

SPC56xP54x, SPC56xP60x

In particular two different transient periods can be distinguished:

A first and quick charge transfer from the internal capacitance C and C to the

●

P1

P2

sampling capacitance C occurs (C is supposed initially completely discharged):

S

considering a worst case (since the time constant in reality would be faster) in which

is reported in parallel to C (call C = C + C ), the two capacitances C and

C

P2

P1

P

P1

P2

P

C are in series, and the time constant is

S

Equation 5

C

 C

S

+ C

S

P

---------------------

+ R  

SW AD



= R

1

C

P

Equation 5 can again be simplified considering only C as an additional worst

S

condition. In reality, the transient is faster, but the A/D converter circuitry has been

designed to be robust also in the very worst case: the sampling time T is always much

S

longer than the internal time constant:

Equation 6



 R

+ R   C « T

SW AD S S

1

The charge of C and C is redistributed also on C , determining a new value of the

P1

P2

S

voltage V on the capacitance according to Equation 7:

A1

Equation 7

V

 C + C + C  = V  C + C



P2

A1

S

P1

P2

A

P1

●

A second charge transfer involves also C (that is typically bigger than the on-chip

F

capacitance) through the resistance R : again considering the worst case in which C

L

P2

and C were in parallel to C (since the time constant in reality would be faster), the

S

P1

time constant is:

Equation 8



 R  C + C + C



P2

2

L

S

P1

In this case, the time constant depends on the external circuit: in particular imposing

that the transient is completed well before the end of sampling time T , a constraint on

S

R sizing is obtained:

L

Equation 9

8.5   = 8.5  R  C + C + C   T

S

2

L

S

P1

P2

Of course, R shall be sized also according to the current limitation constraints, in

L

combination with R (source impedance) and R (filter resistance). Being C

S

F

definitively bigger than C , C and C , then the final voltage V (at the end of the

P1

P2

S

A2

charge transfer transient) will be much higher than V . Equation 10 must be respected

A1

(charge balance assuming now C already charged at V ):

S

A1

Equation 10

V

 C + C + C + C  =V  C + V  C + C + C 

S P1 P2 F A F A1 P1 P2 S

A2

The two transients above are not influenced by the voltage source that, due to the presence

of the R C filter, is not able to provide the extra charge to compensate the voltage drop on

F

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Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Electrical characteristics

C with respect to the ideal source V ; the time constant R C of the filter is very high with

S

A

F F

respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.

S

Figure 19. Spectral representation of input signal

Analog Source Bandwidth (V )

A

T

2 R C (Conversion Rate vs. Filter Pole)

F F

C

Noise

f

 f (Anti-aliasing Filtering Condition)

0

F

2 f f (Nyquist)

0

C

f

0

f

Anti-Aliasing Filter (f = RC Filter pole)

Sampled Signal Spectrum (f = conversion Rate)

C

F

f

C

F

0

f

Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of

0

the anti-aliasing filter, f ), according to the Nyquist theorem the conversion rate f must be at

F

C

least 2f ; it means that the constant time of the filter is greater than or at least equal to twice

0

the conversion period (T ). Again the conversion period T is longer than the sampling time

C

T , which is just a portion of it, even when fixed channel continuous conversion mode is

S

selected (fastest conversion rate at a specific channel): in conclusion it is evident that the

time constant of the filter R C is definitively much higher than the sampling time T , so the

F

S

charge level on C cannot be modified by the analog signal source during the time in which

S

the sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce

the accuracy error due to the voltage drop on C ; from the two charge balance equations

S

above, it is simple to derive Equation 11 between the ideal and real sampled voltage on C :

S

Equation 11

V

C

+ C + C

P1 P2 F

A

--------- = -------------------------------------------------------

+ C + C + C

S

V

C

P1

A2

P2

F

From this formula, in the worst case (when V is maximum, that is for instance 5 V),

A

assuming to accept a maximum error of half a count, a constraint is evident on C value:

F

Equation 12

C

 2048  C

S

F

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Electrical characteristics

SPC56xP54x, SPC56xP60x

3.15.2

ADC conversion characteristics

Table 32. ADC conversion characteristics

Value

Unit

Symbol

Parameter

Conditions⁽¹⁾

Min

Typ

Max

V_{SS_HV_AD}



V_{SS_HV_AD}

+ 0.3

V_INAN

SR Analog input voltage⁽²⁾

—

V

0.3

ADC Clock frequency

(depends on ADC

configuration)

SR

f_CK

—

3⁽⁴⁾

—

60

MHz

(The duty cycle depends

on AD_clk⁽³⁾frequency)

f_s

SR Sampling frequency

—

1.53

—

MHz

ns

f_ADC= 20 MHz,

INPSAMP = 3

125

t_{ADC_S}

D

Sample time⁽⁵⁾

f_ADC= 9 MHz,

—

0.650

—

28.2

—

2.5

3

µs

pF

INPSAMP = 255

f_ADC= 20 MHz⁽⁷⁾

INPCMP = 1

,

t_{ADC_C}

P

D

Conversion time⁽⁶⁾

ADC input sampling

capacitance

(8)

C_S

—

ADC input pin capacitance

1

(8)

C_P1

—

ADC input pin capacitance

2

(8)

C_P2

—

1

ADC input pin capacitance

3

(8)

C_P3

—

1

V_{DD_HV_AD}= 5 V 10%

V_{DD_HV_AD}= 3.3 V 10%

V_{DD_HV_AD}= 5 V 10%

V_{DD_HV_AD}= 3.3 V 10%

—

0.6

3

k

Internal resistance of

analog source

(8)

R_SW1

D

2.15

3.6

Internal resistance of

analog source

(8)

R_SW2

D

Internal resistance of

analog source

(8)

R_AD

—

2

k

Current injection on one ADC

input, different from the

converted one. Remains within

TUE spec.

I_INJ

T

Input current injection

–5

—

5

mA

INL

DNL

OFS

GNE

P

T

Integral Non Linearity

No overload

—

–1.0

—

1.5

—

1

—

1.0

—

LSB

Differential Non Linearity No overload

Offset error

—

Gain error

—

1

—

Total unadjusted error

without current injection

TUE

P

16 precision channels

–2.5

—

2.5

LSB

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SPC56xP54x, SPC56xP60x

Electrical characteristics

Table 32. ADC conversion characteristics (continued)

Value

Unit

Symbol

Parameter

Conditions⁽¹⁾

Min

Typ

Max

Total unadjusted error with

current injection

TUE

T

16 precision channels

10 standard channels

–3

—

3

LSB

Total unadjusted error with

current injection

–4

—

4

1. V_DD= 3.3 V to 3.6 V / 4.5 V to 5.5 V, T_A= –40 °C to T_{A MAX}, unless otherwise specified and analog input voltage from

V_{SS_HV_AD}to V_{DD_HV_AD}

.

2. V_INANmay exceed V_{SS_ADC}and V_{DD_ADC}limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

3. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

4. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.

5. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_{ADC_S}. After the end of the

sample time t_{ADC_S}, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock t_{ADC_S}depend on programming.

6. This parameter includes the sample time t_{ADC_S}

.

7. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.

8. See Figure 16.

3.16

Flash memory electrical characteristics

Table 33. Program and erase specifications

Value

Symbol

Parameter

Conditions

Unit

Initial

Min Typ⁽¹⁾

Max⁽³⁾

max⁽²⁾

T_wprogramP Word Program (32 bits) Time⁽⁴⁾

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

—

30

18

70

50

500

4.1

66

µs

s

T_dwprogramP Double Word (64 bits) Program Time⁽⁴⁾

P Bank Program (64 KB)^{(4), (5)}

T_BKPRG

0.49

2.6

1.2

P Bank Program (1056 KB)^{(4), (5)}

6.6

s

T_MDPRG

P Module Program (512 KB)⁽⁴⁾

1.3

1.65

500

800

600

900

1300

33

s

200

700

300

400

600

T_16kpperaseP 16 KB Block Pre-program and Erase Time

—

5000

ms

T_32kpperaseP 32 KB Block Pre-program and Erase Time

T_64kpperaseP 64 KB Block Pre-program and Erase Time

T_128kpperaseP 128 KB Block Pre-program and Erase Time

—

5000

ms

Code Flash 20

Data Flash 10

t_ESRT

P Erase Suspend Request Rate⁽⁶⁾

—

ms

1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change

pending device characterization.

2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values

are characterized but not guaranteed.

4. Actual hardware programming times. This does not include software overhead.

5. Typical bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require

more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).

6. Time between erase suspend resume and next erase suspend.

Table 34. Flash memory module life

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Number of program/erase cycles per block

for 16 KB blocks over the operating

temperature range (T_J)

P/E

C

—

100000 100000 cycles

Number of program/erase cycles per block

for 32 KB blocks over the operating

temperature range (T_J)

10000

1000

100000 cycles

Number of program/erase cycles per block

for 64 KB blocks over the operating

temperature range (T_J)

Number of program/erase cycles per block

for 128 KB blocks over the operating

temperature range (T_J)

Blocks with 0 – 1000

P/E cycles

20

10

5

—

years

Minimum data retention at 85 °C average

ambient temperature⁽¹⁾

Blocks with 10000 P/E

cycles

Retention

C

Blocks with 100000 P/E

cycles

1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature

range.

Table 35. Flash read access timing

Symbol

C

Parameter

Conditions⁽¹⁾

Max Unit

2 wait states

0 wait states

66

Maximum working frequency for Code Flash

at given number of WS in worst conditions

Fmax

C

MHz

22

Maximum working frequency for Data Flash at

given number of WS in worst conditions

Fmax

C

8 wait states

66

MHz

1. VDD = 3.3 V 10% / 5.0 V 10%, TA = –40 to 125 °C, unless otherwise specified

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SPC56xP54x, SPC56xP60x

Electrical characteristics

3.17

AC specifications

3.17.1

Pad AC specifications

Table 36. Output pin transition times

Value

Unit

Symbol

C

Parameter

Conditions⁽¹⁾

Min Typ Max

T_trCC D Output transition time output pin⁽²⁾C_L= 25 pF V_DD= 5.0 V 10%,

—

50 ns

100

125

40

SLOW configuration

PAD3V5V = 0

T

D

T

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF V_DD= 3.3 V 10%,

PAD3V5V = 1

C_L= 50 pF

50

D

C_L= 100 pF

75

T_trCC D Output transition time output pin⁽²⁾C_L= 25 pF V_DD= 5.0 V 10%,

10 ns

20

MEDIUM configuration

PAD3V5V = 0

SIUL.PCRx.SRC = 1

T

D

T

C_L= 50 pF

C_L= 100 pF

40

C_L= 25 pF V_DD= 3.3 V 10%,

12

PAD3V5V = 1

SIUL.PCRx.SRC = 1

C_L= 50 pF

25

D

C_L= 100 pF

40

T_trCC D Output transition time output pin⁽²⁾C_L= 25 pF V_DD= 5.0 V 10%,

4

6

ns

FAST configuration

PAD3V5V = 0

SIUL.PCRx.SRC = 1

C_L= 50 pF

C_L= 100 pF

12

4

C_L= 25 pF V_DD= 3.3 V 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

C_L= 50 pF

7

C_L= 100 pF

12

4

(3)

T_simCC T Symmetric, same drive strength

between N and P transistor

V_DD= 5.0 V 10%, PAD3V5V = 0

V_DD= 3.3 V 10%, PAD3V5V = 1

ns

5

1. V_DD= 3.3 V 10% / 5.0 V 10%, T_A= –40 °C to T_{A MAX}, unless otherwise specified

2. C_Lincludes device and package capacitances (C_PKG< 5 pF).

3. Transition timing of both positive and negative slopes will differ maximum 50%

3.18

AC timing characteristics

3.18.1

RESET pin characteristics

The SPC56xP54/60 implements a dedicated bidirectional RESET pin.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

(f)

Figure 20. Start-up reset requirements

V

DD

V

DDMIN

V_RESET

V

IH

V

IL

device reset forced by V_RESET

device start-up phase

T_POR

Figure 21. Noise filtering on reset signal

V_RESET

hw_rst

‘1’

V

DD

V

IH

V

IL

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

f. The output drive provided is open drain and hence must be terminated by an external resistor of value 1 k

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Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Electrical characteristics

Table 37. RESET electrical characteristics

Value

Unit

Symbol

C

Parameter

Conditions⁽¹⁾

Min

Typ

Max

Input High Level CMOS

(Schmitt Trigger)

V_IH

V_IL

SR P

—

0.65V_DD

—

V_DD+0.4

V

Input low Level CMOS

(Schmitt Trigger)

0.4

—

0.35V_DD

—

Input hysteresis CMOS

(Schmitt Trigger)

V_HYSCC C

0.1V_DD

Push Pull, I_OL= 2mA,

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

—

0.1V_DD

0.5

Push Pull, I_OL= 1mA,

V_OL

CC P Output low level

V

V_DD= 5.0 V 10%, PAD3V5V = 1⁽²⁾

Push Pull, I_OL= 1mA,

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

C_L= 25pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

—

10

20

40

12

25

C_L= 50pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

C_L= 100pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

Output transition time

T_tr

CC D output pin⁽³⁾

ns

C_L= 25pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

MEDIUM configuration

C_L= 50pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

C_L= 100pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

—

40

—

W_FRSTSR P RESET input filtered pulse

—

ns

RESET input not filtered

W_NFRSTSR P

pulse

500

maximum delay before

internal reset is released

after all VDD_HV reach

nominal supply

T_PORCC D

Monotonic VDD_HV supply ramp

—

1

ms

µA

V

_DD= 3.3 V 10%, PAD3V5V = 1

V_DD= 5.0 V 10%, PAD3V5V = 0

_DD= 5.0 V 10%, PAD3V5V = 1⁽⁴⁾

10

—

150

250

Weak pull-up current

absolute value

|I_WPU

|

CC P

V

1. V_DD= 3.3 V 10% / 5.0 V 10%, T_A= –40 °C to T_{A MAX}, unless otherwise specified

2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device

reference manual).

3. C_Lincludes device and package capacitance (C_PKG< 5 pF).

4. The configuration PAD3V5 = 1 when V_DD= 5 V is only transient configuration during power-up. All pads but RESET and

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Conditions Min Max Unit

3.18.2

IEEE 1149.1 interface timing

Table 38. JTAG pin AC electrical characteristics

No.

Symbol

C

Parameter

1

2

t_JCYC

t_JDC

CC D TCK cycle time

—

100

40

—

5

—

60

3

ns

CC D TCK clock pulse width (measured at V_{DD_HV_IOx}/2)

3

t_TCKRISECC D TCK rise and fall times (40% – 70%)

_TMSS,t_TDISCC D TMS, TDI data setup time

4

t

—

40

—

50

—

5

t_{TMSH, TDIH}

t_TDOV

t_TDOI

t_TDOHZ

t_BSDV

t

CC D TMS, TDI data hold time

25

—

0

6

CC D TCK low to TDO data valid

7

CC D TCK low to TDO data invalid

8

CC D TCK low to TDO high impedance

CC D TCK falling edge to output valid

40

—

50

9

10

11

12

13

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

CC D TCK falling edge to output valid out of high impedance

CC D TCK falling edge to output high impedance

CC D Boundary scan input valid to TCK rising edge

CC D TCK rising edge to boundary scan input invalid

Figure 22. JTAG test clock input timing

TCK

2

3

2

1

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SPC56xP54x, SPC56xP60x

Electrical characteristics

Figure 23. JTAG test access port timing

TCK

4

5

TMS, TDI

6

8

7

TDO

Doc ID 18340 Rev 3

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Figure 24. JTAG boundary scan timing

TCK

9

11

Output

Signals

10

Output

Signals

12

13

Input

Signals

3.18.3

Nexus timing

(1)

Table 39. Nexus debug port timing

Value

No.

Symbol

C

Parameter

Unit

Min

Typ

Max

1

2

t_MCYC

t_MDOV

CC D MCKO cycle time

32

—

ns

–

CC D MCKO edge to MDO data valid

—

0.25 × t_MCYC

0.1 × t_MCYC

–

3

t_MSEOVCC D MCKO edge to MSEO data valid

ns

0.1 × t_MCYC

–

4

5

t_EVTOV

t_TCYC

CC D MCKO edge to EVTO data valid

CC D TCK cycle time

—

0.25 × t_MCYC

—

ns

0.1 × t_MCYC

64⁽²⁾

88/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Electrical characteristics

(1)

Table 39. Nexus debug port timing (continued)

Value

No.

Symbol

C

Parameter

Unit

Min

Typ

Max

t_NTDIS

t_NTMSSCC D TMS data setup time

t_NTDIHCC D TDI data hold time

t_NTMSHCC D TMS data hold time

CC D TDI data setup time

6

—

35

—

ns

6

7

10

—

6

8

9

t_TDOV

t_TDOI

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

1. All values need to be confirmed during device validation.

2. Lower frequency is required to be fully compliant to standard.

Figure 25. Nexus output timing

1

MCKO

2

3

4

MDO

MSEO

EVTO

Output Data Valid

Figure 26. Nexus event trigger and test clock timings

TCK

EVTI

EVTO

5

Doc ID 18340 Rev 3

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Figure 27. Nexus TDI, TMS, TDO timing

TCK

6

7

TMS, TDI

9

8

TDO

3.18.4

External interrupt timing (IRQ pin)

(1)

Table 40. External interrupt timing

No.

Symbol

C

Parameter

IRQ pulse width low

Conditions

Min

Max

Unit

1

2

3

t_IPWL

t_IPWH

t_ICYC

CC

D

—

4

—

t_CYC

IRQ pulse width high

IRQ edge to edge time⁽²⁾

4 + N ⁽³⁾

1. IRQ timing specified at f_SYS= 64 MHz and V_{DD_HV_IOx}= 3.0 V to 5.5 V, T_A= T_Lto T_H, and CL = 200pF with SRC = 0b00.

2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

3. N= ISR time to clear the flag.

90/104

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SPC56xP54x, SPC56xP60x

Electrical characteristics

Figure 28. External interrupt timing

IRQ

1

2

3

3.18.5

DSPI timing

(1)

Table 41. DSPI timing

No. Symbol

C

Parameter

Conditions

Min

Max

Unit

Master (MTFE = 0)

Slave (MTFE = 0)

60

16

26

—

1

t_SCKCC D DSPI cycle time

ns

2

3

4

5

t_CSCCC D PCS to SCK delay

t_ASCCC D After SCK delay

t_SDCCC D SCK duty cycle

—

ns

—

0.4 × t_SCK0.6 × t_SCKns

t_A

CC D Slave access time

SS active to SOUT valid

—

30

16

ns

SS inactive to SOUT High-Z or

invalid

6

t_DISCC D Slave SOUT disable time

7

8

t_PCSCCC D PCSx to PCSS time

t_PASCCC D PCSS to PCSx time

—

13

35

4

—

12

36

12

ns

Master (MTFE = 0)

Slave

9

t_SUICC D Data setup time for inputs

ns

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

Slave

35

–5

4

10

t_HICC D Data hold time for inputs

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

Slave

11

–5

—

11 t_SUOCC D Data valid (after SCK edge)

ns

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

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Electrical characteristics

SPC56xP54x, SPC56xP60x

(1)

Table 41. DSPI timing (continued)

No. Symbol Parameter

C

Conditions

Master (MTFE = 0)

Min

Max

Unit

–2

6

—

Slave

12 t_HOCC D Data hold time for outputs

ns

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

6

–2

1. All timing are provided with 50pF capacitance on output, 1ns transition time on input signal

Figure 29. DSPI classic SPI timing — master, CPHA = 0

2

3

PCSx

1

4

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

10

9

Last Data

SIN

First Data

Data

12

11

Last Data

SOUT

92/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Electrical characteristics

Figure 30. DSPI classic SPI timing — master, CPHA = 1

CSx

SCK Output

(CPOL=0)

10

SCK Output

(CPOL=1)

9

Data

First Data

Last Data

SIN

12

11

SOUT

Last Data

First Data

Figure 31. DSPI classic SPI timing — slave, CPHA = 0

3

2

SS

1

4

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

5

11

12

Data

6

First Data

Last Data

SOUT

SIN

9

10

Data

Last Data

First Data

Doc ID 18340 Rev 3

93/104

Electrical characteristics

SPC56xP54x, SPC56xP60x

Figure 32. DSPI classic SPI timing — slave, CPHA = 1

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

Data

SOUT

SIN

First Data

10

9

Last Data

First Data

Figure 33. DSPI modified transfer format timing — master, CPHA = 0

3

PCSx

4

1

2

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

9

10

SIN

First Data

Last Data

Data

12

11

SOUT

First Data

Data

94/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Electrical characteristics

Figure 34. DSPI modified transfer format timing — master, CPHA = 1

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

10

9

SIN

Last Data

First Data

Data

12

Data

11

First Data

Last Data

SOUT

Figure 35. DSPI modified transfer format timing — slave, CPHA = 0

3

2

SS

1

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

12

11

6

5

First Data

9

Data

Last Data

10

SOUT

SIN

Last Data

First Data

Doc ID 18340 Rev 3

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Electrical characteristics

SPC56xP54x, SPC56xP60x

Figure 36. DSPI modified transfer format timing — slave, CPHA = 1

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

First Data

10

Data

SOUT

SIN

9

First Data

Last Data

Figure 37. DSPI PCS strobe (PCSS) timing

8

7

PCSS

PCSx

96/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package characteristics

4

Package characteristics

4.1

ECOPACK^®

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

4.2

Package mechanical data

4.2.1

LQFP144 mechanical outline drawing

Figure 38. LQFP144 package mechanical drawing

Seating plane

C

A

A2 A1

c

b

0.25 mm

gage plane

ccc

C

k

D

D1

A1

L

D3

L1

108

73

72

109

E3 E1

E

144

37

Pin 1

identification

1

36

ME_1A

e

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Package characteristics

SPC56xP54x, SPC56xP60x

inches⁽¹⁾

Table 42. LQFP144 mechanical data

mm

Typ

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

—

0.050

1.350

0.170

0.090

21.800

19.800

—

1.600

0.150

1.450

0.270

0.200

22.200

20.200

—

0.0630

0.0059

0.0571

0.0106

0.0079

0.8740

0.7953

—

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

—

1.400

0.220

—

0.0551

0.0087

—

c

D

22.000

20.000

17.500

22.000

20.000

17.500

0.500

0.600

1.000

3.5 °

0.8661

0.7874

0.6890

0.8661

0.7874

0.6890

0.0197

0.0236

0.0394

0.0 °

D1

D3

E

21.800

19.800

—

22.200

20.200

—

0.8583

0.7795

—

0.8740

0.7953

—

E1

E3

e

—

L

0.450

—

0.750

—

0.0177

—

0.0295

—

L1

k

0.0 °

7.0°

3.5 °

7.0 °

ccc⁽²⁾

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Tolerance

98/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Package characteristics

4.2.2

LQFP100 mechanical outline drawing

Figure 39. LQFP100 package mechanical drawing

0.25 mm

0.10 inch

GAGE PLANE

k

D

L

D1

L1

D3

51

75

C

76

50

b

E3 E1

E

100

26

Pin 1

identification

1

25

ccc

C

e

A1

A2

A

SEATING PLANE

C

1L_ME

Table 43. LQFP100 mechanical data

mm

inches⁽¹⁾

Typ

Symbol

Min

Typ

Max

Min

Max

A

—

1.600

0.150

1.450

—

0.0630

0.0059

0.0571

A1

A2

0.050

1.350

0.0020

0.0531

1.400

0.0551

Doc ID 18340 Rev 3

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Package characteristics

SPC56xP54x, SPC56xP60x

inches⁽¹⁾

Table 43. LQFP100 mechanical data (continued)

mm

Typ

Symbol

Min

Max

Min

Typ

Max

b

c

0.170

0.090

15.800

13.800

—

0.220

—

0.270

0.200

16.200

14.200

—

0.0067

0.0035

0.6220

0.5433

—

0.0087

—

0.0106

0.0079

0.6378

0.5591

—

D

16.000

14.000

12.000

16.000

14.000

12.000

0.500

0.600

1.000

3.5 °

0.6299

0.5512

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5 °

D1

D3

E

15.800

13.800

—

16.200

14.200

—

0.6220

0.5433

—

0.6378

0.5591

—

E1

E3

e

—

L

0.450

—

0.750

—

0.0177

—

0.0295

—

L1

k

0.0 °

7.0 °

0.0 °

7.0 °

ccc⁽²⁾

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Tolerance

100/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Ordering information

5

Ordering information

(g)

Figure 40. Ordering information scheme

Example code:

Product identifier Core Family Memory Package Temperature Custom vers. Conditioning

SPC56

A

P

60

L3

C

EFA

Y

Y = Tray

R = Tape and Reel

X = Tape and Reel 90°

A = 5 V, 64 MHz

B = 3,3 V, 64 MHz

A = “Airbag” feature set

F = “Full feature” set

E = Data flash memory

B = –40 to 105 °C

C = –40 to 125 °C

L5 = LQFP144

L3 = LQFP100

60 = 1 MB

54 = 768 KB

P = SPC56xP54/60 family

A = Dual core e200z0h

0 = Single core e200z0h

SPC56 = Power Architecture in 90nm

g. Not all configurations are available on the market. Please contact your ST Sales Rappresentative to get the list of orderable

commercial part number.

Doc ID 18340 Rev 3

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Revision history

SPC56xP54x, SPC56xP60x

6

Revision history

Table 44 summarizes revisions to this document.

Table 44. Document revision history

Date

Revision

Substantive changes

21-Dec-2010

1

Initial release

In the Feature list:

Revised the first bullet.

Changed “Up to 82 GPIO” to “Up to 80 GPIO”

Changed “and 82 GPIO” to “and 49 GPIO”

Changed “FlexRay module“ to “1 FlexRay™ module”.

Added Section 1.5, Feature details

Table 4: SPC56xP54/60 series block summary, added FlexRay entry.

In the “LQFP176 pinout (top view)” figure:

– Pin 104 now is TDI, was PB[5]

– Pin 107 now is TDO, was PB[4]

– Pin 71 now is NC, was OKOUT

– Pin 72 now is NC, was OKOUT_B

– Pin 87 now is NC, was NBYPASS_HV

– Pin 88 now is NC, was IPP_LIVI_B_VDDIO

Table 7: Pin muxing:

PB[6] was clk_out_div5, is now clk_out_div256

Removed PB[4] and PB[5] rows

In the A[3] row, changed ABS[2] to ABS[1]

Section 3.11, DC electrical characteristics, added “Peripherals supply

current (5 V and 3.3 V)” table

Table 14: EMI testing specifications, removed all references to SAE

Replaced both Table 12: Thermal characteristics for 144-pin LQFP and

Table 13: Thermal characteristics for 100-pin LQFP

Table 30: PLLMRFM electrical specifications (V_DDPLL= 1.08 V to

1.32 V, V_SS= V_SSPLL= 0 V, TA = TL to TH), changed the max value

of f_SYSfrom 120 to 64

18-Oct-2011

2

Table 33: Program and erase specifications:

Removed all TBC

changed the initial max value of T_BKPRG(Code Flash) from 3.3 to

6.6 s

changed the max value of T_BKPRG(Data Flash) from 1.9 to 4.1 s

changed the max value of T_wprogram(Data Flash) from 300 to 500 µs

Added t_ESRTrow

Table 17: Voltage regulator electrical characteristics, updated

V_{DD_LV_REGCOR}values

Updated Table 18: Low voltage monitor electrical characteristics

Updated Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0) and

Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1)

Removed “NVUSRO[OSCILLATOR_MARGIN] field description”

section.

Removed ordarable parts tables.

102/104

Doc ID 18340 Rev 3

SPC56xP54x, SPC56xP60x

Revision history

Table 44. Document revision history (continued)

Date

Revision

Substantive changes

Removed “Enhanced Full-featured” version.

In the cover page, added “(1 × Master/Slave, 1 × Master Only)“ at the

end of the bullet “2 LINFlex modules (LIN 2.1)”

Table 2: SPC56xP54/60 device comparison, updated the value of

“LINFLEX module” to “2 (1 × Master/Slave, 1 × Master only)”

Section 1.5.4: On-chip flash memory with ECC

replaced two occurrences of “3 wait states” to “2 wait states”

replaced 60 MHz to 64 MHz

Section 1.5.21: Serial communication interface module (LINFlex),

updated first bullet to “Supports LIN Master mode (on both modules),

LIN Slave mode (on one module) and UART mode”

Section 1.5.24: Analog-to-digital converter (ADC), removed bullet

concerning the analog watchdogs from Normal mode features.

Table 5: Supply pins, removed V_{REG_BYPASS}row.

Table 6: System pins:

added V_{REG_BYPASS}row

added a footnote about RESET

Table 9: Absolute maximum ratings:

changed typical value of TV_DDto 0.25 and added a footnote

added V_INANentry

Updated Section 3.8.1: Voltage regulator electrical characteristics

Updated Table 14: EMI testing specifications

Table 18: Low voltage monitor electrical characteristics, changed

maximum value of V_{MLVDDOK_H}to 1.15

15-May-2012

3

Table 20: DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0),

added IPU and IPD rows for RESET pin.

Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0):

added maximum values of I_{DD_LV_CORE}for: RUN, HALT, and STOP

mode

updated values and parameter classification of I_{DD_FLASH}

Table 22: DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1),

added IPU and IPD rows for RESET pin.

Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1):

added maximum values of I_{DD_LV_CORE}for: RUN, HALT, and STOP

mode

updated values and parameter classification of I_{DD_FLASH}

Added Table 26: I/O consumption

Table 31: 16 MHz RC oscillator electrical characteristics, changed

^{minimum and maximum values of}_RCMVARrespectively to -6 and 6.

Renamed Figure 16: Input equivalent circuit (precise channels) (was

“Input equivalent circuit”)

Added Figure 17: Input equivalent circuit (extended channels)

Section 3.15.1: Input impedance and ADC accuracy, updated

Equation 4 and Equation 10

Table 32: ADC conversion characteristics, added V_INAN, C_P3and R_SW2

rows

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SPC56xP54x, SPC56xP60x

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104/104

Doc ID 18340 Rev 3


型号：	SPC560P54L5
厂家：	ST
描述：	用于汽车底盘和安全应用的32位Power Architecture MCU
文件：	总104页 (文件大小：1028K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SPC560P54L5 [STMICROELECTRONICS]

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