SPC56EL54L5 [STMICROELECTRONICS]
用于汽车底盘和安全应用的32位Power Architecture MCU;
| 型号： | SPC56EL54L5 |
| 厂家： | 
ST |
| 描述： | 用于汽车底盘和安全应用的32位Power Architecture MCU |
| 文件： | 总160页 (文件大小：1248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPC56EL60x, SPC56EL54x
SPC564L60x, SPC564L54x
32-bit Power Architecture® microcontroller for automotive
SIL3/ASILD chassis and safety applications
Datasheet − production data
Features
■ High-performance e200z4d dual core
®
– 32-bit Power Architecture technology CPU
– Core frequency as high as 120 MHz
– Dual issue five-stage pipeline core
– Variable Length Encoding (VLE)
– Memory Management Unit (MMU)
LQFP100 (14 x 14x 1.4 mm)
LQFP144 (20 x 20 x 1.4 mm)
■ Decoupled Parallel mode for high-performance
– 4 KB instruction cache with error detection
code
use of replicated cores
– Signal processing engine (SPE)
■ Nexus Class 3+ interface
■ Memory available
■ Interrupts
– Up to 1 MB flash memory with ECC
– Up to 128 KB on-chip SRAM with ECC
– Replicated 16-priority controller
– Replicated 16-channel eDMA controller
– Built-in RWW capabilities for EEPROM
emulation
■ GPIOs individually programmable as input,
output or special function
■ SIL3/ASILD innovative safety concept:
■ Three 6-channel general-purpose eTimer units
LockStep mode and Fail-safe protection
■ 2 FlexPWM units
– Sphere of replication (SoR) for key
components (such as CPU core, eDMA,
crossbar switch)
– Four 16-bit channels per module
■ Communications interfaces
– 2 LINFlexD channels
– Fault collection and control unit (FCCU)
– 3 DSPI channels with automatic chip select
generation
– 2 FlexCAN interfaces (2.0B Active) with 32
message objects
– Redundancy control and checker unit
(RCCU) on outputs of the SoR connected
to FCCU
– Boot-time Built-In Self-Test for Memory
(MBIST) and Logic (LBIST) triggered by
hardware
– FlexRay module (V2.1 Rev. A) with 2
channels, 64 message buffers and data
rates up to 10 Mbit/s
– Boot-time Built-In Self-Test for ADC and
flash memory triggered by software
■ Two 12-bit analog-to-digital converters (ADCs)
– Replicated safety enhanced watchdog
– Replicated junction temperature sensor
– Non-maskable interrupt (NMI)
– 16 input channels
– Programmable cross triggering unit (CTU)
to synchronize ADCs conversion with timer
and PWM
– 16-region memory protection unit (MPU)
– Clock monitoring units (CMU)
– Power management unit (PMU)
■ Sine wave generator (D/A with low pass filter)
■ On-chip CAN/UART bootstrap loader
– Cyclic redundancy check (CRC) unit
■ Single 3.0 V to 3.6 V voltage supply
■ Ambient temperature range –40 °C to 125 °C
■ Junction temperature range –40 °C to 150 °C
August 2012
Doc ID 15457 Rev 8
1/160
This is information on a product in full production.
www.st.com
1
Contents
SPC56XL60/54
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
1.2
1.3
1.4
1.5
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
High-performance e200z4d core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Enhanced Direct Memory Access (eDMA) . . . . . . . . . . . . . . . . . . . . . . 13
On-chip flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Platform flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Platform Static RAM Controller (SRAMC) . . . . . . . . . . . . . . . . . . . . . . . 15
Memory subsystem access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.10 Error Correction Status Module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.11 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.12 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.13 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL) . . . . . . . . . . . . . . 18
1.5.15 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.16 Internal Reference Clock (RC) oscillator . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.17 Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.18 Periodic Interrupt Timer Module (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.19 System Timer Module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.20 Software Watchdog Timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.21 Fault Collection and Control Unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.22 System Integration Unit Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.23 Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.24 Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.25 System Status and Configuration Module (SSCM) . . . . . . . . . . . . . . . . 21
1.5.26 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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1.5.28 Serial communication interface module (LINFlexD) . . . . . . . . . . . . . . . . 24
1.5.29 Deserial Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 24
1.5.30 FlexPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.31 eTimer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.33 Analog-to-Digital Converter module (ADC) . . . . . . . . . . . . . . . . . . . . . . 27
1.5.34 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.35 Cyclic Redundancy Checker (CRC) Unit . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.36 Redundancy Control and Checker Unit (RCCU) . . . . . . . . . . . . . . . . . . 29
1.5.37 Junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.38 Nexus Port Controller (NPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.39 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.40 Voltage regulator / Power Management Unit (PMU) . . . . . . . . . . . . . . . 31
1.5.41 Built-In Self-Test (BIST) capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2
3
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 33
2.1
2.2
2.3
2.4
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.1
3.2
3.3
3.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.4.1
General notes for specifications at maximum junction temperature . . 101
3.5
3.6
3.7
3.8
3.9
Electromagnetic Interference (EMI) characteristics . . . . . . . . . . . . . . . . 102
Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . 103
Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 104
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.10 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.11 Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . 111
3.12 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 111
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3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.14 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . 114
3.15 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.15.1 Input Impedance and ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.16 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.17 SWG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
3.18.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
3.19 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.19.1 Reset sequence duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.19.2 Reset sequence description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.19.3 Reset sequence trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.19.4 Reset sequence — start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.19.5 External watchdog window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.20 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.20.1 RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.20.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.20.4 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3.20.5 External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
4
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.1
4.2
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
SPC56XL60/54 device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Platform memory access time summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LQFP100 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LQFP144 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LFBGA257 pin function summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Thermal characteristics for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Thermal characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Thermal characteristics for LFBGA257 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EMI configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EMI emission testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
,
ESD ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Voltage regulator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Current consumption characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Flash memory program and erase electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 120
Flash memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MPC5643L SWG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Pad AC specifications (3.3 V , IPP_HVE = 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Reset sequence trigger — reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Voltage Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
WKUP/NMI glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Nexus debug port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
LFBGA257 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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List of figures
SPC56XL60/54
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
SPC56XL60/54 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPC56XL60/54 LQFP144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SPC56XL60/54 LFBGA257 pinout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
BCP68 board schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Input Equivalent Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 10. Transient Behavior during Sampling Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 11. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 12. Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 13. Destructive Reset Sequence, BIST enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 14. Destructive Reset Sequence, BIST disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 15. External Reset Sequence Long, BIST enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 16. Functional Reset Sequence Long. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 17. Functional Reset Sequence Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 18. Reset sequence start for Destructive Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 19. Reset sequence start via RESET assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 20. Reset sequence - External watchdog trigger window position . . . . . . . . . . . . . . . . . . . . . 129
Figure 21. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 22. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 23. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 24. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 25. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 26. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 27. Nexus EVTI Input Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 28. Nexus Double Data Rate (DDR) Mode output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 29. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 30. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 31. DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 32. DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 33. DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 34. DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 35. DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 36. DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 37. DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 38. DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 39. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 40. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 41. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 42. LFBGA257 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 43. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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1
Introduction
1.1
Document overview
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC56XL60/54 series of microcontroller units (MCUs). For functional
characteristics, see the SPC56XL60/54 Microcontroller Reference Manual. For use of the
SPC56XL60/54 in a fail-safe system according to safety standard IEC 61508, see the
Safety Application Guide for SPCEL60.
1.2
Description
The Leopard series microcontrollers are system-on-chip devices that are built on Power
Architecture technology and contain enhancements that improve the architecture’s fit in
embedded applications, include additional instruction support for digital signal processing
(DSP) and integrate technologies such as an enhanced time processor unit, enhanced
queued analog-to-digital converter, Controller Area Network, and an enhanced modular
input-output system.
The SPC56XL60/54 family of 32-bit microcontrollers is the latest achievement in integrated
automotive application controllers. It belongs to an expanding range of automotive-focused
products designed to address electrical hydraulic power steering (EHPS), electric power
steering (EPS) and airbag applications. The advanced and cost-efficient host processor
core of the SPC56XL60/54 automotive controller family complies with the Power
Architecture embedded category. It operates at speeds as high as 120 MHz and offers high-
performance processing optimized for low power consumption. It capitalizes on the available
development infrastructure of current Power Architecture devices and is supported with
software drivers, operating systems and configuration code to assist with users’
implementations.
1.3
Device comparison
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Table 1.
SPC56XL60/54
SPC56XL60/54 device summary
Feature
SPC56EL60
SPC56EL54
2 × e200z4
2 × e200z4
Type
(in lock-step or decoupled
operation)
(in lock-step or decoupled
operation)
Architecture
Harvard
Harvard
Execution speed
DMIPS intrinsic performance
SIMD (DSP + FPU)
MMU
0–120 MHz (+2% FM)
0–120 MHz (+2% FM)
>240 MIPS
>240 MIPS
Yes
Yes
CPU
16 entry
16 entry
Instruction set PPC
Instruction set VLE
Instruction cache
MPU-16 regions
Yes
Yes
Yes
4 KB, EDC
Yes
4 KB, EDC
Yes, replicated module
Yes
Yes, replicated module
Yes
Semaphore unit (SEMA4)
Core bus
AHB, 32-bit address, 64-bit data AHB, 32-bit address, 64-bit data
Buses
Internal periphery bus
32-bit address, 32-bit data
Lock Step Mode: 4 × 3
32-bit address, 32-bit data
Lock Step Mode: 4 × 3
Crossbar
Memory
Master × slave ports
Decoupled Parallel Mode: 6 × 3 Decoupled Parallel Mode: 6 × 3
Flash
1 MB, ECC, RWW
128 KB, ECC
768 K, ECC, RWW
96 KB, ECC
Static RAM (SRAM)
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Table 1.
SPC56XL60/54 device summary (continued)
Feature
SPC56EL60
SPC56EL54
16 interrupt levels, replicated
module
16 interrupt levels, replicated
module
Interrupt Controller (INTC)
Periodic Interrupt Timer (PIT)
System Timer Module (STM)
1 × 4 channels
1 × 4 channels
1 × 4 channels, replicated
module
1 × 4 channels, replicated
module
Software Watchdog Timer
(SWT)
Yes, replicated module
Yes, replicated module
eDMA
16 channels, replicated module 16 channels, replicated module
1 × 64 message buffers, dual
channel
1 × 64 message buffers, dual
channel
FlexRay
FlexCAN
2 × 32 message buffers
2 × 32 message buffers
LINFlexD (UART and LIN with
DMA support)
2
2
Modules
Clock out
Yes
Yes
Yes
Yes
Fault Collection and Control Unit
(FCCU)
Cross Triggering Unit (CTU)
eTimer
Yes
Yes
3 × 6 channels(1)
3 × 6 channels(1)
FlexPWM
2 Module 4 × (2 + 1) channels(2) 2 Module 4 × (2 + 1) channels(2)
2 × 12-bit ADC, 16 channels per 2 × 12-bit ADC, 16 channels per
ADC
ADC
Analog-to-Digital Converter
(ADC)
(3 internal, 4 shared and 9
external)
(3 internal, 4 shared and 9
external)
Sine Wave Generator (SWG)
32 point
32 point
3 × DSPI
3 × DSPI
Deserial Serial Peripheral
Interface (DSPI)
as many as 8 chip selects
as many as 8 chip selects
Cyclic Redundancy Checker
(CRC) unit
Modules
(cont.)
Yes
Yes
Junction temperature sensor
(TSENS)
Yes, replicated module
Yes, replicated module
Digital I/Os
≥ 16
≥ 16
3.3 V with integrated
3.3 V with integrated
bypassable ballast transistor
bypassable ballast transistor
Device power supply
External ballast transistor not
needed for bare die
External ballast transistor not
needed for bare die
Supply
Analog reference voltage
3.0 V – 3.6 V and 4.5 V – 5.5 V 3.0 V – 3.6 V and 4.5 V – 5.5 V
Frequency-modulated phase-
locked loop (FMPLL)
2
2
Clocking
Internal RC oscillator
16 MHz
16 MHz
External crystal oscillator
4 – 40 MHz
4 – 40 MHz
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Table 1.
SPC56XL60/54
SPC56XL60/54 device summary (continued)
Feature SPC56EL60
Nexus
SPC56EL54
Debug
Level 3+
Level 3+
100 pins
144 pins
100 pins
144 pins
LQFP
Packages
LBGA(3)
LBGA257
LBGA257
Temperature range (junction)
–40 to 150 °C
–40 to 150 °C
Ambient temperature range
using external ballast transistor
(LQFP)
Temperature
–40 to 125 °C
–40 to 125 °C
1. The third eTimer (eTimer_2) is available with external I/O access only in the BGA package, on the LQFP package
eTimer_2 is available internally only without any external I/O access.
2. The second FlexPWM module is available only in the BGA package.
3. LBGA257 available only as development package.
1.4
Block diagram
Figure 1 shows a top-level block diagram of the SPC56XL60/54 device.
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PMU
JTAG
Nexus
e200z4
e200z4
SWT
ECSM
STM
SWT
ECSM
STM
SPE
VLE
SPE
VLE
INTC
INTC
MMU
MMU
FlexRay
RC
SEMA4
eDMA
SEMA4
eDMA
I-CACHE
I-CACHE
Crossbar Switch
Memory Protection Unit
ECC logic for SRAM
Crossbar Switch
Memory Protection Unit
ECC logic for SRAM
PBRIDGE
PBRIDGE
RC
RC
TSENS
Flash memory
SRAM
TSENS
ECC bits + logic
ECC bits
RC
ADC
– Analog-to-Digital Converter
– Boot Assist Module
– Clock Monitoring Unit
– Cyclic Redundancy Check unit
– Cross Triggering Unit
– Serial Peripherals Interface
– Error Correction Code
LINFlexD – LIN controller with DMA support
MC – Mode Entry, Clock, Reset, & Power
PBRIDGE – Peripheral bridge
BAM
CMU
CRC
CTU
DSPI
ECC
PIT
– Periodic Interrupt Timer
PMU
RC
RTC
– Power Management Unit
– Redundancy Checker
– Real Time Clock
ECSM
eDMA
FCCU
– Error Correction Status Module
– Enhanced Direct Memory Access controller
– Fault Collection and Control Unit
SEMA4
SIUL
SSCM
STM
– Semaphore Unit
– System Integration Unit Lite
– System Status and Configuration Module
– System Timer Module
FlexCAN – Controller Area Network controller
FMPLL
INTC
– Frequency Modulated Phase Locked Loop
– Interrupt Controller
SWG
SWT
TSENS
XOSC
– Sine Wave Generator
– Software Watchdog Timer
– Temperature Sensor
IRCOSC – Internal RC Oscillator
JTAG – Joint Test Action Group interface
– Crystal Oscillator
Figure 1.
SPC56XL60/54 block diagram
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1.5
Feature details
1.5.1
High-performance e200z4d core
®
The e200z4d Power Architecture core provides the following features:
●
2 independent execution units, both supporting fixed-point and floating-point operations
Dual issue 32-bit Power Architecture technology compliant
●
–
–
5-stage pipeline (IF, DEC, EX1, EX2, WB)
In-order execution and instruction retirement
●
Full support for Power Architecture instruction set and Variable Length Encoding (VLE)
–
–
Mix of classic 32-bit and 16-bit instruction allowed
Optimization of code size possible
●
●
Thirty-two 64-bit general purpose registers (GPRs)
Harvard bus (32-bit address, 64-bit data)
–
I-Bus interface capable of one outstanding transaction plus one piped with no wait-
on-data return
–
D-Bus interface capable of two transactions outstanding to fill AHB pipe
●
I-cache and I-cache controller
4 KB, 256-bit cache line (programmable for 2- or 4-way)
–
●
●
●
●
●
●
●
No data cache
16-entry MMU
8-entry branch table buffer
Branch look-ahead instruction buffer to accelerate branching
Dedicated branch address calculator
3 cycles worst case for missed branch
Load/store unit
–
–
–
–
–
Fully pipelined
Single-cycle load latency
Big- and little-endian modes supported
Misaligned access support
Single stall cycle on load to use
●
●
Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine
cycles)
●
Single precision floating-point unit
–
–
1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 ×
32 division
–
Special square root and min/max function implemented
●
Signal processing support: APU-SPE 1.1
Support for vectorized mode: as many as two floating-point instructions per clock
–
●
●
Vectored interrupt support
Reservation instruction to support read-modify-write constructs
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●
Extensive system development and tracing support via Nexus debug port
1.5.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave
port, although one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic selects the higher priority master and grants it ownership of the slave port.
All other masters requesting that slave port are stalled until the higher priority master
completes its transactions.
The crossbar provides the following features:
●
4 masters and 3 slaves supported per each replicated crossbar
–
Masters allocation for each crossbar: e200z4d core with two independent bus
interface units (BIU) for I and D access (2 masters), one eDMA, one FlexRay
–
Slaves allocation for each crossbar: a redundant flash-memory controller with 2
slave ports to guarantee maximum flexibility to handle Instruction and Data array,
one redundant SRAM controller with 1 slave port each and 1 redundant peripheral
bus bridge
●
●
32-bit address bus and 64-bit data bus
Programmable arbitration priority
–
Requesting masters can be treated with equal priority and are granted access to a
slave port in round-robin method, based upon the ID of the last master to be
granted access or a priority order can be assigned by software at application run
time
●
Temporary dynamic priority elevation of masters
The XBAR is replicated for each processing channel.
1.5.3
1.5.4
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each
master (eDMA, FlexRay, CPU) can be assigned different access rights to each region.
●
16-region MPU with concurrent checks against each master access
32-byte granularity for protected address region
●
The memory protection unit is replicated for each processing channel.
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware microarchitecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is used to minimize the
overall block size.
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The eDMA module provides the following features:
16 channels supporting 8-, 16-, and 32-bit value single or block transfers
●
●
●
Support variable sized queues and circular buffered queue
Source and destination address registers independently configured to post-increment
or stay constant
●
●
●
●
Support major and minor loop offset
Support minor and major loop done signals
DMA task initiated either by hardware requestor or by software
Each DMA task can optionally generate an interrupt at completion and retirement of the
task
●
●
Signal to indicate closure of last minor loop
Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processing channel.
1.5.5
On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory
(NVM) can be used for instruction storage or data storage, or both. The flash memory
module interfaces with the system bus through a dedicated flash memory array controller. It
supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to
flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow
no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz.
The flash memory module provides the following features
●
Up to 1 MB of flash memory in unique multi-partitioned hard macro
Sectorization:
●
–
–
1 MB: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
768 KB: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 1 × 256 KB
●
●
EEPROM emulation (in software) within same module but on different partition
16 KB test sector and 16 KB shadow block for test, censorship device and user option
bits
●
Wait states:
–
–
–
3 wait states for frequencies =< 120 MHz
2 wait states for frequencies =< 80 MHz
1 wait state for frequencies =< 60 MHz
●
●
●
Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
1-bit error correction, 2-bit error detection
1.5.6
On-chip SRAM with ECC
The SPC56XL60/54 SRAM provides a general-purpose single port memory.
ECC handling is done on a 32-bit boundary for data and it is extended to the address to
have the highest possible diagnostic coverage including the array internal address decoder.
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The SRAM module provides the following features:
●
System SRAM: 128 KB
●
ECC on 32-bit word (syndrome of 7 bits)
–
ECC covers SRAM bus address
●
●
1-bit error correction, 2-bit error detection
Wait states:
–
–
1 wait state for frequencies =< 120 MHz
0 wait states for frequencies =< 80 MHz
1.5.7
Platform flash memory controller
The following list summarizes the key features of the flash memory controller:
●
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned
reads within the 32-bit container are supported. Only aligned word writes are
supported.
●
●
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each
bank.
Code flash (bank0) interface provides configurable read buffering and page prefetch
support.
–
Four page-read buffers (each 128 bits wide) and a prefetch controller support
speculative reading and optimized flash access.
●
●
●
Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The
buffers implement a least-recently-used replacement algorithm to maximize
performance.
Programmable response for read-while-write sequences including support for stall-
while-write, optional stall notification interrupt, optional flash operation abort , and
optional abort notification interrupt.
Separate and independent configurable access timing (on a per bank basis) to support
use across a wide range of platforms and frequencies.
●
●
●
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.5.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection
and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
●
●
●
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
SRAM array
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The following functions are implemented:
●
ECC encoding (32-bit boundary for data and complete address bus)
ECC decoding (32-bit boundary and entire address)
●
●
Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
1.5.9
Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the
data phase of the access. Slower memories or peripherals may require additional data
phase wait states. Additional data phase wait states may also occur if the slave being
accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of
memory accesses.
Table 2.
Platform memory access time summary
Data phase
AHB transfer
Description
wait states
e200z4d instruction fetch
e200z4d instruction fetch
0
Flash memory prefetch buffer hit (page hit)
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
3
e200z4d data read
e200z4d data write
e200z4d data write
0–1
0
SRAM read
SRAM 32-bit write
0
SRAM 64-bit write (executed as 2 x 32-bit writes)
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d data write
0–2
0
e200z4d flash memory read
e200z4d flash memory read
Flash memory prefetch buffer hit (page hit)
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
3
1.5.10
Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform
memories (flash memory and SRAM). It does not implement the actual ECC calculation. A
detected error (double error for flash memory or SRAM) is also reported to the FCCU. The
following errors and indications are reported into the ECSM dedicated registers:
●
●
●
●
ECC error status and configuration for flash memory and SRAM
ECC error reporting for flash memory
ECC error reporting for SRAM
ECC error injection for SRAM
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1.5.11
Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
●
Duplicated periphery
●
Master access privilege level per peripheral (per master: read access enable; write
access enable)
●
●
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
1.5.12
Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for
statically scheduled hard real-time systems.
For high-priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a
modifiable priority mask, the priority can be raised temporarily so that all tasks which share
the resource can not preempt each other.
The INTC provides the following features:
●
●
●
Duplicated periphery
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
●
Priority elevation for shared resource
The INTC is replicated for each processor.
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Introduction
SPC56XL60/54
1.5.13
System clocks and clock generation
The following list summarizes the system clock and clock generation on this device:
●
Lock status continuously monitored by lock detect circuitry
●
●
Loss-of-clock (LOC) detection for reference and feedback clocks
On-chip loop filter (for improved electromagnetic interference performance and fewer
external components required)
●
●
Programmable output clock divider of system clock (÷1, ÷2, ÷4, ÷8)
FlexPWM module and as many as three eTimer modules running on an auxiliary clock
independent from system clock (with max frequency 120 MHz)
●
●
On-chip crystal oscillator with automatic level control
Dedicated internal 16 MHz internal RC oscillator for rapid start-up
–
Supports automated frequency trimming by hardware during device startup and by
user application
●
Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and
SWG)
1.5.14
Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum
reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency
modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio
are all software configurable. The FMPLLs have the following major features:
●
●
●
Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
Voltage controlled oscillator (VCO) range: 256–512 MHz
Frequency modulation via software control to reduce and control emission peaks
–
Modulation depth 2% if centered or 0% to –4% if downshifted via software control
register
–
Modulation frequency: triangular modulation with 25 kHz nominal rate
●
●
●
Option to switch modulation on and off via software interface
Output divider (ODF) for reduced frequency operation without re-lock
3 modes of operation
–
–
–
Bypass mode
Normal FMPLL mode with crystal reference (default)
Normal FMPLL mode with external reference
●
●
●
●
Lock monitor circuitry with lock status
Loss-of-lock detection for reference and feedback clocks
Self-clocked mode (SCM) operation
On-chip loop filter
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Introduction
●
Auxiliary FMPLL
–
–
Used for FlexRay due to precise symbol rate requirement by the protocol
Used for motor control periphery and connected IP (A/D digital interface CTU) to
allow independent frequencies of operation for PWM and timers and jitter-free
control
–
–
Option to enable/disable modulation to avoid protocol violation on jitter and/or
potential unadjusted error in electric motor control loop
Allows to run motor control periphery at different (precisely lower, equal or higher
as required) frequency than the system to ensure higher resolution
1.5.15
1.5.16
Main oscillator
The main oscillator provides these features:
●
●
●
●
Input frequency range 4–40 MHz
Crystal input mode
External reference clock (3.3 V) input mode
FMPLL reference
Internal Reference Clock (RC) oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor
is compared to the stable bandgap reference voltage. The RC oscillator is the device safe
clock.
The RC oscillator provides these features:
●
●
●
Nominal frequency 16 MHz
5% variation over voltage and temperature after process trim
Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the FMPLL
●
RC oscillator is used as the default system clock during startup and can be used as
back-up input source of FMPLL(s) in case XOSC fails
1.5.17
Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME)
These modules provide the following:
●
●
●
●
Clock gating and clock distribution control
Halt, stop mode control
Flexible configurable system and auxiliary clock dividers
Various execution modes
–
–
–
–
HALT and STOP mode as reduced activity low power mode
Reset, Idle, Test, Safe
Various RUN modes with software selectable powered modules
No stand-by mode implemented (no internal switchable power domains)
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Introduction
SPC56XL60/54
1.5.18
Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features:
●
4 general purpose interrupt timers
●
●
32-bit counter resolution
Can be used for software tick or DMA trigger operation
1.5.19
1.5.20
System Timer Module (STM)
The STM implements the following features:
●
Up-counter with 4 output compare registers
OS task protection and hardware tick implementation per AUTOSAR requirement
(a)
●
The STM is replicated for each processor.
Software Watchdog Timer (SWT)
This module implements the following features:
●
●
●
●
●
Fault tolerant output
Safe internal RC oscillator as reference clock
Windowed watchdog
Program flow control monitor with 16-bit pseudorandom key generation
Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.5.21
Fault Collection and Control Unit (FCCU)
The FCCU module has the following features:
●
Redundant collection of hardware checker results
●
Redundant collection of error information and latch of faults from critical modules on
the device
●
●
Collection of self-test results
Configurable and graded fault control
–
Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset,
or Safe mode entered)
–
External reaction (failure is reported to the external/surrounding system via
configurable output pins)
1.5.22
System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general
purpose I/O (GPIO), internal peripheral multiplexing, and system reset operation. The reset
configuration block contains the external pin boot configuration logic. The pad configuration
block controls the static electrical characteristics of I/O pins. The GPIO block provides
uniform and discrete input/output control of the I/O pins of the MCU.
a. Automotive Open System Architecture
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Introduction
The SIU provides the following features:
Centralized pad control on a per-pin basis
●
–
–
–
–
–
Pin function selection
Configurable weak pull-up/down
Configurable slew rate control (slow/medium/fast)
Hysteresis on GPIO pins
Configurable automatic safe mode pad control
●
Input filtering for external interrupts
1.5.23
1.5.24
Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.
Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is
executed only if serial booting mode is selected via boot configuration pins.
The BAM provides the following features:
●
●
●
●
Enables booting via serial mode (FlexCAN or LINFlex-UART)
Supports programmable 64-bit password protection for serial boot mode
Supports serial bootloading of either Power Architecture code (default) or VLE code
Automatic switch to serial boot mode if internal flash memory is blank or invalid
1.5.25
System Status and Configuration Module (SSCM)
The SSCM on this device features the following:
●
●
●
System configuration and status
Debug port status and debug port enable
Multiple boot code starting locations out of reset through implementation of search for
valid Reset Configuration Half Word
●
●
Sets up the MMU to allow user boot code to execute as either Power Architecture code
(default) or as VLE code out of flash memory
Triggering of device self-tests during reset phase of device boot
1.5.26
FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-
time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth.
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Introduction
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The FlexCAN module provides the following features:
Full implementation of the CAN protocol specification, version 2.0B
●
–
–
–
–
Standard data and remote frames
Extended data and remote frames
0 to 8 bytes data length
Programmable bit rate as fast as 1Mbit/s
●
●
32 message buffers of 0 to 8 bytes data length
Each message buffer configurable as receive or transmit buffer, all supporting standard
and extended messages
●
●
●
●
●
●
●
●
●
●
Programmable loop-back mode supporting self-test operation
3 programmable mask registers
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Transmit features
–
Supports configuration of multiple mailboxes to form message queues of scalable
depth
–
–
–
Arbitration scheme according to message ID or message buffer number
Internal arbitration to guarantee no inner or outer priority inversion
Transmit abort procedure and notification
●
●
Receive features
–
–
–
Individual programmable filters for each mailbox
8 mailboxes configurable as a 6-entry receive FIFO
8 programmable acceptance filters for receive FIFO
Programmable clock source
–
–
System clock
Direct oscillator clock to avoid FMPLL jitter
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Introduction
1.5.27
FlexRay
The FlexRay module provides the following features:
●
●
●
●
●
●
Full implementation of FlexRay Protocol Specification 2.1 Rev. A
64 configurable message buffers can be handled
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
Message buffers configurable as transmit or receive
Message buffer size configurable
Message filtering for all message buffers based on Frame ID, cycle count, and
message ID
●
●
●
Programmable acceptance filters for receive FIFO
Message buffer header, status, and payload data stored in system memory (SRAM)
Internal FlexRay memories have error detection and correction
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Introduction
SPC56XL60/54
1.5.28
Serial communication interface module (LINFlexD)
The LINFlexD module (LINFlex with DMA support) on this device features the following:
●
Supports LIN Master mode, LIN Slave mode and UART mode
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
Manages LIN frame transmission and reception without CPU intervention
LIN features
●
●
●
–
–
–
–
Autonomous LIN frame handling
Message buffer to store as many as 8 data bytes
Supports messages as long as 64 bytes
Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing,
checksum and Time-out errors)
–
–
–
–
–
Classic or extended checksum calculation
Configurable break duration of up to 50-bit times
Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
Diagnostic features (Loop back, LIN bus stuck dominant detection)
Interrupt driven operation with 16 interrupt sources
●
●
LIN slave mode features
–
–
Autonomous LIN header handling
Autonomous LIN response handling
UART mode
–
–
–
–
–
–
–
–
–
–
–
Full-duplex operation
Standard non return-to-zero (NRZ) mark/space format
Data buffers with 4-byte receive, 4-byte transmit
Configurable word length (8-bit, 9-bit, 16-bit, or 17-bit words)
Configurable parity scheme: none, odd, even, always 0
Speed as fast as 2 Mbit/s
Error detection and flagging (Parity, Noise and Framing errors)
Interrupt driven operation with four interrupt sources
Separate transmitter and receiver CPU interrupt sources
16-bit programmable baud-rate modulus counter and 16-bit fractional
Two receiver wake-up methods
●
Support for DMA enabled transfers
1.5.29
Deserial Serial Peripheral Interface (DSPI)
The DSPI modules provide a synchronous serial interface for communication between the
SPC56XL60/54 and external devices.
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Introduction
A DSPI module provides these features:
●
●
●
●
●
●
●
●
●
●
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
As many as 8 chip select lines available, depending on package and pin multiplexing
4 clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for de-
glitching
●
●
●
FIFOs for buffering as many as 5 transfers on the transmit and receive side
Queueing operation possible through use of the eDMA
General purpose I/O functionality on pins when not used for SPI
1.5.30
FlexPWM
The pulse width modulator module (FlexPWM) contains four PWM channels, each of which
is configured to control a single half-bridge power stage. Two modules are included on
LFBGA257 devices; on the LQFP144 package, only one module is present. Additionally,
four fault input channels are provided per FlexPWM module.
This PWM is capable of controlling most motor types, including:
●
●
●
●
●
AC induction motors (ACIM)
Permanent Magnet AC motors (PMAC)
Brushless (BLDC) and brush DC motors (BDC)
Switched (SRM) and variable reluctance motors (VRM)
Stepper motors
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Introduction
SPC56XL60/54
A FlexPWM module implements the following features:
●
16 bits of resolution for center, edge aligned, and asymmetrical PWMs
Maximum operating frequency as high as 120 MHz
●
–
Clock source not modulated and independent from system clock (generated via
secondary FMPLL)
●
●
●
●
●
●
Fine granularity control for enhanced resolution of the PWM period
PWM outputs can operate as complementary pairs or independent channels
Ability to accept signed numbers for PWM generation
Independent control of both edges of each PWM output
Synchronization to external hardware or other PWM supported
Double buffered PWM registers
–
–
Integral reload rates from 1 to 16
Half cycle reload capability
●
●
●
●
●
●
Multiple ADC trigger events can be generated per PWM cycle via hardware
Fault inputs can be assigned to control multiple PWM outputs
Programmable filters for fault inputs
Independently programmable PWM output polarity
Independent top and bottom deadtime insertion
Each complementary pair can operate with its own PWM frequency and deadtime
values
●
●
●
●
Individual software control for each PWM output
All outputs can be forced to a value simultaneously
PWMX pin can optionally output a third signal from each channel
Channels not used for PWM generation can be used for buffered output compare
functions
●
●
●
Channels not used for PWM generation can be used for input capture functions
Enhanced dual edge capture functionality
Option to supply the source for each complementary PWM signal pair from any of the
following:
–
–
–
External digital pin
Internal timer channel
External ADC input, taking into account values set in ADC high- and low-limit
registers
●
DMA support
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Introduction
1.5.31
eTimer module
The MPC5643L provides three eTimer modules (on the LQFP package eTimer_2 is
available internally only without any external I/O access). Six 16-bit general purpose
up/down timer/counters per module are implemented with the following features:
●
Maximum clock frequency of 120 MHz
Individual channel capability
●
–
–
–
–
–
–
–
Input capture trigger
Output compare
Double buffer (to capture rising edge and falling edge)
Separate prescaler for each counter
Selectable clock source
0–100% pulse measurement
Rotation direction flag (Quad decoder mode)
●
Maximum count rate
–
–
Equals peripheral clock divided by 2 for external event counting
Equals peripheral clock for internal clock counting
●
●
●
●
●
●
●
●
Cascadeable counters
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Preloadable counters
Pins available as GPIO when timer functionality not in use
DMA support
1.5.32
1.5.33
Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values
for external devices (ex: resolver).
Analog-to-Digital Converter module (ADC)
The ADC module features include:
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Introduction
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Analog part:
2 on-chip ADCs
●
–
–
–
12-bit resolution SAR architecture
Same digital interface as in the SPC560P family
A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16
channels)
–
One channel dedicated to each T-sensor to enable temperature reading during
application
–
–
–
–
Separated reference for each ADC
Shared analog supply voltage for both ADCs
One sample and hold unit per ADC
Adjustable sampling and conversion time
Digital part:
4 analog watchdogs comparing ADC results against predefined levels (low, high,
●
range) before results are stored in the appropriate ADC result location
2 modes of operation: CPU Mode or CTU Mode
CPU mode features
●
●
–
–
Register based interface with the CPU: one result register per channel
ADC state machine managing three request flows: regular command, hardware
injected command, software injected command
–
–
Selectable priority between software and hardware injected commands
4 analog watchdogs comparing ADC results against predefined levels (low, high,
range)
–
DMA compatible interface
●
CTU mode features
–
–
–
–
–
Triggered mode only
4 independent result queues (1 × 16 entries, 2 × 8 entries, 1 × 4 entries)
Result alignment circuitry (left justified; right justified)
32-bit read mode allows to have channel ID on one of the 16-bit parts
DMA compatible interfaces
●
Built-in self-test features triggered by software
1.5.34
Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on
user selected conditions without CPU load during the PWM period and with minimized CPU
load for dynamic configuration.
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Introduction
The CTU implements the following features:
●
Cross triggering between ADC, FlexPWM, eTimer, and external pins
●
Double buffered trigger generation unit with as many as 8 independent triggers
generated from external triggers
●
●
●
●
Maximum operating frequency less than or equal to 120 MHz
Trigger generation unit configurable in sequential mode or in triggered mode
Trigger delay unit to compensate the delay of external low pass filter
Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
●
●
●
●
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with as many as 24 ADC commands
Each trigger capable of generating consecutive commands
ADC conversion command allows control of ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
●
DMA support with safety features
1.5.35
Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on
data written to its input register.
The CRC unit has the following features:
●
●
3 sets of registers to allow 3 concurrent contexts with possibly different CRC
computations, each with a selectable polynomial and seed
Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores
result in internal register.
The following standard CRC polynomials are implemented:
8
4
3
2
–
–
–
x + x + x + x + 1 [8-bit CRC]
16
12
5
x
+ x + x + 1 [16-bit CRC-CCITT]
32
26
23
22
16
12
11
10
8
7
5
4
2
x
+ x + x + x + x + x + x + x + x + x + x + x + x + x + 1
[32-bit CRC-ethernet(32)]
●
●
Key engine to be coupled with communication periphery where CRC application is
added to allow implementation of safe communication protocol
Offloads core from cycle-consuming CRC and helps checking configuration signature
for safe start-up or periodic procedures
●
●
CRC unit connected as peripheral bus on internal peripheral bus
DMA support
1.5.36
Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals).
It has the following features:
●
Duplicated module to guarantee highest possible diagnostic coverage (check of
checker)
●
Multiple times replicated IPs are used as checkers on the SoR outputs
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Introduction
SPC56XL60/54
1.5.37
Junction temperature sensor
The junction temperature sensor provides a value via an ADC channel that can be used by
software to calculate the device junction temperature.
The key parameters of the junction temperature sensor include:
●
Nominal temperature range from –40 to 150 °C
●
Software temperature alarm via analog ADC comparator possible
1.5.38
Nexus Port Controller (NPC)
The NPC module provides real-time development support capabilities for this device in
compliance with the IEEE-ISTO 5001-2003. This development support is supplied for MCUs
without requiring external address and data pins for internal visibility.
The NPC block interfaces to the host processor and internal buses to provide development
support as per the IEEE-ISTO 5001-2003 Class 3+, including selected features from Class
4 standard.
The development support provided includes program trace, data trace, watchpoint trace,
ownership trace, run-time access to the MCUs internal memory map and access to the
Power Architecture internal registers during halt. The Nexus interface also supports a JTAG
only mode using only the JTAG pins. The following features are implemented:
●
●
●
●
●
Full and reduced port modes
MCKO (message clock out) pin
4 or 12 MDO (message data out) pins
2 MSEO (message start/end out) pins
EVTO (event out) pin
(b)
–
Auxiliary input port
EVTI (event in) pin
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
Supports JTAG mode
Host processor (e200) development support features
●
●
–
●
–
Data trace via data write messaging (DWM) and data read messaging (DRM).
This allows the development tool to trace reads or writes, or both, to selected
internal memory resources.
–
Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership
trace by providing visibility of which process ID or operating system task is
activated. An ownership trace message is transmitted when a new process/task is
activated, allowing development tools to trace ownership flow.
–
Program trace via branch trace messaging (BTM). Branch trace messaging
displays program flow discontinuities (direct branches, indirect branches,
exceptions, etc.), allowing the development tool to interpolate what transpires
between the discontinuities. Thus, static code may be traced.
b. 4 MDO pins on LQFP144 package, 12 MDO pins on LFBGA257 package.
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–
–
–
Watchpoint messaging (WPM) via the auxiliary port
Watchpoint trigger enable of program and/or data trace messaging
Data tracing of instruction fetches via private opcodes
1.5.39
IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. All data input to and output
from the JTAGC block is communicated in serial format. The JTAGC block is compliant with
the IEEE standard.
The JTAG controller provides the following features:
●
IEEE Test Access Port (TAP) interface with 5 pins:
–
–
–
–
–
TDI
TMS
TCK
TDO
JCOMP
●
●
Selectable modes of operation include JTAGC/debug or normal system operation
5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
–
–
–
–
–
BYPASS
IDCODE
EXTEST
SAMPLE
SAMPLE/PRELOAD
●
●
3 test data registers: a bypass register, a boundary scan register, and a device
identification register. The size of the boundary scan register is parameterized to
support a variety of boundary scan chain lengths.
TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
1.5.40
Voltage regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the following features:
●
Single external rail required
●
Single high supply required: nominal 3.3 V both for packaged and Known Good Die
option
–
Packaged option requires external ballast transistor due to reduced dissipation
capacity at high temperature but can use embedded transistor if power dissipation
is maintained within package dissipation capacity (lower frequency of operation)
–
Known Good Die option uses embedded ballast transistor as dissipation capacity
is increased to reduce system cost
●
●
All I/Os are at same voltage as external supply (3.3 V nominal)
Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages
(reset, configuration, normal operation) and, to maximize safety coverage, one LVD can
be tested while the other operates (on-line self-testing feature)
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1.5.41
Built-In Self-Test (BIST) capability
This device includes the following protection against latent faults:
●
Boot-time Memory Built-In Self-Test (MBIST)
Boot-time scan-based Logic Built-In Self-Test (LBIST)
Run-time ADC Built-In Self-Test (BIST)
●
●
●
Run-time Built-In Self Test of LVDs
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Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
Figure 2 shows the LQFP100 pinout.
75
NMI
1
A[4]
74
A[6]
2
VPP_TEST
D[14]
73
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
3
72
C[14]
4
71
C[13]
5
70
D[12]
6
69
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
7
68
8
67
9
66 VSS_LV_COR
VDD_HV_REG_0
VSS_LV_COR
10
11
65 VDD_LV_COR
64 A[3]
VDD_LV_COR 12
VDD_HV_IO 13
VSS_HV_IO 14
D[9] 15
LQFP100 package
63 VDD_HV_IO
62 VSS_HV_IO
B[4]
61
TCK
60
VDD_HV_OSC 16
VSS_HV_OSC 17
TMS
59
B[5]
58
18
19
20
21
22
23
24
25
XTAL
EXTAL
RESET
D[8]
D[5]
A[2]
57
C[12]
56
C[11]
D[11]
D[10]
A[1]
55
54
53
D[6]
52
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
A[0]
51
Figure 2.
LQFP100 pinout
Figure 3 shows the SPC56XL60/54 in the LQFP144 package.
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Package pinouts and signal descriptions
SPC56XL60/54
NMI
A[6]
D[1]
F[4]
1
2
3
4
5
6
7
8
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
108
107
106
105
104
103
102
101
100
F[5]
VDD_HV_IO
VSS_HV_IO
F[6]
MDO0
9
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
99
D[12]
G[6]
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
LQFP144 package
F[8]
VDD_HV_IO
VSS_HV_IO
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[10]
G[11]
A[1]
A[0]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
Figure 3.
SPC56XL60/54 LQFP144 pinout (top view)
Figure 4 shows the SPC56XL60/54 in the LFBGA257 package.
34/160
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
V
V
V
V
V
H[2]
V
V
V
V
SS_HV
_IO
SS_HV
_IO
DD_HV
_IO
DD_HV
_IO
SS_HV
_IO
SS_HV
_IO
A
B
C
D
E
F
H[0]
G[14]
D[3]
C[15]
A[12]
H[10]
H[14]
A[10]
B[2]
C[10]
A[14]
V
V
SS_HV
_IO
SS_HV
_IO
SS_HV
_IO
DD_HV
_IO
SS_HV
_IO
B[6]
F[3]
D[2]
A[9]
D[4]
D[0]
H[12]
E[15]
E[14]
I[1]
B[3]
F[14]
F[15]
F[13]
B[1]
B[0]
V
V
FCCU_
F[1]
V
V
V
DD_HV
_IO
(1)
SS_HV
_IO
DD_HV
DD_HV
SS_HV
_IO
NC
A[13]
I[0]
JCOMP H[11]
A[4]
F[12]
G[3]
I[3]
_REG_2
_REG_2
V
V
V
V
V
V
PP
SS_LV_
COR
DD_LV_
COR
DD_HV
_IO
SS_HV
_IO
DD_HV
_IO
F[5]
F[4]
F[6]
G[12]
A[15]
D[1]
A[7]
C[5]
C[4]
C[6]
NMI
A[8]
A[6]
A[5]
F[0]
A[11]
NC
E[13]
D[14]
G[2]
I[2]
_TEST
MDO0
H[1]
NC
NC
C[14]
V
V
V
V
V
V
V
V
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
C[13]
H[13]
G[4]
G[6]
H[6]
H[15]
A[3]
B[4]
H[5]
G[5]
G[7]
G[9]
V
V
V
V
V
V
V
DD_HV
_IO
DD_LV_
COR
SS_LV_
COR
SS_LV_
COR
SS_LV_
COR
SS_LV_
COR
SS_LV_
COR
DD_LV_
COR
G
H
J
H[3]
D[12]
H[9]
V
V
V
SS_HV
_IO
DD_HV
DD_HV
_FLA
G[13]
F[7]
V
V
V
V
V
V
V
V
SS_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
_REG_1
V
V
V
V
DD_HV
DD_HV
DD_HV
SS_HV
_FLA
G[15]
F[8]
V
V
V
V
V
V
V
V
V
V
DD_LV
_REG_0
_REG_0
_REG_1
K
L
F[9]
C[7]
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
H[8]
H[7]
H[4]
F[10]
F[11]
D[9]
D[8]
D[5]
D[6]
NC
NC
NC
TCK
B[5]
V
V
DD_HV
_OSC
DD_HV
_IO
M
N
P
R
T
V
V
V
V
V
C[11]
NC
TMS
A[2]
V
V
SS_HV
_IO
SS_LV_
PLL
XTAL
C[12]
G[10]
V
V
V
V
V
V
V
V
V
SS_HV
_OSC
DD_LV_
PLL
DD_LV_
COR
SS_LV_
COR
SS_HV
_IO
DD_HV
_IO
DD_LV_
COR
SS_LV_
COR
DD_HV
_IO
RESET
B[8]
NC
B[14]
B[15]
E[10]
G[8]
D[11]
FCCU
_F[0]
V
V
V
V
SS_HV
_IO
DD_HV
DD_HV
SS_HV
_IO
EXTAL
D[7]
C[1]
B[7]
E[5]
E[6]
E[7]
B[10]
B[11]
B[13]
E[9]
C[0]
BCTRL
E[0]
A[1]
_ADR0
_ADR1
V
V
V
V
V
V
SS_HV
_IO
DD_HV
_IO
SS_HV
_ADR0
SS_HV
_ADR1
DD_HV
_IO
SS_HV
_IO
NC
E[12]
A[0]
D[10]
V
V
V
V
V
V
V
SS_HV
_IO
SS_HV
_IO
DD_HV
_ADV
SS_HV
_ADV
DD_HV
SS_HV
_IO
SS_HV
_IO
U
E[4]
4
C[2]
5
E[2]
6
B[9]
B[12]
8
E[11]
11
NC
12
NC
13
G[11]
15
NC
3
_PMU
1
2
7
9
10
14
16
17
1. NC = Not connected (the pin is physically not connected to anything on the device)
Figure 4.
SPC56XL60/54 LFBGA257 pinout (top view)
Table 3 (LQFP100 pin function summary), Table 4, and Table 5 provide the pin function
summaries for the 100-pin, 144-pin, and 257-pin packages, respectively, listing all the
signals multiplexed to each pin.
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 3.
Pin #
LQFP100 pin function summary
Port/function
Peripheral
Output function
1
NMI
—
GPIO[6]
SCK
SIUL
DSPI_1
SIUL
GPIO[6]
SCK
2
A[6]
D[1]
A[7]
—
EIRQ[6]
GPIO[49]
ETC[2]
—
SIUL
GPIO[49]
ETC[2]
EXT_TGR
—
eTimer_1
CTU_0
FlexRay
SIUL
3
4
CA_RX
GPIO[7]
—
GPIO[7]
SOUT
—
DSPI_1
SIUL
EIRQ[7]
GPIO[36]
CS0
SIUL
GPIO[36]
CS0
DSPI_0
FlexPWM_0
SSCM
SIUL
5
6
7
C[4]
A[8]
C[5]
X[1]
X[1]
DEBUG[4]
—
—
EIRQ[22]
GPIO[8]
SIN
SIUL
GPIO[8]
—
DSPI_1
SIUL
—
EIRQ[8]
GPIO[37]
SCK
SIUL
GPIO[37]
SCK
DSPI_0
SSCM
FlexPWM_0
SIUL
DEBUG[5]
—
—
FAULT[3]
EIRQ[23]
GPIO[5]
CS0
—
SIUL
GPIO[5]
CS0
DSPI_1
eTimer_1
DSPI_0
SIUL
8
9
A[5]
C[7]
ETC[5]
CS7
ETC[5]
—
—
EIRQ[5]
GPIO[39]
A[1]
SIUL
GPIO[39]
A[1]
FlexPWM_0
SSCM
DSPI_0
DEBUG[7]
—
—
SIN
10
11
VDD_HV_REG_0
VSS_LV_COR
—
—
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Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
Table 3.
LQFP100 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
12
13
14
VDD_LV_COR
VDD_HV_IO
VSS_HV_IO
—
—
—
SIUL
GPIO[57]
GPIO[57]
X[0]
15
D[9]
FlexPWM_0
LINFlexD_1
X[0]
TXD
—
16
17
18
19
20
VDD_HV_OSC
VSS_HV_OSC
XTAL
—
—
—
EXTAL
—
RESET
—
GPIO[56]
CS2
SIUL
DSPI_1
GPIO[56]
—
21
D[8]
eTimer_1
DSPI_0
ETC[4]
CS5
ETC[4]
—
FlexPWM_0
SIUL
—
FAULT[3]
GPIO[53]
—
GPIO[53]
CS3
22
23
D[5]
D[6]
DSPI_0
FlexPWM_0
SIUL
—
FAULT[2]
GPIO[54]
—
GPIO[54]
CS2
DSPI_0
FlexPWM_0
FlexPWM_0
X[3]
X[3]
—
FAULT[1]
24
25
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
—
—
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
CS3
GPIO[55]
—
—
26
D[7]
CS4
Analog output
F[0]
—
27
28
29
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
FCCU
F[0]
—
—
SIUL
LINFlexD_0
ADC_0
—
GPIO[23]
RXD
30
B[7]
—
—
AN[0]
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 3.
Pin #
LQFP100 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
eTimer_0
ADC_0
SIUL
—
—
—
—
—
—
—
—
GPIO[24]
ETC[5]
AN[1]
31
B[8]
GPIO[66]
AN[5]
32
E[2]
ADC_0
33
34
VDD_HV_ADR0
VSS_HV_ADR0
SIUL
ADC_0
ADC_1
SIUL
GPIO[25]
AN[11]
35
36
37
38
B[9]
B[10]
B[11]
B[12]
—
—
—
—
—
—
—
GPIO[26]
AN[12]
ADC_0
ADC_1
SIUL
GPIO[27]
AN[13]
ADC_0
ADC_1
SIUL
GPIO[28]
AN[14]
ADC_0
ADC_1
39
40
41
42
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIUL
LINFlexD_1
ADC_1
SIUL
GPIO[29]
RXD
43
B[13]
AN[0]
GPIO[30]
ETC[4]
EIRQ[19]
AN[1]
eTimer_0
SIUL
44
45
B[14]
C[0]
ADC_1
SIUL
GPIO[32]
AN[3]
ADC_1
SIUL
GPIO[64]
AN[5]
46
47
E[0]
ADC_1
BCTRL
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Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
Table 3.
LQFP100 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
48
49
50
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
—
—
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[0]
ETC[0]
SCK
GPIO[0]
ETC[0]
SCK
51
52
A[0]
A[1]
—
EIRQ[0]
GPIO[1]
ETC[1]
—
SIUL
GPIO[1]
ETC[1]
SOUT
—
eTimer_0
DSPI_2
SIUL
EIRQ[1]
GPIO[58]
A[0]
SIUL
GPIO[58]
A[0]
53
54
55
56
D[10]
D[11]
C[11]
C[12]
FlexPWM_0
eTimer_0
SIUL
—
ETC[0]
GPIO[59]
B[0]
GPIO[59]
B[0]
FlexPWM_0
eTimer_0
SIUL
—
ETC[1]
GPIO[43]
ETC[4]
—
GPIO[43]
ETC[4]
CS2
eTimer_0
DSPI_2
SIUL
GPIO[44]
ETC[5]
CS3
GPIO[44]
ETC[5]
—
eTimer_0
DSPI_2
SIUL
GPIO[2]
ETC[2]
A[3]
GPIO[2]
ETC[2]
A[3]
eTimer_0
FlexPWM_0
DSPI_2
MC_RGM
SIUL
57
58
A[2]
B[5]
—
SIN
—
ABS[0]
EIRQ[2]
GPIO[21]
TDI
—
SIUL
GPIO[21]
—
JTAGC
59
60
TMS
TCK
—
—
SIUL
GPIO[20]
TDO
GPIO[20]
—
61
B[4]
JTAGC
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 3.
Pin #
LQFP100 pin function summary (continued)
Port/function
Peripheral
Output function
62
63
VSS_HV_IO
VDD_HV_IO
—
—
SIUL
eTimer_0
DSPI_2
GPIO[3]
ETC[3]
CS0
GPIO[3]
ETC[3]
CS0
64
A[3]
FlexPWM_0
MC_RGM
SIUL
B[3]
B[3]
—
ABS[2]
EIRQ[3]
—
65
66
67
68
69
VDD_LV_COR
VSS_LV_COR
VDD_HV_REG_1
VSS_HV_FLA
VDD_HV_FLA
—
—
—
—
—
SIUL
FlexPWM_0
LINFlexD_1
SIUL
GPIO[60]
X[1]
GPIO[60]
X[1]
70
71
72
D[12]
—
RXD
GPIO[45]
ETC[1]
—
GPIO[45]
ETC[1]
EXT_IN
EXT_SYNC
GPIO[46]
ETC[2]
—
eTimer_1
CTU_0
C[13]
FlexPWM_0
SIUL
—
GPIO[46]
ETC[2]
EXT_TGR
GPIO[62]
B[1]
C[14]
D[14]
eTimer_1
CTU_0
SIUL
GPIO[62]
B[1]
73
74
FlexPWM_0
eTimer_0
—
ETC[3]
(1)
VPP_TEST
—
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
GPIO[4]
ETC[0]
CS1
GPIO[4]
ETC[0]
—
75
A[4]
ETC[4]
—
ETC[4]
FAB
—
EIRQ[4]
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Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 3.
LQFP100 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
FlexCAN_0
eTimer_1
SSCM
GPIO[16]
TXD
GPIO[16]
—
76
B[0]
ETC[2]
DEBUG[0]
—
ETC[2]
—
SIUL
EIRQ[15]
GPIO[17]
ETC[3]
—
SIUL
GPIO[17]
ETC[3]
DEBUG[1]
—
eTimer_1
SSCM
77
78
B[1]
FlexCAN_0
FlexCAN_1
SIUL
RXD
—
RXD
—
EIRQ[16]
GPIO[42]
—
SIUL
GPIO[42]
CS2
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
C[10]
A[3]
A[3]
—
FAULT[1]
GPIO[18]
—
GPIO[18]
TXD
LINFlexD_0
SSCM
79
80
B[2]
B[3]
DEBUG[2]
—
DEBUG[2]
EIRQ[17]
GPIO[19]
DEBUG[3]
RXD
SIUL
SIUL
GPIO[19]
DEBUG[3]
—
SSCM
LINFlexD_0
SIUL
GPIO[10]
CS0
GPIO[10]
CS0
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
81
82
A[10]
A[11]
B[0]
B[0]
X[2]
X[2]
—
EIRQ[9]
GPIO[11]
SCK
SIUL
GPIO[11]
SCK
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
A[0]
A[0]
A[2]
A[2]
—
EIRQ[10]
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 3.
Pin #
LQFP100 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
DSPI_2
GPIO[12]
SOUT
A[2]
GPIO[12]
—
83
84
A[12]
FlexPWM_0
FlexPWM_0
SIUL
A[2]
B[2]
B[2]
—
EIRQ[11]
JCOMP
GPIO[47]
—
JCOMP
—
—
SIUL
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
FlexRay
eTimer_1
FlexPWM_0
CTU_0
ETC[0]
A[1]
85
C[15]
—
EXT_IN
EXT_SYNC
GPIO[48]
—
FlexPWM_0
SIUL
—
GPIO[48]
CA_TX
ETC[1]
B[1]
FlexRay
eTimer_1
FlexPWM_0
86
D[0]
ETC[1]
B[1]
87
88
VDD_HV_IO
VSS_HV_IO
—
—
SIUL
FlexRay
GPIO[51]
CB_TX
ETC[4]
A[3]
GPIO[51]
—
89
90
D[3]
D[4]
eTimer_1
FlexPWM_0
SIUL
ETC[4]
A[3]
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
GPIO[52]
—
FlexRay
eTimer_1
FlexPWM_0
ETC[5]
B[3]
91
92
93
VDD_HV_REG_2
VDD_LV_COR
VSS_LV_COR
—
—
—
SIUL
GPIO[9]
CS1
GPIO[9]
—
DSPI_2
94
A[9]
FlexPWM_0
FlexPWM_0
B[3]
B[3]
—
FAULT[0]
42/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 3.
LQFP100 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
FlexPWM_0
DSPI_2
FlexPWM_0
SIUL
GPIO[13]
B[2]
GPIO[13]
B[2]
95
A[13]
—
SIN
—
FAULT[0]
EIRQ[12]
GPIO[22]
—
—
SIUL
GPIO[22]
clk_out
CS2
MC_CGM
DSPI_2
SIUL
96
97
B[6]
—
—
EIRQ[18]
F[1]
FCCU_F[1]
FCCU
F[1]
SIUL
GPIO[38]
SOUT
B[1]
GPIO[38]
—
DSPI_0
FlexPWM_0
SSCM
98
99
C[6]
A[14]
A[15]
B[1]
DEBUG[6]
—
—
SIUL
EIRQ[24]
GPIO[14]
—
SIUL
GPIO[14]
TXD
FlexCAN_1
eTimer_1
SIUL
ETC[4]
—
ETC[4]
EIRQ[13]
GPIO[15]
ETC[5]
RXD
SIUL
GPIO[15]
ETC[5]
—
eTimer_1
FlexCAN_1
FlexCAN_0
SIUL
100
—
RXD
—
EIRQ[14]
1. VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4.
Pin #
LQFP144 pin function summary
Port/function
Peripheral
Output function
Input function
1
NMI
—
GPIO[6]
SCK
—
SIUL
DSPI_1
SIUL
GPIO[6]
SCK
2
A[6]
EIRQ[6]
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 4.
Pin #
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
eTimer_1
CTU_0
FlexRay
SIUL
GPIO[49]
ETC[2]
EXT_TGR
—
GPIO[49]
ETC[2]
—
3
D[1]
CA_RX
GPIO[84]
—
GPIO[84]
MDO[3]
GPIO[85]
MDO[2]
—
4
5
F[4]
F[5]
NPC
SIUL
GPIO[85]
—
NPC
6
7
VDD_HV_IO
VSS_HV_IO
—
SIUL
NPC
GPIO[86]
MDO[1]
—
GPIO[86]
—
8
9
F[6]
MDO0
SIUL
DSPI_1
SIUL
GPIO[7]
SOUT
—
GPIO[7]
—
10
11
12
13
A[7]
C[4]
A[8]
C[5]
EIRQ[7]
GPIO[36]
CS0
SIUL
GPIO[36]
CS0
DSPI_0
FlexPWM_0
SSCM
SIUL
X[1]
X[1]
DEBUG[4]
—
—
EIRQ[22]
GPIO[8]
SIN
SIUL
GPIO[8]
—
DSPI_1
SIUL
—
EIRQ[8]
GPIO[37]
SCK
SIUL
GPIO[37]
SCK
DSPI_0
SSCM
FlexPWM_0
SIUL
DEBUG[5]
—
—
FAULT[3]
EIRQ[23]
GPIO[5]
CS0
—
SIUL
GPIO[5]
CS0
DSPI_1
eTimer_1
DSPI_0
SIUL
14
A[5]
ETC[5]
CS7
ETC[5]
—
—
EIRQ[5]
44/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
LQFP144 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
FlexPWM_0
SSCM
GPIO[39]
A[1]
GPIO[39]
A[1]
15
C[7]
DEBUG[7]
—
—
DSPI_0
SIN
16
17
18
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
—
—
—
SIUL
NPC
SIUL
NPC
GPIO[87]
MCKO
GPIO[88]
MSEO[1]
—
GPIO[87]
—
19
20
F[7]
F[8]
GPIO[88]
—
21
22
VDD_HV_IO
VSS_HV_IO
—
SIUL
NPC
GPIO[89]
MSEO[0]
GPIO[90]
EVTO
GPIO[91]
—
GPIO[89]
—
23
24
25
F[9]
F[10]
F[11]
SIUL
GPIO[90]
—
NPC
SIUL
GPIO[91]
EVTI
NPC
SIUL
GPIO[57]
X[0]
GPIO[57]
X[0]
26
D[9]
FlexPWM_0
LINFlexD_1
TXD
—
27
28
29
30
31
VDD_HV_OSC
VSS_HV_OSC
XTAL
—
—
—
EXTAL
—
RESET
—
SIUL
DSPI_1
GPIO[56]
CS2
GPIO[56]
—
32
33
D[8]
D[5]
eTimer_1
DSPI_0
ETC[4]
CS5
ETC[4]
—
FlexPWM_0
SIUL
—
FAULT[3]
GPIO[53]
—
GPIO[53]
CS3
DSPI_0
FlexPWM_0
—
FAULT[2]
Doc ID 15457 Rev 8
45/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 4.
Pin #
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
GPIO[54]
GPIO[54]
—
DSPI_0
CS2
34
D[6]
FlexPWM_0
FlexPWM_0
X[3]
X[3]
—
FAULT[1]
35
36
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
—
—
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
GPIO[55]
CS3
—
—
37
D[7]
CS4
analog output
—
38
39
40
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
FCCU
F[0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F[0]
SIUL
ADC_0
SIUL
GPIO[33]
AN[2]
41
42
C[1]
E[4]
GPIO[68]
AN[7]
ADC_0
SIUL
GPIO[23]
RXD
43
B[7]
LINFlexD_0
ADC_0
SIUL
AN[0]
GPIO[69]
AN[8]
44
45
46
E[5]
C[2]
E[6]
ADC_0
SIUL
GPIO[34]
AN[3]
ADC_0
SIUL
GPIO[70]
AN[4]
ADC_0
SIUL
GPIO[24]
ETC[5]
AN[1]
47
B[8]
eTimer_0
ADC_0
SIUL
GPIO[71]
AN[6]
48
49
E[7]
E[2]
ADC_0
SIUL
GPIO[66]
AN[5]
ADC_0
50
51
VDD_HV_ADR0
VSS_HV_ADR0
46/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
LQFP144 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
—
GPIO[25]
52
B[9]
ADC_0
ADC_1
—
—
—
—
—
—
—
AN[11]
GPIO[26]
AN[12]
SIUL
53
54
55
B[10]
B[11]
B[12]
ADC_0
ADC_1
SIUL
GPIO[27]
AN[13]
ADC_0
ADC_1
SIUL
GPIO[28]
AN[14]
ADC_0
ADC_1
56
57
58
59
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIUL
LINFlexD_1
ADC_1
SIUL
GPIO[29]
RXD
60
61
62
63
B[13]
E[9]
AN[0]
GPIO[73]
AN[7]
ADC_1
SIUL
GPIO[31]
EIRQ[20]
AN[2]
B[15]
E[10]
SIUL
ADC_1
SIUL
GPIO[74]
AN[8]
ADC_1
SIUL
GPIO[30]
ETC[4]
EIRQ[19]
AN[1]
eTimer_0
SIUL
64
B[14]
ADC_1
SIUL
GPIO[75]
AN[4]
65
66
67
E[11]
C[0]
ADC_1
SIUL
GPIO[32]
AN[3]
ADC_1
SIUL
GPIO[76]
AN[6]
E[12]
ADC_1
Doc ID 15457 Rev 8
47/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 4.
Pin #
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
—
—
GPIO[64]
AN[5]
68
E[0]
ADC_1
69
70
71
72
BCTRL
—
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
—
—
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[0]
ETC[0]
SCK
GPIO[0]
ETC[0]
SCK
73
74
A[0]
A[1]
—
EIRQ[0]
GPIO[1]
ETC[1]
—
SIUL
GPIO[1]
ETC[1]
SOUT
—
eTimer_0
DSPI_2
SIUL
EIRQ[1]
GPIO[107]
—
SIUL
GPIO[107]
DBG3
—
75
76
G[11]
D[10]
FlexRay
FlexPWM_0
SIUL
FAULT[3]
GPIO[58]
A[0]
GPIO[58]
A[0]
FlexPWM_0
eTimer_0
SIUL
—
ETC[0]
GPIO[106]
—
GPIO[106]
DBG2
CS3
FlexRay
DSPI_2
FlexPWM_0
SIUL
77
78
G[10]
D[11]
—
—
FAULT[2]
GPIO[59]
B[0]
GPIO[59]
B[0]
FlexPWM_0
eTimer_0
SIUL
—
ETC[1]
GPIO[105]
—
GPIO[105]
DBG1
CS1
FlexRay
DSPI_1
FlexPWM_0
SIUL
79
80
G[9]
—
—
FAULT[1]
EIRQ[29]
GPIO[43]
ETC[4]
—
—
SIUL
GPIO[43]
ETC[4]
CS2
C[11]
eTimer_0
DSPI_2
48/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
LQFP144 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
FlexRay
DSPI_0
FlexPWM_0
SIUL
GPIO[104]
DBG0
CS1
GPIO[104]
—
81
G[8]
—
—
FAULT[0]
EIRQ[21]
GPIO[44]
ETC[5]
—
—
SIUL
GPIO[44]
ETC[5]
CS3
82
83
C[12]
G[7]
eTimer_0
DSPI_2
SIUL
GPIO[103]
B[3]
GPIO[103]
B[3]
FlexPWM_0
SIUL
GPIO[2]
ETC[2]
A[3]
GPIO[2]
ETC[2]
A[3]
eTimer_0
FlexPWM_0
DSPI_2
MC_RGM
SIUL
84
A[2]
—
SIN
—
ABS[0]
EIRQ[2]
GPIO[101]
X[3]
—
SIUL
GPIO[101]
X[3]
85
86
G[5]
B[5]
FlexPWM_0
DSPI_2
SIUL
CS3
—
GPIO[21]
—
GPIO[21]
TDI
JTAGC
87
88
TMS
TCK
—
—
SIUL
GPIO[20]
TDO
—
GPIO[20]
—
89
B[4]
JTAGC
90
91
VSS_HV_IO
VDD_HV_IO
—
SIUL
eTimer_0
DSPI_2
GPIO[3]
ETC[3]
CS0
GPIO[3]
ETC[3]
CS0
92
A[3]
FlexPWM_0
MC_RGM
SIUL
B[3]
B[3]
—
ABS[2]
EIRQ[3]
—
93
94
VDD_LV_COR
VSS_LV_COR
—
—
Doc ID 15457 Rev 8
49/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 4.
Pin #
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
95
96
97
VDD_HV_REG_1
VSS_HV_FLA
VDD_HV_FLA
—
—
—
SIUL
FlexPWM_0
SIUL
GPIO[102]
A[3]
GPIO[102]
A[3]
98
G[6]
GPIO[60]
X[1]
GPIO[60]
X[1]
99
D[12]
FlexPWM_0
LINFlexD_1
SIUL
—
RXD
GPIO[100]
B[2]
GPIO[100]
B[2]
100
101
G[4]
FlexPWM_0
eTimer_0
SIUL
—
ETC[5]
GPIO[45]
ETC[1]
EXT_IN
EXT_SYNC
GPIO[98]
X[2]
GPIO[45]
ETC[1]
—
eTimer_1
CTU_0
C[13]
FlexPWM_0
SIUL
—
GPIO[98]
X[2]
102
103
104
105
G[2]
C[14]
G[3]
FlexPWM_0
DSPI_1
SIUL
CS1
—
GPIO[46]
ETC[2]
EXT_TGR
GPIO[99]
A[2]
GPIO[46]
ETC[2]
—
eTimer_1
CTU_0
SIUL
GPIO[99]
A[2]
FlexPWM_0
eTimer_0
SIUL
—
ETC[4]
GPIO[62]
B[1]
GPIO[62]
B[1]
D[14]
F[12]
FlexPWM_0
eTimer_0
SIUL
—
ETC[3]
GPIO[92]
ETC[3]
EIRQ[30]
GPIO[92]
ETC[3]
—
106
107
eTimer_1
SIUL
(1)
VPP_TEST
—
50/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
LQFP144 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
GPIO[4]
ETC[0]
CS1
GPIO[4]
ETC[0]
—
108
A[4]
ETC[4]
—
ETC[4]
FAB
—
EIRQ[4]
GPIO[16]
—
SIUL
GPIO[16]
TXD
FlexCAN_0
eTimer_1
SSCM
109
B[0]
ETC[2]
DEBUG[0]
—
ETC[2]
—
SIUL
EIRQ[15]
GPIO[17]
ETC[3]
—
SIUL
GPIO[17]
ETC[3]
DEBUG[1]
—
eTimer_1
SSCM
110
111
B[1]
FlexCAN_0
FlexCAN_1
SIUL
RXD
—
RXD
—
EIRQ[16]
GPIO[42]
—
SIUL
GPIO[42]
CS2
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
C[10]
A[3]
A[3]
—
FAULT[1]
GPIO[93]
ETC[4]
EIRQ[31]
GPIO[95]
RXD
GPIO[93]
ETC[4]
—
112
113
F[13]
F[15]
eTimer_1
SIUL
SIUL
GPIO[95]
—
LINFlexD_1
SIUL
GPIO[18]
TXD
GPIO[18]
—
LINFlexD_0
SSCM
114
B[2]
DEBUG[2]
—
—
SIUL
EIRQ[17]
GPIO[94]
—
SIUL
GPIO[94]
TXD
115
116
F[14]
B[3]
LINFlexD_1
SIUL
GPIO[19]
DEBUG[3]
—
GPIO[19]
—
SSCM
LINFlexD_0
RXD
Doc ID 15457 Rev 8
51/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 4.
Pin #
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[77]
ETC[5]
CS3
GPIO[77]
ETC[5]
—
117
E[13]
—
EIRQ[25]
GPIO[10]
CS0
SIUL
GPIO[10]
CS0
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
118
119
120
121
A[10]
E[14]
A[11]
E[15]
B[0]
B[0]
X[2]
X[2]
—
EIRQ[9]
GPIO[78]
ETC[5]
EIRQ[26]
GPIO[11]
SCK
SIUL
GPIO[78]
ETC[5]
—
eTimer_1
SIUL
SIUL
GPIO[11]
SCK
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
A[0]
A[0]
A[2]
A[2]
—
EIRQ[10]
GPIO[79]
—
SIUL
GPIO[79]
CS1
DSPI_0
SIUL
—
EIRQ[27]
GPIO[12]
—
SIUL
GPIO[12]
SOUT
A[2]
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
122
123
A[12]
A[2]
B[2]
B[2]
—
EIRQ[11]
JCOMP
GPIO[47]
—
JCOMP
—
—
SIUL
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
FlexRay
eTimer_1
FlexPWM_0
CTU_0
ETC[0]
A[1]
124
C[15]
—
EXT_IN
EXT_SYNC
FlexPWM_0
—
52/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
LQFP144 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[48]
CA_TX
ETC[1]
B[1]
GPIO[48]
—
FlexRay
125
D[0]
eTimer_1
FlexPWM_0
ETC[1]
B[1]
126
127
VDD_HV_IO
VSS_HV_IO
—
—
SIUL
FlexRay
GPIO[51]
CB_TX
ETC[4]
A[3]
GPIO[51]
—
128
129
D[3]
D[4]
eTimer_1
FlexPWM_0
SIUL
ETC[4]
A[3]
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
GPIO[52]
—
FlexRay
eTimer_1
FlexPWM_0
ETC[5]
B[3]
130
131
132
VDD_HV_REG_2
VDD_LV_COR
VSS_LV_COR
—
—
—
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[80]
A[1]
GPIO[80]
A[1]
133
F[0]
—
ETC[2]
EIRQ[28]
GPIO[9]
—
—
SIUL
GPIO[9]
CS1
DSPI_2
134
135
A[9]
FlexPWM_0
FlexPWM_0
B[3]
B[3]
—
FAULT[0]
VDD_LV_COR
—
SIUL
FlexPWM_0
DSPI_2
GPIO[13]
B[2]
GPIO[13]
B[2]
136
137
A[13]
—
SIN
FlexPWM_0
SIUL
—
FAULT[0]
EIRQ[12]
—
VSS_LV_COR
—
Doc ID 15457 Rev 8
53/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 4.
Pin #
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
MC_CGM
DSPI_2
SIUL
GPIO[22]
clk_out
CS2
GPIO[22]
—
138
139
B[6]
—
—
EIRQ[18]
GPIO[83]
—
SIUL
GPIO[83]
CS6
F[3]
DSPI_0
SIUL
GPIO[50]
ETC[3]
X[3]
GPIO[50]
ETC[3]
X[3]
eTimer_1
FlexPWM_0
FlexRay
FCCU
140
141
D[2]
—
CB_RX
F[1]
FCCU_F[1]
F[1]
SIUL
GPIO[38]
SOUT
B[1]
GPIO[38]
—
DSPI_0
FlexPWM_0
SSCM
142
143
144
C[6]
A[14]
A[15]
B[1]
DEBUG[6]
—
—
SIUL
EIRQ[24]
GPIO[14]
—
SIUL
GPIO[14]
TXD
FlexCAN_1
eTimer_1
SIUL
ETC[4]
—
ETC[4]
EIRQ[13]
GPIO[15]
ETC[5]
RXD
SIUL
GPIO[15]
ETC[5]
—
eTimer_1
FlexCAN_1
FlexCAN_0
SIUL
—
RXD
—
EIRQ[14]
1. VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 5.
Pin #
LFBGA257 pin function summary
Port/function
Peripheral
Output function
Input function
A1
A2
A3
VSS_HV_IO_RING
VSS_HV_IO_RING
VDD_HV_IO_RING
—
—
—
SIUL
NPC
GPIO[114]
MDO[5]
GPIO[114]
—
A4
H[2]
54/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
NPC
GPIO[112]
MDO[7]
GPIO[110]
MDO[9]
GPIO[51]
CB_TX
ETC[4]
A[3]
GPIO[112]
—
A5
H[0]
SIUL
GPIO[110]
—
A6
A7
G[14]
D[3]
NPC
SIUL
GPIO[51]
—
FlexRay
eTimer_1
FlexPWM_0
SIUL
ETC[4]
A[3]
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
GPIO[47]
—
FlexRay
eTimer_1
FlexPWM_0
CTU_0
ETC[0]
A[1]
A8
C[15]
—
EXT_IN
EXT_SYNC
FlexPWM_0
—
A9
VDD_HV_IO_RING
—
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
GPIO[12]
SOUT
A[2]
GPIO[12]
—
A10
A[12]
A[2]
B[2]
B[2]
—
EIRQ[11]
GPIO[122]
X[2]
SIUL
GPIO[122]
X[2]
A11
A12
H[10]
H[14]
FlexPWM_1
eTimer_2
SIUL
ETC[2]
GPIO[126]
A[3]
ETC[2]
GPIO[126]
A[3]
FlexPWM_1
eTimer_2
SIUL
ETC[4]
GPIO[10]
CS0
ETC[4]
GPIO[10]
CS0
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
A13
A14
A[10]
B[2]
B[0]
B[0]
X[2]
X[2]
—
EIRQ[9]
GPIO[18]
—
SIUL
GPIO[18]
TXD
LINFlexD_0
SSCM
DEBUG[2]
—
—
SIUL
EIRQ[17]
Doc ID 15457 Rev 8
55/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 5.
Pin #
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
GPIO[42]
CS2
GPIO[42]
—
DSPI_2
A15
C[10]
FlexPWM_0
FlexPWM_0
A[3]
A[3]
—
FAULT[1]
A16
A17
B1
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
—
—
—
B2
—
SIUL
MC_CGM
DSPI_2
SIUL
GPIO[22]
clk_out
CS2
GPIO[22]
—
B3
B[6]
—
—
EIRQ[18]
GPIO[14]
—
SIUL
GPIO[14]
TXD
FlexCAN_1
eTimer_1
SIUL
B4
B5
B6
A[14]
F[3]
ETC[4]
—
ETC[4]
EIRQ[13]
GPIO[83]
—
SIUL
GPIO[83]
CS6
DSPI_0
SIUL
GPIO[9]
CS1
GPIO[9]
—
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
A[9]
B[3]
B[3]
—
FAULT[0]
GPIO[52]
—
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
FlexRay
eTimer_1
FlexPWM_0
SIUL
B7
B8
D[4]
D[0]
ETC[5]
B[3]
GPIO[48]
CA_TX
ETC[1]
B[1]
GPIO[48]
—
FlexRay
eTimer_1
FlexPWM_0
ETC[1]
B[1]
B9
VSS_HV_IO_RING
H[12]
—
SIUL
GPIO[124]
B[2]
GPIO[124]
B[2]
B10
FlexPWM_1
56/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
DSPI_0
SIUL
GPIO[79]
CS1
GPIO[79]
—
B11
E[15]
—
EIRQ[27]
GPIO[78]
ETC[5]
EIRQ[26]
GPIO[19]
—
SIUL
GPIO[78]
ETC[5]
—
B12
B13
B14
E[14]
B[3]
eTimer_1
SIUL
SIUL
GPIO[19]
DEBUG[3]
—
SSCM
LINFlexD_0
SIUL
RXD
GPIO[93]
ETC[4]
—
GPIO[93]
ETC[4]
EIRQ[31]
GPIO[16]
—
F[13]
eTimer_1
SIUL
SIUL
GPIO[16]
TXD
FlexCAN_0
eTimer_1
SSCM
SIUL
B15
B[0]
ETC[2]
DEBUG[0]
—
ETC[2]
—
EIRQ[15]
B16
B17
C1
VDD_HV_IO_RING
VSS_HV_IO_RING
VDD_HV_IO_RING
Not connected
VSS_HV_IO_RING
FCCU_F[1]
—
—
—
C2
—
C3
—
C4
FCCU
SIUL
F[1]
F[1]
GPIO[50]
ETC[3]
X[3]
GPIO[50]
ETC[3]
X[3]
eTimer_1
FlexPWM_0
FlexRay
SIUL
C5
C6
D[2]
—
CB_RX
GPIO[13]
B[2]
GPIO[13]
B[2]
FlexPWM_0
DSPI_2
A[13]
—
SIN
FlexPWM_0
SIUL
—
FAULT[0]
EIRQ[12]
—
C7
C8
VDD_HV_REG_2
VDD_HV_REG_2
—
—
Doc ID 15457 Rev 8
57/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 5.
Pin #
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
eTimer_2
DSPI_0
FlexPWM_1
—
GPIO[128]
ETC[0]
CS4
GPIO[128]
ETC[0]
—
C9
I[0]
—
FAULT[0]
JCOMP
GPIO[123]
A[2]
C10
C11
JCOMP
H[11]
—
SIUL
GPIO[123]
A[2]
FlexPWM_1
SIUL
GPIO[129]
ETC[1]
CS5
GPIO[129]
ETC[1]
—
eTimer_2
DSPI_0
FlexPWM_1
SIUL
C12
C13
I[1]
—
FAULT[1]
GPIO[94]
—
GPIO[94]
TXD
F[14]
LINFlexD_1
SIUL
GPIO[17]
ETC[3]
DEBUG[1]
—
GPIO[17]
ETC[3]
—
eTimer_1
SSCM
C14
C15
C16
B[1]
VSS_HV_IO_RING
A[4]
FlexCAN_0
FlexCAN_1
SIUL
RXD
—
RXD
—
EIRQ[16]
—
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
GPIO[4]
ETC[0]
CS1
GPIO[4]
ETC[0]
—
ETC[4]
—
ETC[4]
FAB
—
EIRQ[4]
GPIO[92]
ETC[3]
EIRQ[30]
GPIO[85]
—
SIUL
GPIO[92]
ETC[3]
—
C17
F[12]
eTimer_1
SIUL
SIUL
GPIO[85]
MDO[2]
GPIO[84]
MDO[3]
D1
D2
F[5]
F[4]
NPC
SIUL
GPIO[84]
—
NPC
58/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
eTimer_1
FlexCAN_1
FlexCAN_0
SIUL
GPIO[15]
ETC[5]
—
GPIO[15]
ETC[5]
RXD
D3
A[15]
—
RXD
—
EIRQ[14]
GPIO[38]
—
SIUL
GPIO[38]
SOUT
B[1]
DSPI_0
FlexPWM_0
SSCM
D4
C[6]
B[1]
DEBUG[6]
—
—
SIUL
EIRQ[24]
D5
D6
VSS_LV_CORE_RING
VDD_LV_CORE_RING
—
—
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[80]
A[1]
GPIO[80]
A[1]
D7
F[0]
—
ETC[2]
EIRQ[28]
—
D8
D9
VDD_HV_IO_RING
VSS_HV_IO_RING
Not connected
—
—
D10
—
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
GPIO[11]
SCK
A[0]
GPIO[11]
SCK
D11
A[11]
E[13]
A[0]
A[2]
A[2]
—
EIRQ[10]
GPIO[77]
ETC[5]
—
SIUL
GPIO[77]
ETC[5]
CS3
—
eTimer_0
DSPI_2
SIUL
D12
D13
EIRQ[25]
GPIO[95]
RXD
SIUL
GPIO[95]
—
F[15]
LINFlexD_1
D14
D15
VDD_HV_IO_RING
—
(1)
VPP_TEST
—
SIUL
GPIO[62]
B[1]
GPIO[62]
B[1]
D16
D[14]
FlexPWM_0
eTimer_0
—
ETC[3]
Doc ID 15457 Rev 8
59/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 5.
Pin #
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
GPIO[99]
A[2]
GPIO[99]
A[2]
D17
G[3]
FlexPWM_0
eTimer_0
—
ETC[4]
E1
E2
MDO0
F[6]
—
SIUL
NPC
GPIO[86]
MDO[1]
GPIO[49]
ETC[2]
EXT_TGR
—
GPIO[86]
—
SIUL
GPIO[49]
ETC[2]
—
eTimer_1
CTU_0
FlexRay
E3
D[1]
CA_RX
E4
NMI
—
E14
Not connected
—
SIUL
eTimer_1
CTU_0
SIUL
GPIO[46]
ETC[2]
EXT_TGR
GPIO[98]
X[2]
GPIO[46]
ETC[2]
—
E15
E16
C[14]
G[2]
GPIO[98]
X[2]
FlexPWM_0
DSPI_1
SIUL
CS1
—
GPIO[131]
ETC[3]
CS7
GPIO[131]
ETC[3]
—
eTimer_2
DSPI_0
CTU_0
FlexPWM_1
SIUL
E17
I[3]
EXT_TGR
—
—
FAULT[3]
GPIO[113]
—
GPIO[113]
MDO[6]
GPIO[108]
MDO[11]
GPIO[7]
SOUT
—
F1
F2
H[1]
NPC
SIUL
GPIO[108]
—
G[12]
NPC
SIUL
GPIO[7]
—
F3
F4
A[7]
A[8]
DSPI_1
SIUL
EIRQ[7]
GPIO[8]
SIN
SIUL
GPIO[8]
—
DSPI_1
SIUL
—
EIRQ[8]
F6
F7
VDD_LV_CORE_RING
VDD_LV_CORE_RING
—
—
60/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
F8
F9
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
Not connected
—
—
F10
F11
F12
F14
—
—
—
—
GPIO[45]
ETC[1]
—
SIUL
eTimer_1
CTU_0
GPIO[45]
ETC[1]
F15
C[13]
EXT_IN
EXT_SYNC
GPIO[130]
ETC[2]
FlexPWM_0
SIUL
—
GPIO[130]
ETC[2]
CS6
eTimer_2
DSPI_0
FlexPWM_1
SIUL
F16
F17
I[2]
—
—
FAULT[2]
GPIO[100]
B[2]
GPIO[100]
B[2]
G[4]
FlexPWM_0
eTimer_0
SIUL
—
ETC[5]
GPIO[115]
MDO[4]
—
GPIO[115]
—
G1
G2
H[3]
NPC
VDD_HV_IO_RING
SIUL
DSPI_0
SSCM
GPIO[37]
SCK
DEBUG[5]
—
GPIO[37]
SCK
G3
C[5]
—
FlexPWM_0
SIUL
FAULT[3]
EIRQ[23]
GPIO[6]
SCK
—
SIUL
GPIO[6]
SCK
—
G4
A[6]
DSPI_1
SIUL
EIRQ[6]
G6
G7
VDD_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VDD_LV_CORE_RING
—
—
G8
—
G9
—
G10
G11
G12
—
—
—
Doc ID 15457 Rev 8
61/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 5.
Pin #
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
FlexPWM_0
LINFlexD_1
SIUL
GPIO[60]
X[1]
GPIO[60]
X[1]
G14
G15
D[12]
—
RXD
GPIO[125]
X[3]
GPIO[125]
X[3]
H[13]
FlexPWM_1
eTimer_2
SIUL
ETC[3]
GPIO[121]
B[1]
ETC[3]
GPIO[121]
B[1]
G16
G17
H[9]
G[6]
FlexPWM_1
DSPI_0
SIUL
CS7
—
GPIO[102]
A[3]
GPIO[102]
A[3]
FlexPWM_0
SIUL
GPIO[109]
MDO[10]
—
GPIO[109]
—
H1
H2
G[13]
NPC
VSS_HV_IO_RING
SIUL
DSPI_0
FlexPWM_0
SSCM
GPIO[36]
CS0
GPIO[36]
CS0
H3
H4
C[4]
A[5]
X[1]
X[1]
DEBUG[4]
—
—
SIUL
EIRQ[22]
GPIO[5]
CS0
SIUL
GPIO[5]
CS0
DSPI_1
eTimer_1
DSPI_0
SIUL
ETC[5]
CS7
ETC[5]
—
—
EIRQ[5]
H6
H7
VDD_LV
VSS_LV
—
—
H8
VSS_LV
—
H9
VSS_LV
—
H10
H11
H12
H14
H15
H16
VSS_LV
—
VSS_LV
—
VDD_LV
—
VSS_LV
—
VDD_HV_REG_1
VDD_HV_FLA
—
—
62/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
FlexPWM_1
DSPI_0
SIUL
GPIO[118]
B[0]
GPIO[118]
B[0]
H17
H[6]
CS5
—
GPIO[87]
MCKO
GPIO[111]
MDO[8]
—
GPIO[87]
—
J1
J2
F[7]
NPC
SIUL
GPIO[111]
—
G[15]
NPC
J3
J4
VDD_HV_REG_0
VDD_HV_REG_0
VDD_LV
—
J6
—
J7
VSS_LV
—
J8
VSS_LV
—
J9
VSS_LV
—
J10
J11
J12
J14
J15
J16
VSS_LV
—
VSS_LV
—
VDD_LV
—
VDD_LV
—
VDD_HV_REG_1
VSS_HV_FLA
—
—
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[127]
B[3]
GPIO[127]
B[3]
J17
K1
H[15]
ETC[5]
GPIO[89]
MSEO[0]
GPIO[88]
MSEO[1]
RDY
ETC[5]
GPIO[89]
—
F[9]
F[8]
RDY
NPC
SIUL
GPIO[88]
—
K2
K3
NPC
NPC
—
SIUL
GPIO[132]
GPIO[39]
A[1]
GPIO[132]
GPIO[39]
A[1]
SIUL
FlexPWM_0
SSCM
DSPI_0
K4
C[7]
DEBUG[7]
—
—
SIN
K6
K7
K8
VDD_LV
VSS_LV
VSS_LV
—
—
—
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 5.
Pin #
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
K9
VSS_LV
VSS_LV
—
—
K10
K11
K12
K14
VSS_LV
—
VDD_LV
—
Not connected
—
SIUL
FlexPWM_1
DSPI_0
SIUL
GPIO[120]
A[1]
GPIO[120]
A[1]
K15
K16
H[8]
H[7]
CS6
GPIO[119]
X[1]
—
GPIO[119]
X[1]
FlexPWM_1
eTimer_2
SIUL
ETC[1]
GPIO[3]
ETC[3]
CS0
B[3]
ETC[1]
GPIO[3]
ETC[3]
CS0
eTimer_0
DSPI_2
FlexPWM_0
MC_RGM
SIUL
K17
A[3]
B[3]
—
ABS[2]
EIRQ[3]
GPIO[90]
—
—
SIUL
GPIO[90]
EVTO
GPIO[91]
—
L1
L2
F[10]
F[11]
NPC
SIUL
GPIO[91]
EVTI
NPC
SIUL
GPIO[57]
X[0]
GPIO[57]
X[0]
L3
D[9]
FlexPWM_0
LINFlexD_1
TXD
—
—
L4
L6
Not connected
VDD_LV
—
L7
VSS_LV
—
L8
VSS_LV
—
L9
VSS_LV
—
L10
L11
L12
L14
L15
VSS_LV
—
VSS_LV
—
VDD_LV
—
Not connected
TCK
—
—
64/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[116]
X[0]
GPIO[116]
X[0]
L16
H[4]
ETC[0]
GPIO[20]
TDO
—
ETC[0]
GPIO[20]
—
L17
B[4]
JTAGC
M1
M2
VDD_HV_OSC
VDD_HV_IO_RING
—
SIUL
DSPI_1
GPIO[56]
CS2
ETC[4]
CS5
—
GPIO[56]
—
M3
D[8]
eTimer_1
DSPI_0
ETC[4]
—
FlexPWM_0
FAULT[3]
M4
M6
Not connected
VDD_LV
—
—
M7
VDD_LV
—
M8
VDD_LV
—
M9
VDD_LV
—
M10
M11
M12
VDD_LV
—
VDD_LV
—
VDD_LV
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[43]
ETC[4]
CS2
GPIO[21]
—
GPIO[43]
ETC[4]
—
M14
C[11]
GPIO[21]
TDI
M15
M16
B[5]
JTAGC
TMS
—
SIUL
GPIO[117]
A[0]
GPIO[117]
A[0]
M17
H[5]
FlexPWM_1
DSPI_0
CS4
—
—
N1
N2
XTAL
VSS_HV_IO_RING
—
SIUL
GPIO[53]
CS3
—
GPIO[53]
—
N3
N4
D[5]
DSPI_0
FlexPWM_0
FAULT[2]
VSS_LV_PLL0_PLL1
—
Doc ID 15457 Rev 8
65/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 5.
Pin #
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
N14
Not connected
—
GPIO[44]
ETC[5]
CS3
GPIO[2]
ETC[2]
A[3]
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[44]
ETC[5]
—
N15
C[12]
A[2]
GPIO[2]
ETC[2]
A[3]
eTimer_0
FlexPWM_0
DSPI_2
MC_RGM
SIUL
N16
N17
SIN
—
ABS[0]
EIRQ[2]
GPIO[101]
X[3]
—
SIUL
GPIO[101]
X[3]
CS3
—
G[5]
FlexPWM_0
DSPI_2
—
P1
P2
VSS_HV_OSC
RESET
—
SIUL
GPIO[54]
CS2
X[3]
—
GPIO[54]
—
DSPI_0
P3
D[6]
FlexPWM_0
FlexPWM_0
X[3]
FAULT[1]
P4
P5
P6
VDD_LV_PLL0_PLL1
VDD_LV_CORE_RING
VSS_LV_CORE_RING
—
—
—
SIUL
—
GPIO[24]
ETC[5]
AN[1]
P7
B[8]
eTimer_0
ADC_0
—
—
P8
P9
Not connected
VSS_HV_IO_RING
VDD_HV_IO_RING
—
—
P10
—
SIUL
eTimer_0
SIUL
—
GPIO[30]
ETC[4]
—
P11
B[14]
—
EIRQ[19]
AN[1]
ADC_1
—
P12
P13
P14
VDD_LV_CORE_RING
VSS_LV_CORE_RING
VDD_HV_IO_RING
—
—
—
66/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
FlexRay
DSPI_2
FlexPWM_0
SIUL
GPIO[106]
GPIO[106]
—
DBG2
P15
G[10]
CS3
—
—
FAULT[2]
GPIO[104]
—
GPIO[104]
FlexRay
DSPI_0
FlexPWM_0
SIUL
DBG0
P16
P17
G[8]
G[7]
CS1
—
—
FAULT[0]
EIRQ[21]
GPIO[103]
B[3]
—
SIUL
GPIO[103]
FlexPWM_0
B[3]
R1
R2
R3
EXTAL
—
FCCU_F[0]
FCCU
F[0]
F[0]
VSS_HV_IO_RING
—
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
GPIO[55]
—
CS3
R4
R5
D[7]
B[7]
CS4
—
analog output
—
SIUL
—
—
—
—
—
—
—
GPIO[23]
RXD
LINFlexD_0
ADC_0
SIUL
AN[0]
GPIO[70]
AN[4]
R6
R7
E[6]
ADC_0
VDD_HV_ADR0
SIUL
GPIO[26]
AN[12]
R8
R9
B[10]
ADC_0
ADC_1
—
VDD_HV_ADR1
—
—
—
—
—
—
—
SIUL
LINFlexD_1
ADC_1
SIUL
GPIO[29]
RXD
R10
R11
B[13]
B[15]
AN[0]
GPIO[31]
EIRQ[20]
AN[2]
SIUL
ADC_1
Doc ID 15457 Rev 8
67/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 5.
Pin #
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
—
GPIO[32]
AN[3]
R12
R13
C[0]
ADC_1
—
BCTRL
—
GPIO[1]
ETC[1]
SOUT
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[1]
ETC[1]
—
R14
A[1]
EIRQ[1]
R15
R16
VSS_HV_IO_RING
—
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[59]
B[0]
—
GPIO[59]
B[0]
D[11]
ETC[1]
GPIO[105]
—
GPIO[105]
DBG1
CS1
—
FlexRay
DSPI_1
FlexPWM_0
SIUL
R17
G[9]
—
FAULT[1]
EIRQ[29]
—
T1
T2
T3
VSS_HV_IO_RING
VDD_HV_IO_RING
Not connected
—
—
—
SIUL
ADC_0
SIUL
—
GPIO[33]
AN[2]
T4
T5
C[1]
E[5]
—
—
GPIO[69]
AN[8]
ADC_0
SIUL
—
—
GPIO[71]
AN[6]
T6
T7
E[7]
ADC_0
—
VSS_HV_ADR0
—
SIUL
—
GPIO[27]
AN[13]
T8
B[11]
ADC_0
ADC_1
—
T9
VSS_HV_ADR1
E[9]
—
—
—
—
—
SIUL
ADC_1
SIUL
GPIO[73]
AN[7]
T10
GPIO[74]
AN[8]
T11
E[10]
ADC_1
68/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
SIUL
ADC_1
SIUL
—
—
GPIO[76]
AN[6]
T12
E[12]
—
GPIO[64]
AN[5]
T13
T14
E[0]
A[0]
ADC_1
SIUL
—
GPIO[0]
ETC[0]
SCK
—
GPIO[0]
ETC[0]
SCK
eTimer_0
DSPI_2
SIUL
EIRQ[0]
GPIO[58]
A[0]
SIUL
GPIO[58]
A[0]
—
T15
D[10]
FlexPWM_0
eTimer_0
ETC[0]
T16
T17
U1
VDD_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
Not connected
—
—
—
U2
—
U3
—
SIUL
ADC_0
SIUL
—
GPIO[68]
AN[7]
U4
U5
U6
E[4]
C[2]
E[2]
—
—
GPIO[34]
AN[3]
ADC_0
SIUL
—
—
GPIO[66]
AN[5]
ADC_0
SIUL
—
—
GPIO[25]
U7
U8
B[9]
ADC_0
ADC_1
—
—
—
AN[11]
GPIO[28]
AN[14]
SIUL
B[12]
ADC_0
ADC_1
U9
VDD_HV_ADV
VSS_HV_ADV
—
—
—
—
—
—
—
U10
SIUL
GPIO[75]
AN[4]
U11
E[11]
ADC_1
U12
U13
U14
Not connected
Not connected
VDD_HV_PMU
Doc ID 15457 Rev 8
69/160
Package pinouts and signal descriptions
SPC56XL60/54
Input function
Table 5.
Pin #
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
SIUL
GPIO[107]
GPIO[107]
—
U15
G[11]
FlexRay
DBG3
—
FlexPWM_0
FAULT[3]
U16
U17
VSS_HV_IO_RING
VSS_HV_IO_RING
—
—
1. VPP_TEST should always be tied to ground (VSS) for normal operations.
2.2
Supply pins
Table 6.
Supply pins
Supply
Pin #
100 144
pkg pkg
257
pkg
Symbol
Description
VREG control and power supply pins
BCTRL
Voltage regulator external NPN ballast base control pin
47
48
49
50
69
R13
VDD_LV_COR Core logic supply
70 VDD_LV(1)
71 VSS_LV(2)
VSS_LV_COR Core regulator ground
VDD_HV_PMU Voltage regulator supply
72
U14
ADC_0/ADC_1 reference voltage and ADC supply
VDD_HV_ADR0 ADC_0 high reference voltage
VSS_HV_ADR0 ADC_0 low reference voltage
VDD_HV_ADR1 ADC_1 high reference voltage
VSS_HV_ADR1 ADC_1 low reference voltage
VDD_HV_ADV ADC voltage supply for ADC_0 and ADC_1
VSS_HV_ADV ADC ground for ADC_0 and ADC_1
Power supply pins (3.3 V)
33
34
39
40
41
42
50
51
56
57
58
59
R7
T7
R9
T9
U9
U10
VDD_HV_IO
VSS_HV_IO
3.3 V Input/Output supply voltage
3.3 V Input/Output ground
—
—
10
13
14
16
17
62
63
6
7
VDD_HV(3)
VSS_HV(4)
J3
VDD_HV_REG_0 VDD_HV_REG_0
VDD_HV_IO 3.3 V Input/Output supply voltage
VSS_HV_IO 3.3 V Input/Output ground
16
21 VDD_HV(3)
22 VSS_HV(4)
VDD_HV_OSC Crystal oscillator amplifier supply voltage
VSS_HV_OSC Crystal oscillator amplifier ground
27
28
M1
P1
VSS_HV_IO
VDD_HV_IO
3.3 V Input/Output ground
90 VSS_HV(4)
91 VDD_HV(3)
3.3 V Input/Output supply voltage
70/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 6.
Supply pins (continued)
Supply
Pin #
100 144
pkg pkg
257
pkg
Symbol
Description
VDD_HV_REG_1 VDD_HV_REG_1
VSS_HV_FLA VSS_HV_FLA
VDD_HV_FLA VDD_HV_FLA
67
68
69
87
88
91
95
96
97
H15
J16
H16
VDD_HV_IO
VSS_HV_IO
VDD_HV_IO
VSS_HV_IO
126 VDD_HV(3)
127 VSS_HV(4)
VDD_HV_REG_2 VDD_HV_REG_2
130
C7
Power supply pins (1.2 V)
VSS_LV_COR
VSS_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected 11
between these pins and the nearest VDD_LV_COR pin.
17 VSS_HV(2)
18 VDD_LV(1)
VDD_LV_COR
VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected 12
between these pins and the nearest VSS_LV_COR pin.
VSS_LV_PLL0_PLL1 /
VSS 1V2
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling
capacitor must be connected between this pin and VDD_LV_PLL.
24
35
36
N4
P4
VDD_LV_PLL0_PLL1
Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must 25
be connected between this pin and VSS_LV_PLL.
VDD 1V2
VDD_LV_COR
VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected 28
between these pins and the nearest VSS_LV_COR pin.
39 VDD_LV(1)
40 VSS_LV(2)
70 VDD_LV(1)
71 VSS_LV(2)
93 VDD_LV(1)
94 VSS_LV(2)
131 VDD_LV(1)
VSS_LV_COR
VSS_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected 29
between these pins and the nearest VDD_LV_COR pin.
VDD_LV_COR
VDD_LV_COR Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VSS_LV_REGCOR.
—
—
VSS_LV_REGCOR0
VSS_LV_COR Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VDD_LV_REGCOR.
VDD_LV_COR
VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected 65
between these pins and the nearest VSS_LV_COR pin.
VSS_LV_COR
VSS_LV_COR / 1.2 V Decoupling pins for core logic. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV_COR pin.
66
VDD_LV_COR
VDD 1V2
Decoupling pins for core logic. Decoupling capacitor must be connected 92
between these pins and the nearest VDD_LV_COR pin.
Doc ID 15457 Rev 8
71/160
Package pinouts and signal descriptions
SPC56XL60/54
Pin #
Table 6.
Supply pins (continued)
Supply
100 144
pkg pkg
257
pkg
Symbol
Description
VSS_LV_COR
VSS 1V2
VDD 1V2
VSS 1V2
Decoupling pins for core logic. Decoupling capacitor must be connected 93
between these pins and the nearest VDD_LV_COR pin.
132 VSS_LV(2)
135 VDD_LV(1)
137 VSS_LV(2)
VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
—
—
VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
1. VDD_LV balls are tied together on the LFBGA257 substrate.
2. VSS_LV balls are tied together on the LFBGA257 substrate.
3. VDD_HV balls are tied together on the LFBGA257 substrate.
4. VSS_HV balls are tied together on the LFBGA257 substrate.
2.3
System pins
Table 7.
System pins
Pin #
Symbol
Description
Direction
100 144 257
pkg pkg pkg
Dedicated pins
MDO0(1)
NMI(2)
XTAL
Nexus Message Data Output — line
Output only
Input only
Input only
—
1
9
1
E1
E4
N1
Non Maskable Interrupt
Input for oscillator amplifier circuit and internal clock generator
18
29
Input/Output
EXTAL(3)
Oscillator amplifier output
19
30
R1
(4)
TMS(2)
TCK(2)
JTAG state machine control
JTAG clock
Input only
Input only
Input only
59
60
84
87 M16
88 L15
123 C10
JCOMP(5)
JTAG compliance select
Reset pin
Bidirectional reset with Schmitt-Trigger characteristics and
noise filter. This pin has medium drive strength. Output drive is
open drain and must be terminated by an external resistor of
value 1KOhm.(6)
RESET
Bidirectional
20
74
31
P2
Test pin
Pin for testing purpose only. To be tied to ground in normal
operating mode.
VPP TEST
107 D15
1. This pad is configured for Fast (F) pad speed.
72/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
2. This pad contains a weak pull-up.
3. EXTAL is an "Output" in "crystal" mode, and is an "Input" in "ext clock" mode.
4. In XOSC Bypass Mode, the analog portion of crystal oscillator (amplifier) is disabled. An external clock can be applied at
EXTAL as an input. In XOSC Normal Mode, EXTAL is an output
5. This pad contains a weak pull-down.
6. RESET output shall be considered valid only after the 3.3V supply reaches its stable value.
Note:
None of system pins (except RESET) provides an open drain output.
2.4
Pin muxing
Table 8 defines the pin list and muxing for this device.
Each entry of Table 8 shows all the possible configurations for each pin, via the alternate
functions. The default function assigned to each pin after reset is indicated by ALT0.
Note:
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.
Pins labeled “Reserved” are to be tied to ground. Not doing so may cause unpredictable
device behavior.
Doc ID 15457 Rev 8
73/160
Table 8.
Pin muxing
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
Port A
SIUL
GPIO[0]
ETC[0]
ALT0
ALT1
GPIO[0]
—
PSMI[35];
PADSEL=0
eTimer_0
ETC[0]
SCK
A[0]
A[1]
PCR[0]
PCR[1]
—
—
M
S
51
52
73
74
T14
R14
PSMI[1];
PADSEL=0
DSPI_2
SCK
ALT2
SIUL
SIUL
—
—
EIRQ[0]
GPIO[1]
—
—
GPIO[1]
ALT0
PSMI[36];
PADSEL=0
eTimer_0
ETC[1]
ALT1
ETC[1]
M
S
DSPI_2
SIUL
SOUT
—
ALT2
—
—
—
—
—
EIRQ[1]
GPIO[2]
SIUL
GPIO[2]
ALT0
PSMI[37];
PADSEL=0
eTimer_0
FlexPWM_0
DSPI_2
ETC[2]
A[3]
ALT1
ALT3
—
ETC[2]
A[3]
PSMI[23];
PADSEL=0
A[2]
PCR[2]
Pull down
M
S
57
84
N16
PSMI[2];
PADSEL=0
—
SIN
MC_RGM
SIUL
—
—
—
—
ABS[0]
—
—
EIRQ[2]
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[3]
ETC[3]
ALT0
ALT1
GPIO[3]
ETC[3]
—
PSMI[38];
PADSEL=0
eTimer_0
PSMI[3];
PADSEL=0
DSPI_2
CS0
B[3]
ALT2
ALT3
CS0
B[3]
A[3]
PCR[3]
Pull down
M
S
64
92
K17
PSMI[27];
PADSEL=0
FlexPWM_0
MC_RGM
SIUL
—
—
—
—
ABS[2]
EIRQ[3]
GPIO[4]
—
—
—
SIUL
GPIO[4]
ALT0
PSMI[9];
PADSEL=0
eTimer_1
DSPI_2
ETC[0]
CS1
ALT1
ALT2
ALT3
ETC[0]
—
—
A[4]
PCR[4]
Pull down
M
S
75
108 C16
PSMI[7];
PADSEL=0
eTimer_0
ETC[4]
ETC[4]
MC_RGM
SIUL
—
—
—
—
FAB
EIRQ[4]
GPIO[5]
CS0
—
—
—
—
SIUL
GPIO[5]
CS0
ALT0
ALT1
DSPI_1
PSMI[14];
PADSEL=0
A[5]
PCR[5]
eTimer_1
ETC[5]
ALT2
ETC[5]
—
M
S
8
14
H4
DSPI_0
SIUL
CS7
—
ALT3
—
—
—
—
EIRQ[5]
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
DSPI_1
SIUL
GPIO[6]
SCK
ALT0
ALT1
—
GPIO[6]
SCK
—
—
—
—
—
—
—
—
—
—
—
A[6]
A[7]
A[8]
PCR[6]
PCR[7]
PCR[8]
—
—
—
M
S
2
4
6
2
G4
F3
F4
—
EIRQ[6]
GPIO[7]
—
SIUL
GPIO[7]
SOUT
—
ALT0
ALT1
—
DSPI_1
SIUL
M
M
S
S
10
12
EIRQ[7]
GPIO[8]
SIN
SIUL
GPIO[8]
—
ALT0
—
DSPI_1
SIUL
—
—
EIRQ[8]
GPIO[9]
—
SIUL
GPIO[9]
CS1
ALT0
ALT1
DSPI_2
PSMI[27];
PADSEL=1
A[9]
PCR[9]
—
M
S
94
134
B6
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[16];
PADSEL=0
FlexPWM_0
SIUL
—
—
FAULT[0]
GPIO[10]
CS0
GPIO[10]
CS0
ALT0
ALT1
—
PSMI[3];
PADSEL=1
DSPI_2
PSMI[24];
PADSEL=0
A[10]
PCR[10]
FlexPWM_0
B[0]
ALT2
B[0]
—
M
S
81
118 A13
PSMI[29];
PADSEL=0
FlexPWM_0
SIUL
X[2]
—
ALT3
—
X[2]
EIRQ[9]
—
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[11]
SCK
ALT0
ALT1
GPIO[11]
SCK
—
PSMI[1];
PADSEL=1
DSPI_2
PSMI[20];
PADSEL=0
A[11]
A[12]
A[13]
PCR[11]
FlexPWM_0
FlexPWM_0
A[0]
A[2]
ALT2
ALT3
A[0]
A[2]
—
—
—
M
S
82
83
95
120 D11
PSMI[22];
PADSEL=0
SIUL
SIUL
—
—
EIRQ[10]
GPIO[12]
—
—
—
—
GPIO[12]
SOUT
ALT0
ALT1
DSPI_2
PSMI[22];
PADSEL=1
FlexPWM_0
FlexPWM_0
A[2]
B[2]
ALT2
ALT3
A[2]
B[2]
PCR[12]
M
S
122 A10
PSMI[26];
PADSEL=0
SIUL
SIUL
—
—
EIRQ[11]
GPIO[13]
—
—
GPIO[13]
ALT0
PSMI[26];
PADSEL=1
FlexPWM_0
DSPI_2
B[2]
—
ALT2
—
B[2]
SIN
PSMI[2];
PADSEL=1
PCR[13]
M
S
136
C6
PSMI[16];
PADSEL=1
FlexPWM_0
SIUL
—
—
—
—
FAULT[0]
EIRQ[12]
—
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[14]
TXD
ALT0
ALT1
GPIO[14]
—
—
—
FlexCAN_1
A[14]
PCR[14]
—
M
S
99
143
B4
PSMI[13];
PADSEL=0
eTimer_1
ETC[4]
ALT2
ETC[4]
SIUL
SIUL
—
—
EIRQ[13]
GPIO[15]
—
—
GPIO[15]
ALT0
PSMI[14];
PADSEL=1
eTimer_1
ETC[5]
—
ALT2
—
ETC[5]
RXD
PSMI[34];
PADSEL=0
A[15]
PCR[15]
FlexCAN_1
—
M
S
100 144
D3
PSMI[33];
PADSEL=0
FlexCAN_0
SIUL
—
—
—
—
RXD
EIRQ[14]
Port B
—
SIUL
GPIO[16]
TXD
ALT0
ALT1
GPIO[16]
—
—
—
FlexCAN_0
PSMI[11];
PADSEL=0
B[0]
PCR[16]
eTimer_1
ETC[2]
ALT2
ETC[2]
—
M
S
76
109 B15
SSCM
SIUL
DEBUG[0]
—
ALT3
—
—
—
—
EIRQ[15]
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
eTimer_1
SSCM
GPIO[17]
ETC[3]
DEBUG[1]
—
ALT0
ALT2
ALT3
—
GPIO[17]
ETC[3]
—
—
PSMI[12];
PADSEL=0
—
B[1]
PCR[17]
—
M
S
77
110 C14
PSMI[33];
PADSEL=1
FlexCAN_0
RXD
PSMI[34];
PADSEL=1
FlexCAN_1
—
—
RXD
SIUL
SIUL
—
—
EIRQ[16]
GPIO[18]
—
—
—
—
—
—
—
—
GPIO[18]
TXD
ALT0
ALT1
ALT3
—
LINFlexD_0
SSCM
SIUL
B[2]
B[3]
PCR[18]
PCR[19]
—
—
M
M
S
S
79
80
114 A14
DEBUG[2]
—
—
EIRQ[17]
GPIO[19]
—
SIUL
GPIO[19]
DEBUG[3]
ALT0
ALT3
SSCM
116 B13
PSMI[31];
PADSEL=0
LINFlexD_0
—
—
RXD
SIUL
JTAGC
SIUL
GPIO[20]
TDO
ALT0
ALT1
ALT0
—
GPIO[20]
—
—
—
—
—
B[4](2)
B[5]
PCR[20]
PCR[21]
—
F
S
S
61
58
89
86
L17
GPIO[21]
—
GPIO[21]
TDI
Pull up
M
M15
JTAGC
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
MC_CGM
DSPI_2
SIUL
GPIO[22]
clk_out
CS2
ALT0
ALT1
ALT2
GPIO[22]
—
—
—
—
—
—
B[6]
PCR[22]
—
F
S
96
138
B3
—
—
EIRQ[18]
GPI[23]
SIUL
—
ALT0
—
PSMI[31];
PADSEL=1
B[7]
B[8]
PCR[23]
PCR[24]
LINFlexD_0
—
RXD
—
—
—
—
—
—
30
31
43
47
R5
P7
ADC_0
SIUL
—
—
—
AN[0](3)
GPI[24]
—
—
ALT0
PSMI[8];
PADSEL=2
eTimer_0
—
—
ETC[5]
ADC_0
SIUL
—
—
—
AN[1](3)
GPI[25]
—
—
ALT0
B[9]
PCR[25]
PCR[26]
PCR[27]
PCR[28]
—
—
—
—
—
—
—
—
—
—
—
—
35
36
37
38
52
53
54
55
U7
R8
T8
U8
ADC_0
ADC_1
—
—
—
—
—
—
—
—
ALT0
—
AN[11](3)
GPI[26]
—
—
—
—
—
—
—
SIUL
B[10]
B[11]
B[12]
ADC_0
ADC_1
AN[12](3)
GPI[27]
SIUL
ALT0
—
ADC_0
ADC_1
AN[13](3)
GPI[28]
SIUL
ALT0
—
ADC_0
ADC_1
AN[14](3)
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
—
—
ALT0
—
GPI[29]
RXD
—
PSMI[32];
PADSEL=0
B[13]
PCR[29]
LINFlexD_1
—
—
—
43
60
R10
ADC_1
SIUL
—
—
—
AN[0](3)
GPI[30]
—
—
ALT0
PSMI[7];
PADSEL=2
eTimer_0
—
—
ETC[4]
B[14]
B[15]
PCR[30]
PCR[31]
—
—
—
—
—
—
44
—
64
62
P11
R11
SIUL
ADC_1
SIUL
—
—
—
—
—
—
—
EIRQ[19]
AN[1](3)
GPI[31]
EIRQ[20]
AN[2](3)
Port C
—
—
—
—
—
ALT0
—
SIUL
ADC_1
—
SIUL
ADC_1
SIUL
—
—
—
—
—
—
ALT0
—
GPI[32]
AN[3](3)
GPI[33]
AN[2](3)
GPI[34]
AN[3](3)
—
—
—
—
—
—
C[0]
C[1]
C[2]
PCR[32]
PCR[33]
PCR[34]
—
—
—
—
—
—
—
—
—
45
—
—
66
41
45
R12
T4
ALT0
—
ADC_0
SIUL
ALT0
—
U5
ADC_0
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[36]
CS0
ALT0
ALT1
GPIO[36]
CS0
—
—
DSPI_0
PSMI[28];
PADSEL=0
C[4]
PCR[36]
FlexPWM_0
X[1]
ALT2
X[1]
—
M
S
5
11
H3
SSCM
SIUL
DEBUG[4]
—
ALT3
—
—
EIRQ[22]
GPIO[37]
SCK
—
—
—
—
—
SIUL
GPIO[37]
SCK
ALT0
ALT1
ALT3
DSPI_0
SSCM
DEBUG[5]
—
C[5]
PCR[37]
—
M
S
7
13
G3
PSMI[19];
PADSEL=0
FlexPWM_0
—
—
FAULT[3]
SIUL
SIUL
—
—
EIRQ[23]
GPIO[38]
—
—
—
—
GPIO[38]
SOUT
ALT0
ALT1
DSPI_0
PSMI[25];
PADSEL=0
C[6]
C[7]
PCR[38]
PCR[39]
FlexPWM_0
B[1]
ALT2
B[1]
—
—
M
M
S
S
98
142
D4
K4
SSCM
SIUL
DEBUG[6]
—
ALT3
—
—
—
—
—
EIRQ[24]
GPIO[39]
SIUL
GPIO[39]
ALT0
PSMI[21];
PADSEL=0
FlexPWM_0
A[1]
ALT2
A[1]
9
15
SSCM
DEBUG[7]
—
ALT3
—
—
—
—
DSPI_0
SIN
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[42]
CS2
ALT0
ALT1
GPIO[42]
—
—
—
DSPI_2
PSMI[23];
PADSEL=1
C[10]
PCR[42]
—
M
S
78
111 A15
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[17];
PADSEL=0
FlexPWM_0
SIUL
—
—
FAULT[1]
GPIO[43]
ETC[4]
GPIO[43]
ETC[4]
ALT0
ALT1
—
PSMI[7];
PADSEL=1
C[11]
C[12]
PCR[43]
PCR[44]
eTimer_0
—
—
M
M
S
S
55
56
80
82
M14
N15
DSPI_2
SIUL
CS2
ALT2
ALT0
—
—
—
GPIO[44]
GPIO[44]
PSMI[8];
PADSEL=0
eTimer_0
ETC[5]
ALT1
ETC[5]
DSPI_2
SIUL
CS3
ALT2
ALT0
—
—
—
GPIO[45]
GPIO[45]
PSMI[10];
PADSEL=0
eTimer_1
CTU_0
ETC[1]
—
ALT1
—
ETC[1]
C[13]
C[14]
PCR[45]
PCR[46]
—
—
M
M
S
S
71
72
101 F15
PSMI[0];
PADSEL=0
EXT_IN
PSMI[15];
PADSEL=0
FlexPWM_0
SIUL
—
—
EXT_SYNC
GPIO[46]
ETC[2]
—
GPIO[46]
ETC[2]
ALT0
ALT1
ALT2
—
PSMI[11];
PADSEL=1
eTimer_1
CTU_0
103 E15
EXT_TGR
—
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[47]
ALT0
ALT1
GPIO[47]
—
—
—
FlexRay
CA_TR_EN
PSMI[9];
PADSEL=1
eTimer_1
FlexPWM_0
CTU_0
ETC[0]
A[1]
—
ALT2
ALT3
—
ETC[0]
A[1]
PSMI[21];
PADSEL=1
C[15]
PCR[47]
—
SYM
S
85
124
A8
PSMI[0];
PADSEL=1
EXT_IN
EXT_SYNC
PSMI[15];
PADSEL=1
FlexPWM_0
—
—
Port D
GPIO[48]
—
SIUL
GPIO[48]
CA_TX
ALT0
ALT1
—
—
FlexRay
PSMI[10];
PADSEL=1
D[0]
D[1]
PCR[48]
PCR[49]
—
—
SYM
S
S
86
125
B8
E3
eTimer_1
ETC[1]
ALT2
ETC[1]
PSMI[25];
PADSEL=1
FlexPWM_0
SIUL
B[1]
ALT3
ALT0
ALT2
B[1]
GPIO[49]
ETC[2]
GPIO[49]
ETC[2]
—
PSMI[11];
PADSEL=2
eTimer_1
M
3
3
CTU_0
EXT_TGR
—
ALT3
—
—
—
—
FlexRay
CA_RX
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[50]
ETC[3]
ALT0
ALT2
GPIO[50]
ETC[3]
—
PSMI[12];
PADSEL=1
eTimer_1
D[2]
D[3]
PCR[50]
—
—
M
S
—
140
128
C5
A7
PSMI[30];
PADSEL=0
FlexPWM_0
X[3]
ALT3
X[3]
FlexRay
SIUL
—
—
CB_RX
GPIO[51]
—
—
—
—
GPIO[51]
CB_TX
ALT0
ALT1
FlexRay
PSMI[13];
PADSEL=1
PCR[51]
SYM
S
89
eTimer_1
ETC[4]
A[3]
ALT2
ALT3
ETC[4]
A[3]
PSMI[23];
PADSEL=2
FlexPWM_0
SIUL
GPIO[52]
ALT0
ALT1
GPIO[52]
—
—
—
FlexRay
CB_TR_EN
PSMI[14];
PADSEL=2
D[4]
D[5]
PCR[52]
PCR[53]
—
—
SYM
S
S
90
22
129
33
B7
N3
eTimer_1
ETC[5]
B[3]
ALT2
ALT3
ETC[5]
B[3]
PSMI[27];
PADSEL=2
FlexPWM_0
SIUL
GPIO[53]
CS3
ALT0
ALT1
GPIO[53]
—
—
—
DSPI_0
M
PSMI[18];
PADSEL=0
FlexPWM_0
—
—
FAULT[2]
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[54]
CS2
ALT0
ALT1
GPIO[54]
—
—
—
DSPI_0
PSMI[30];
PADSEL=1
D[6]
D[7]
PCR[54]
—
—
M
S
23
26
34
37
P3
R4
FlexPWM_0
FlexPWM_0
X[3]
—
ALT3
—
X[3]
PSMI[17];
PADSEL=1
FAULT[1]
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
CS3
ALT0
ALT1
ALT3
—
GPIO[55]
—
—
—
—
—
—
—
—
PCR[55]
M
S
CS4
analog output
GPIO[56]
CS2
—
SIUL
ALT0
ALT1
GPIO[56]
—
DSPI_1
PSMI[13];
PADSEL=2
eTimer_1
DSPI_0
ETC[4]
CS5
—
ALT2
ALT3
—
ETC[4]
—
D[8]
D[9]
PCR[56]
PCR[57]
—
—
M
M
S
S
21
15
32
26
M3
L3
—
PSMI[19];
PADSEL=1
FlexPWM_0
FAULT[3]
SIUL
GPIO[57]
X[0]
ALT0
ALT1
ALT2
GPIO[57]
X[0]
—
—
—
FlexPWM_0
LINFlexD_1
TXD
—
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[58]
A[0]
ALT0
ALT1
GPIO[58]
A[0]
—
PSMI[20];
PADSEL=1
FlexPWM_0
D[10]
D[11]
D[12]
D[14]
PCR[58]
—
—
—
—
M
S
53
54
70
73
76
78
99
T15
R16
G14
PSMI[35];
PADSEL=1
eTimer_0
SIUL
—
GPIO[59]
B[0]
—
ETC[0]
GPIO[59]
B[0]
ALT0
ALT1
—
PSMI[24];
PADSEL=1
FlexPWM_0
PCR[59]
PCR[60]
PCR[62]
M
M
M
S
S
S
PSMI[36];
PADSEL=1
eTimer_0
SIUL
—
GPIO[60]
X[1]
—
ETC[1]
GPIO[60]
X[1]
ALT0
ALT1
PSMI[28];
PADSEL=1
FlexPWM_0
PSMI[32];
PADSEL=1
LINFlexD_1
SIUL
—
GPIO[62]
B[1]
—
RXD
GPIO[62]
B[1]
ALT0
ALT1
—
PSMI[25];
PADSEL=2
FlexPWM_0
105 D16
PSMI[38];
PADSEL=1
eTimer_0
—
—
ETC[3]
Port E
SIUL
ADC_1
SIUL
—
—
—
—
ALT0
—
GPI[64]
AN[5](3)
GPI[66]
AN[5](3)
—
—
—
—
E[0]
E[2]
PCR[64]
PCR[66]
—
—
—
—
—
—
46
32
68
49
T13
U6
ALT0
—
ADC_0
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
ADC_0
SIUL
—
—
ALT0
—
GPI[68]
AN[7](3)
GPI[69]
AN[8](3)
GPI[70]
AN[4](3)
GPI[71]
AN[6](3)
GPI[73]
AN[7](3)
GPI[74]
AN[8](3)
GPI[75]
AN[4](3)
GPI[76]
AN[6](3)
GPIO[77]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E[4]
E[5]
PCR[68]
PCR[69]
PCR[70]
PCR[71]
PCR[73]
PCR[74]
PCR[75]
PCR[76]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
42
44
46
48
61
63
65
67
U4
T5
—
ALT0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADC_0
SIUL
—
—
ALT0
—
E[6]
R6
ADC_0
SIUL
—
—
ALT0
—
E[7]
T6
ADC_0
SIUL
—
—
ALT0
—
E[9]
T10
T11
U11
T12
ADC_1
SIUL
—
—
ALT0
—
E[10]
E[11]
E[12]
ADC_1
SIUL
—
—
ALT0
—
ADC_1
SIUL
—
—
ALT0
—
ADC_1
SIUL
—
GPIO[77]
ALT0
PSMI[8];
PADSEL=1
eTimer_0
ETC[5]
ALT1
ETC[5]
E[13]
PCR[77]
—
M
S
—
117 D12
DSPI_2
SIUL
CS3
—
ALT2
—
—
—
—
EIRQ[25]
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[78]
ETC[5]
ALT0
ALT1
GPIO[78]
ETC[5]
—
PSMI[14];
PADSEL=3
E[14]
E[15]
PCR[78]
PCR[79]
eTimer_1
—
—
M
S
—
—
119 B12
121 B11
SIUL
SIUL
—
GPIO[79]
CS1
—
ALT0
ALT1
—
EIRQ[26]
GPIO[79]
—
—
—
—
—
DSPI_0
SIUL
M
M
S
S
—
EIRQ[27]
Port F
SIUL
GPIO[80]
A[1]
ALT0
ALT1
GPIO[80]
—
PSMI[21];
PADSEL=2
FlexPWM_0
A[1]
F[0]
PCR[80]
—
—
133
D7
PSMI[37];
PADSEL=1
eTimer_0
—
—
ETC[2]
SIUL
SIUL
DSPI_0
SIUL
NPC
—
—
EIRQ[28]
GPIO[83]
—
—
—
—
—
—
—
—
—
—
GPIO[83]
CS6
ALT0
ALT1
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
F[3]
F[4]
F[5]
F[6]
PCR[83]
PCR[84]
PCR[85]
PCR[86]
—
—
—
—
M
F
F
F
S
S
S
S
—
—
—
—
139
4
B5
D2
D1
E2
GPIO[84]
MDO[3]
GPIO[85]
MDO[2]
GPIO[86]
MDO[1]
GPIO[84]
—
SIUL
NPC
GPIO[85]
—
5
SIUL
NPC
GPIO[86]
—
8
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
GPIO[87]
MCKO
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
GPIO[87]
—
—
—
—
—
—
—
—
—
—
—
—
F[7]
F[8]
PCR[87]
PCR[88]
PCR[89]
PCR[90]
PCR[91]
—
—
—
—
—
F
S
—
—
—
—
—
19
20
23
24
25
J1
K2
K1
L1
L2
GPIO[88]
MSEO[1]
GPIO[89]
MSEO[0]
GPIO[90]
EVTO
GPIO[88]
—
F
F
S
S
S
S
GPIO[89]
—
F[9]
GPIO[90]
—
F[10]
F[11]
F
GPIO[91]
—
GPIO[91]
EVTI
M
GPIO[92]
GPIO[92]
PSMI[12];
PADSEL=2
F[12]
F[13]
PCR[92]
PCR[93]
eTimer_1
ETC[3]
ALT1
ETC[3]
—
—
M
M
S
S
—
—
106 C17
112 B14
SIUL
SIUL
—
—
EIRQ[30]
GPIO[93]
—
—
GPIO[93]
ALT0
PSMI[13];
PADSEL=3
eTimer_1
ETC[4]
ALT1
ETC[4]
SIUL
SIUL
—
—
EIRQ[31]
GPIO[94]
—
—
—
—
—
GPIO[94]
TXD
ALT0
ALT1
ALT0
F[14]
F[15]
PCR[94]
PCR[95]
—
—
M
M
S
S
—
—
115 C13
113 D13
LINFlexD_1
SIUL
GPIO[95]
GPIO[95]
PSMI[32];
PADSEL=2
LINFlexD_1
—
—
RXD
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
FCCU
F[0]
FCCU_
F[0]
—
—
FCCU
FCCU
F[0]
F[1]
ALT0
ALT0
—
—
—
—
S
S
S
S
27
97
38
R2
C4
FCCU_
F[1]
F[1]
141
Port G
SIUL
GPIO[98]
X[2]
ALT0
ALT1
GPIO[98]
—
PSMI[29];
PADSEL=1
G[2]
G[3]
PCR[98]
PCR[99]
FlexPWM_0
X[2]
—
—
M
M
S
S
—
—
102 E16
DSPI_1
SIUL
CS1
ALT2
ALT0
—
—
—
GPIO[99]
GPIO[99]
PSMI[22];
PADSEL=2
FlexPWM_0
A[2]
ALT1
A[2]
104 D17
PSMI[7];
PADSEL=3
eTimer_0
SIUL
—
GPIO[100]
B[2]
—
ETC[4]
GPIO[100]
B[2]
ALT0
ALT1
—
PSMI[26];
PADSEL=2
FlexPWM_0
G[4]
G[5]
PCR[100]
PCR[101]
—
—
M
M
S
S
—
—
100 F17
PSMI[8];
PADSEL=3
eTimer_0
SIUL
—
GPIO[101]
X[3]
—
ETC[5]
GPIO[101]
X[3]
ALT0
ALT1
ALT2
—
PSMI[30];
PADSEL=2
FlexPWM_0
DSPI_2
85
N17
CS3
—
—
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[102]
A[3]
ALT0
ALT1
ALT0
ALT1
GPIO[102]
A[3]
—
G[6]
G[7]
PCR[102]
PCR[103]
—
—
M
S
—
—
98
83
G17
P17
PSMI[23];
PADSEL=3
FlexPWM_0
SIUL
GPIO[103]
B[3]
GPIO[103]
B[3]
M
M
S
S
PSMI[27];
PADSEL=3
FlexPWM_0
SIUL
GPIO[104]
DBG0
ALT0
ALT1
ALT2
GPIO[104]
—
—
—
FlexRay
DSPI_0
—
—
CS1
G[8]
PCR[104]
—
—
81
P16
PSMI[16];
PADSEL=2
FlexPWM_0
—
—
FAULT[0]
SIUL
SIUL
—
GPIO[105]
DBG1
—
EIRQ[21]
GPIO[105]
—
—
—
—
—
ALT0
ALT1
ALT2
FlexRay
DSPI_1
CS1
—
G[9]
PCR[105]
PCR[106]
—
—
M
M
S
S
—
—
79
77
R17
P15
PSMI[17];
PADSEL=2
FlexPWM_0
—
—
FAULT[1]
SIUL
SIUL
—
GPIO[106]
DBG2
—
EIRQ[29]
GPIO[106]
—
—
—
—
—
ALT0
ALT1
ALT2
FlexRay
DSPI_2
G[10]
CS3
—
PSMI[18];
PADSEL=1
FlexPWM_0
—
—
FAULT[2]
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[107]
DBG3
ALT0
ALT1
GPIO[107]
—
—
—
FlexRay
G[11]
PCR[107]
—
M
S
—
75
U15
PSMI[19];
PADSEL=2
FlexPWM_0
—
—
FAULT[3]
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
GPIO[108]
MDO[11]
GPIO[109]
MDO[10]
GPIO[110]
MDO[9]
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
GPIO[108]
—
—
—
—
—
—
—
—
—
G[12]
G[13]
G[14]
G[15]
PCR[108]
PCR[109]
PCR[110]
PCR[111]
—
—
—
—
F
F
F
F
S
S
S
S
—
—
—
—
—
—
—
—
F2
H1
A6
J2
GPIO[109]
—
GPIO[110]
—
GPIO[111]
MDO[8]
GPIO[111]
—
Port H
GPIO[112]
—
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
GPIO[112]
MDO[7]
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
—
—
—
—
—
—
—
—
H[0]
H[1]
H[2]
H[3]
PCR[112]
PCR[113]
PCR[114]
PCR[115]
—
—
—
—
F
F
F
F
S
S
S
S
—
—
—
—
—
—
—
—
A5
F1
A4
G1
GPIO[113]
MDO[6]
GPIO[113]
—
GPIO[114]
MDO[5]
GPIO[114]
—
GPIO[115]
MDO[4]
GPIO[115]
—
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[116]
X[0]
ALT0
ALT1
GPIO[116]
X[0]
—
—
FlexPWM_1
H[4]
PCR[116]
—
M
S
—
—
L16
PSMI[39];
PADSEL=0
eTimer_2
ETC[0]
ALT2
ETC[0]
SIUL
FlexPWM_1
DSPI_0
GPIO[117]
A[0]
ALT0
ALT1
ALT3
ALT0
ALT1
ALT3
ALT0
ALT1
GPIO[117]
A[0]
—
—
—
—
—
—
—
—
H[5]
H[6]
PCR[117]
PCR[118]
—
—
M
M
S
S
—
—
—
—
M17
H17
CS4
—
SIUL
GPIO[118]
B[0]
GPIO[118]
B[0]
FlexPWM_1
DSPI_0
CS5
—
SIUL
GPIO[119]
X[1]
GPIO[119]
X[1]
FlexPWM_1
H[7]
PCR[119]
—
M
S
—
—
K16
PSMI[40];
PADSEL=0
eTimer_2
ETC[1]
ALT2
ETC[1]
SIUL
FlexPWM_1
DSPI_0
GPIO[120]
A[1]
ALT0
ALT1
ALT3
ALT0
ALT1
ALT3
ALT0
ALT1
ALT2
GPIO[120]
A[1]
—
—
—
—
—
—
—
—
—
H[8]
H[9]
PCR[120]
PCR[121]
PCR[122]
—
—
—
M
M
M
S
S
S
—
—
—
—
—
—
K15
G16
A11
CS6
—
SIUL
GPIO[121]
B[1]
GPIO[121]
B[1]
FlexPWM_1
DSPI_0
CS7
—
SIUL
GPIO[122]
X[2]
GPIO[122]
X[2]
H[10]
FlexPWM_1
eTimer_2
ETC[2]
ETC[2]
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
FlexPWM_1
SIUL
GPIO[123]
A[2]
ALT0
ALT1
ALT0
ALT1
ALT0
ALT1
GPIO[123]
A[2]
—
—
—
—
—
—
H[11]
H[12]
PCR[123]
PCR[124]
—
—
M
S
—
—
—
—
C11
B10
GPIO[124]
B[2]
GPIO[124]
B[2]
M
M
S
S
FlexPWM_1
SIUL
GPIO[125]
X[3]
GPIO[125]
X[3]
FlexPWM_1
H[13]
PCR[125]
—
—
—
G15
PSMI[42];
PADSEL=0
eTimer_2
ETC[3]
ALT2
ETC[3]
SIUL
GPIO[126]
A[3]
ALT0
ALT1
ALT2
ALT0
ALT1
ALT2
GPIO[126]
A[3]
—
—
—
—
—
—
H[14]
H[15]
PCR[126]
PCR[127]
FlexPWM_1
eTimer_2
SIUL
—
—
M
M
S
S
—
—
—
—
A12
J17
ETC[4]
GPIO[127]
B[3]
ETC[4]
GPIO[127]
B[3]
FlexPWM_1
eTimer_2
ETC[5]
ETC[5]
Port I
SIUL
GPIO[128]
ETC[0]
ALT0
ALT1
GPIO[128]
—
PSMI[39];
PADSEL=1
eTimer_2
ETC[0]
I[0]
PCR[128]
—
M
S
—
—
C9
DSPI_0
CS4
—
ALT2
—
—
—
—
FlexPWM_1
FAULT[0]
Table 8.
Pin muxing (continued)
Pad
Pin #
speed(1)
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
SRC SRC 100 144 257
= 1
= 0
pkg pkg pkg
SIUL
GPIO[129]
ETC[1]
ALT0
ALT1
GPIO[129]
ETC[1]
—
PSMI[40];
PADSEL=1
eTimer_2
I[1]
I[2]
PCR[129]
—
—
M
S
—
—
—
—
C12
F16
DSPI_0
FlexPWM_1
SIUL
CS5
—
ALT2
—
—
—
—
—
FAULT[1]
GPIO[130]
GPIO[130]
ALT0
PSMI[41];
PADSEL=1
eTimer_2
ETC[2]
ALT1
ETC[2]
PCR[130]
M
S
DSPI_0
FlexPWM_1
SIUL
CS6
—
ALT2
—
—
—
—
—
FAULT[2]
GPIO[131]
GPIO[131]
ALT0
PSMI[42];
PADSEL=1
eTimer_2
ETC[3]
ALT1
ETC[3]
I[3]
PCR[131]
PCR[132]
—
—
M
F
S
S
—
—
—
—
E17
K3
DSPI_0
CTU_0
FlexPWM_1
SIUL
CS7
EXT_TGR
—
ALT2
ALT3
—
—
—
—
—
—
—
—
FAULT[3]
GPIO[132]
—
GPIO[132]
RDY
ALT0
ALT2
RDY
NPC
1. Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium, F = Fast, SYM = Symmetric (for FlexRay)
2. The default function of this pin out of reset is ALT1 (TDO).
3. Analog
Note:
Open Drain can be configured by the PCRn for all pins used as output (except FCCU_F[0] and FCCU_F[1] ).
SPC56XL60/54
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for this device.
This device is designed to operate at 120 MHz. The electrical specifications are preliminary
and are from previous designs, design simulations, or initial evaluation. These specifications
may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications
have been completed.
The “Symbol” column of the electrical parameter and timings tables contains an additional
column containing “SR”, “CC”, “P”, “C”, “T”, or “D”.
●
●
●
“SR” identifies system requirements—conditions that must be provided to ensure
normal device operation. An example is the input voltage of a voltage regulator.
“CC” identifies controller characteristics—indicating the characteristics and timing of
the signals that the chip provides.
“P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define
normal device operation. They specify how each characteristic is guaranteed.
–
–
P: parameter is guaranteed by production testing of each individual device.
C: parameter is guaranteed by design characterization. Measurements are taken
from a statistically relevant sample size across process variations.
–
–
T: parameter is guaranteed by design characterization on a small sample size
from typical devices under typical conditions unless otherwise noted. All values
are shown in the typical (“typ”) column are within this category.
D: parameters are derived mainly from simulations.
3.2
Absolute maximum ratings
(1)
Table 9.
Absolute maximum ratings
Symbol
Parameter
Conditions
Min
Max(2)
Unit
VDD_HV_REG SR 3.3 V voltage regulator supply voltage
VDD_HV_IOx SR 3.3 V input/output supply voltage
VSS_HV_IOx SR Input/output ground voltage
VDD_HV_FLA SR 3.3 V flash supply voltage
VSS_HV_FLA SR Flash memory ground
—
—
—
—
—
–0.3
–0.3
–0.1
–0.3
–0.1
4.0(3), (4)
4.0(3), (4)
0.1
V
V
V
V
V
4.0(3), (4)
0.1
3.3 V crystal oscillator amplifier supply
VDD_HV_OSC SR
voltage
—
—
—
–0.3
–0.1
–0.3
4.0(3), (4)
0.1
V
V
V
3.3 V crystal oscillator amplifier reference
VSS_HV_OSC SR
voltage
(5)
VDD_HV_ADR0
3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
SR
6.0
VDD_HV_ADR1
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Electrical characteristics
SPC56XL60/54
(1)
Table 9.
Absolute maximum ratings (continued)
Symbol
Parameter
Conditions
Min
Max(2)
Unit
VSS_HV_ADR0
ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
SR
—
–0.1
0.1
V
VSS_HV_ADR1
VDD_HV_ADV SR 3.3 V ADC supply voltage
VSS_HV_ADV SR 3.3 V ADC supply ground
—
—
–0.3
–0.1
4.0(3), (4)
0.1
V
V
3.0 × 10-6
(3.0 V/sec)
TVDD
SR Supply ramp rate
—
—
0.5 V/µs
6.0(6)
V/µs
–0.3
–0.3
Voltage on any pin with respect to ground
SR
VDD + 0.3(6),
VIN
V
(VSS_HV_IOx
)
Relative to VDD
(7)
Injected input current on any pin during
overload condition
IINJPAD
SR
SR
—
–10
10
mA
Absolute sum of all injected input currents
during overload condition
IINJSUM
TSTG
—
—
–50
–55
50
mA
°C
SR Storage temperature
150
1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress
have not yet been determined.
3. 5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining.
4. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
5. VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated be operated at different voltages, and need to be supplied by the
same voltage source.
6. Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
7. Only when VDD < 5.2 V.
3.3
Recommended operating conditions
Table 10. Recommended operating conditions (3.3 V)
Symbol Parameter
VDD_HV_REG SR 3.3 V voltage regulator supply voltage
Conditions
Min(1)
Max
Unit
—
—
—
—
—
—
3.0
3.0
0
3.6
3.6
0
V
V
V
V
V
V
VDD_HV_IOx
VSS_HV_IOx
VDD_HV_FLA
VSS_HV_FLA
SR 3.3 V input/output supply voltage
SR Input/output ground voltage
SR 3.3 V flash supply voltage
SR Flash memory ground
3.0
0
3.6
0
VDD_HV_OSC SR 3.3 V crystal oscillator amplifier supply voltage
3.0
3.6
3.3 V crystal oscillator amplifier reference
VSS_HV_OSC SR
voltage
—
—
0
0
V
V
(2)
VDD_HV_ADR0
3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
4.5 to 5.5 or
3.0 to 3.6
SR
VDD_HV_ADR1
98/160
Doc ID 15457 Rev 8
SPC56XL60/54
Electrical characteristics
Table 10. Recommended operating conditions (3.3 V) (continued)
Symbol
VDD_HV_ADV SR 3.3 V ADC supply voltage
VSS_HV_AD0 ADC_0 ground and low reference voltage
VSS_HV_AD1
Parameter
Conditions
Min(1)
Max
Unit
—
3.0
3.6
V
SR
—
—
—
0
0
0
0
V
V
V
ADC_1 ground and low reference voltage
VSS_HV_ADV
SR 3.3 V ADC supply ground
SR Internal supply voltage
VDD_LV_REGCOR
—
—
(3)
VSS_LV_REGCOR
SR Internal reference voltage
—
0
0
V
(4)
(2)
VDD_LV_CORx
SR Internal supply voltage
—
—
0
—
0
V
V
(3)
VSS_LV_CORx
SR Internal reference voltage
SR Internal supply voltage
—
(2)
VDD_LV_PLL
—
—
—
V
(3)
VSS_LV_PLL
SR Internal reference voltage
SR Ambient temperature under bias
SR Junction temperature under bias
—
fCPU ≤ 120 MHz
—
0
0
V
TA
TJ
–40
–40
125
150
°C
°C
1. Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.
2. VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same voltage
source.
3. Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced by an
on-chip voltage regulator.
4. For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds
(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used.
3.4
Thermal characteristics
(1)
Table 11.
Symbol
Thermal characteristics for LQFP100 package
Parameter
Conditions
Value
Unit
Single layer board – 1s
46
34
36
28
19
8
Thermal resistance, junction-to-ambient natural
convection(2)
RθJA
D
°C/W
Four layer board – 2s2p
Single layer board – 1s
Thermal resistance, junction-to-ambient forced
convection at 200 ft/min
RθJMA
D
°C/W
Four layer board – 2s2p
RθJB
RθJC
ΨJT
D
D
D
Thermal resistance junction-to-board(3)
Thermal resistance junction-to-case(4)
Junction-to-package-top natural convection(5)
—
—
—
°C/W
°C/W
°C/W
2
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
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Electrical characteristics
SPC56XL60/54
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
(1)
Table 12. Thermal characteristics for LQFP144 package
Symbol
Parameter
Conditions
Value
Unit
Single layer board – 1s
44
36
35
30
24
8
Thermal resistance, junction-to-ambient
natural convection(2)
RθJA
D
°C/W
Four layer board – 2s2p
Single layer board – 1s
Thermal resistance, junction-to-ambient forced
convection at 200 ft/min
RθJMA
D
°C/W
Four layer board – 2s2p
RθJB
RθJC
ΨJT
D
D
D
Thermal resistance junction-to-board(3)
Thermal resistance junction-to-case(4)
Junction-to-package-top natural convection(5)
—
—
—
°C/W
°C/W
°C/W
2
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
(1)
Table 13. Thermal characteristics for LFBGA257 package
Symbol
Parameter
Conditions
Value
Unit
Single layer board – 1s
46
26
37
22
13
8
Thermal resistance junction-to-ambient natural
convection(2)
RθJA
D
°C/W
Four layer board – 2s2p
Single layer board – 1s
Thermal resistance, junction-to-ambient forced
convection at 200 ft/min
RθJMA
D
°C/W
Four layer board – 2s2p
RθJB
RθJC
ΨJT
D
D
D
Thermal resistance junction-to-board(3)
Thermal resistance junction-to-case(4)
Junction-to-package-top natural convection(5)
—
—
—
°C/W
°C/W
°C/W
2
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
100/160
Doc ID 15457 Rev 8
SPC56XL60/54
Electrical characteristics
3.4.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, T , can be obtained from Equation 1:
J
Equation 1 T = T + (R
× P )
D
J
A
θJA
where:
o
T
= ambient temperature for the package ( C)
A
o
R
= junction to ambient thermal resistance ( C/W)
θJA
P
= power dissipation in the package (W)
D
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
Equation 2 R
= R
+ R
θJC θCA
θJA
where:
R
R
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
θJA
θJC
θCA
R
is device related and cannot be influenced by the user. The user controls the thermal
θJC
environment to change the case to ambient thermal resistance, R
. For instance, the user
θCA
can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (Ψ ) can be used to determine the
JT
junction temperature with a measurement of the temperature at the top center of the
package case using Equation 3:
Equation 3 T = T + (Ψ × P )
J
T
JT
D
where:
T
= thermocouple temperature on top of the package (°C)
= thermal characterization parameter (°C/W)
= power dissipation in the package (W)
T
Ψ
P
JT
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
Doc ID 15457 Rev 8
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Electrical characteristics
References
SPC56XL60/54
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998,
pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San
Diego, 1999, pp. 212–220.
3.5
Electromagnetic Interference (EMI) characteristics
The characteristics in Table 15 were measured using:
●
●
●
Device configuration, tet conditions, and EM testing per standard IEC61967-2
Supply voltage of 3.3 V DC
Ambient temperature of 25 °C
The configuration information referenced in Table 15 is explained in Table 14.
Table 14. EMI configuration summary
Configuration name
Description
– High emission = all pads have max slew rate, LVDS pads running at 40 MHz
– Oscillator frequency = 40 MHz
Configuration A
Configuration B
– System bus frequency = 80 MHz
– No PLL frequency modulation
– IEC level I (≤ 36 dBμV)
– Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
– Oscillator frequency = 40 MHz
– System bus frequency = 80 MHz
– 2% PLL frequency modulation
– IEC level K(≤ 30 dBμV)
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Table 15. EMI emission testing specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Configuration A; frequency range
150 kHz–50 MHz
—
16
—
Configuration A; frequency range 50–
150 MHz
—
—
—
—
—
—
—
16
32
25
15
21
30
24
—
—
—
—
—
—
—
Configuration A; frequency range 150–
500 MHz
Configuration A; frequency range 500–
1000 MHz
VEME
CC Radiated emissions
dBμV
Configuration B; frequency range 50–
150 MHz
Configuration B; frequency range 50–
150 MHz
Configuration B; frequency range 150–
500 MHz
Configuration B; frequency range 500–
1000 MHz
EMC testing was performed and documented according to these standards: [IEC61508-2-
7.4.5.1.b, IEC61508-2-7.2.3.2.e, IEC61508-2-Table-A.17 (partially), IEC61508-2-Table-
B.5(partially),SRS2110]
EME testing was performed and documented according to these standards: [IEC 61967-2 &
-4]
EMS testing was performed and documented according to these standards: [IEC 62132-2 &
-4]
Contact FSL for detailed information pertaining to the EMC, EME, and EMS testing and
results.
3.6
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).
(1), (2)
Table 16. ESD ratings
No.
Symbol
Parameter
Conditions
Class Max value(3) Unit
Electrostatic discharge TA = 25 °C
1
VESD(HBM)
SR
SR
H1C
M2
2000
200
V
V
(Human Body Model)
conforming to AEC-Q100-002
Electrostatic discharge TA = 25 °C
2
VESD(MM)
(Machine Model)
conforming to AEC-Q100-003
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Table 16. ESD ratings
(continued)
Parameter
No.
Symbol
Conditions
Class Max value(3) Unit
500
Electrostatic discharge TA = 25 °C
(Charged Device Model) conforming to AEC-Q100-011
3
VESD(CDM)
SR
C3A
V
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3. Data based on characterization results, not tested in production.
3.7
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin.
●
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 17. Latch-up results
No.
Symbol
LU
Parameter
Conditions
Class
II level A
1
SR Static latch-up class
TA = 125 °C conforming to JESD 78
3.8
Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
●
●
●
●
●
●
●
●
●
●
High power regulator HPREG1 (internal ballast to support core current)
High power regulator HPREG2 (external NPN to support core current)
Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (V
)
DDIO
Low voltage detector (LVD_MAIN_2) for 3.3 V supply (V
)
DDREG
Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (V
)
DDFLASH
Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPV
)
DD
Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPV
)
DD
High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when
external NPN transistor is present on board to supply core current. The MPC5643L always
powers up using HPREG1 if an external NPN transistor is present. Then the MPC5643L
makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is
fully operational, the controller part of HPREG1 is switched off.
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The following bipolar transistors are supported:
●
BCP68 from ON Semiconductor
BCX68 from Infineon
●
Table 18. Recommended operating characteristics
Symbol
Parameter
Value
Unit
hFE(β )
DC current gain (Beta)
85 - 375
1.5
—
Maximum power dissipation @
TA=25°C(1)
PD
W
A
ICMaxDC
VCESAT
VBE
Maximum peak collector current
1.0
Collector-to-emitter saturation
voltage(Max)
600(2)
1.0
mV
V
Base-to-emitter voltage (Max)
1. derating factor 12mW/degC
2. Adjust resistor at bipolar transistor collector for 3.3V to avoid VCE<VCESAT
The recommended external ballast transistor is the bipolar transistor BCP68 with the gain
range of 85 up to 375 (for IC=500mA, VCE=1V) provided by several suppliers. This includes
the gain variations BCP68-10, BCP68-16 and BCP68-25.The most important parameters for
the interoperability with the integrated voltage regulator are the DC current gain (hFE) and
the temperature coefficient of the gain (XTB). While the specified gain range of most BCP68
vendors is the same, there are slight variations in the temperature coefficient parameter.
MPC5643LVoltage regulator operation was simulated against the typical variation on
temperature coefficient and against the specified gain range to have a robust design.
Table 19. Voltage regulator electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Min, max values shall be
granted with respect to
tolerance, voltage,
temperature, and aging
variations.
External decoupling/
stability capacitor
Cext
12
—
40
µF
Combined ESR of
external capacitor
SR
—
—
0.01
5
—
—
0.10
—
Ω
Number of pins for
SR external decoupling/
stability capacitor
—
Ceramic capacitors,
taking into account
tolerance, aging, voltage
and temperature
variation
Total capacitance on
1.2 V pins
C
SR
300
—
—
—
900
2.5
nF
V1V2
Start-up time after main
supply stabilization
tSU
Cload = 10 µF × 4
ms
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Table 19. Voltage regulator electrical specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Main High Voltage
Power - Low Voltage
Detection, upper
threshold
—
—
—
—
2.9
V
Main supply low voltage
detector, lower threshold
—
—
D
—
2.6
—
—
—
V
V
Before a destructive
reset initialization phase
completion
1.355
1.495
Digital supply high
voltage detector upper
threshold
D
After a destructive reset
initialization phase
completion
1.39
1.315
1.35
—
—
—
—
—
1.47
1.455
1.38
Before a destructive
reset initialization phase
completion
Digital supply high
voltage detector lower
threshold
—
D
D
V
After a destructive reset
initialization phase
completion
Digital supply low
voltage detector lower
threshold
Before a destructive
reset initialization phase
completion
—
—
1.080
1.16
1.140
1.22
V
V
Digital supply low
voltage detector upper
threshold
After a destructive reset
initialization phase
completion
D
D
POR rising/ falling
supply threshold voltage
—
—
—
—
1.6
3
—
—
2.6
V
SR Supply ramp rate
0.5 ×106
V/s
3.3V noise rejection at
the input of
LVD_MAIN: Time
constant of RC filter at
LVD input
—
—
—
D
D
D
1.1
0.1
0.1
—
—
—
—
—
—
µs
µs
µs
LVD comparator
1.2V noise rejection at
the input of
HVD_DIG: Time
constant of RC filter at
LVD input
LVD comparator
1.2V noise rejection at
the input of
LVD_DIG: Time
constant of RC filter at
LVD input
LVD comparator
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VDD
BCP68
BCRTL
V1V2 ring on board
Lb
Rb
ESR
Cext
Rs
C
v1v2
Cint
V1V2 pin
SPC56XL60/54
Figure 5.
BCP68 board schematic example
Note:
The combined ESR of the capacitors used on 1.2 V pins (V1V2 in the picture) shall be in the
range of 1 mΩ to 100 mΩ. The minimum value of the ESR is constrained by the resonance
caused by the external components, bonding inductance, and internal decoupling. The
minimum ESR is required to avoid the resonance and make the regulator stable.
3.9
DC electrical characteristics
Table 20 gives the DC electrical characteristics at 3.3 V (3.0 V < V
< 3.6 V).
DD_HV_IOx
(1)
Table 20. DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIL
D Minimum low level input voltage
P Maximum level input voltage
P Minimum high level input voltage
D Maximum high level input voltage
T Schmitt trigger hysteresis
—
–0.1(2)
—
—
—
—
—
—
—
V
V
V
V
V
V
—
—
0.35 VDD_HV_IOx
VIH
—
0.65 VDD_HV_IOx
—
VIH
—
—
—
0.1 VDD_HV_IOx
—
VDD_HV_IOx + 0.1(2)
VHYS
VOL_S
—
P Slow, low level output voltage
IOL = 1.5 mA
0.5
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(1)
Table 20. DC electrical characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOH = –
1.5 mA
VDD_HV_IOx
0.8
–
VOH_S
VOL_M
VOH_M
VOL_F
VOH_F
P Slow, high level output voltage
P Medium, low level output voltage
—
—
—
—
—
—
0.5
—
V
V
V
V
V
IOL = 2 mA
—
VDD_HV_IOx
0.8
–
P Medium, high level output voltage IOH = –2 mA
P Fast, high level output voltage
P Fast, high level output voltage
IOL = 1.5 mA
—
0.5
—
IOH = –
1.5 mA
VDD_HV_IOx
0.8
–
–
Symmetric, high level output
voltage
VOL_SYM
P
I
OL = 1.5 mA
OH = –
—
—
—
0.5
—
V
Symmetric, high level output
voltage
I
VDD_HV_IOx
0.8
VOH_SYM
IINJ
IPU
P
V
1.5 mA
T DC injection current per pin
P Equivalent pull-up current
—
–1
–130
—
—
—
—
—
—
1
mA
V
IN = VIL
VIN = VIH
VIN = VIL
VIN = VIH
—
µA
µA
–10
—
10
IPD
P Equivalent pull-down current
—
130
Input leakage current
(all bidirectional ports)
-1
—
—
—
1
0.5
1
Input leakage current
P
TJ = –40 to
+150 °C
IIL
-0.5
μA
(all ADC input-only ports)
Input leakage current
-1
(shared ADC input-only ports)
VILR
VIHR
P RESET, low level input voltage
P RESET, high level input voltage
D RESET, Schmitt trigger hysteresis
D RESET, low level output voltage
—
—
–0.1(2)
—
—
—
—
—
—
0.35 VDD_HV_IOx
V
V
V
V
0.65 VDD_HV_IOx
VDD_HV_IOx+0.1(2)
VHYSR
VOLR
—
0.1 VDD_HV_IOx
—
0.5
—
IOL = 2 mA
VIN = VIL
VIN = VIH
—
10
—
RESET, equivalent pull-down
IPD
D
µA
current
130
1. These specifications are design targets and subject to change per device characterization.
2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
3.10
Supply current characteristics
Current consumption data is given in Table 21. These specifications are design targets and
are subject to change per device characterization.
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Table 21. Current consumption characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
1.2 V supplies
50 mA+
2.18 mA*fCPU[MHz]
TJ = ambient
—
—
VDD_LV_COR = 1.32 V
IDD_LV_FULL
+ IDD_LV_PLL
T Operating current
mA
1.2 V supplies
80 mA+
2.50 mA*fCPU[MHz]
TJ = 150 °C
VDD_LV_COR = 1.32 V
—
—
—
—
—
—
—
—
—
—
1.2 V supplies
26 mA+
2.10 mA*fCPU[MHz]
TJ = ambient
VDD_LV_COR = 1.32 V
IDD_LV_TYP
T Operating current
mA
mA
(2)
+ IDD_LV_PLL
1.2 V supplies
41 mA+
2.30 mA*fCPU[MHz]
TJ = 150 °C
VDD_LV_COR = 1.32 V
1.2 V supplies
TJ = ambient
279 mA
318 mA
VDD_LV_COR = 1.32 V
IDD_LV_TYP
P Operating current
(2)
+ IDD_LV_PLL
1.2 V supplies
TJ = 150 °C
VDD_LV_COR = 1.32 V
1.2 V supplies during
LBIST (full LBIST
configuration)
—
—
—
—
250
290
TJ = ambient
VDD_LV_COR = 1.32 V
IDD_LV_BIST
+ IDD_LV_PLL
T Operating current
mA
1.2 V supplies during
LBIST (full LBIST
configuration)
TJ = 150 °C
VDD_LV_COR = 1.32 V
1.2V supplies
Tj=105C
IDD_LV_TYP
IDD_LV_PLL
+
T Operating current
T Operating current
—
—
—
—
275
299
mA
mA
VDD_LV_COR = 1.2V
1.2V supplies
Tj=125C
IDD_LV_TYP
IDD_LV_PLL
+
VDD_LV_COR = 1.2V
1.2V supplies
Tj=105C
IDD_LV_TYP
IDD_LV_PLL
+
T Operating current
T Operating current
—
—
—
—
189
214
mA
mA
VDD_LV_COR = 1.2V
DPM Mode
1.2V supplies
Tj=125C
IDD_LV_TYP
IDD_LV_PLL
+
VDD_LV_COR = 1.2V
DPM Mode
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Table 21. Current consumption characteristics (continued)
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
1.2V supplies
Tj=150C
IDD_LV_TYP
IDD_LV_PLL
+
T Operating current
—
—
253
mA
VDD_LV_COR = 1.2V
DPM Mode
TJ = ambient
T
—
—
—
—
—
—
—
—
—
—
—
—
50
57
72
58
64
80
VDD_LV_COR = 1.32 V
TJ = 55 °C
VDD_LV_COR = 1.32 V
Operating current in
VDD STOP mode
IDD_LV_STOP
T
mA
TJ = 150 °C
VDD_LV_COR = 1.32 V
P
T
TJ = ambient
VDD_LV_COR = 1.32 V
TJ = 55 °C
VDD_LV_COR = 1.32 V
Operating current in
VDD HALT mode
IDD_LV_HALT
T
mA
mA
TJ = 150 °C
VDD_LV_COR = 1.32 V
P
TJ = 150 °C
120 MHz
(3),
IDD_HV_ADC
T Operating current
—
—
—
—
—
—
10
3
ADC operating at
60 MHz
(4)
VDD_HV_ADC = 3.6 V
TJ = 150 °C
120 MHz
ADC operating at
60 MHz
VDD_HV_REF = 3.6 V
(4)
IDD_HV_AREF
T Operating current
mA
TJ = 150 °C
120 MHz
5
ADC operating at
60 MHz
VDD_HV_REF = 5.5 V
TJ = 150 °C
3.3 V supplies
120 MHz
IDD_HV_OSC T Operating current
—
—
—
—
900
4
μA
TJ = 150 °C
3.3 V supplies
120 MHz
IDD_HV_FLASH
T Operating current
mA
(5)
1. Devices configured for DPM mode, single core only with Core 0 executing typical code at 120 MHz from SRAM and Core 1
in reset. If core execution mode not specified, the device is configured for LSM mode with both cores executing typical code
at 120 MHz from SRAM.
2. Enabled Modules in 'Typical mode': FlexPWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1,
PIT, CRC, PLL0/1, I/O supply current excluded
3. Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum
injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.
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4. This value is the total current for both ADCs.
5. VFLASH is only available in the calibration package.
3.11
Temperature sensor electrical characteristics
Table 22. Temperature sensor electrical characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
—
P
D
Accuracy
Minimum sampling period
TJ = –40 °C to 150 °C
—
–10
4
10
—
°C
µs
TS
3.12
Main oscillator electrical characteristics
The device provides an oscillator/resonator driver. Figure 6 describes a simple model of the
internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
EXTAL
C
L
R
EXTAL
P
XTAL
EXTAL
XTAL
C
L
DEVICE
V
DD
I
R
XTAL
DEVICE
DEVICE
Figure 6.
Crystal oscillator and resonator connection scheme
Note:
XTAL/EXTAL must not be directly used to drive external circuits.
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MTRANS
1
0
V
XTAL
1/f
XOSCHS
V
XOSCHS
90%
10%
V
XOSCHSOP
T
valid internal clock
XOSCHSSU
Figure 7.
Main oscillator electrical characteristics
×
Table 23. Main oscillator electrical characteristics
Value
Typ
Symbol
Parameter
Conditions(1)
Unit
Max
Min
S
R
fXOSCHS
gmXOSCHS
Oscillator frequency
—
4.0
—
—
40.0
MHz
Oscillator
transconductance
P
D
VDD = 3.3 V 10%
4.5
13.25
mA/V
fOSC = 4, 8, 10, 12, 16 MHz
fOSC = 40 MHz
1.3
1.1
—
—
—
—
VXOSCHS
Oscillation amplitude
V
Oscillation operating
point
VXOSCHSOP
IXOSCHS
D
D
—
—
0.82
—
V
Oscillator consumption
—
—
—
—
—
—
—
3.5
6
mA
f
OSC = 4, 8, 10, 12 MHz(2)
TXOSCHSSU
T
Oscillator start-up time
ms
fOSC = 16, 40 MHz(2)
2
S
R
Input high level CMOS
Schmitt Trigger
0.65 × VD
VIH
VIL
Oscillator bypass mode
—
—
VDD + 0.4
V
V
D
S
R
Input low level CMOS
Schmitt Trigger
Oscillator bypass mode
–0.4
0.35 × VDD
1. VDD = 3.3 V 10%, TJ = –40 to +150 °C, unless otherwise specified.
2. The recommended configuration for maximizing the oscillator margin are:
XOSC_MARGIN = 0 for 4 MHz quartz
XOSC_MARGIN = 1 for 8/16/40 MHz quartz
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3.13
FMPLL electrical characteristics
Table 24. FMPLL electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
FMPLL reference
frequency range(1)
REF_CRYSTAL
fREF_EXT
D
Crystal reference
4
—
40
MHz
Phase detector input
fPLL_IN
D frequency range (after pre-
divider)
—
—
4
—
16
MHz
Clock frequency range in
normal mode
fFMPLLOUT
fFREE
D
4
—
—
—
120(2)
150
MHz
MHz
Measured using clock division
P Free running frequency
20
16
(typically ÷16)
On-chip FMPLL
fsys
D
—
120
MHz
ns
frequency(2)
tCYC
D System clock period
—
Lower limit
—
1.6
24
—
—
—
1 / fsys
3.7
fLORL
fLORH
Loss of reference
D
MHz
frequency window(3)
Upper limit
56
Self-clocked mode
fSCM
D
—
20
—
—
—
150
200
MHz
µs
frequency(4),(5)
Stable oscillator (fPLLIN = 4 MHz),
stable VDD
Lock time
P
tLOCK
tlpll
tdc
D FMPLL lock time (6), (7)
D Duty cycle of reference
—
—
—
—
—
200
60
μs
40
%
CLKOUT period
T
Long-term jitter (avg. over 2 ms
interval), fFMPLLOUT maximum
CJITTER
–6
—
—
—
—
—
—
—
—
—
6
ns
ps
ps
ps
jitter(8),(9),(10),(11)
PHI @ 120 MHz,
175
185
200
Input clock @ 4 MHz
PHI @ 100 MHz,
Single period jitter (peak to
peak)
ΔtPKJIT
T
Input clock @ 4 MHz
PHI @ 80 MHz,
Input clock @ 4 MHz
PHI @ 16 MHz,
ΔtLTJIT T Long term jitter
fLCK D Frequency LOCK range
fUL
fCS
6
6
ns
Input clock @ 4 MHz
—
–6
–18
0.25
–0.5
—
—
—
—
—
—
% fFMPLLOUT
D Frequency un-LOCK range
D Modulation depth
—
Center spread
Down spread
—
18 % fFMPLLOUT
2.0
-8.0
100
%
fDS
fFMPLLOUT
fMOD
D Modulation frequency(12)
kHz
1. Considering operation with FMPLL not bypassed.
2. With FM; the value does not include a possible +2% modulation
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Electrical characteristics
SPC56XL60/54
3. “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked
mode.
4. Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the
f
LOR window.
5. fVCO is the frequency at the output of the VCO; its range is 256–512 MHz.
f
f
SCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
SYS = fVCO÷ODF
6. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
FMPLL, load capacitors should not exceed these limits.
7. This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in
the synthesizer control register (SYNCR).
8. This value is determined by the crystal manufacturer and board design.
9. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER
percentage for a given interval.
10. Proper PC board layout procedures must be followed to achieve specifications.
11. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either
fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12. Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.
3.14
16 MHz RC oscillator electrical characteristics
Table 25. RC oscillator electrical characteristics
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
fRC
P
RC oscillator frequency
15.04
16
16.96 MHz
—
3.15
ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital
Converter.
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Electrical characteristics
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
(2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
(5)
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal
)
Offset Error OSE
Figure 8.
ADC characteristics and error definitions
3.15.1
Input Impedance and ADC Accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it
sources charge during the sampling phase, when the analog signal source is a high-
impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: C being substantially a switched capacitance, with a frequency
S
equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For
instance, assuming a conversion rate of 1 MHz, with C equal to 7.5 pF, a resistance of
S
133 kΩ is obtained (R = 1 / (f × C ), where fc represents the conversion rate at the
EQ
C
S
considered channel). To minimize the error induced by the voltage partitioning between this
resistance (sampled voltage on C ) and the sum of R + R , the external circuit must be
S
S
F
designed to respect the Equation 4:
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Electrical characteristics
Equation 4
SPC56XL60/54
R + R
S
F
1
2
--------------------
V •
< -- LSB
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on resistive
path. Internal switch resistances (R
resistances.
and R ) can be neglected with respect to external
SW
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
C
S
V
C
C
C
P2
A
F
P1
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 9.
Input Equivalent Circuit
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances C , C and C are initially charged at the source voltage V (refer to the
F
P1
P2
A
equivalent circuit reported in Figure 9): A charge sharing phenomenon is installed when the
sampling phase is started (A/D switch close).
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Electrical characteristics
Voltage Transient on CS
V
CS
V
A
ΔV < 0.5 LSB
V
A2
1
2
τ1 < (RSW + RAD) CS << TS
V
A1
τ2 = RL (CS + CP1 + CP2)
T
t
S
Figure 10. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
●
A first and quick charge transfer from the internal capacitance C and C to the
P1 P2
sampling capacitance C occurs (C is supposed initially completely discharged):
S
S
considering a worst case (since the time constant in reality would be faster) in which
C
is reported in parallel to C (call C = C + C ), the two capacitances C and
P2
P1 P P1 P2 P
C are in series, and the time constant is
S
Equation 5
C • C
P
S
---------------------
τ = (R
+ R
) •
1
SW
AD
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst
S
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time T is always much
S
longer than the internal time constant:
Equation 6
τ < (R
+ R
) • C « T
S S
1
SW
AD
The charge of C and C is redistributed also on C , determining a new value of the
P1
P2
S
voltage V on the capacitance according to Equation 7:
A1
Equation 7
V
• (C + C + C ) = V • (C + C
P1 P2 P1
)
P2
A1
S
A
●
A second charge transfer involves also C (that is typically bigger than the on-chip
F
capacitance) through the resistance R : again considering the worst case in which C
L
P2
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Electrical characteristics
SPC56XL60/54
and C were in parallel to C (since the time constant in reality would be faster), the
S
P1
time constant is:
Equation 8
τ < R • (C + C + C )
P2
2
L
S
P1
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time T , a constraints on
S
R sizing is obtained:
L
Equation 9
10 • τ = 10 • R • (C + C + C ) < T
P1 P2 S
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in
L
combination with R (source impedance) and R (filter resistance). Being C
S
F
F
definitively bigger than C , C and C , then the final voltage V (at the end of the
P1
P2
S
A2
charge transfer transient) will be much higher than V . Equation 10 must be respected
A1
(charge balance assuming now C already charged at V ):
S
A1
Equation 10
V
• (C + C + C + C ) = V • C + V • (C + C + C )
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence
of the R C filter, is not able to provide the extra charge to compensate the voltage drop on
F
F
C with respect to the ideal source V ; the time constant R C of the filter is very high with
S
A
F F
respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
Analog Source Bandwidth (V )
A
T
f
≤ 2 R C (Conversion Rate vs. Filter Pole)
F F
C
Noise
= f (Anti-aliasing Filtering Condition)
F
0
2 f ≤ f (Nyquist)
0
C
f
0
f
Anti-Aliasing Filter (f = RC Filter pole)
Sampled Signal Spectrum (f = conversion Rate)
C
F
f
f
f
C
F
0
f
f
Figure 11. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of
0
the anti-aliasing filter, f ), according to the Nyquist theorem the conversion rate f must be at
F
C
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Electrical characteristics
least 2f ; it means that the constant time of the filter is greater than or at least equal to twice
0
the conversion period (T ). Again the conversion period T is longer than the sampling time
C
C
T , which is just a portion of it, even when fixed channel continuous conversion mode is
S
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter R C is definitively much higher than the sampling time T , so the
F
F
S
charge level on C cannot be modified by the analog signal source during the time in which
S
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on C ; from the two charge balance equations
S
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on C :
S
Equation 11
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
V
C
+ C + C + C
A2
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V),
A
assuming to accept a maximum error of half a count, a constraint is evident on C value:
F
Equation 12
C
> 8192 • C
F
S
Table 26. ADC conversion characteristics
Symbol
Parameter
Conditions(1)
Min Typ Max Unit
ADC Clock frequency (depends on ADC
configuration)
S
R
fCK
—
3
—
60
MHz
(2)
(The duty cycle depends on AD_CK
frequency)
S
R
983.6
fs
Sampling frequency
—
—
—
KHz
(3)
tsample
tconv
D Sample time(4)
60 MHz
60 MHz
383
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
D Conversion time(5)
(6)
CS
D ADC input sampling capacitance
D ADC input pin capacitance 1
D ADC input pin capacitance 2
—
—
—
7.32
5((7))
0.8
0.3
875
825
3
pF
(6)
CP1
—
pF
(6)
CP2
—
pF
VREF range = 4.5 to 5.5 V
—
kΩ
(6)
RSW1
D Internal resistance of analog source
VREF range = 3.0 to 3.6 V
—
W
(6)
RAD
D Internal resistance of analog source
P Integral non linearity
P Differential non linearity(8)
T Offset error
—
—
—
—
—
—
W
INL
DNL
OFS
GNE
–3
–1
–6
–6
LSB
LSB
LSB
LSB
2
6
T Gain error
6
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Electrical characteristics
SPC56XL60/54
Table 26. ADC conversion characteristics (continued)
Symbol
Parameter
Conditions(1)
Min Typ Max Unit
(single ADC channel)
150C
IS1WINJ
Max leakage
—
—
—
250
3
nA
Max positive/negative injection
–3
mA
(double ADC channel)
150C
Max leakage
—
—
—
300
3.6
nA
IS1WWINJ
|Vref_ad0 - Vref_ad1| <
150mV
Max positive/negative injection
–3.6
mA
SNR
SNR
T Signal-to-noise ratio
Vref = 3.3V
Vref = 5.0V
67
69
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
dB
dB
T Signal-to-noise ratio
THD
T Total harmonic distortion
T Signal-to-noise and distortion
T Effective number of bits
—
-65
65
dB
SINAD
ENOB
—
dB
—
10.5
–6
bits
LSB
LSB
LSB
LSB
Without current injection
With current injection
Without current injection
With current injection
Total unadjusted error for IS1WINJ (single
ADC channels)
TUEIS1WINJ
T
–8
8
P
–8
8
Total unadjusted error for IS1WWINJ
TUEIS1WWINJ
(double ADC channels)
T
–10
10
1. VDD = 3.3 V, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF
.
2. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3. This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is
not possible.
4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the
sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tsample depend on programming.
5. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
6. See Figure 9.
7. For the 144-pin package
8. No missing codes
3.16
Flash memory electrical characteristics
Table 27. Flash memory program and erase electrical specifications
Initial
Typ Factory
Lifetime
Max(3)
No.
Symbol
Parameter
Max
Unit
(1)
Avg
(2)
(4)
(5)
(5)
(5)
1
2
3
4
TDWPROGRAM
TPPROGRAM
T16KPPERASE
T48KPPERASE
*
*
*
*
Double word (64 bits) program time(4)
Page(128 bits) program time(5)
38
45
—
—
500
500
µs
µs
53
160
16 KB block pre-program and erase time
48 KB block pre-program and erase time
270 1000 500 5000
625 1500 750 5000
ms
ms
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Electrical characteristics
Initial
Table 27. Flash memory program and erase electrical specifications
Typ Factory
Lifetime
Max(3)
No.
Symbol
Parameter
Max
Unit
(1)
Avg
(2)
(5)
(5)
(5)
5
6
7
T64KPPERASE
T128KPPERASE
T256KPPERASE
*
*
*
64 KB block pre-program and erase time
128 KB block pre-program and erase time
256 KB block pre-program and erase time
800 1800 900
5000
ms
ms
ms
1500 2600 1300 7500
3000 5200 2600 15000
1. Typical program and erase times represent the median performance and assume nominal supply values and
operation at 25C. These values are characterized, but not tested.I
2. Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for <
100 program/erase cycles, nominal supply values and operation at 25C. These values are verified at production
test.
3. Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product
life. These values are characterized, but not tested.
4. Program times are actual hardware programming times and do not include software overhead.
5. Program times are actual hardware programming times and do not include software overhead.
Table 28. Flash memory timing
Value
Symbol
Parameter
Unit
Min
Typ
Max
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low
TRES
TDONE
TPSRT
TESRT
D
D
D
D
—
—
100
ns
ns
µs
ms
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared
—
100
10
—
—
5
Time between program suspend resume and the next program
suspend request.(1)
—
Time between erase suspend resume and the next erase
suspend request.(2)
1. Repeated suspends at a high frequency may result in the operation timing out, and the flash module will
respond by completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish
(MCR[DONE] = 1 during Program operation). The minimum time between suspends to ensure this does not
occur is TPSRT
.
2. If Erase suspend rate is less than TESRT, an increase of slope voltage ramp occurs
during erase pulse. This improves erase time but reduces cycling figure due to
overstress
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Electrical characteristics
SPC56XL60/54
Table 29. Flash memory module life
Value
Minimum Typical Maximum
No. Symbol
Parameter
Unit
Number of program/erase cycles per block for 16 KB,
1
2
P/E
P/E
C 48 KB, and 64 KB blocks over the operating temperature 100000
—
—
—
cycles
cycles
range(1)
Number of program/erase cycles per block for 128 KB
C and 256 KB blocks over the operating temperature
1000
100000(2)
range(1)
Minimum data retention at 85 °C average ambient
temperature(3)
20
10
5
—
—
—
—
—
—
Blocks with 0–1,000 P/E cycles
3 Retention C
years
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
1. Operating temperature range is TJ from –40 °C to 150 °C. Typical endurance is evaluated at 25 °C.
2. Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks.
3. Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
3.17
SWG electrical characteristics
Table 30. MPC5643L SWG Specifications
Value
Symbol Parameter
Minimum
Typical
Maximum
T
T
T
T
T
T
T
T
T
T
Input clock
12 MHz
1kHz
0.4 V
-6%
16 MHz
—
20 MHz
50 kHz
2.0V
6%
Frequency Range
Peak to Peak(1)
Peak to Peak variation(2)
Common Mode(3)
Common Mode variation
SiNAD(4)
—
—
—
1.3 V
—
—
-6%
6%
45 dB
25 pF
0 µA
230 Ω
—
—
Load C
—
100 pF
100 µA
360 Ω
Load I
—
ESD Pad Resistance(5)
—
1. Peak to Peak value is measured with no R or I load.
2. Peak to Peak excludes noise, SiNAD must be considered.
3. Common mode value is measured with no R or I load.
4. SiNAD is measured at Max Peak to Peak voltage.
5. Internal device routing resistance. ESD pad resistance is in series and must be considered for max Peak to Peak voltages,
depending on application I load and/or R load.
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Electrical characteristics
3.18
AC specifications
3.18.1
Pad AC specifications
(1)
Table 31. Pad AC specifications (3.3 V , IPP_HVE = 0 )
Tswitchon(1)
(ns)
Rise/Fall(2)
(ns)
Frequency
(MHz)
Current slew(3)
(mA/ns)
Load drive
(pF)
No.
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
3
3
3
3
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
40
40
40
40
15
15
15
15
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
50
75
100
12
25
40
70
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
2
0.01
0.01
0.01
0.01
2.5
2.5
2.5
2.5
3
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
25
50
1
Slow
T
T
2
2
100
200
25
2
2
40
20
13
7
7
7
50
2
Medium
7
100
200
25
7
72
55
40
25
50
40
40
40
40
25
6
7
7
50
3
4
Fast
T
T
6
12
18
5
7
100
200
25
6
7
Symmetric
8
3
1. Propagation delay from VDD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition.
2. Slope at rising/falling edge.
3. Data based on characterization results, not tested in production.
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Electrical characteristics
SPC56XL60/54
VDDE/2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
Pad
Output
VOL
Figure 12. Pad output delay
3.19
Reset sequence
This section shows the duration for different reset sequences. It describes the different reset
sequences and it specifies the start conditions and the end indication for the reset
sequences.
3.19.1
Reset sequence duration
Table 32 specifies the minimum and the maximum reset sequence duration for the five
different reset sequences described in Section 3.19.2, Reset sequence description.
Table 32. RESET sequences
TReset
No.
Symbol
Parameter
Conditions
Unit
Min
Typ Max(1)
Destructive Reset Sequence, BIST
enabled
1
2
3
TDRB
CC
CC
CC
40
47
51
ms
µs
Destructive Reset Sequence, BIST
disabled
TDR
—
500
41
4200 5000
External Reset Sequence Long, BIST
enabled
TERLB
45
49
ms
4
5
TFRL
TFRS
CC Functional Reset Sequence Long
CC Functional Reset Sequence Short
—
—
35
1
150
4
400
10
µs
µs
1. The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.
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Electrical characteristics
3.19.2
Reset sequence description
The figures in this section show the internal states of the chip during the five different reset
sequences. The doted lines in the figures indicate the starting point and the end point for
which the duration is specified in Table 32. The start point and end point conditions as well
as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3,
Reset sequence trigger mapping.
With the beginning of DRUN mode the first instruction is fetched and executed. At this point
application execution starts and the internal reset sequence is finished.
The figures below show the internal states of the chip during the execution of the reset
sequence and the possible states of the signal pin RESET.
Note:
RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an
external reset generator or by the chip internal reset circuitry. A high level on this pin can
only be generated by an external pull up resistor which is strong enough to overdrive the
weak internal pull down resistor. The rising edge on RESET in the following figures indicates
the time when the device stops driving it low. The reset sequence durations given in table
Table 32 are applicable only if the internal reset sequence is not prolonged by an external
reset generator keeping RESET asserted low beyond the last PHASE3.
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Establish IRC
and PWR
Device
Config
Self Test
Setup
Device
Config
Application
Execution
Flash init
MBIST
LBIST
Flash init
TDRB, min < TReset < TDRB, max
Figure 13. Destructive Reset Sequence, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
DRUN
Establish IRC
and PWR
Device
Config
Application
Execution
Flash init
TDR, min < TReset < TDR, max
Figure 14. Destructive Reset Sequence, BIST disabled
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Electrical characteristics
SPC56XL60/54
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Device
Config
Self Test
Setup
Device
Config
Application
Execution
Flash init
MBIST
LBIST
Flash init
TERLB, min < TReset < TERLB, max
Figure 15. External Reset Sequence Long, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
DRUN
Device
Config
Application
Execution
Flash init
TFRL, min < TReset < TFRL, max
Figure 16. Functional Reset Sequence Long
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE3
DRUN
Application
Execution
TFRS, min < TReset < TFRS, max
Figure 17. Functional Reset Sequence Short
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Electrical characteristics
The reset sequences shown in Figure 16 and Figure 17 are triggered by functional reset
events. RESET is driven low during these two reset sequences only if the corresponding
functional reset source (which triggered the reset sequence) was enabled to drive RESET
(c)
low for the duration of the internal reset sequence .
3.19.3
Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences. It
specifies the reset sequence start conditions as well as the reset sequence end indications
that are the basis for the timing data provided in Table 32.
Table 33. Reset sequence trigger — reset sequence
Reset Sequence
Reset
Sequence
Reset
Sequence
Start
External
Reset
Sequenc
e Long,
BIST
Reset
Sequence
Trigger
Destructiv
e Reset
Sequence, Sequence,
Destructiv
e Reset
Functiona Functiona
l Reset
Sequenc
e Long
l Reset
Sequenc
e Short
End
Indication
Condition
BIST
BIST
enabled(1)
disabled(1)
enabled
All internal
destructivereset
sources
Section ,
Destructive
reset
cannot
trigger
cannot
trigger
cannot
trigger
(LVDs or
triggers
internal HVD
during power-up
and during
operation)
Release of
RESET(2)
Section ,
External
reset via
RESET
Assertion of
RESET(3)
cannot trigger
cannot trigger
triggers(4) triggers(5) triggers(6)
All internal
functional reset
sources
configured for
long reset
cannot
trigger
cannot
trigger
triggers
Sequence
starts with
internal
reset
Release of
RESET(7)
All internal
functional reset
sources
configured for
short reset
trigger
cannot
trigger
cannot
trigger
cannot trigger
triggers
1. Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.
2. End of the internal reset sequence (as specified in Table 32) can only be observed by release of RESET if it is not held low
externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till RESET is released
externally.
c. See RGM_FBRE register for more details.
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Electrical characteristics
SPC56XL60/54
3. The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before. RESET
does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST disabled. However, it
can prolong these sequences if RESET is held low externally beyond the end of the internal sequence (beyond PHASE3).
4. If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the shadow sector
of the NVM.
5. If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the shadow
sector of the NVM.
6. If RESET is configured for short reset
7. Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for the
functional reset source which triggered the reset sequence.
3.19.4
Reset sequence — start condition
The impact of the voltage thresholds on the starting point of the internal reset sequence are
becoming important if the voltage rails / signals ramp up with a very slow slew rate
compared to the overall reset sequence duration.
Destructive reset
Figure 18 shows the voltage threshold that determines the start of the Destructive Reset
Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled.
V
Supply Rail
Vmax
Vmin
t
TReset, max starts here
TReset, min starts here
Figure 18. Reset sequence start for Destructive Resets
Table 34. Voltage Thresholds
Variable name
Value
Refer to Table 19
Vmin
Refer to Table 19
Vmax
Supply Rail
VDD_HV_PMU
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Electrical characteristics
External reset via RESET
Figure 19 shows the voltage thresholds that determine the start of the reset sequences
initiated by the assertion of RESET as specified in Table 33.
V
RESET
0.65 * VDD_HV_IO
0.35 * VDD_HV_IO
t
TReset, max starts here
TReset, min starts here
Figure 19. Reset sequence start via RESET assertion
3.19.5
External watchdog window
If the application design requires the use of an external watchdog the data provided in
Section 3.19, Reset sequence can be used to determine the correct positioning of the
trigger window for the external watchdog. Figure 20 shows the relationships between the
minimum and the maximum duration of a given reset sequence and the position of an
external watchdog trigger window.
Watchdog needs to be triggered within this window
TWDStart, min
External Watchdog Window Closed
TWDStart, max
External Watchdog Window Open
External Watchdog Window Closed
External Watchdog Window Open
Watchdog trigger
Basic Application Init
TReset, min
Application Running
Basic Application Init
TReset, max
Application Running
Application time required to
prepare watchdog trigger
Earliest
Application
Start
Latest
Application
Start
Internal Reset Sequence
Start condition (signal or voltage rail)
Figure 20. Reset sequence - External watchdog trigger window position
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Electrical characteristics
SPC56XL60/54
3.20
AC timing characteristics
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows:
• TJ = –40 to 150 C
• Supply voltages as specified in Table 10
• Input conditions: All Inputs: tr, tf = 1 ns
• Output Loading: All Outputs: 50 pF
3.20.1
RESET pin characteristics
The SPC56XL60/54 implements a dedicated bidirectional RESET pin.
VDD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 21. Start-up reset requirements
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 22. Noise filtering on reset signal
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Electrical characteristics
Table 35. RESET electrical characteristics
No. Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
CL = 25pF
CL = 50pF
CL = 100pF
—
—
—
—
—
—
—
—
12
25
40
40
—
Output transition time output
pin(2)
1
Ttr
D
ns
—
2
3
WFRST P nRESET input filtered pulse
—
ns
ns
WNFRST P nRESET input not filtered pulse
—
500
1. VDD = 3.3 V 10%, TJ = –40 to +150 °C, unless otherwise specified
2. CL includes device and package capacitance (CPKG < 5 pF).
3.20.2
WKUP/NMI timing
Table 36. WKUP/NMI glitch filter
No.
Symbol
WFNMI
WNFNMI
Parameter
Min
Typ
Max
Unit
1
2
D
D
NMI pulse width that is rejected
NMI pulse width that is passed
—
—
—
45
—
ns
ns
205
3.20.3
IEEE 1149.1 JTAG interface timing
Table 37. JTAG pin AC electrical characteristics
No.
Symbol
Parameter
Conditions
Min Max Unit
1
2
tJCYC
tJDC
D
D
D
D
D
D
D
D
D
D
D
D
D
TCK cycle time
—
—
—
—
—
—
—
—
—
—
—
—
—
62.5
—
ns
%
TCK clock pulse width (measured at VDDE/2)
TCK rise and fall times (40%–70%)
TMS, TDI data setup time
40 60
3
tTCKRISE
—
5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
tTMSS, TDIS
TMSH, tTDIH
tTDOV
tTDOI
tTDOHZ
tBSDV
t
—
—
20
—
20
50
50
50
—
—
5
t
TMS, TDI data hold time
25
—
0
6
TCK low to TDO data valid
7
TCK low to TDO data invalid
8
TCK low to TDO high impedance
—
—
—
—
50
50
11
12
13
14
15
TCK falling edge to output valid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
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Electrical characteristics
SPC56XL60/54
TCK
2
3
3
2
1
Figure 23. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 24. JTAG test access port timing
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Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 25. JTAG boundary scan timing
3.20.4
Nexus timing
(1)
Table 38. Nexus debug port timing
No.
Symbol
Parameter
Conditions Min Max Unit
1
2
tMCYC
tMDC
D
D
MCKO Cycle Time
MCKO Duty Cycle
—
—
15.6
40
—
ns
%
60
tMCY
3
4
5
tMDOV
tEVTIPW
tEVTOPW
D
D
D
MCKO Low to MDO, MSEO, EVTO Data Valid(2)
—
—
—
–0.1 0.25
C
tTCY
EVTI Pulse Width
4.0
1
—
C
tMCY
EVTO Pulse Width
C
6
7
tTCYC
tTDC
tNTDIS,
D
D
TCK Cycle Time(3)
TCK Duty Cycle
—
—
62.5
40
—
ns
%
60
8
D
TDI, TMS Data Setup Time
—
8
—
ns
tNTMSS
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Electrical characteristics
SPC56XL60/54
(1)
Table 38. Nexus debug port timing
(continued)
Parameter
No.
Symbol
Conditions Min Max Unit
tNTDIH,
tNTMSH
9
D
D
TDI, TMS Data Hold Time
5
0
—
ns
ns
10
tJOV
TCK Low to TDO/RDY Data Valid
25
1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured
from 50% of MCKO and 50% of the respective signal.
2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3. The system clock frequency needs to be four times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
Figure 26. Nexus output timing
4
EVTI
Figure 27. Nexus EVTI Input Pulse Width
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Electrical characteristics
MCKO
MDO, MSEO
MDO/MSEO data are valid during MCKO rising and falling edge
Figure 28. Nexus Double Data Rate (DDR) Mode output timing
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Electrical characteristics
SPC56XL60/54
6
7
TCK
8
9
TMS, TDI
10
TDO/RDY
Figure 29. Nexus TDI, TMS, TDO timing
3.20.5
External interrupt timing (IRQ pin)
Table 39. External interrupt timing
No.
Symbol
Parameter
IRQ pulse width low
Conditions
Min
Max Unit
1
2
3
tIPWL
tIPWH
tICYC
D
—
—
—
3
3
6
—
—
—
tCYC
tCYC
tCYC
D
D
IRQ pulse width high
IRQ edge to edge time(1)
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
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Electrical characteristics
IRQ
1
2
3
Figure 30. External interrupt timing
3.20.6
DSPI timing
Table 40. DSPI timing
No. Symbol
Parameter
Conditions
Min
Max
Unit
D
Master (MTFE = 0)
62
62
16
16
16
—
—
—
—
—
1
tSCK
D
D
D
D
D
D
DSPI cycle time
Slave (MTFE = 0)
ns
Slave Receive Only Mode(1)
2
3
4
5
tCSC
tASC
tSDC
tA
PCS to SCK delay
After SCK delay
SCK duty cycle
—
ns
ns
—
—
tSCK/2 - 10 tSCK/2 + 10 ns
Slave access time
SS active to SOUT valid
—
—
40
10
ns
ns
SS inactive to SOUT High-Z or
invalid
6
tDIS
D
Slave SOUT disable time
7
8
tPCSC
tPASC
D
D
PCSx to PCSS time
PCSS to PCSx time
—
—
13
13
20
2
—
—
—
—
—
—
—
—
—
—
4
ns
ns
Master (MTFE = 0)
Slave
9
tSUI
D
D
D
Data setup time for inputs
Data hold time for inputs
Data valid (after SCK edge)
ns
ns
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
5
20
–5
4
10 tHI
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
11
–5
—
—
—
—
23
12
4
11 tSUO
ns
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
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Electrical characteristics
SPC56XL60/54
Table 40. DSPI timing (continued)
No. Symbol
Parameter
Conditions
Master (MTFE = 0)
Min
Max
Unit
–2
6
—
—
—
—
Slave
12 tHO
D
Data hold time for outputs
ns
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
6
–2
1. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on
SIN, but no valid data is transmitted on SOUT.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
First Data
Data
Data
12
11
Last Data
SOUT
The numbers shown are referenced in Table 40.
Figure 31. DSPI classic SPI timing — master, CPHA = 0
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Electrical characteristics
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
The numbers shown are referenced in Table 40.
Figure 32. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
The numbers shown are referenced in Table 40.
Figure 33. DSPI classic SPI timing — slave, CPHA = 0
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Electrical characteristics
SPC56XL60/54
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
The numbers shown are referenced in Table 40.
Figure 34. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
The numbers shown are referenced in Table 40.
Figure 35. DSPI modified transfer format timing — master, CPHA = 0
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Electrical characteristics
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
The numbers shown are referenced in Table 40.
Figure 36. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
The numbers shown are referenced in Table 40.
Figure 37. DSPI modified transfer format timing – slave, CPHA = 0
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Electrical characteristics
SPC56XL60/54
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
The numbers shown are referenced in Table 40.
Figure 38. DSPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
The numbers shown are referenced in Table 40.
Figure 39. DSPI PCS strobe (PCSS) timing
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Package characteristics
4
Package characteristics
4.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
4.2
Package mechanical data
Figure 40. LQFP100 package mechanical drawing
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Package characteristics
SPC56XL60/54
Table 41. LQFP100 mechanical data
mm
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
—
0.050
1.350
0.170
0.090
15.800
13.800
—
—
1.600
0.150
1.450
0.270
0.200
16.200
14.200
—
—
—
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
—
A1
—
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
—
—
A2
1.400
0.220
—
0.0551
0.0087
—
b
c
D
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5 °
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5 °
D1
D3
E
15.800
13.800
—
16.200
14.200
—
0.6220
0.5433
—
0.6378
0.5591
—
E1
E3
e
—
—
—
—
L
0.450
—
0.750
—
0.0177
—
0.0295
—
L1
k
0.0 °
7.0 °
0.0 °
7.0 °
Tolerance
ccc
mm
inches
0.0031
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 41. LQFP144 package mechanical drawing
Table 42. LQFP144 mechanical data
mm
inches(1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.6
0.15
1.45
0.27
0.2
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
0.05
1.35
0.17
0.09
21.8
19.8
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
1.4
0.0551
0.0087
0.22
c
D
22
20
22.2
20.2
0.8661
0.7874
0.6890
0.8661
D1
D3
E
17.5
22
21.8
22.2
0.8583
0.8740
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Package characteristics
SPC56XL60/54
Table 42. LQFP144 mechanical data (continued)
mm
inches(1)
Symbol
Typ
Min
Max
Typ
Min
Max
E1
20
17.5
0.5
0.6
1
19.8
20.2
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
0.7795
0.7953
E3
e
L
0.45
0.75
7.0°
0.0177
0.0295
7.0°
L1
k
3.5°
0.0°
mm
0.08
0.0°
Tolerance
ccc
inches
0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
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Package characteristics
Figure 42. LFBGA257 package mechanical drawing
Table 43. LFBGA257 mechanical data
Doc ID 15457 Rev 8
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Package characteristics
SPC56XL60/54
TITLE: LFBGA 14x14x1.7 257 F17x17 PITCH 0.8 BALL 0.4
PACKAGE CODE:
JEDEC/EIAJ REFERENCE NUMBER: JEDEC STANDARD NO.95 SECTION 4.5
(Fine pitch, Square Ball Grid Array Package Design Guide)
DIMENSIONS
DATABOOK
(mm)
DRAWING
(mm)
REF.
MIN.
0.21
TYP.
MAX.
1.70
MIN.
TYP.
MAX.
NOTES
(1)
A
A1
A2
A3
A4
b
D
D1
E
1.45
0.35
1.14
0.34
0.80
0.45
14.15
0.25
1.03
0.26
0.77
0.35
13.85
0.30
1.085
0.30
0.785
0.40
14.00
12.80
14.00
12.80
0.80
1.085
0.30
0.80
0.45
14.15
0.35
13.85
0.40
14.00
12.80
14.00
12.80
0.80
(2)
13.85
14.15
13.85
14.15
E1
e
F
0.6
0.6
ddd
eee
fff
0.12
0.15
0.08
0.12
0.15
0.08
(3)
(4)
NOTES:
(1) - LFBGA stands for Low profile Fine Pitch Ball Grid Array.
- Low Profile: The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A2 Typ+A1 Typ +¥ (A1²+A3²+A4² tolerance values)
- Low profile: 1.20mm < A 1.70mm / Fine pitch: e < 1.00mm pitch.
(2) – The typical ball diameter before mounting is 0.40mm.
(3) - The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position
with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie
within this tolerance zone.
(4) - The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above
The axis of each ball must lie simultaneously in both tolerance zones.
(5) - The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metallized markings, or other feature of package body or integral heatslug.
- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
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Ordering information
5
Ordering information
(d)
Figure 43. Commercial product code structure
Example code:
Product identifier Core Family Memory Package Temperature Device options Conditioning
SPC56
E
L
60
L5
C
Y
B
F
Q
Y = Tray
R = Tape and Reel
Q = Quality management safety level
S = ASILD/SIL3 safety level
O = No FlexRay
F = FlexRay
C = 80 MHz
B = 120 MHz
B = –40 °C to 105 °C
C = –40 °C to 125 °C
L3 = LQFP100
L5 = LQFP144
60 = 1 MB flash memory
54 = 768 K flash memory
L = SPC56XL family
E = e200z4d dual core
4 = Single core
SPC56 = Power Architecture in 90 nm
d. Not all configurations are available on the market. Please contact your ST Sales Rappresentative to get the list of orderable
commercial part number.
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Revision history
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6
Revision history
Table 44. Document revision history
Date
Revision
Changes
02-Mar-2009
1
Initial release.
Updated, Advance Information.
05-May-2009
2
– Revised SINAD/SNR specifications.
– Updated pinout and pin multiplexing information.
Updated, Advance Information, Public release.
– Throughout this document, added information for LFBGA257 package.
– Updated feature summary.
– Updated Table 1, SPC56XL60/54 device summary.
– Updated Section 1.3, Feature Details.
– Updated pin-out and pin multiplexing tables.
– In Section 3, Electrical characteristics, added symbols for signal
characterization methods.
– In Table 9, updated maximum ratings.
29-Oct-2009
3
– In Table 12 and Table 13, removed moving-air thermal characteristics.
– Updated Section 3.8, Voltage regulator electrical characteristics.
– Updated Section 3.14, ADC electrical characteristics.
– Updated Section 3.15, Flash memory electrical characteristics.
– Updated Section 3.17.1, RESET pin characteristics.
– Removed External interrupt timing (IRQ pin) timing specifications.
– Updated Section 3.17.6, DSPI timing.
Updated Section 5, Ordering information.
Editorial changes and improvements.
Revised the 257-pin package pin pitch (was 1.4 mm, is 0.8 mm).
Added information about the 100-pin LQFP.
In the Overview section:
– Renamed the peripheral bridge to “PBRIDGE”.
– Revised the information for FlexRay.
– Revised the “Clock, reset, power, mode and test control module” section.
– Revised the “Platform memory access time summary” table and replaced
TBDs by meaningful values.
14-Jun-2010
4
Extensive revisions to signal descriptions and pin muxing information.
In the “Recommended operating conditions (3.3 V)” table, changed the
specification for VDD_HV_ADR0 and VDD_HV_ADR1 (was “...3.3 V”, is “...3.6 V”).
Revised the “EMI testing specifications” table.
In the “HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical
specifications” table, added a specification for the digital low voltage detector
upper threshold.
Revised the “FMPLL electrical characteristics” table.
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Revision history
Table 44. Document revision history (continued)
Date
Revision
Changes
In the “Main oscillator electrical characteristics” table, changed the maximum
specification for gmXOSCHS (was 11 mA/V, is 11.8 mA/V).
Revised the “ADC electrical characteristics” section.In the “ADC conversion
characteristics” table:
4
14-Jun-2010
– Changed the tADC_S specification (was TBD, is minimum of 383 ns).
– Added the footnote “No missing codes” to the DNL specification.
– Added specifications for SNR, THD, SINAD, and ENOB.
Revised the “Ordering information” section.
(continued)
Editorial changes and improvements.
Revised the Overview section.
Replaced references to PowerPC with references to Power Architecture.
In the feature summary, changed “As much as 128 KB on-chip SRAM” to
“128 KB on-chip SRAM”.
In the “Feature details” section:
– In the “On-chip SRAM with ECC” section, added information about required
RAM wait states.
– In the PIT section, deleted “32-bit counter for real time interrupt, clocked from
main external oscillator” (not supported on this device).
– In the flash-memory section, changed “16 KB Test” to “16 KB test sector”,
revised the wait state information, and deleted the associated Review_Q&A
content.
– In the SRAM section, revised the wait state information.
In the 100-pin pinout diagram:
– Renamed pin 41 (was VDD_HV_ADV0_ADV1, is VDD_HV_ADV).
– Renamed pin 42 (was VSS_HV_ADV0_ADV1, is VSS_HV_ADV).
In the 144-pin pinout diagram:
– Renamed pin 58 (was VDD_HV_ADV0_ADV1, is VDD_HV_ADV).
– Renamed pin 59 (was VSS_HV_ADV0_ADV1, is VSS_HV_ADV).
Added the “LQFP100 pin function summary” table.
23-Nov-2010
5
In the “LQFP144 pin function summary” table, for pin 39, changed VSS_LV_COR
to VDD_LV_COR
.
In the “Supply pins” table:
– Changed the description for VDD_LV_COR (was “Voltage regulator supply
voltage”, is “Core logic supply”).
– Changed the description for VDD_HV_PMU (was “Core regulator supply”, is
“Voltage regulator supply”).
In the “Pin muxing” table:
– In the “Pad speed” column headings, changed “SRC = 0” to “SRC = 1” and
“SRC = 1” to “SRC = 0”
– For port B[6], changed the pad speed for SRC=0 (was M, is F).
In the “Thermal characteristics” section, added meaningful values to the
thermal-characteristics tables.
Added the “SWG electrical specifications” section.
In the “Voltage regulator electrical characteristics” section, changed the table
title (was “HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD
electrical specifications”, is “Voltage regulator electrical characteristics”) and
revised the table.
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Table 44. Document revision history (continued)
Date
Revision
Changes
In the “BCP68 board schematic example” figure, removed the resistor at the
base of the BCP68 transistor.
In the “DC electrical characteristics” table:
– Changed the guarantee parameter for IINJ (was P, is T).
– Added a specification for input leakage current for shared ADC input-only
ports.
Revised the “Flash memory module life” table.
In the “FMPLL electrical characteristics” table, revised the footnote defining
fSCM and fVCO
.
In the “Main oscillator electrical characteristics” table:
– Changed the max specification for gmXOSCHS (was 11.8 mA/V, is 13.25
mA/V).
5
23-Nov-2010
(continued)
– Revised the conditions for TXOSCHSSU
.
In the ‘RC oscillator electrical characteristics” table, deleted the specification
for ΔRCMTRIM
.
Revised the “ADC conversion characteristics” table.
In the “RESET pin characteristics” section, changed “nRSTIN” to “RESET”.
Added the “Reset sequence” section.
Revised the footnotes in the “Nexus debug port timing” table.
Added the mechanical drawing for the 100-pin package.
In the “Order codes” table, added a footnote about frequency modulation to the
“Speed (MHz)” column heading.
Editorial changes.
In the “Document overview” section, added information about how content
specific to silicon versions (“cut1” and “cut2”) is presented.
In the isometric miniature package drawings on the front page, removed the
third dimension.
Changed Symbol from P to D for “Conversion Time” in “ADC conversion
characteristics” table.
Added classification symbol “D” to seven entries in “Voltage regulator electrical
specifications“ table.
Removed irrelevant Flexcan specs.
Updated Table “Voltage Thresholds” to reference values specified in Table
“Voltage Regulator Electrical Specifications”.
RDY pin added for cut2.
23-Mar-2011
6
In the “System pins” table, added a footnote about the MDO0 pad speed.
Updated Rsw1 values.
Added TUE-related spec information for single and double ADC channels.
Added AC Test Timing Conditions to the “AC timing characteristics” section.
Added a statement on the first page describing cut1 versus cut2.
Moved the first paragraph from the “Description” section to the beginning of the
“Document overview” section.
Changed pad speed from “M” to “SYM” for FlexRay pins in the “Pin Muxing”
table and added this pad type to the footnote.
Moved the newly added device current specification entries from the “DC
electrical characteristics“ table into a newly created “Supply current
characteristics“ table.
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Revision history
Table 44. Document revision history (continued)
Date
Revision
Changes
Added symbol “CC” to the description in the “Introduction” section.
Updated “Input leakage current” specs in the “DC electrical characteristics”
table.
Changed TADC_S to Tsample and TADC_C toTconv in the “ADC conversion
characteristics” table and footnotes.
Removed “IINJ” from the “ADC conversion characteristics” table as this is
included in IS1WIKNJ and IS1WWiNJ.
Changed RESET_B to RESET in the "Reset sequence" section.
Added the “Flash memory timing” table.
Added cut2 specs for TDRB and TERLB to the “Reset sequences” table.
Added “WKUP/NMI Timing” subsection and “WKUP/NMI Glitch Filter” table to
the “AC timing characteristics” section.
Added “Nexus DDR Mode output timing” table to the “Nexus timing” section.
Removed the “CLKOUT” diagram from the “External interrupt timing (IRQ pin)”
section as it is not relevant.
Corrected an error in the IRQ timing in the “External interrupt timing” figure.
Updated the tSDC parameters in the “DSPI timing” table.
Renamed the “Electromagnetic Interference (EMI) characteristics” section (is
“Electromagnetic Interference (EMI) characteristics (cut1)”) and revised all
information in that section.
In the “Voltage regulator electrical characteristics” section, added the BCX68
from Infineon to the list of supported transistors.
6
23-Mar-2011
(continued)
Revised the “Voltage regulator electrical specifications” table to include cut1
and cut2 information.
Renamed the “Supply current characteristics” section (is “Supply current
characteristics (cut2)”) and revised it to show meaningful data.
In the footnotes of the “Main oscillator electrical characteristics” table, changed
SELMARGIN to XOSC_MARGIN.
In the “ADC conversion characteristics” table:
– Changed “LSB” to “Counts”.
– Created separate rows for the TUE specifications.
Removed the BGA row from the “Temperature” table entry.
Added bullet regarding HALT and STOP in the “Clock, reset, power, mode and
test control modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)“
subsection of the “Features“ section.
In the “Analog-to-Digital Converter module“ subsection of the “Feature Details”
section, changed “Motor control mode“ to “CTU mode“ to be consistent with
the nomenclature used in the Reference Manual.
Updated the JCOMP entries in the “Pin function summary“ table.
Added footnotes regarding pad pull devices to NMI, TMS, TCK, and JCOMP in
the “System pins“ table.
Added “Time constant of RC filter at LVD input” parameters to the “Main supply
LVD (LVD Main) specifications“ table.
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Revision history
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Table 44. Document revision history (continued)
Date
Revision
Changes
In the “Supply current characteristics (cut2)“ table:
– Changed “IDD_LV_MAX” to “IDD_LV_MAX“;
– Removed all “40-120 MHz” frequency ranges from the “Conditions” column;
– Updated the “Max” values column;
– Added parameter “IDD_LV_TYP + IDD_LV_PLL“ with “P” classification and
special footnote;
– Changed all “25°C“ temperature conditions to “ambient”;
– Added “TJ = 150 °C“ condition to parameters IDD_HV_ADC, IDD_HV_AREF.,
IDD_HV_OSC, and IDD_HV_FLASH
.
Changed the timing diagram in the “Main oscillator electrical characteristics”
section to reference MTRANS assertion instead of VDDMIN
.
Updated the jitter specs in the “FMPLL electrical characteristics“ table.
In the “ADC conversion characteristics“ table, changed all parameters with
units of “counts” to units of “LSB” and updated Min/Max values.
6
Changed IDD_LV_BIST + IDD_LV_PLL operating current (for both cases) to TBD.
23-Mar-2011
(continued)
In the “Supply current characteristics (cut2)” section, added a footnote that
IDD_HV_ADC and IDD_HV_AREF represent the total current of both ADCs in the
“Current consumption characteristics” table.
In the “ADC conversion characteristics” table:
– Changed DNL min from -2 to -1.
– Changed OFS min from -2 to -6.
– Changed OFS max from 2 to 6.
– Changed GNE min from -2 to -6.
– Changed GNE max from 2 to 6.
– Changed SNR min from 69 to 67.
– Changed TUE min (without current injection) from -6 to -8.
– Changed TUE max (without current injection) from 6 to 8.
– Changed TUE min (with current injection) from -8 to -10.
Changed TUE max (with current injection) from 8 to 10.
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Revision history
Table 44. Document revision history (continued)
Date
Revision
Changes
In the “Description” section, changed the first paragraph and its bullets to
paragraph form only.
In the “Voltage regulator electrical specifications“ table, changed the CV1V2 Min
value from “—“ to 300 nF, and changed the Max value from 300 nF to 900 nF.
In the “Supply current characteristics (cut2)“ table, corrected the “IDD_LV_TYP
+ IDD_LV_PLL“ values as follows:
– Changed the maximum value for “TJ = ambient“ from “279 mA+
2.10 mA*fCPU“ to “279 mA”.
– Changed the maximum value for “TJ = 150 °C“ from “318 mA+
2.30 mA*fCPU“ to 318 mA.
– Changed the frequency multiplier “fCPU” in the max value to read
“fCPU[MHz]“ for “IDD_LV_FULL + IDD_LV_PLL“ and “IDD_LV_TYP + IDD_LV_PLL“.
14-Sep-2011
7
In the “JTAG pin AC electrical characteristics“ table:
– Changed tJCYC min from 100ns to 62.5ns.
– Changed tJDC units from “ns” to “%”.
In the “Nexus debug port timing“ table:
– Changed tTCYC min from 40ns to 62.5 ns.
– Changed tJOV parameter description from “TCK Low to TDO Data Valid“ to
“TCK Low to TDO/RDY Data Valid“.
Changed “DDR” to “Double Data Rate (DDR)“ in the “Nexus DDR Mode output
timing“ figure.
Changed “TDO” to “TDO/RDY” in the “Nexus TDI, TMS, TDO timing“ figure.
Removed “fmax” from the “DSPI timing” table.
Deleted “Order code” table.
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Revision history
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Table 44. Document revision history (continued)
Date
Revision
Changes
Editorial changes.
In the “Block diagram” section, removed one PMU from the figure.
In the 257-pin pinout figure, changed cut2 to cut2/3 in Notes.
In the pin function summary table, changed cut2 to cut2/3.
In the “System pins” table:
– Added Note regarding Open Drain Enable.
– Added description to RESET pin.
In the pin-muxing table:
– Added Note about Open Drain.
– Changed cut2 to cut2/3.
– Changed all entries of column 'Weak pull config during reset’ to ' - ' , except
for PCR[2], PCR[3], PCR[4] and PCR[21].
In the “Absolute maximum ratings” table:
– Removed the “VSS_HV_REG” row.
– Added the footnote “Internal structures hold the input voltage...” to the VIN
maximum specifications.
In the “Recommended operating conditions” table, removed the “VSS_HV_REG
”
row.
In the “Thermal characteristics” section:
– Added the “Thermal characteristics for LQFP100 package“ table.
– Updated values and footnote 1 in the 144 package table.
– Updated footnote 1 in the 257 package table.
In the “Supply current characteristics“ table:
– Added footnote 1 to parameter “IDD_LV_TYP + IDD_LV_PLL“ (symbol “T”).
– Changed “IDD_LV_STOP” at 150C from 80mA to 72mA.
– Changed “IDD_LV_HALT” at 150C from 72mA to 80mA.
In the “FMPLL electrical characteristics” table:
01-Aug-2012
8
– Deleted the footnote “This value is true when operating at frequencies above
60 MHz...” from the specification for fCS and fDS
.
– Changed “fSYS” to “fFMPLLOUT” in the entries for the CJITTER, fLCK, fUL, fCS
,
and fDS specifications.
In the “ADC conversion characteristics” table:
– Revised the entry for TUEIS1WINJ (was P/T and “Total unadjusted error for
IS1WINJ”, is T and “Total unadjusted error for IS1WINJ (single ADC
channels)”).
– Revised the entry for TUEIS1WWINJ (was “Total unadjusted error for
IS1WWINJ”, is “Total unadjusted error for IS1WWINJ (double ADC
channels)”).
In the “Temperature sensor electrical characteristics“ table, for TJ = TA to
125 °C, changed Min/Max from values -7/+7 to -10/+10.
In the “Input Impedance and ADC Accuracy“ section:
– Changed CS in the text from 3 pF to 7.5 pF.
– Changed Req in the text from 330 kΩ to 133 kΩ.
– Removed RL, RSW, and RAD from the external network design constraint
equation and the sentence immediately preceding it.
– Changed the CF constraint value equation constant from 2048 to 8192.
In the “ADC conversion characteristics“ table, changed INL Min/Max values
from -2/+2 to -3/+3.
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Revision history
Table 44. Document revision history (continued)
Date
Revision
Changes
– In Section 1.5.31, “eTimer module” changed text from “The MPC5643L
provides three eTimer modules on the 257 MAPBGA device, and two eTimer
modules on the 144 LQFP package” to “The MPC5643L provides three
eTimer modules (on the LQFP package eTimer_2 is available internally only
without any external I/O access)”.
– In Section 3.5, “Electromagnetic Interference (EMI) characteristics”,added
additional information at the end of this section.
– In Section 3.8, Voltage regulator electrical characteristics, added text related
to external ballast transistor.
– In Table 4 and Table 5 (LFBGA257 pin function summary), moved EVTI from
output function to input function.
– In Table 7 (System pins), changed the direction for EXTAL from “Output
Only” to “Input/Output”.
– InTable 7, added table footnote for symbol “EXTAL”.
– Changed the row (TVdd) in Table 9 (Absolute maximum ratings).
– In Table 9, Maximum value for “VDD_HV_IOX” and “VDD_HV_FLA” changed from
“3.6” to “4.0”.
– In Table 21 (Current consumption characteristics), added max value 250 and
290 mA for symbol IDD_LV_BIST+IDD_LV_PLL
.
– Added five additional RunIDD parameters in Table 21 (Current consumption
characteristics).
8
01-Aug-2012
(cont.)
– In Table 22 (Temperature sensor electrical characteristics), changed
condition for parameter “Accuracy” from “-40°C to 25°C” to “-40°C to 150°C”
– In Table 24 (FMPLL electrical characteristics),added ‘150’ to the max value
for ‘fSCM’ In Table 25 (RC oscillator electrical characteristics),changes done
are:
fRC symbol- Added min value ‘15.04’ and max value ‘16.96’.Removed condition
“TJ=25°C”
Removed row containing Δ RCMVAR symbol.
– In Figure 9, added the name ‘CS’ to the capacitor in the internal circuit
scheme.
– Removed references to Cut1 and Cut2:
Renamed Section ”Electromagnetic Interference (EMI) characteristics (cut1)” to
“Electromagnetic Interference (EMI) characteristics” .
In Table 26 (ADC conversion characteristics), removed reference to cut2 only
for symbol ‘IS1WINJ’ and ‘TUEIS1WWINJ’.
In Section 1.1, Document overview, modified text to remove references to
‘Cut1’.
– In Table 26 (ADC conversion characteristics), for tCONV added ‘60 MHz’ to
‘conditions’ and ‘600’ to the ‘Min’ value.
Separated SNR into two specifications with conditions Vref 3.3 V and 5.0 V
respectively.
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Revision history
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Table 44. Document revision history (continued)
Date
Revision
Changes
Changed min value to ‘-72’ for symbol ‘THD’.
– In Table 26 (ADC conversion characteristics), changed ADC specification
parameter ‘THD’ minimum limit from -72 to -65dB.
– In Table 27 (Flash memory program and erase electrical specifications),
changes done are as follows:
TDWPROGRAM, changed typical value from ‘39’ to ‘38’.
TPPROGRAM, changed typical value from ‘48’ to ‘45’ and intial max value from
‘100’ to ‘160’.
T16KPPERASE, inserted typical value ‘270’ and factory avg ‘1000’.
T48KPPERASE, inserted typical value ‘625’ and factory avg ‘1500’.
T64KPPERASE, inserted typical value ‘800’ and factory avg ‘1800’.
T128KPPERASE, inserted typical value ‘1500’ and factory avg ‘2600’.
T256KPPERASE, inserted typical value ‘3000’ and factory avg ‘5200’.
Updated table footnote and removed min column in Table 27 (Flash memory
program and erase electrical specifications)
– In Table 28 (Flash memory timing), added symbol TPSRT ,TESRT and added
table footnote for TPSRT ,TESRT .
– Added Table 30 (MPC5643L SWG Specifications)
– In Table 30 (MPC5643L SWG Specifications)
Added table footnote for Common Mode.
Changed text from “internal device pad resistance” to “internal device routing
resistance”.
8
01-Aug-2012
(cont.)
– Added Figure 27 in Section 3.20.4, “Nexus timing”.
– In Table 31 (Pad AC specifications (3.3 V , IPP_HVE = 0 )), removed the row
of pad “Pull Up/Downc(3.6 V max)”.
– In Figure 43, updated part numbers (changed ‘PPC’ to ‘SPC’ and ‘F0’ to
‘F2’).
– Replaced Figure 41, Figure 42 with the new versions.
– InTable 19 (Voltage regulator electrical specifications),changed the symbol
of spec external decoupling capacitor from SR to Cext
.
In Figure 5, changed the ESR range in note text to 1 mW to 100 mW from
30 mW to 150 mW.
– In Section 1.5.32, “Sine Wave Generator (SWG)” removed the following text:
Frequency range from 1kHz to 50kHz.
Sine wave amplitude from 0.47 V to 2.26 V.
– In Table 21 (Current consumption characteristics),changed symbol from ‘C’
to ‘T’ , added “operating current” to the parameter and updated the maximum
value for five additional RunIDD parameters.
– In Table 21 (Current consumption characteristics), changed “Conditions”
from ‘1.2 V supplies’ to ‘1.2 V supplies during LBIST (full LBIST
configuration)’ for all the parameters.
Removed Table “SWG electrical characteristics”.
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Revision history
Table 44. Document revision history (continued)
Date
Revision
Changes
– In Table 19 (Voltage regulator electrical specifications), changed the “Digital
supply high voltage detector upper threshold low limit (After a destructive
reset initialization phase completion)” from 1.43V to 1.38V.
– Added Table 18 (Recommended operating characteristics).
– Updated the IDD values in Table 21 (Current consumption characteristics).
Changed conditions text from “1.2 supplies during LBIST (full LBIST
configuration)” to “1.2 V supplies” for all the IDD parameters except
IDD_LV_BIST+IDD_LV_PLL. Added footnote in “Conditions” for the DPM mode.
8
01-Aug-2012
(cont.)
– Removed Cut references from the whole document.
In Table 26 (ADC conversion characteristics), changed the sampling frequency
value from ‘1 MHz’ to ‘983.6 KHz’.
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