SR1-LBRU [STMICROELECTRONICS]
Integrated test mode;
| 型号： | SR1-LBRU |
| 厂家： | 
ST |
| 描述： | Integrated test mode |
| 文件： | 总21页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SR1
4 pin Smart Reset™
Datasheet - production data
Applications
Wearable
Activity tracker
Smartwatch
Smartglasses
UDFN6 (1.00 x 1.45 mm)
Features
Operating voltage range 2 V to 5.5 V
Low supply current 1 µA
Integrated test mode
Single Smart Reset™ push-button input with
fixed extended reset setup delay (t
) from
SRC
0.5 s to 10 s in 0.5 s steps (typ.), option with
internal input pull-up resistor
Push-button controlled reset pulse duration
– Option 1: fully push-button controlled, no
fixed or minimum pulse width guaranteed
– Option 2: defined output reset pulse
duration (t
), factory-programmed
REC
Single reset output
– Active low or active high
– Push-pull or open drain with optional pull-
up resistor
Fixed Smart Reset input logic voltage levels
Operating temperature: -40 °C to +85 °C
UDFN6 package 1.00 mm x 1.45 mm
®
ECOPACK 2 (RoHS compliant, Halogen-
Free)
May 2014
DocID026048 Rev 2
1/21
This is information on a product in full production.
www.st.com
Contents
SR1
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Smart Reset input (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RST output undervoltage behavior (for open-drain option) . . . . . . . . . . . . 6
4
Typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
6
7
8
9
10
11
12
13
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Description
1
Description
TM
The Smart Reset devices provide a useful feature which ensures that inadvertent short
reset push-button closures do not cause system resets. This is done by implementing an
extended Smart Reset input delay time (t
), which ensures a safe reset and eliminates
SRC
the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish
between a software generated interrupt and a hard system reset. When the input push-
button is connected to the microcontroller interrupt input, and is closed for a short time, the
processor can only be interrupted. If the system still does not respond properly, continuing
to keep the push-button closed for the extended setup time t
processor through the reset output.
causes a hard reset of the
SRC
The SR1 has one Smart Reset input (SR) with preset delayed Smart Reset setup time
(t ). The reset output (RST) is asserted after the Smart Reset input is held active for the
SRC
selected t
delay time. The RST output remains asserted either until the SR input goes to
SRC
inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output
reset pulse duration is fixed for t (i.e. factory-programmed). The device fully operates
REC
over a broad V range from 2.0 V to 5.5 V.
CC
1.1
Test mode
After pulling SR up to V
(V + 1.4 V) or above, the counter starts to count the initial
CC
TEST
shortened t
(42 ms, typ.). After t
expires, the RST output either goes down for
SRC-INI
SRC-INI
t
(if t
option is used) or stays low as long as overvoltage on SR is detected (if t
REC
REC REC
option is not used). This is feedback, and the user only knows that the device is locked in
test mode. Each time the SR input is connected to ground in test mode, a shortened
t
(t
/128) is used instead of regular t
(0.5 s - 10 s). In this way the device
SRC-SHORT SRC
SRC
can be quickly tested without repeating test mode triggering. Return to normal mode is
possible by performing a new startup of the device (i.e. V goes to 0 V and back to its
CC
original state).
The advantages of this solution are its high glitch immunity, user feedback regarding entry
into test mode, and testability within the full V range.
CC
DocID026048 Rev 2
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21
Description
SR1
1.2
Logic diagram
Figure 1. SR1 logic diagram
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1.3
Pin connections
Figure 2. UDFN6 pin connections (top view)
(1)
RST
NC
1
2
3
6
5
4
(1)
V
SR1
NC
V
SS
SR
CC
UDFN6
AM07463v2
1. Not connected (not bonded); should be connected to VSS
.
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SR1
Device overview
2
Device overview
Table 1. Signal names
Pin n°
Name
Type
Description
Reset output, active low, open drain.
1
2
3
RST
VSS
SR
Output
Supply ground Ground
Input Smart Reset input, active low.
Positive supply voltage for the device. A 0.1 µF decoupling
4
VCC
Supply voltage ceramic capacitor is recommended to be connected between
VCC and VSS pins.
5
6
NC
NC
-
-
Not connected (not bonded); should be connected to VSS
.
.
Not connected (not bonded); should be connected to VSS
Figure 3. SR1 block diagram
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DocID026048 Rev 2
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Pin descriptions
SR1
3
Pin descriptions
3.1
Power supply (VCC)
This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling
capacitor is recommended to be connected between the V and V pins, as close to the
CC
SS
SR1 device as possible.
3.2
Power-up sequence
In normal mode, if different input side (SR) and V voltage domains are used, power-on
CC
sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode
entry: there should not be logic high present on the SR input before the V power-up.
CC
However V and V(SR) rising at the same time is OK (e.g. if both are in the same voltage
CC
domain), the device will then safely start into normal operating mode, with RST output
inactive (in High-Z mode for open-drain option).
3.3
3.4
Ground (VSS)
This is the ground pin for the device.
Smart Reset input (SR)
Push-button Smart Reset input, active low with optional pull-up resistor. SR input needs to
be asserted for at least t
to assert the reset output (RST).
SRC
By connecting a voltage higher than V + 1.4 V to the SR input the device enters test mode
CC
(see Section 1: Description on page 3 for more information).
3.5
Reset output (RST)
RST is active low or active high, open drain or push-pull reset output with optional internal
pull-up resistor.
Output reset pulse width is optional as follows:
Neither fixed nor minimum output reset pulse duration (releasing the push-button while
reset output is active, causes the output to de-assert)
Fixed, factory-programmed output reset pulse duration for t
Reset input state.
independent on Smart
REC
3.6
RST output undervoltage behavior (for open-drain option)
High-Z on RST output below the specified operating voltage range is guaranteed at V
CC
power-on or in case that valid V dropped while the device was idle, i.e. while both output
CC
and input were inactive.
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Typical application diagrams
4
Typical application diagrams
Figure 4. Typical application diagram - input, output and SR1 device in one voltage
domain
SR1
AM07466v1
Figure 5. Typical application diagram - SR1 device in a different voltage domain than
input and output
V
V
CC
DD
V
V
CC
DD
RST
RESET
SR1
MCU
SR
INT/NMI
V
V
SS
SS
PUSH -BUTTON
SWITCH
AM07466v2
1. Open-drain RST output type and fixed SR input logic threshold allows to use the device in different voltage
domains. To prevent entering test mode by creating a condition V(SR) > VCC + 1.1 V typ., VCC should be
powered up before or together with voltage on the SR input.
DocID026048 Rev 2
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Typical application diagrams
SR1
Figure 6. Typical application diagram in different voltage domains - SR input in V
BAT
domain like V totally disables the test mode
CC
SR1
AM07466v3
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Timing diagrams
5
Timing diagrams
Figure 7. RST output without t
option
REC
1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode
by creating
a condition V(SR) > VCC +1.1 V typ.
Figure 8. RST output with t
option
REC
1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode
by creating
a condition V(SR) > VCC +1.1 V typ.
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Typical operating characteristics
SR1
6
Typical operating characteristics
Figure 9. Supply current (I ) vs. temperature (T )
CC
A
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Figure 10. Smart Reset delay (t
) vs. temperature (T ), t = 4.0 s (typ.)
SRC
SRC
A
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Typical operating characteristics
Figure 11. Test mode entry voltage (V
) vs. temperature (T )
A
TEST
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Figure 12. Initial test mode time (t
) vs. temperature (T )
A
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Maximum ratings
SR1
7
Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 3: Operating and
measurement conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics™ SURE program and other relevant quality documents.
Table 2. Absolute maximum ratings
Symbol
Parameter
Storage temperature (VCC off)
Value
Unit
TSTG
-55 to +150
260
°C
°C
V
(1)
TSLD
Lead solder temperature for 10 seconds
Input or output voltage
VIO
-0.3 to 5.5
-0.3 to 7
VCC
Supply voltage
V
ESD
Electrostatic discharge protection, human body model (JESD22-
A114-B level 2)
VHBM
VRCDM
VMM
2
kV
kV
V
Electrostatic discharge protection, charged device model, all pins
1
Electrostatic discharge protection, machine model, all pins
(JESD22-A115-A level A)
200
Latch-up (VCC pin, SR reset input pin)
EIA/JESD78
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
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DC and AC parameters
8
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in Table 4: DC and AC characteristics are
derived from tests performed under the measurement conditions summarized in Table 3:
Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 3. Operating and measurement conditions
Symbol
Parameter
Value
Unit
VCC
TA
Supply voltage
2.0 to 5.5
-40 to +85
5
V
°C
ns
V
Ambient operating temperature
Input rise and fall times
tR, tF
Input pulse voltages
0.2 to 0.8 VCC
0.3 to 0.7 VCC
Input and output timing reference voltages
V
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DC and AC parameters
SR1
Table 4. DC and AC characteristics
Symbol
Parameter
Test conditions(1)
Min.
Typ.(2)
Max.
Unit
VCC
Supply voltage
Supply current
2.0
5.5
V
SR = VCC, tREC and tSRC
counter is not running
ICC
0.4
1.0
µA
VCC 4.5 V, sinking 3.2 mA
0.3
0.3
V
V
VOL
Reset output voltage low VCC 3.3 V, sinking 2.5 mA
VCC 2.0 V, sinking 1 mA
0.3
V
140
240
210
360
280
480
ms
ms
Reset timeout delay,
(device option)
tREC
factory-programmed
Internal output pull-up
(device option)
RPUO
65
k
resistor on RST
VRST = 5.5 V, open drain
ILO
Output leakage current
device option without output
pull-up resistor
-0.1
0.1
µA
Smart Reset
TA = -40 to +85 °C
TA = 25 °C
0.8 x tSRC
0.9 x tSRC
VSS-0.3
0.85
1.2 x tSRC
1.1 x tSRC
0.3
(3)
tSRC
Smart Reset delay
tSRC
s
VIL
VIH
SR input voltage low
SR input voltage high
V
V
5.5
Internal input pull-up
resistor on SR
RPUI
(device option)
65
k
device option without input
pull-up resistor
ILEAK
SR input leakage current
Input glitch immunity
-0.1
0.1
µA
s
tSRC
Test mode
VTEST
Test mode entry voltage
Initial test mode time
VCC +0.9
28
VCC +1.1 VCC +1.4
V
tSRC-INI
42
56
ms
Shortened Smart Reset
delay
tSRC-SHORT
t
SRC / 128
ms
1. Valid for ambient operating temperature TA = -40 to +85 °C, VCC = 2.0 to 5.5 V.
2. Typical values are at 25 °C and VCC = 3.3 V unless otherwise noted.
3. Factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps.
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Package information
9
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 13. UDFN6, (1.00 x 1.45 x 0.50 mm), 0.50 mm pitch package outline
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Package information
SR1
Table 5. UDFN6, (1.00 x 1.45 x 0.50 mm), 0.50 mm pitch package mechanical data
Dimensions
Symbol
(mm)
Typ.
(inches)
Typ.
Note(1)
Min.
Max.
Min.
Max.
A
A1
b
0.50
0.00
0.18
1.40
0.95
0.45
0.20
0.30
0.55
0.02
0.25
1.45
1.00
0.50
0.60
0.05
0.30
1.50
1.05
0.55
0.0197
0.000
0.0217
0.0008
0.0098
0.0571
0.0394
0.0197
0.0236
0.0020
0.0118
0.0591
0.0413
0.0217
0.0071
0.0551
0.0374
0.0177
0.0079
0.0118
D
E
e
k
L
0.35
0.40
0.0138
0.0157
1. Package outline exclusive of any mold flashes dimensions and metal burrs.
Figure 14. Footprint recommendation for UDFN6 (1.00 x 1.45 x 0.50 mm), 0.50 mm
pitch
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Tape and reel information
10
Tape and reel information
Figure 15. Carrier tape
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Figure 16. Pin 1 orientation
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Part numbering
SR1
11
Part numbering
Table 6. Ordering information scheme
SR1
Example:
H
A
R
U
Device type
SR1
(1)
Smart Reset setup delay (tSRC
)
C = factory programmable tSRC = 1.5 s (typ.)
H = factory programmable tSRC = 4.0 s (typ.)
L = factory programmable tSRC = 6.0 s (typ.)
P = factory programmable tSRC = 7.5 s (typ.)
U = factory programmable tSRC = 10.0 s (typ.)
Inputs, outputs type(2)
A = active low SR input with no pull-up,
active low open drain RST output with no pull-up
B = active low SR input with pull-up,
active low open drain RST output with no pull-up
Reset timeout period (tREC
)
A = factory programmable tREC = 210 ms (typ.)
B = factory programmable tREC = 360 ms (typ.)
R = push-button controlled (no defined tREC
)
Package
U = UDFN-6L
1. Smart Reset delay (tSRC) is available from 0.5 s to 10 s in 0.5 s steps (typ.). Minimum order quantities may
apply. Contact local sales office for availability.
2. Push-pull reset output type also available (active low or active high). SR input and open drain reset output
available with optional pull-up resistor. Minimum order quantities may apply. Contact local sales office for
availability.
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Package marking information
12
Package marking information
Table 7. Package marking
Smart Reset
inputs(1)
Output
type(2)
tREC
Part number
tSRC (s)
Package Topmark
option(3)
SR1CARU
SR1HARU
1.5
4.0
6.0
7.5
7.5
7.5
10.0
AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
OD, AL
No tREC
No tREC
No tREC
210 ms
No tREC
360 ms
No tREC
UDFN6
UDFN6
UDFN6
UDFN6
UDFN6
UDFN6
UDFN6
CA
HA
LA
PB
PA
PC
UA
AL
SR1LARU
AL
SR1PAAU
AL
AL
SR1PARU
SR1PBBU
AL + pull-up
AL
SR1UARU
1. AL = active low.
2. OD = open drain, AL = active low.
3. No tREC = push-button controlled reset pulse width, any other value represents typical value of tREC
.
Figure 17. Package marking (top view)
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Revision history
SR1
13
Revision history
Table 8. Document revision history
Changes
Date
Revision
10-Mar-2014
13-May-2014
1
2
Initial release
Modified tREC values Table 4 on page 14
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