ST10F252M-4T3 [STMICROELECTRONICS]
16-BIT, FLASH, 40MHz, RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100;
| 型号： | ST10F252M-4T3 |
| 厂家： | 
ST |
| 描述： | 16-BIT, FLASH, 40MHz, RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总328页 (文件大小：3205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST10F252M
16-bit MCU with 256 Kbyte Flash memory and 16 Kbyte RAM
Features
■ 16-bit CPU with DSP functions
– 50.0 ns instruction cycle time at 40 MHz
(maximum) CPU clock
– Multiply/accumulate unit (MAC)16 x 16-bit
multiplication, 40-bit accumulator, repeat
unit
– Enhanced boolean bit manipulations
LQFP10
– Additional instructions to support HLL and
operating systems
– 4.85 µs minimum conversion time.
■ 4-channel PWM unit and 4-Channel XPWM.
■ X-peripherals clock gating feature.
– Single-cycle context switching support
■ Memory organization
– 256 Kbyte on-chip IFlash memory
(single voltage with program/erase
controller, full performance, 32-bit fetch)
– 100K erasing/programming cycles
– Up to 16 Mbytes linear address space for
code and data (5 Mbyte with CAN)
■ Serial channels
– Two synch./asynch. serial channels
– Two high-speed synchronous channels
2
– One I C standard interface.
■ Fail-safe protection
– 2 Kbyte on-chip internal RAM (IRAM)
– 14 Kbyte extension RAM (XRAM).
– Programmable watchdog timer
– Oscillator watchdog.
■ Fast and flexible bus
■ Two CAN 2.0B interfaces operating on 1 or 2
CAN buses (64 or 2x32 message, C-CAN
version)
– Programmabexternal bus characteristics
for different address ranges (when 6 ADC
added channels are not selected)
■ On-chip bootstrap loader.
– 5 programmable chip-select signals
■ Clock generation
– Hold-acknowledge bus arbitration support.
– On-chip PLL with 4 to 8 MHz oscillator
– Direct or pre-scaled clock input.
■ Interrupt
– 8-channel peripheral event controller for
single cycle, interrupt driven data transfer
■ Real time clock.
■ Up to 76 general purpose I/O lines individually
programmable as input, output or special
function.
– 16-priority-level interrupt system with 56
sources, sample-rate down to 25.0 ns.
■ Two multi-functional general purpose timer
■ Idle, power down and stand-by modes.
units with 5 timers.
■ Voltage supply for 5 V 10% (embedded
■ Two 16-channel capture/compare units(18
regulator for 1.8 V core supply).
used).
o
■ Temperature range: -40 to +125 C.
■ 16-channel A/D converter
– 10-channel 10-bit (accuracy 2LSB)
– 6-channel (lower accuracy)
February 2008
Rev 1
1/331
www.st.com
1
Contents
ST10F252M
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
3
4
Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1
4.2
4.3
XPERCON and XPEREMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
XRAM2 memory range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
6
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1
The system configuration register SYCON . . . . . . . . . . . . . . . . . . . . . . 36
Multiplier-accumulator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1
6.2
MAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.1
6.1.2
6.1.3
Enhanced addressing capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Program control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Instruction pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Particular pipeline effects with the MAC unit . . . . . . . . . . . . . . . . . . . . . 40
Address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16 x 16 signed / unsigned parallel multiplier . . . . . . . . . . . . . . . . . . . . . 42
40-bit signed arithmetic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
40-bit adder/subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
The accumulator shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Repeat unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2.10 MAC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2.11 Number representation and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3
MAC register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3.1
Address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2/328
ST10F252M
Contents
6.3.2
Accumulator and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7
External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.1
Controlling the external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.1.1
External bus controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.2
EA functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8
Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1
8.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2.1
8.2.2
8.2.3
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3
8.4
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
Flash control register 0 low (FCR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Flash control register 0 high (FCR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash control registelow (FCR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Flash control register 1 high (FCR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Flash data register 0 low (FDR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash data register 0 high (FDR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flash data register 1 low (FDR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flash data register 1 high (FDR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flash address register low (FARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.4.10 Flash address register high (FARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.4.11 Flash error register (FER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.5
Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash non-volatile write protection I register (FNVWPIR) . . . . . . . . . . . 64
Flash non-volatile access protection register 0 (FNVAPR0) . . . . . . . . . 64
Flash non-volatile access protection register 1 low (FNVAPR1L) . . . . . 65
Flash non-volatile access protection register 1 high (FNVAPR1H) . . . . 65
XBus Flash volatile temporary access unprotection register
(XFVTAUR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.5.7
8.5.8
8.5.9
Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3/328
Contents
ST10F252M
8.6
8.7
Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.1
Fast external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.1.1
9.1.2
External interrupt source selection register (EXISEL) . . . . . . . . . . . . . . 72
External interrupt control register (EXICON) . . . . . . . . . . . . . . . . . . . . . 74
9.2
9.3
9.4
X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Exception and traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10
11
Capture compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12
13
PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
13.2 I/O’s spcial features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.2.Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.2.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
13.3 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.3.1 Alternate functions of PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.3.2 Disturb protection on analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
13.4 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.4.1 Alternate functions of PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13.5 PORT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.1 Alternate functions of PORT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.6 PORT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.6.1 Alternate functions of PORT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.7 PORT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.7.1 Alternate functions of PORT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4/328
ST10F252M
Contents
13.8 PORT7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.8.1 Alternate functions of PORT7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.9 PORT5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.9.1 Alternate functions of PORT5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.9.2 Disturb protection on analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14
Analog / digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.1 Mode selection and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
14.1.1 Fixed channel conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.1.2 Auto scan conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.1.3 Wait for ADDAT read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.1.4 Channel injection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.1.5 ADC power down (ADOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.2 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
14.3 ADC interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15
16
Programmable output clock dder . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.1 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
16.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . 138
16.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
16.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
16.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . 139
17
18
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18.1 Memory and pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18.1.1 CAN1 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18.1.2 CAN2 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18.1.3 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
18.2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
18.3 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
18.3.1 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5/328
Contents
ST10F252M
18.4 Clock prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
18.5 CAN module: functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
18.6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
18.7 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
18.7.1 Software initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
18.7.2 CAN message transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
18.7.3 Disabled automatic retransmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
18.7.4 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
18.7.5 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
18.7.6 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
18.7.7 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 153
18.7.8 Basic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
18.7.9 Software control of pin CAN_TX . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
18.8 Programmer’s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
18.8.1 Hardware reset description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
18.8.2 CAN protocol related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
18.8.3 Message interface register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
18.8.4 IFx message buffer sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
18.8.5 Message Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
18.8.6 Transmission request registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
18.8.7 New data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
18.8.8 Interrupt pending registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
18.8.Message valid registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
18.9 CAN application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
18.9.1 Management of message objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
18.9.2 Message handler state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
18.9.3 Configuration of a transmit object . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
18.9.4 Updating a transmit object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
18.9.5 Configuration of a receive object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
18.9.6 Handling of received messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
18.9.7 Configuration of a FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
18.9.8 Reception of messages with FIFO buffers . . . . . . . . . . . . . . . . . . . . . . 178
18.9.9 Handling of interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
18.9.10 Configuration of bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
19
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6/328
ST10F252M
Contents
20
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
20.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
20.6 Bidirectional Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
20.8 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
21
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
21.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
21.2.1 Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
21.2.2 Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
21.2.3 Real time clock and power down mode . . . . . . . . . . . . . . . . . . . . . . . . 219
21.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
21.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
21.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
21.3.3 Real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
22
Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
22.1 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
22.1.1 RTCCON: RTC control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
22.1.2 RTC prescaler divider loaded value registers . . . . . . . . . . . . . . . . . . . 224
22.1.3 RTC prescaler divider current value registers . . . . . . . . . . . . . . . . . . . 225
22.1.4 RTC programmable counter registers . . . . . . . . . . . . . . . . . . . . . . . . . 226
22.1.5 RTC alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
22.2 Programming the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
23
24
System start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
24.1 Selection between user-code or standard bootstrap . . . . . . . . . . . . . . . 231
24.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
24.2.1 Entering the standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . 231
7/328
Contents
ST10F252M
24.2.2 ST10 configuration in BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
24.2.3 Booting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
24.2.4 Hardware to activate BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
24.2.5 Memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . 236
24.2.6 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
24.2.7 Exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
24.2.8 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
24.3 Standard bootstrap with UART (RS232 or K-Line) . . . . . . . . . . . . . . . . . 238
24.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
24.3.2 Entering bootstrap via UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
24.3.3 ST10 configuration in UART BSL (RS232 or K-Line) . . . . . . . . . . . . . . 239
24.3.4 Loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
24.3.5 Choosing the baud rate for the BSL via UART . . . . . . . . . . . . . . . . . . 240
24.4 Standard bootstrap with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
24.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
24.4.2 Entering the CAN bootstrap loader (BSL) . . . . . . . . . . . . . . . . . . . . . . 242
24.4.3 ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
24.4.4 Loading the startup e via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
24.4.5 Choosing the baud rate for the BSL via CAN . . . . . . . . . . . . . . . . . . . 244
24.4.6 How to compute the baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . 247
24.4.7 Bootstrap via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
24.5 Comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . 248
24.5.Software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
24.5.2 Hardware aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
25
2
Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
26.1 General purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
26.2 Special function register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
26.2.1 Registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
26.2.2 Registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
26.3 X-registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
26.3.1 X-registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
26.3.2 X-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
26.4 Flash control registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
8/328
ST10F252M
Contents
26.4.1 Registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
26.4.2 Registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
27
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
27.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
27.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
27.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
27.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
27.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
27.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
27.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
27.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
27.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
27.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
27.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
27.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
27.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
27.8.2 Definition of internal ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
27.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
27.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
27.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
27.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
7.8.7 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
27.8.8 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
27.8.9 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
27.8.10 PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
27.8.11 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
27.8.12 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
27.8.13 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
27.8.14 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
27.8.15 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
27.8.16 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
27.8.17 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
27.8.18 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 321
28
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
9/328
Contents
29
ST10F252M
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
30
10/328
ST10F252M
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
IFlash addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
XPERCON register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
XRAM2 memory range functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Definition of address areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
XRAM2EN of XPERCON register programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
System configuration register SYSCON functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Example of MAC register read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pointer post-modification combinations for IDXi and Rwn . . . . . . . . . . . . . . . . . . . . . . . . . 41
Parallel data move addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Limiter output using CoSTORE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Address pointer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Offset register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MAH register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MAL register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Status word register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Control register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Repeat register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Register address in CoReg addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
External bus controller functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Address space reserved for the Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Flash modules sectorization (read opons). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash modules sectorization (write operations or with ROMS1=’1’or Bootstrap mode) . . . 54
Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Flash control register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Flash control register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Flash control reter 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Banks (BxS) d sectors (BxFy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash dta register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Flash non-volatile write protection I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash non-volatile access protection register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flash non-volatile access protection register 1 high. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
XBus Flash volatile temporary access unprotection register . . . . . . . . . . . . . . . . . . . . . . . 65
Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
External interrupt source selection register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
EXIxSS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CAN parallel mode pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
External interrupt control register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table .
Tble 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
11/328
List of tables
ST10F252M
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Tble 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 85
Port input control register (PICON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Additional port input control register (XPICON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
P0L and P0H registers functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DP0L and DP0H registers functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Disturb protection register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
P1L and P1H registers functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DP1L and DP1H registers functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
XSSCPORT register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
XS1PORT register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
XPWPORT register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
PORT2 register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PORT2 direction register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PORT2 open drain control register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PORT2 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PORT3 register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PORT3 direction register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PORT3 open drain control register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PORT3 alternative functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
PORT4 register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
PORT4 direction register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PORT4 open drain control register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PORT4 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
PORT7 register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PORT7 direction register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PORT7 open drain control register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PORT7 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PORT5 register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PORT5 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PORT5 digital diable register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ADCON functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ADDAT and ADDAT2 registers functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ADC programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
CLKOUTDIV functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
ASC asynchronous baudrates by reload value and deviation errors (fCPU = 40 MHz) . . 138
ASC synchronous baudrates by reload value and deviation errors (fCPU = 40 MHz) . . . 139
Synchronous baudrate and reload values (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . 140
CAN1 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
CAN2 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
XMISC register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
C-CAN register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
CAN control register (addresses 0x01 and 0x00) functions . . . . . . . . . . . . . . . . . . . . . . . 156
Status register (addresses 0x03 and 0x02) functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Error counter (addresses 0x05 and 0x04) functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Bit timing register (addresses 0x07 and 0x06) functions . . . . . . . . . . . . . . . . . . . . . . . . . 159
Test register (addresses 0x0B and 0x0A) functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
BRP extension register (addresses 0x0D and 0x0C) functions . . . . . . . . . . . . . . . . . . . . 161
IF1 and IF2 message interface register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
IFx command request registers functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 100. IFx command mask registers functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12/328
ST10F252M
List of tables
Table 101. IFx command mask registers functions (direction - write). . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 102. IFx command mask registers functions (direction - read). . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 103. IFx Data A and Data B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 104. Message object functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 105. Interrupt register (addresses 0x09 and 0x08) functions . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 106. Transmission request register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 107. New data register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 108. Interrupt pending register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 109. Message valid register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 110. Parameters of the CAN bit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 111. WDTCON register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 112. Reset flag settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 113. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 114. Reset events summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 115. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 212
Table 116. XMISC register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 117. SYSCON PWDCFG functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 118. EXICON register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 119. RTC control register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 120. RTC external interrupt control register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 121. RTC external interrupt select register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 122. RTC/CAPCOM interrupt control requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 123. Start up configuration register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 124. ST10F252M boot mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 125. Register configuration in BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 126. Register configuration in UART BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 127. Ranges of timer contents in function of BRP value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 128. Software topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 129. Hardware topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 130. Manufacturer identifier register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 131. Chip identifier register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 132. Internal memory nd size identifier register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 133. Programming voltage description register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 134. Generapurpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 135. General purpose registers (GPRs) bit wise addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 136. Special function registers listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 137. Special function registers listed by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 138. Registers listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Tble 139. Registers listed by address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 140. Flash registers listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 141. Flash registers listed by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 142. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 143. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 144. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 145. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 146. Flash characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 147. Flash data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 148. A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 149. A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 150. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 151. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 152. PLL characteristics (V = 5V 10%, V = 0V, T = -40 to +125°C) . . . . . . . . . . . . . . 305
DD
SS
A
13/328
List of tables
ST10F252M
Table 153. Main oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 154. Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 155. External clock drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 156. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 157. Multiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 158. Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Table 159. CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 160. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table 161. SSC slave mode timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 162. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Table 163. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
14/328
ST10F252M
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ST10F252M memory mapping (user mode: flash read operations or XADRS = F006h) . . 33
ST10F252M memory mapping (user mode: flash write operations or ROMS1=1). . . . . . . 34
CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Example of parallel data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Pipeline diagram for MAC interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 10. EA/VSTBY external circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. Flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 12. Write operation control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 13. X-interrupt basic structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 14. SFR and port pins associated with CAPCOM units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 15. SFRs and port pins associated with timer block GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 16. SFRs and port pins associated with timer block GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 17. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 18. SFRs, XBUS registers and pins associated with the parallel ports. . . . . . . . . . . . . . . . . . . 87
Figure 19. Output drivers in push/pull mode and in open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 20. Hysteresis concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 21. PORT0 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 22. Block diagram of a PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 23. Block diagram of input section of PORT0L pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 24. Block diagram of a PORT0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 25. PORT1 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 26. Block diagram of a PORT1 pin P1H.7...P1H.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 27. Block diagram of pins P1H.3 ...P1H.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 28. Block diagram oin P1L.6, P1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 29. Block diagraof pins P1L.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 30. Block dagram of pins P1L.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 31. Block diagram of pins P1L.3...P1L.0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 32. PORT2 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 33. Block diagram of a PORT2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 4. PORT3 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Fgure 35. Block diagram of PORT3 pin with alternate input or alternate output function . . . . . . . . . 111
Figure 36. Block diagram of pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) . . . . . . . . . . . . . . . . . . . 112
Figure 37. PORT4 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 38. Block diagram of pins P4.0 ... P4.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 39. Block diagram of pin P4.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 40. Block diagram of pin P4.5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 41. Block diagram of pin P4.6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 42. Block diagram of pin P4.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 43. PORT7 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 44. Block diagram of PORT7 pins P7.3...P7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 45. PORT5 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 46. Block diagram of a PORT5 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 47. SFRs, XBUS registers and port pins associated with the A/D converter . . . . . . . . . . . . . 126
Figure 48. Analog to digital converter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
15/328
List of figures
ST10F252M
Figure 49. Auto scan conversion mode example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 50. Wait for read mode example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 51. Channel injection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 52. Channel injection example with wait for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 53. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . 147
Figure 54. Connection to single CAN bus via one common transceiver . . . . . . . . . . . . . . . . . . . . . . 147
Figure 55. Connection to two different CAN buses (for example, for gateway application). . . . . . . . 148
Figure 56. Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . 148
Figure 57. Block diagram of the C-CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 58. CAN core in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 59. CAN core in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 60. CAN core in loop back combined with silent mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 61. Structure of a message object in the message memory. . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 62. Data transfer between IFx registers and message RAM . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 63. Initialisation of a transmit object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 64. Initialization of a receive object. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 65. CPU Handling of a FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 66. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 67. The propagation time segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 68. Synchronisation on “late” and “early” edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 69. Filtering of short dominant spikes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 70. Structure of the CAN Core’s CAN Protocol Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 71. Asynchronous power-on RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 72. Asynchronous power-on RESET (EA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 73. Asynchronous hardware RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 74. Asynchronous hardware RESET (EA=. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 75. Synchronous short / long hardware RESET (EA=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 76. Synchronous short / long hardware RESET (EA=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 77. Synchronous long hardware RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 78. Synchronous long hardware RESET (EA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 79. SW / WDT unidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 80. SW / WDT unidictional RESET (EA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 81. SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 82. SW / WDT bidirectional RESET (EA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 83. SW / WDT bidirectional RESET (EA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 84. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 85. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 86. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Fure 87. EXICON register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 88. RPD pin: external circuit to exit power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 89. Simplified power down exit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 90. Power down exit sequence using an external interrupt (PLL x 2). . . . . . . . . . . . . . . . . . . 219
Figure 91. SFRs associated with the RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 92. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 93. RTC prescaler register function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 94. RTC prescaler divider register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 95. PORT0 configuration during Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 96. ST10F252M new bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 97. Booting steps for ST10F252M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 98. Hardware provisions to activate BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 99. Memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 100. UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
16/328
ST10F252M
List of figures
Figure 101. Baudrate deviation between host and ST10F252M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 102. CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 103. Register configuration in CAN BSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 104. Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 105. Reset Boot Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 106. Internal memory and size identifier register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 107. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 108. Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 287
Figure 109. A/D conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 110. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 111. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 112. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 113. Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 114. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 115. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 116. ST10F252M PLL jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 117. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 118. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 119. External memory cycle: multiplexed bus, with/without read/write delay, normal ALE. . . . 310
Figure 120. External memory cycle: multiplexed bus, with/without read/wrie delay, extended ALE. . 311
Figure 121. External memory cycle: multiplexed bus, with/without r/w elay, normal ALE, r/w CS. . . 312
Figure 122. External memory cycle: multiplexed bus, with/without r/w delay, extended ALE, r/w CS. 313
Figure 123. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 316
Figure 124. External memory cycle: demultiplexed bus, with/without r/w delay, extended ALE . . . . . 317
Figure 125. External memory cycle: demultiplexed busith/without r/w delay, normal ALE, r/w CS. 318
Figure 126. External memory cycle: Demultiplexes, without r/w delay, extended ALE, r/w CS . . 319
Figure 127. CLKOUT and READY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 128. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 129. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 130. LQFP100 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
17/328
Introduction
ST10F252M
1
Introduction
1.1
Description
The ST10F252M is a new derivative of the STMicroelectronics ST10 family of 16-bit single-
chip CMOS microcontrollers.
The ST10F252M combines high CPU performance (up to 24 million instructions per second)
with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip
high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation
via PLL.
The ST10F252M is processed in 0.18 µm CMOSM8 technology. The MCU core and the
logic is supplied with a 5 V to 1.8 V on-chip voltage regulator. The part is supplied with a
single 5 V supply and I/Os work at 5 V.
The ST10F252M is an optimized version of ST10F252E device, upward compatible with the
following set of differences.
●
The AC and DC parameters are modified due to a difference in the maximum CPU
frequency. Refer to Section 27.5 and Section 27.8 for detailed description.
2
●
●
●
●
●
●
●
XASC, XSSC, XPWM and I C have been changed. Refer to Chapter 13.
No external bus is available when all 16 ADC channels are selected.
Pin T3EUD is added for encoder interface aalternate function of P1H.0.
A/D Converter has 16 channels, 10 aron standard Port5, 6 channels on Port0.
XPERCON register bit mapping mified according to new peripherals implementation.
External bus NO ARBITRATION and READY, hold and ready pins not available
On-chip low power oscillator, 32 KHz, is no longer available.
Figure 1.
Logic symbol
V18 VDD VSS
Port 0
16-bit
XTAL1
XTAL2
Port 1
16-bit
RSTIN
RSTOUT
VAREF
Port 2
14-bit
VAGND
Port 3
12-bit
ST10F252M
NMI
EA / VSTBY
Port 4 (high)
4-bit
RPD
ALE
Port 5
10-bit
RD
Port 7 or Port 4 (low)
4-bit
WR / WRL
18/328
ST10F252M
2
Pin data
Pin data
Figure 2.
Pin configuration (top view)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
2
3
4
5
6
7
8
9
75
74
73
72
71
70
69
68
67
66
65
64
62
61
60
59
58
57
56
55
54
53
52
51
P0H.4 / AD12 / AN15
P0H.3 / AD11 / AN14
P0H.2 / AD10 / AN13
P0H.1 / AD9 / AN12
P0H.0 / AD8 / AN11
P0L.7 / AD7 / AN10
P0L.6 / AD6
RSTIN
RSTOUT
NMI
P2.2 / CC2IO
P2.3 / CC3IO
P2.4 / CC4IO
P2.5 / CC5IO
P2.6 / CC6IO
P2.7 / CC7IO
P0L.5 / AD5
P0L.4 / AD4
10
11
12
13
14
15
16
17
18
19
20
P0L.3 / A3
P2.8 / CC8IO / EX0IN
P2.9 / CC9IO / EX1IN
P0L.2 /
PAD1
V
DD
P0L.0 / AD0
V
SS
ST10F252M
V
V
18
18
V
P2.10 / CC10IO / EX2IN
P2.11 / CC11IO / EX3IN
P2.12 / CC12IO / EX4IN
P2.13 / CC13IO / EX5IN
P2.14 / CC14IO / EX6IN
P2.15 / CC15IO / EX7IN / T7IN
P5.0 / AN0
SS
V
DD
EA / Vstby
ALE
WR / WRLN
RD
21
22
23
RPD
P4.7 / A23 / CAN2_TxD
P5.1 / AN1
P4.6 / A22 / CAN1_TxD / CAN2_TxD
P4.5 / A21 / CAN1_RxD / CAN2_RxD
P4.4 / A20 / CAN2_RxD
P5.2 / AN2
24
25
P5.3 / AN3
P5.4 / AN4
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TQFP100
Table 1.
Symbol
Pin description
Pin
Type
Function
Reset Input with Schmitt-trigger characteristics. A low level at this pin for a
specified duration while the oscillator is running resets the ST10F252M. An internal
RSTIN
1
I
pull-up resistor permits power-on reset using only a capacitor connected to VSS.
In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register),
the RSTIN line is pulled low for the duration of the internal reset sequence.
Internal reset indication output. This pin is set to a low level when the device is
executing either a hardware, a software or a watchdog timer reset. RSTOUT
remains low until the EINIT (end of initialization) instruction is executed.
RSTOUT
2
3
O
I
Non-maskable interrupt input. A high to low transition at this pin causes the CPU to
vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the
PWRDN (power-down) instruction is executed, the NMI pin must be low in order to
force the ST10F252M to go into power-down mode. If NMI is high and PWDCFG
=’0’, when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
NMI
19/328
Pin data
Table 1.
ST10F252M
Pin description (continued)
Symbol
Pin
Type
Function
PORT2 is a 14-bit bidirectional I/O port. It is bitwise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT2 outputs can be configured as
push/pull or open drain drivers. The input threshold of PORT2 is selectable (TTL or
CMOS).
4-11
15-20
I/O
The following PORT2 pins have alternate functions:
4
...
9
I/O P2.2
... ...
CC2IO
...
CAPCOM1: CC2 capture input / compare output
...
I/O P2.7
CC7IO
CC8IO
EX0IN
CC9IO
EX1IN
CC10IO
EX2IN
...
CAPCOM1: CC7 capture input / compare output
CAPCOM1: CC8 capture input / compare output
Fast external interrupt 0 input
I/O
P2.8
I
10
11
P2.2 - P2.15
I/O
CAPCOM1: CC9 capture-in/compae-out
Fast external interrupt 1input
P2.9
I
I/O
I
CAPCOM1: CC10 capture-in/compare-out
Fast external interrupt 2 input
15
...
P2.10
... ...
I/O
...
CC15IO
EX7IN
T7IN
CAPCOM1: CC15 capture-in/compare-out
st external interrupt 7 input
20
I
I
I
P2.15
CAPCOM2 timer T7 count input
21-25
28-32
PORT5 is a 10-bit input-only port with Schmitt-trigger characteristics. The pins of
PORT5 can be the analog input channels (up to 10) for the A/D converter where
P5.x equivals ANx (analog input channel x).
P5.0–P5.9
I
ORT3 is a 12-bit (P3.3:5, P3.14 are missing) bidirectional I/O port, bitwise
33-35
36,
39-45
46
I/programmable for input or output via direction bit. Programming an I/O pin as input
I/O forces the corresponding output driver to high impedance state. PORT3 outputs
I/O can be configured as push/pull or open drain drivers. The input threshold of
PORT3 is selectable (TTL or CMOS).
The following PORT3 pins have alternate functions:
33
34
35
36
39
40
41
42
43
I
O
I
P3.0
P3.1
P3.2
P3.6
P3.7
T0IN
CAPCOM:1 timer T0 count input
T6OUT
CAPIN
T3IN
GPT2: timer T6 toggle latch output
P3.0–P3.2,
P3.6
GPT2: register CAPREL capture input
I
GPT1: timer T3 count / gate input
P3.7-P3.13
P3.15
I
T2IN
GPT1: timer T2 input for count / gate / reload / capture
SSC0 master-receiver / slave-transmitter I/O
SSC0 master-transmitter / slave-receiver O/I
ASC0: clock / data output (asynchronous / synchronous)
ASC0: data input (asynchronous) or I/O (synchronous)
External memory high byte enable signal
External memory high byte write strobe
I/O P3.8
I/O P3.9
MRST0
MTSR0
TxD0
O
P3.10
I/O P3.11
RxD0
BHE
O
44
P3.12
O
WRH
20/328
ST10F252M
Pin data
Table 1.
Symbol
Pin description (continued)
Pin
Type
Function
P3.0–P3.2,
P3.6
45
I/O P3.13
SCLK0
SSC0: master clock output / slave clock input
System clock output (programmable divider on CPU
clock)
P3.7-P3.13
P3.15
46
O
P3.15
CLKOUT
PORT7 is a 4-bit bidirectional I/O port, bitwise programmable for input or output via
direction bit (this port is connected to pins 47-50 only if bit P7EN of XMISC register
is set.). Programming an I/O pin as input forces the corresponding output driver to
47-50
I/O high impedance state. PORT7 outputs can be configured as push/pull or open
drain drivers. The input threshold of PORT7 is selectable (TTL or CMOS).
The following PORT7 pins have alternate functions: (only if bit P7EN of XMISC
register is set)
P7.0–P7.3
47
...
O
P7.0
POUT0
...
PWM0: channel 0 output
PWM0: channel 1 output
PWM0: channel 3 output
... ...
50
O
P7.3
POUT3
PORT4 is an 8-bit bidirectional I/O port. P4.0-P4.3 are connected to pins 47-50
only if P7EN of XMISC is not set (default aftereset).
It is bit-wise programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance state.
In case of an external bus configuraon, PORT4 can be used to output the
segment address lines (A16.19 output only if bit P7EN of XMISC register is not
set):
47-54
I/O
47
48
49
50
O
O
O
O
O
I
P4.0
P4.1
P4.2
4.3
A16
A17
A18
A19
A20
Segment address line
Segment address line
Segment address line
Segment address line
Segment address line
P4.0–P4.7
51
P4.4
CAN2_RxD CAN2: receive data input
A21 Segment address line
O
I
52
P4.5
CAN1_RxD CAN1: receive data input
CAN2_RxD CAN2: receive data input
I
O
O
O
O
O
A22
Segment address line
53
54
P4.6
P4.7
CAN1_TxD
CAN2_TxD
A23
CAN1 transmit data output
CAN2 transmit data output
Segment address line
CAN2_TxD
CAN2 transmit data output
Timing pin for the return from interruptible power-down and synchronous /
asynchronous reset selection.
RPD
RD
55
56
-
External memory read strobe. RD is activated for every external instruction or data
read access.
O
21/328
Pin data
Table 1.
ST10F252M
Pin description (continued)
Symbol
Pin
Type
Function
External memory write strobe. In WR-mode this pin is activated for every external
data write access. In WRL-mode this pin is activated for low byte data write
accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in SYSCON register for mode selection.
WR/WRL
ALE
57
O
Address latch enable output. In case of use of external addressing or of
multiplexed mode, this signal is the latch command pf the address lines.
58
59
O
External access enable pin.
A low level applied to this pin during and after Reset forces the ST10F252M to start
the program from the external memory space. A high level forces ST10F252M to
start in the internal memory space. This pin is also used (when Stand-by mode is
entered, that is ST10F252M under reset and main VDD turned off) to provide a
reference voltage for the low-power embedded voltage regulator which generates
the internal 1.8V supply for the RTC module (when not disabled) and to retain data
inside the Stand-by portion of the XRAM (16 Kbyte).
EA / VSTBY
I
It can range from 4.5 to 5.5V. In running mode, this pin cabe tied low during reset
RTC and XRAM activities, since the presence of a table VDD guarantees the
proper biasing of all those modules.
PORT0 is a two 8-bit bidirectional I/O ports P0L and P0H, bitwise programmable
for input or output via direction bit. Progamming an I/O pin as input forces the
corresponding output driver to high pedance state. The input threshold of
PORT0 is selectable (TTL or CMOS).
In case of an external bucoguration, PORT0 serves as the address (A) and as
the address / data (AD) in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bus modes
Data path width
P0L.0 – P0L.7:
P0H.0 – P0H.7:
8-bit
16-bit
D0 – D7
I/O
D0 - D7
D8 - D15
63-70
71-78
P0L.0-P0L.7,
P0H.0-P0H.7
I/O
Multiplexed bus modes
Data path width
P0L.0 – P0L.7:
P0H.0 – P0H.7:
8-bit
16-bit
AD0 – AD7
A8 – A15
AD0 - AD7
AD8 - AD15
The pins of P0L / P0H also serve as the additional (up to six) analog input channels
for the A/D converter, where P0L.7 equals to AN10 and P0H.x equals ANy (Analog
input channel y, where y = x + 11). This additional function has a higher priority on
demultiplexed bus function.
PORT1 is a two 8-bit bidirectional I/O ports P1L and P1H, bitwise programmable
for input or output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes: If at least BUSCONx is configured
such that the demultiplexed mode is selected, the pins of PORT1 are not available
for general purpose I/O function. The input threshold of PORT1 is selectable (TTL
or CMOS).
79-86
89-96
I/O
O
P1L.0-P1L.7,
P1H.0-P1H.7
The following PORT1 pins have alternate functions:
79
P1L.0
XPOUT
XPWM: channel 0 output
22/328
ST10F252M
Pin data
Table 1.
Symbol
Pin description (continued)
Pin
Type
Function
80
81
82
83
84
85
86
O
O
O
O
P1L.1
P1L.2
P1L.3
P1L.4
XPOUT
XPOUT
XPOUT
TxD1
XPWM: channel 1 output
XPWM: channel 2 output
XPWM: channel 3 output
ASC1: data input (asynchronous / synchronous)
I/O P1L.5
I/O P1L.6
I/O P1L.7
I/O P1H.0
RxD1
SCL
ASC1: data input (asynchronous) or I/O (synchronous)
I2C interface serial clock
SDA
I2C interface serial data
General purpose input
P1L.0-P1L.7,
P1H.0-P1H.7
89
I
P3.4
T3EUD
MRST1
MTSR1
SCLK1
CC24I
CC25I
CC26I
CC27I
GPT3: external up / down
90
91
92
93
94
95
96
98
I/O P1H.1
I/O P1H.2
I/O P1H.3
SSC1: master-receiver / slave-transmitter I/O
SSC1: master-transmitter / slareceiver O/I
SSC1: master clock output / slave clock input
CAPCOM2: CC24 apture input
I
I
P1H.4
P1H.5
P1H.6
P1H.7
XTAL2
CAPCOM2: CC25 capture input
I
CAPCOM2: CC26 capture input
I
APCOM2: CC27 capture input
XTAL2
O
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while leaving XTAL2
unconnected. Minimum and maximum high/low and rise/fall times specified in the
AC characteristics must be observed.
XTAL1
VAREF
VAGND
99
26
27
I
-
-
TAL1
Main oscillator amplifier circuit and/or external clock input.
A/D converter reference voltage and analog supply.
A/D converter reference and analog ground.
1.8 V decoupling pin.
V18
VDD
VSS
14, 62
O
-
A decoupling capacitor (typical value of 10 nF, max. 100 nF) must be connected
between this pin and nearest VSS pin.
12, 38,
60, 87,
97
Digital supply voltage = +5 V during normal operation, idle mode and power-down
modes.
It can be turned off when Stand-by RAM mode is selected.
13, 37,
61, 88,
100
-
Digital ground.
23/328
Functional description
ST10F252M
3
Functional description
The architecture of the ST10F252M combines advantages of both RISC and CISC
processors and an advanced peripheral subsystem. The block diagram gives an overview of
the different on-chip components and the high bandwidth internal bus structure of the
ST10F252M.
Figure 3.
Block diagram
16
16
16
XRAM2
12K
(STBY)
32
IFlash
256K
IRAM
2K
CPU-Core and MAC Unit
16
XRAM1
2K
(PEC)
Watchdog
Oscillator
PEC
16
16
16
XPWM
XASC
16 16
16 16
16 16
Interrupt Controller
XRTC
PLL
5V-1.8V
Voltage
Regulator
XI2C
XSSC
XCAN1
XCAN2
16
16
8
14
BRG
BRG
Port 5
10
Port 3
12
Port 7
4
24/328
ST10F252M
Memory organization
4
Memory organization
The memory space of the ST10F252M is configured in a unified memory architecture. Code
memory, data memory, registers and I/O ports are organized within the same linear address
space of 16 Mbytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bit
addressable.
IFlash: 256 Kbytes of on-chip Flash memory. It is divided in eight blocks (B0F0...B0F7) that
constitute the Bank 0. When bootstrap mode is selected, the Test-Flash Block B0TF
(4 Kbytes) appears at address 00’0000h: refer to Chapter 8: Internal Flash memory for more
details on memory mapping in boot mode. The summary of address range for IFlash is the
following Table 2:
Table 2.
IFlash addresses
Blocks
User Mode
Size
B0TF
B0F0
B0F1
B0F2
B0F3
B0F4
B0F5
B0F6
B0F7
Not visible
4K
8K
00’0000h - 00’1FFFh
00’2000h - 00’3FFFh
00’4000h - 00’5FFFh
00’6000h - 00’7FFFh
000h - 01’FFFFh
02’0000h - 02’FFFFh
03’0000h - 03’FFFFh
04’0000h - 04’FFFFh
05’0000h - 07’FFFFh
08’0000h - 08’FFFFh
8K
8K
8K
32K
64K
64K
64K
192K
64K
Reserved area
FlaRegs
Note:
When bit ROMEN in SYSCON register is set, the address 05’0000h - 07’FFFFh is
considered as reserved (no external memory access is enabled). Trying to read in this
address area outputs dummy data (software trap 009Bh).
IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0
to R15) and/or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group. Base
address is 00’F600h, upper address is 00’FDFFh.
XRAM: 14Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage for
data, user stack and code.
The XRAM is divided into two areas, the first 2 Kbytes named XRAM1 and the second
12 Kbyte named XRAM2, connected to the internal XBUS and are accessed like an external
memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (50 ns
access at 40 MHz CPU clock). Byte and Word accesses are possible.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If bit XRAM1EN or XPEN is cleared,
then any access in the address range 00’E000h - 00’E7FFh will be directed to external
25/328
Memory organization
ST10F252M
memory interface, using the BUSCONx register corresponding to address matching
ADDRSELx register.
The XRAM2 address range is the one selected programming XADDR3 register, if XPEN (bit
2 in SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is
cleared, then any access in the address range programmed for XRAM2 will be directed to
external memory interface, using the BUSCONx register corresponding to address
matching ADDRSELx register.
After reset, the XRAM2 address range is 09’0000h-09’3FFFh and is mirrored every
16 Kbyte boundary until 0F’FFFFh.
XRAM2 also represents the Stand-by RAM, which can be maintained biased through
EA/V
pin when the main supply V is turned off.
STBY
DD
As the XRAM appears like external memory, it cannot be used as system stack or as
register banks. The XRAM is not provided for single bit storage and therefore is not bit
addressable.
SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for he special function
register areas. SFRs are Wordwide registers which are used to conl and to monitor the
function of the different on-chip units.
CAN1: Address range 00’EF00h - 00’EFFFh is reserved fr the CAN1 module access. The
CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
0 of the XPERCON register. Accesses to the CAN1 module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 100 ns at 40 MHz CPU clock. No trate waitstate is used.
CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 module access. The
CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
1 of the XPERCON register. Accesses to the CAN2 module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used.
Note:
If one or the two AN modules are used, Port 4 cannot be programmed to output all eight
segment address lines. Thus, only four segment address lines can be used, reducing the
externamemory space to 5 Mbytes (1 Mbyte per CS line).
XRTC: Address range 00’ED00h - 00’EDFFh is reserved for the XRTC module access. The
XRTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON
register. Accesses to the XRTC module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two wait states give an access time of 100.0 ns at
40 MHz CPU clock. No tristate waitstate is used.
XPWM: Address range 00’EC00h - 00’ECFFh is reserved for the XPWM module access.
The XPWM is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the
XPERCON register. Accesses to the XPWM module use demultiplexed addresses and a 16-
bit data bus (only word accesses are possible). Two waitstates give an access time of
100.0 ns at 40 MHz CPU clock. No tristate waitstate is used. Only word access is allowed.
XASC: Address range 00’E900h - 00’E9FFh is reserved for the XASC module access. The
XASC is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON
register. Accesses to the XASC module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100.0 ns at
40 MHz CPU clock. No tristate waitstate is used.
26/328
ST10F252M
Memory organization
XSSC: Address range 00’E800h - 00’E8FFh is reserved for the XSSC module access. The
XSSC is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON
register. Accesses to the XSSC module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100.0 ns at
40 MHz CPU clock. No tristate waitstate is used.
2
2
XI C: Address range 00’EA00h - 00’EAFFh is reserved for the XI C module access. The
2
XI C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON
2
register. Accesses to the XI C module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100.0 ns at
40 MHz CPU clock. No tristate waitstate is used.
X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set
of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON
register and bit10 of the XPERCON register. Accesses to these additional features use
demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two
waitstates give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is
used. The following set of features are provided:
●
●
●
●
●
●
●
●
CLKOUT programmable divider
XBUS interrupt management registers
CAN2 multiplexing on P4.5/P4.6
CAN1-2 main clock prescaler
main voltage regulator disable for power-don mode
TTL / CMOS threshold selection for Port0, Port1, and Port5
Flash temporary unprotection
Port4/Port7 selection for pins 47-50
In order to keep the needs of designs where more memory is required than is provided on
the chip, up to 16 Mbytes of external memory can be connected to the microcontroller.
Note:
When P7EN bit is set in XMISC register, the Port7 low nibble is available on the pins 47 to
50 and Port4 low s not available. Therefore the relative address lines are not available and
the external memory space is reduced to 64 Kbytes."
Visibility of XBUS peripherals
In order to keep the ST10F252M compatible with ST10F168 / ST10F269, the XBUS
peripherals can be selected to be visible on the external address / data bus. Different bits for
X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the
global enabling with XPEN bit in SYSCON register, the corresponding address space, port
pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and
not available. Refer to Chapter 26: Register set on page 254
XPERCON and XPEREMU clock gating
As already mentioned, the XPERCON register has to be programmed to enable the single
X-BUS modules separately. The XPERCON is a read/write ESFR register.
The new feature of clock gating has been implemented by mean of this register. Once the
EINIT instruction has been executed, all the peripherals (except RAMs and XMISC), not
enabled in the XPERCON register are not be clocked. The clock gating can reduce power
consumption and improve EMI when the user doesn’t use all the X-Peripherals
Note:
When the clock has been gated in the disabled Peripherals, no Reset will be raised once the
EINIT instruction has been executed.
27/328
Memory organization
ST10F252M
4.1
XPERCON and XPEREMU registers
Once the XPEN bit of the SYSCON register is set and at least one of the X-peripherals
(except memories) is activated, the register XPEREMU must be written with the same
content of XPERCON: this is mandatory to allow correct emulation of the features on the
X-BUS for the new ST10 generation.
XPEREMU must be programmed after XPERCON and after SYSCON so that the final
configuration for X-peripherals is stored in XPEREMU and used for the emulation hardware
setup.
XPERCON
15
14
13
12
11
10
9
8
7
6
5
-
4
3
2
1
0
reserved
-
-
-
-
-
RW
RW
RW
RW
RW
RW
W
RW
RW
RW
Table 3.
Bit
XPERCON register functions
Name
Function
15:11
Reserved
XBUS additional tures enable bit
‘0’: Access e additional miscellaneous features is disabled. The
address range 00’EB00h-00’EBFFh is directed to external memory
only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XSSCEN, XPWMEN
and XI2CEN are ‘0’ also.
10
XMISCEN
XI2CEN
‘1’: The Additional Features are enabled and can be accessed.
XI2C enable bit
‘0’: Accesses to the on-chip XI2C are disabled, external access is
performed. The address range 00’EA00h-00’EAFFh is directed to
external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN,
XSSCEN, XPWMEN and XMISCEN are ‘0’ also.
9
‘1’: The on-chip XI2C is enabled and can be accessed.
XSSC enable bit
‘0’: Accesses to the on-chip XSSC are disabled, external access is
performed. The address range 00’E800h-00’E8FFh is directed to
external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN,
XI2CEN, XPWMEN and XMISCEN are ‘0’ also.
8
XSSCEN
XASCEN
‘1’: The on-chip XSSC is enabled and can be accessed.
XASC enable bit
‘0’: Accesses to the on-chip XASC are disabled, external access is
performed. The address range 00’E900h-00’E9FFh is directed to
external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN,
XI2CEN, XPWMEN and XMISCEN are ‘0’ also.
7
‘1’: The on-chip XASC is enabled and can be accessed.
28/328
ST10F252M
Memory organization
Table 3.
Bit
XPERCON register functions (continued)
Name
Function
XPWM enable
‘0’: Accesses to the on-chip XPWM module are disabled, external
access is performed. The address range 00’EC00h-00’ECFF is
directed to external memory only if CAN1EN, CAN2EN, XASCEN,
XSSCEN, XI2CEN, XRTCEN and XMISCEN are ‘0’ also.
6
5
4
XPWMEN
Reserved
XRTCEN
‘1’: The on-chip XPWM module is enabled and can be accessed.
XRTC enable
‘0’: Accesses to the on-chip XRTC module are disabled, external
access is performed. The address range 00’ED00h-00’EDFF is
directed to external memory only if CAN1EN, CAN2EN, XASCEN,
XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also.
‘1’: The on-chip XRTC module is enabled and can be accessed.
XRAM2 enable bit
‘0’: Accesses to the on-chip 16 Kbyte AM are disabled, external
access is performed.
3
2
XRAM2EN
XRAM1EN
‘1’: The on-chip 16 Kbyte XRAM ienabled and can be accessed.
XRAM1 enable bit
‘0’: Accesses to the on-cip 2 Kbyte XRAM are disabled. The address
range 00’E000h-E7FFh is directed to external memory.
‘1’: The on-2 Kbyte XRAM is enabled and can be accessed.
CAN2 enable bit
‘0’: Accesses to the on-chip CAN2 X=peripheral and its functions are
disabled (P4.4 and P4.7 pins can be used as general purpose I/Os, but
the address range 00’EC00h-00’EFFFh is directed to external memory
only if CAN1EN, XRTCEN, XASCEN, XSSCEN, XI2CEN, XPWMEN
and XMISCEN are ‘0’ also).
1
0
CAN2EN
CAN1EN
‘1’: The on-chip CAN2 X-peripheral is enabled and can be accessed.
CAN1 enable bit
‘0’: Accesses to the on-chip CAN1 X-peripheral and its functions are
disabled (P4.5 and P4.6 pins can be used as general purpose I/Os, but
the address range 00’EC00h-00’EFFFh is directed to external memory
only if CAN2EN, XRTCEN, XASCEN, XSSCEN, XI2CEN, XPWMEN an
XMISCEN are ‘0’ also).
‘1’: The on-chip CAN1 X-peripheral is enabled and can be accessed.
2
Note:
When CAN1, CAN2, XRTC, XASC, XSSC, XI C, XPWM and the XBUS additional features
are all disabled via XPERCON setting, any access in the address range 00’E800h -
00’EFFFh is directed to external memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx register. All pins involved with
29/328
Memory organization
ST10F252M
X-peripherals, can be used as general purpose I/O whenever the related module is not
enabled.
2
When one or more of the peripherals XASC, XI C, XSSC, and XPWM are enabled, port P1
cannot be used for external memory addressing, that is, the external bus controller in
demultiplexed mode is not available.
The default XPER selection after reset is identical to XBUS configuration of
ST10F168/ST10F269: CAN1 is enabled, CAN2 is disabled, XRAM1 (2 Kbyte XRAM) is
enabled, XRAM2 (16 Kbyte XRAM) is disabled; all the other X-peripherals are disabled after
reset.
The register XPERCON cannot be changed after the global enabling of X-peripherals, that
is, after setting of bit XPEN in SYSCON register.
In Emulation mode, all the X-peripherals are enabled (XPERCON bits are all set). It is up to
the bondout chip (ST10R201) whether of not to redirect an access to external memory or to
XBUS.
Reserved bits of XPERCON register are always written to ‘0’.
XPEREMU
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
The bit meaning is exactly the same as XPERCON.
4.2
Emulation dedicated registers
A set of four addional registers are for emulation purpose only. Similarly to XPEREMU, they
are write only registers.
Emulation register 1
15
14
13
12
11
10
W
9
8
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Emulation register 2
15
14
13
12
11
10
W
9
8
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
30/328
ST10F252M
Memory organization
Emulation register 3
15
14
13
12
11
10
W
9
8
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Emulation register 4
RegTitle
15
14
13
12
11
10
W
9
8
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
4.3
XRAM2 memory range
XRAM2 memory range is addressed by an internal XBUS chip seleThis internal chip
select is enabled when XPEN bit of the SYSCON register is sand XRAM2EN bit of the
XPERCOM register is set. Although this address range is accessed as external memory, it
does not occupy the BUSCONx or ADDRSELx registers but is selected via additional
dedicated XBCON/XADRS registers. The XADRS reet value is mask-programmed but the
XADRS3 register used for flash control registers nd XRAM2 memory range can be
accessed and modified.
XRAM2 memory range
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RGSAD
RGSZ
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 4
it
XRAM2 memory range functions
Name
Function
Range Start Address
Defines the upper bits (A8...A19) of the start address of the respective
address area. Bits A23...A20 of the resulting address are set to 0. See
Table 5.
15:4
3:0
RGSAD
RGSZ
Range Size Selection
Defines the size of the address area controlled by XBCON3 and
XADRS3 register pair. See Table 5.
The register functionality is the same as the one of ADDRSELx registers use for external
address range selection. However, the XADRS3 register is protected and it can only be
written before the EINIT instruction execution. The range start address can be only on
boundaries specified by the selected range size. Table 5 gives a definition of Range Size
Selection and Range Start Address.
Upon Reset, the XADRS3 register is programmed so that address range 08’0000h-
0F’FFFFh is accessed with the internal XBUS chip select. The range 08’0000h-08’FFFFh is
31/328
Memory organization
ST10F252M
overlapped by IFlash memory space (flash control register), which has higher priority on
XBUS space.
The address range defined by XADRS3 can be reduced by reprogramming it before EINIT
execution; the area which is no longer inside the new address range becomes external
memory space (apart from range 08’0000h-08’FFFFh, which is dedicated to IFlash as long
as ROMEN bit in SYSCON register is set).
The address range defined by XADRS3 has priority over any external address range
defined through ADDRSELx (x=1...4) registers.
Table 5.
Definition of address areas
Bit-field RGSZ Resulting Window Size
Relevant bit (R) of Start Address (A19...A8)
A19
A8
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 x x
256 bytes
512 bytes
1 Kbyte
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
x
R
R
R
R
R
R
R
R
R
R
x
R
R
R
R
R
R
R
R
R
x
R
R
R
R
R
R
R
R
x
R
R
R
R
R
R
x
x
x
x
x
R
R
R
R
R
R
x
x
x
x
x
R
R
R
R
R
x
x
x
x
R
R
R
R
x
x
x
x
R
R
R
x
x
x
x
x
x
x
R
R
x
x
x
x
x
x
x
x
x
x
R
x
x
x
x
x
x
x
x
x
x
x
2 Kbytes
4 Kbytes
8 Kbytes
16 Kbytes
32 Kbytes
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
Reserved
x
x
x
x
x
x
x
x
x
x
x
x
x
x
XRAM2 can be remapped on any 16 Kbyte Boundary within 00’8000h-00’BFFF address
area and within 09’0000h-0F’FFFFF address area.
For example, to map the 16Kbyte XRAM2 in page 60 (starting address 0F’0000h,
compatible with ST10F276), XADRS3 must be initialized with the value F006 . To map the
H
16Kbyte XRAM2 n page 2 (starting address 00’8000h, compatible with ST10F280),
XADRS3 must be initialized with the value 0806 .
H
Note:
If XADRS3 is not reprogrammed after reset, the XRAM2 address window overlaps the one
dedicated to IFlash. So Segment 8 address range mapping depends on bits ROMEN and
XPEN of SYSCON register, and XRAM2EN of XPERCON register programming as
summarized in Table 6.
Table 6.
ROMEN
XRAM2EN of XPERCON register programming
XPEN
XRAM2EN
Segment 8
0
0
0
1
0
1
1
x
x
0
1
x
External memory
External memory
Reserved
IFlash registers
32/328
ST10F252M
Figure 4.
Memory organization
ST10F252M memory mapping (user mode: flash read operations or XADRS = F006h)
Code
Segment
Data
Page
Data
Page
Code
Segment
FF FFFF
1023
11 FFFF
67
66
65
64
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
255
17
11 0000
10 FFFF
00 FFFF
SFR
512
2K
00 FE00
00 FDFF
16
10 0000
0F FFFF
I-RAM
15
0F 0000
0E FFFF
X-Peripherals (2Kbyte)
Stand-by RAM
00 F600
00 F5FF
14
0E 0000
0D FFFF
00 F000
00 EFFF
1K
Reserved
ESFR
XCAN1
XCAN2
256
256
256
00 F200
00 F1FF
00 EF00
00 EEFF
13
0D 0000
0C FFFF
512
00 F000
00 EFFF
XCAN1
XCAN2
XRTC
256
256
256
256
EE00
EDFF
12
0C 0000
0B FFFF
XPWM
XRTC
XPWM
XMiscellaneous 256
00 ED00
00 ECFF
XI2C
XASC
XSSC
56
256
256
11
0B 0000
0A FFFF
256
256
256
256
256
00 E800
00 E7FF
00 EC00
00 EBFF
10
0A 0000
09 FFFF
XMiscellaneous
XI2C
00 EB00
00 EAFF
XRAM1
2K
9
09 0000
08 FFFF
00 EA00
00 E9FF
Flash Registers
+
FPEC RAM/ROM
00 E000
00 DFFF
XASC
XSSC
8
08 0000
07 FFFF
33
32
00 E900
00 E8FF
3
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
reserved
reserved
reserved
7
07 0000
06 FFF
00 E800
00 E7FF
6
06 0000
05 FFFF
5
05 0000
04 FFFF
B0F7
(IFlash)
4
04 0000
03 FFFF
Ext. Memory
8K
B0F6
(IFlash)
3
03 0000
02 FFFF
B0F5
(IFlash)
2
02 0000
01 FFFF
8
7
B0F4
(IFlash)
6
1
01 0000
00 FFFF
5
Ext. Memory
4
3
2
B0F3
B0F2
B0F1
B0F0
0
00 0000
1
0
0
0
00 0000
00 C000
Flash + XRAM - 1Mbyte
Data Page 3 (Segment 0) - 16Kbyte
16 MB
* XRAM2 (Stand-by RAM) can be located on any 16K boundary within memory space marked
33/328
Memory organization
ST10F252M
Figure 5.
ST10F252M memory mapping (user mode: flash write operations or ROMS1=1)
Code
Segment
Data
Page
Data
Page
Code
Segment
FF FFFF
1023
11 FFFF
67
66
65
64
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
3
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
255
17
11 0000
10 FFFF
00 FFFF
SFR
512
2K
00 FE00
00 FDFF
16
10 0000
0F FFFF
I-RAM
15
0F 0000
0E FFFF
X-Peripherals (2Kbyte)
Stand-by RAM
00 F600
00 F5FF
14
0E 0000
0D FFFF
00 F000
00 EFFF
1K
Reserved
ESFR
XCAN1
XCAN2
256
256
256
00 F200
00 F1FF
00 EF00
00 EE
13
0D 0000
0C FFFF
512
00 F000
00 EFFF
XCAN1
XCAN2
XRTC
256
256
256
256
26
256
256
256
0EE00
00 EDFF
12
0C 0000
0B FFFF
XPWM
XRTC
XPWM
XMiscellaneous
XI2C
00 ED00
00 ECFF
11
0B 0000
0A FFFF
XASC
XSSC
256
256
256
256
256
00 E800
00 E7FF
00 EC00
00 EBFF
10
0A 0000
09 FFFF
XMiscellaneous
XI2C
00 EB00
00 EAFF
XRAM1
2K
9
09 0000
08 FFFF
00 EA00
00 E9FF
00 E000
00 DFFF
Flash Registers
+
XASC
XSSC
8
08 0000
07 FFFF
FPEC RAM/ROM
00 E900
00 E8FF
Reserved
Reserved
Reserved
7
07 0000
06 FF
00 E800
00 E7FF
6
06 0000
05 FFFF
5
05 0000
04 FFFF
B0F7
4
04 0000
03 FFFF
(IFlash)
Ext. Memory
8K
B0F6
(IFlash)
3
03 0000
02 FFFF
B0F5
(IFlash)
2
02 0000
01 FFFF
8
7
B0F4
(IFlash)
6
1
01 0000
00 FFFF
B0F3
B0F2
B0F1
B0F0
5
4
3
2
0
00 0000
Ext. Memory
1
0
0
0
00 0000
00 C000
Flash + XRAM - 1Mbyte
Data Page 3 (Segment 0) - 16Kbyte
16 MB
* XRAM2 (Stand-by RAM) can be located on any 16K boundary within memory space marked
34/328
ST10F252M
Central processing unit
5
Central processing unit
The central processing unit (CPU) includes a four-stage instruction pipeline, a 16-bit
arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware provides for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Most of the ST10F252M’s instructions can be executed in one instruction cycle which
requires 50 ns at 40 MHz CPU clock. For example, shift and rotate instructions are
processed in one instruction cycle independent of the number of bits to be shifted. Multiple-
cycle instructions have been optimized; branches are carried out in two cycles, 16 x 16 bit
multiplication in five cycles and a 32/16 bit division in ten cycles. The jump cache reduces
the execution time of repeatedly performed jumps in a loop, from two cycles to one cycle.
Figure 6.
CPU block diagram (MAC unit not included)
1
CPU
MDH
2K Byte
Internal
RAM
SP
STKOV
R15
MDL
STKUN
Mul./Div.-HW
Bit-Mask Gen.
256 Kbyte
Bank
n
Exec. Unit
Instr. Ptr
General
Purpose
Registers
Flash
memory
4-Stage
Pipeline
U
16-Bit
32
R0
PSW
SYSCON
Bank
i
Barrel-Shift
CP
BUSCON 0
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Bank
0
ADDRSEL 4
16
Code Seg. Ptr.
Data Pg. Ptrs
The CPU uses an actual register context consisting of up to 16 wordwide GPRs physically
allocated within the on-chip RAM area. A context pointer (CP) register determines the base
address of the active register bank to be accessed by the CPU. The number of register
banks is only restricted by the available internal RAM space. For easy parameter passing, a
register bank may overlap others.
A system stack of up to 1024 bytes is provided as a storage for temporary data. The system
stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack
pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared
against the stack pointer value upon each stack access for the detection of a stack overflow
or underflow.
35/328
Central processing unit
ST10F252M
5.1
The system configuration register SYSCON
This bit-addressable register provides general system configuration and control functions.
The RESET value for register SYSCON depends on the state of the Port 0 pins during
RESET.
System configuration register SYSCON
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 7.
Bit
System configuration register SYSCON functions
Name
Function
15:14
Reserved
System stack size
13
12
STKSZ
ROMS1
Selects the size of the system stak (in the internal I-RAM) from 32 to
1024 words.
Internal memory mappi
‘0’: Internal memory area mapped to segment 0
(00’0000h...7FFh).
‘1’: Internal mory area mapped to segment 1
(01’0000h...01’7FFFh).
Segmentation disable/enable control
‘0’: Segmentation enabled (CSP is saved/restored during interrupt
entry/exit).
11
SGTDIS
‘1’: Segmentation disabled (only IP is saved/restored).
Internal memory enable (set according to pin EA during reset)
‘0’: Internal memory disabled: accesses to the I-Flash memory area
use the external bus.
‘1’: Internal memory enabled.
10
9
ROMEN
BYTDIS
Disable/enable control for pin BHE (set according to data bus width)
‘0’: Pin BHE enabled.
‘1’: Pin BHE disabled, pin P3.12 may be used for general purpose I/O.
System clock output enable (CLKOUT)
‘0’: CLKOUT disabled, pin P3.15 may be used for general purpose I/O.
‘1’: CLKOUT enabled, pin P3.15 outputs the system clock or a
prescaled value of system clock according to XCLKOUTDIV register
setting (see Section 15).
8
CLKEN
Write configuration control (inverted copy of WRC bit of RP0H)
‘0’: Pins WR and BHE retain their normal function.
‘1’: Pin WR act as WRL, pin BHE acts as WRH.
7
6
WRCFG
Reserved
36/328
ST10F252M
Central processing unit
System configuration register SYSCON functions (continued)
Table 7.
Bit
Name
Function
Power down mode configuration control
‘0’: Power down mode can only be entered during PWRDN instruction
execution if NMI pin is low, otherwise the instruction has no effect. To
exit power down mode, an external reset must occurs by asserting the
RSTIN pin.
5
PWDCFG
‘1’: Power down mode can only be entered during PWRDN instruction
execution if all enabled fast external interrupt EXxIN pins are in their
inactive level. Exiting this mode can be done by asserting one enabled
EXxIN pin or with external reset.
Oscillator watchdog disable control
‘0’: Oscillator watchdog (OWD) is enabled. If PLL is bypassed, the
OWD monitors XTAL1 activity. If there is no activity on XTAL1 for at
least 1 µs, the CPU clock is switched automatically to PLL’s base
frequency (around 750 kHz-3 MHz).
4
OWDDIS
‘1’: OWD is disabled. If the PLL is bypassed, the PU clock is always
driven by XTAL1 signal. The PLL is turned off reduce power supply
current.
XBUS peripheral enable bit
‘0’: Accesses to the on-chip X-peripherals and their functions are
disabled.
‘1’: The on-chip X-periphrals are enabled and can be accessed.
3
3
1
XPEN
BDRSTEN
VIBLE
Bidirectionesenable
‘0’: RSTIN piis an input pin only. SW Reset or WDT Reset have no
effect on this pin.
‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024
TCL during reset sequence.
Visible mode control
‘0’: Accesses to XBUS peripherals are internal.
‘1’: XBUS peripherals accesses are visible externally on the external
pins.
37/328
Multiplier-accumulator unit
ST10F252M
6
Multiplier-accumulator unit
The multiplier-accumulator (MAC) unit is a specialized co-processor that improves the
performance of signal processing algorithms. It includes:
●
●
●
a multiply-accumulate unit.
an address generation unit, able to feed the MAC unit with two operands per cycle.
a repeat unit, to execute a series of multiply-accumulate instructions.
The CPU can supply the MAC with up to two operands per instruction cycle. The MAC
instructions multiply, multiply-accumulate, 32-bit signed arithmetic operations and the
CoMOV transfer instruction are part of the standard instruction set. Full details are provided
in the ‘ST10 Family Programming Manual’.
6.1
MAC features
6.1.1
Enhanced addressing capabilities
The MAC has the following enhanced addressing capabilities:
●
double indirect addressing mode with pointer post-modification
●
parallel data move allows one operand movduring multiply-accumulate instructions
without penalty
●
coSTORE instruction (for fast acto the MAC SFRs) and CoMOV (for fast memory
to memory table transfer).
6.1.2
General
The MAC also has the following features:
●
●
●
●
●
●
●
●
two-cycle ecution for all MAC operations
16 x 16 signed/unsigned parallel multiplier
40-bit signed arithmetic unit with automatic saturation mode
40-bit accumulator
8-bit left/right shifter
scaler (one-bit left shifter)
data limiter
full instruction set with multiply and multiply-accumulate, 32-bit signed arithmetic and
compare instructions
●
three 16-bit status and control registers: MSW (MAC status word), MCW (MAC control
word), and MRW (MAC repeat word).
The working register of the MAC unit is a dedicated 40-bit wide accumulator register. A set
of consistent flags is automatically updated in the MSW register (see Section 6.3.2) after
each MAC operation. These flags allow branching on specific conditions. Unlike the PSW
flags, these flags are not preserved automatically by the CPU upon entry into an interrupt or
trap routine. All dedicated MAC registers must be saved on the stack if the MAC unit is
shared between different tasks and interrupts.
38/328
ST10F252M
Multiplier-accumulator unit
6.1.3
Program control
MAC program control features include:
●
●
a repeat unit that allows some MAC co-processor instructions to be repeated up to
8192 times – repeated instructions may be interrupted
MAC interrupt (class B trap) on MAC condition flags.
6.2
MAC operation
*
Figure 7.
MAC unit architecture
Operand 1
16
Operand 2
16
(1)
GPR Pointers
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
16 x 16
signed/unsgn
Mplier
QX0 IDX Offset Register
QX1 IDX Offset Register
Concatenation
32
32
Mux
Sign Extend
Scaler
MRW
0h
08000h
0h
40
40
40 40
Mux
40
Mux
Repeat Unit
MCW
Interrupt
Controller
40
A
40
B
ST10 CPU
40-bit Signed Arithmetic Unit
MSW
40
Flags MAE
MAH
40
MAL
Control Unit
Data
Limiter
8-bit Left/Right
Shifter
1. Shared with standard ALU.
6.2.1
Instruction pipelining
All MAC instructions use the four-stage pipeline. During each stage the following tasks are
performed.
1. FETCH: All new instructions are double-word instructions.
2. DECODE: If required, operand addresses are calculated and the resulting operands
are fetched. IDX and GPR pointers are post-modified if necessary.
3. EXECUTE: Performs the MAC operation. At the end of the cycle, the accumulator and
the MAC condition flags are updated if required. Modified GPR pointers are written-
back during this stage, if required.
4. WRITEBACK: Operand write-back in the case of parallel data move.
39/328
Multiplier-accumulator unit
ST10F252M
6.2.2
Particular pipeline effects with the MAC unit
Because the registers used by the MAC are shared with the standard ALU and because of
the MAC instructions pipelining, some care must be taken when switching from the
“standard instruction set” to the “MAC instruction set”.
Initialization of the pointers and offset registers
The MAC instructions which use IDXi pointer are mostly not capable of using a IDXi register
value, which is updated by an immediately preceding instruction. Thus, to make sure that
the IDXi register value is used, at least one instruction must be inserted between a IDXi-
changing instruction and one MAC instruction which explicitly uses IDXi in its addressing
mode as shown in the following example,
I : MOV IDX0, #0F200h
update IDX0 register
n
I
: …
must not be an CoXXX [IDX0⊗], [Rw ⊗] instruction
n+1
n+2
m
first operand read at (IDX0) address provide the MAC
function
I
:CoXXX [IDX0+QX1], [R2]
parallel data move to (((IDX0))-((QX1))) address (if
CoXXX is CoMACM)
move (R2) content to (IDX0) address (if CoXXX is
CoMOV)
(IDX<(IDX0) + (QX1) post modification of the pointer
The requirements between the update of one of the offset registers, QXi and QRi, and their
next use are the same.
Read access to MAC registers (CoReg)
At least one instruction which does not use the MAC must be inserted between two
instructions that ad from a MAC register. This is because the accumulator and the status
of the MAC are modified during the execute stage.
Table 8.
Example of MAC register read access
Code
MSW (before)
MSW (after)
Comment
MOV MSW, #0
-
0000h
-
MOV R0, #0
-
CoADD R0, R0
0000h
0200h
0200h
00FFh
MSW.Z set at execute
Error!
BFLDL MSW, #FFh, #FFh
In this example, the BFLDL instruction performs a read access to the MSW during the
decode stage while the MSW.Z flag is only set at the end of the execute stage of the
CoADD.
6.2.3
Address generation
MAC instructions can use some standard ST10 addressing modes such as GPR direct or
#data4 for immediate shift value.
40/328
ST10F252M
Multiplier-accumulator unit
Addressing modes have been added to supply the MAC with two new operands per
instruction cycle. These allow indirect addressing with address pointer post-modification.
Double indirect addressing requires two pointers. Any GPR can be used for one pointer, the
other pointer is provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset
registers QR0/QR1 and QX0/QX1 are associated with each pointer (GPR or IDX ). The GPR
i
pointer allows access to the entire memory space, but IDX are limited to the internal dual-
i
port RAM, except for the CoMOV instruction.
Table 9 shows the various combinations of pointer post-modification for each of these 2 new
addressing modes. In this document, the symbols “[Rw ⊗]” and “[IDX ⊗]” refer to these
n
i
addressing modes.
Table 9. Pointer post-modification combinations for IDXi and Rwn
Symbol Mnemonic Address pointer operation
[IDX ] (IDX ) ←(IDX ) (no-op)
i
i
i
[IDX +]
(IDX ) ←(IDX ) +2 (i=0,1)
i i
i
“[IDX ⊗]” stands for
[IDX -]
(IDX ) ←(IDX ) -2 (i=0,1)
i i
i
i
[IDX +QX ]
(IDX ) ←(IDX ) + (QX (i, j =0,1)
i i j
i
j
[IDX - QX ]
(IDX ) ←(IDX ) - QX ) (i, j =0,1)
i i j
i
j
[Rwn]
(Rwn) ←(Rwn) (no-op)
[Rwn+]
(Rwn) ←(Rwn) +2 (n=0-15)
(Rwn) ←(Rwn) -2 (k=0-15)
“[Rwn⊗]” stands for
[Rwn-]
[Rwn+QR ]
(Rwn) ←(Rwn) + (QR ) (n=0-15;j =0,1)
j
j
[Rwn - QR ]
(Rwn) ←(Rwn) - (QR ) (n=0-15; j =0,1)
j
j
For the CoMACM class of instruction, a parallel data move mechanism is implemented. This
class of instructin is only available with double indirect addressing mode. Parallel data
move allows e operand, pointed to by IDX , to be moved to a new location in parallel with
i
the MAoperation. The write-back address of parallel data move is calculated depending
on the post-modification of IDX . It is obtained by the reverse operation than the one used to
i
calculate the new value of IDX . Table 10 shows these rules.
i
Table 10. Parallel data move addressing
Instruction
Writeback address
CoMACM [IDXi+],...
CoMACM [IDXi-],...
<IDXi-2>
<IDXi+2>
<IDXi-QXj>
<IDXi+QXj>
CoMACM [IDXi+QXj],...
CoMACM [IDXi-QXj],...
41/328
Multiplier-accumulator unit
ST10F252M
The parallel data move shifts a table of operands in parallel with a computation on those
operands. Its specific use is for signal processing algorithms like filter computation. Figure 8
gives an example of parallel data move with CoMACM instruction.
Figure 8.
Example of parallel data move
CoMACM [IDX0+], [R2+]
16-bit
n+2
n
n+2
n
IDX0
X
IDX0
X
X
Parallel Data Move
n-2
n-4
n-2
n-4
Before Execution
After Execution
6.2.4
6.2.5
16 x 16 signed / unsigned parallel multiplier
The multiplier executes 16 x 16-bit parallel signed/unsigned fraional and integer multiplies.
The multiplier has two 16-bit input ports, and a 32-bit product output port. The input ports
can accept data from the MA-bus and from the MB-bus. The output is sign-extended and
feeds a scaler that shifts the multiplier output accordig to the shift mode bit MP specified in
the co-processor control word (MCW). The produt can be shifted one bit left to compensate
for the extra sign bit gained in multiplying two 16-bit signed (2’s complement) fractional
numbers if bit MP is set.
40-bit signed arithmetic unit
The arithmetic unit is over 32 bits wide to allow intermediate overflow in a series of
multiply/accumulate operations. The extension flag E, contained in the most significant byte
of MSW, is set when the accumulator has overflowed beyond the 32-bit boundary, that is,
when there are sgnificant (non-sign) bits in the top eight (signed arithmetic) bits of the
accumuator.
The 40-bit arithmetic unit has two 40-bit input ports A and B. The A-input port accepts data
from four possible sources: 00,0000,0000h, 00,0000,8000h (round), the sign-extended
product, or the sign-extended data conveyed by the 32-bit bus resulting from the
concatenation of MA- and MB-buses. Product and concatenation can be shifted left by one
according to MP for the multiplier or to the instruction for the concatenation. The B-input port
is fed either by the 40-bit shifted/not shifted and inverted/not inverted accumulator or by
00,0000,0000h. A-input and B-input ports can receive 00,0000,0000h to allow direct
transfers from the B-source and A-source, respectively, to the accumulator (in the case of
multiplication or shift). The output of the arithmetic unit goes to the accumulator.
It is also possible to saturate the accumulator on a 32-bit value, automatically after every
accumulation. Automatic saturation is enabled by setting the saturation bit MS in the MCW
register. When the accumulator is in the saturation mode and an 32-bit overflow occurs, the
accumulator is loaded with either the most positive or the most negative value representable
in a 32-bit value, depending on the direction of the overflow. The value of the accumulator
upon saturation is 00,7fff,ffffh (positive) or ff,8000,0000h (negative) in signed arithmetic.
Automatic saturation sets the SL flag MSW. This flag is a sticky flag which means it stays set
until it is explicitly reset.
40-bit overflow of the accumulator sets the SV flag in MSW. This flag is also a sticky flag.
42/328
ST10F252M
Multiplier-accumulator unit
6.2.6
40-bit adder/subtracter
The 40-bit adder/subtracter allows intermediate overflows in a series of multiply/accumulate
operations. The adder/subtracter has two input ports. One input is the feedback of the 40-bit
signed accumulator output through the ACCU-shifter.The second input is the 32-bit operand
coming from the one-bit scaler. The 32-bit operands are sign-extended to 40-bit before the
addition/subtraction is performed.
The output of the adder/subtracter goes to the 40-bit signed accumulator. It is also possible
to round and to saturate the result to 32-bit automatically after every accumulation before to
be loaded into the accumulator. The round operation is performed by adding 00’00008000h
to the result. Automatic saturation is enabled by setting the MCW.MS saturation bit.
When the 40-bit signed accumulator is in the overflow saturation mode and an overflow
occurs, the accumulator is loaded with either the most positive or the most negative possible
32-bit value, depending on the direction of the overflow as well as the arithmetic used. The
value of the accumulator upon saturation is 00’7FFF FFFFh (positive) or FF’8000’0000h
(negative).
6.2.7
Data limiter
Saturation arithmetic is also provided to selectively limit overflow, when reading the
accumulator by means of a CoSTORE <destination> MAS instruction. Limiting is performed
on the MAC accumulator. If the contents of the accumulator can be represented in the
destination operand size without overflow, the dalimiter is disabled and the operand is not
modified. If the contents of the accumulatocannot be represented without overflow in the
destination operand size, the limiter situtes a ‘limited’ data as explained in Table 11’
Table 11. Limiter output using CoSTORE instruction
ME-flag
MN-flag
MAS value (saturated MAH value)(1)
Unchanged(2)
0
1
1
x
0
1
7FFFh(3)
8000h(4)
1. If the data limiter is activated, a read with “CoSTORE <destination>, <MAH> instruction” or “CoSTORE
<destination>, <MAS> instruction” gives different results.
2. When the data limiter is disabled, a reading with “CoSTORE <destination>, <MAH> instruction” or
“CoSTORE <destination>, <MAS> instruction” gives the same result.
3. If the data limiter is activated, a read with “CoSTORE <destination>, <MAH> instruction” or “CoSTORE
<destination>, <MAS> instruction” gives different results.
4. If the data limiter is activated, a read with “CoSTORE <destination>, <MAH> instruction” or “CoSTORE
<destination>, <MAS> instruction” gives different results.
6.2.8
The accumulator shifter
The accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The
source accumulator shifting operation are:
●
●
●
no shift (unmodified)
up to 8-bit arithmetic left shift
up to 8-bit arithmetic right shift
MSW.ME, MSW.MSV and MSW.MSL bits (see the MSW register description) are affected
by left shifts. Therefore, if the saturation detection is enabled (MCW.MS bit is set), the
behavior is similar to the one of the adder/subtracter.
43/328
Multiplier-accumulator unit
ST10F252M
Some precautions are required for left shift with enabled saturation. If the MSW.MAE
bit-field (the most significant byte of the 40-bit signed accumulator) contains significant bits,
the 32-bit value in the accumulator is generally saturated. However, it is possible that a left
shift may move some significant bits out of the accumulator. The 40-bit result will be
misinterpreted and will be either not be saturated or saturated incorrectly. There is a chance
that the result of a left shift may produce a result which can saturate an original positive
number to the minimum negative value, or vice versa.
6.2.9
Repeat unit
The MAC includes a repeat unit that allows the repetition of some co-processor instructions
13
up to 2 (8192) times. The repeat count may be specified either by an immediate value (up
to 31 times) or by the content of the repeat count (bits 12 to 0) in the MAC repeat word
(MRW). If the repeat count is “N” the instruction is executed “N+1” times. At each iteration of
a cumulative instruction, the repeat count is tested for zero. If it is zero the instruction is
terminated, otherwise the repeat count is decremented and the instruction is repeated.
During such a repeat sequence, the repeat flag in MRW is set until the last execution of the
repeated instruction.
The syntax of repeated instructions is shown in the following amples:.
1
Repeat #24 times
CoMAC[IDX0+],[R0+]
; repeated 24 imes
In this example, the instruction is repeated accorng to a 5-bit immediate value. The repeat
count in MRW is automatically loaded with this value minus one (MRW=23).
1
MOV MRW, #00FFh
oad MRW
NOP
; instruction latency
Repeat MRW times
CoMACM [IDX1-],[R2+]
; repeated 256 times
In this example, te instruction is repeated according to the repeat count in MRW. Due to the
pipeline procsing at least one instruction should be inserted between the write of MRW
and thext repeated instruction.
Repeat sequences may be interrupted. When an interrupt occurs during a repeat sequence,
the sequence is stopped and the interrupt routine is executed. The repeat sequence
resumes at the end of the interrupt routine. During the interrupt, MR remains set, indicating
that a repeated instruction has been interrupted and the repeat count holds the number
(minus 1) of repetition that remains to complete the sequence. If the repeat unit is used in
the interrupt routine, MRW must be saved and restored before the end of the interrupt
routine.
Note:
The repeat count should be used with caution. In this case, MR should be written as 0. In
general, MR should not be set otherwise correct instruction processing can not be
guaranteed.
6.2.10
MAC interrupt
The MAC can generate an interrupt according to the value of the status flags C (carry), SV
(overflow), E (extension) or SL (limit) of the MSW. The MAC interrupt is globally enabled
when the MIE flag in MCW is set. When it is enabled the flags C, SV, E or SL can trigger a
MAC interrupt when they are set provided that the corresponding mask flag, CM, VM, EM or
LM in MCW, is also set. A MAC interrupt request sets the MIR flag in MSW; this flag must be
44/328
ST10F252M
Multiplier-accumulator unit
reset during the interrupt routine otherwise the interrupt processing restarts when returning
from the interrupt routine.
The MAC interrupt is implemented as a class B hardware trap (trap number Ah - trap priority
I). The associated trap flag in the TFR register is MACTRP, bit #6 of the TFR (this flag must
also be reset in a MAC interrupt request).
As the MAC status flags are updated (or eventually written by software) during the execute
stage of the pipeline, the response time of a MAC interrupt request is three instruction
cycles (see Figure 9). It is the number of instruction cycles required between the time the
request is sent and the time the first instruction located at the interrupt vector location enters
the pipeline. The IP value stacked after a MAC interrupt does not point to the instruction that
triggers the interrupt.
Figure 9.
Pipeline diagram for MAC interrupt response time
Response Time
N
N+1
N
N+2
N+1
N
N+3
N+2
N+1
N
N+4
I1
I2
FETCH
N-1
N-2
N-3
TRAP (1)
N+2
TR(2)
TRAP (1)
N+2
I1
DECODE
N-1
N-2
TRAP (2)
TRAP (1)
EXECUTE
WRITEBACK
N-1
N1
MAC errupt Request
6.2.11
Number representation and rounding
The MAC supports the two’s-complement representation of binary numbers. In this format,
the sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to
one for negative numbers. Unsigned numbers are supported only by multiply/multiply-
accumulate instructions which specifies whether each operand is signed or unsigned.
In two’s comment fractional format, the N-bit operand is represented using the 1.[N-1]
format signed bit, N-1 fractional bits). Such a format can represent numbers between -1
-[N-1]
and +1-2
. This format is supported when MP of MCW is set.
The MAC implements ‘two’s complement rounding’. With this rounding type, one is added to
the bit to the right of the rounding point (bit 15 of MAL), before truncation (MAL is cleared).
6.3
MAC register set
6.3.1
Address registers
The addressing modes require (E)SFRs: two address pointers IDX0 / IDX1 and four offset
registers QX0 / QX1 and QR0 / QR1.
45/328
Multiplier-accumulator unit
Address pointer
ST10F252M
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID Xy
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 12. Address pointer functions
Bit
Name
Function
15.0
IDXy
16-bit IDXy address
Offset register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
QXz/QRz
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Table 13. Offset register functions
Bit
Name
Function
16-bit addrffset for IDXy pointers (QXz) or GPR pointers (QRz).
15.0
QRz/QXz
As MAC instructions handle word operands, bit 0 of these offset
registers is hard-wired to ‘0’.
6.3.2
Accumulator and control registers
The MAC unit Ss include the 40-bit accumulator (MAL, MAH and the low byte of MSW)
and three conol registers: the status word MSW, the control word MCW and the repeat
word MRW.
MAH and MAL are located in the non bit-addressable SFR space.
MAH register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MAH
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 14. MAH register functions
Bit
Name
Function
MAC unit accumulator high (bits [31..16])
15.0
MAH
46/328
ST10F252M
Multiplier-accumulator unit
MAL register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MAL
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 15. MAL register functions
Bit
Name
Function
MAC unit accumulator low (bits [15..0])
15.0 MAL
Status word register
15
MIR
R
14
Res.
-
13
12
11
SV
RW
10
C
9
Z
8
N
7
6
5
4
3
2
1
0
SL
E
E
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 16. Status word register functions
Bit
Name
Function
MAC interruequest
15
14
MIR
Set when the MAC unit generates an interrupt request.
Reserved
Sticky limit flag
Set when the result of a MAC operation is automatically saturated. Also
used for CoMIN, CoMAX instructions to indicate that the accumulator
has changed. It remains set until it is explicitly reset by software.
13
SL
Extension flag
12
11
E
Set when MAE contains significant bits at the end of a MAC operation
Sticky overflow flag
SV
Set when a MAC operation produces a 40-bit arithmetic overflow. It
remains set until it is explicitly reset by software.
Carry flag
19
9
C
Z
Set when a MAC operation produces a carry or a borrow bit.
Zero flag
Set when the accumulator is zero at the end of a MAC operation.
Negative flag
8
N
Set when the accumulator is negative at the end of a MAC operation.
7:0
MAE
Accumulator extension (bits [39:32])
Note:
The MAC condition flags are evaluated (if required) by the instruction being executed. In
particular, they are not affected by any instruction of the regular instruction set. In
consequence, their values may not be consistent with the accumulator content. For
example, loading the accumulator with MOV instructions will not modify the condition flags
47/328
Multiplier-accumulator unit
Control register
ST10F252M
15
14
LM
RW
13
EM
RW
12
VM
RW
11
10
MP
RW
9
8
7
6
5
4
3
2
1
0
MIE
RW
CM
RW
MS
RW
reserved
Table 17. Control register functions
Bit
Name
Function
MAC Interrupt Enable
15
MIE
‘0’: MAC interrupt globally disabled,
‘1’: MAC interrupt globally enabled.
SL Mask
14
13
12
11
LM
EM
VM
CM
When set, the SL Flag can generate a MAC interrupt request.
E Mask
When set, the E Flag can generate a MAC intert request.
SV Mask
When set, the SV Flag can generate a MAC interrupt request.
C Mask
When set, the C Flag can generate a MAC interrupt request.
Product Shift Mode
10
MP
When set, eblethe one-bit left shift of the multiplier output in case
of a signed-ned multiplication
Saturation Mode
9
MS
When set, enables automatic 32-bit saturation of the result of a MAC
operation
8:0
Reserved
Repearegister
15
14
-
13
-
12
11
10
9
8
7
6
5
4
3
2
1
0
MR
RW
Repeat Count
RW
Table 18. Repeat register functions
Bit
Name
Function
Repeat Flag
15
MR
Set when a repeated instruction is executed
13-bit unsigned integer value
12.0
Repeat Count
Indicates the number of time minus one a repeated instruction must be
executed
Note:
As for the CPU Core SFRs, any write operation with the regular instruction set to a single
byte of a MAC SFR clears the non-addressed complementary byte within the specified SFR.
Non-implemented SFR bits cannot be modified and will always supply a read value of’0’.
48/328
ST10F252M
Multiplier-accumulator unit
These registers are mapped in the SFR space and can addressed by the regular instruction
set like any SFR. They can also be addressed by the new instruction CoSTORE. This
instruction allows the user to access the MAC registers without any pipeline side effect.
CoSTORE uses a specific 5-bit addressing mode called CoReg. The following table gives
the address of the MAC registers in this CoReg addressing mode.
Table 19. Register address in CoReg addressing mode
Registers
Description
Address
MSW
MAC unit status word
00000b
MAH
MAS
MAL
MAC unit accumulator high
“limited” MAH /signed
00001b
00010b
00100b
00101b
00110b
MAC unit accumulator low
MAC unit control word
MAC unit repeat word
MCW
MRW
49/328
External bus controller
ST10F252M
7
External bus controller
All of the external memory accesses are performed by the on-chip external bus controller
(EBC), when no additional (6) ADC channels are selected. The EBC can be programmed to
single chip mode when no external memory is required, or to one of four different external
memory access modes:
●
●
●
●
16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed
16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed
16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed
16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed
In demultiplexed bus modes, addresses are output on PORT1 and data is input and output
on PORT0 or P0L, respectively. In the multiplexed bus modes, both addresses and data use
PORT0 for input and output.
Timing characteristics of the external bus interface (memory cycle time, memory tri-state
time, length of ALE and read write delay) are programmable giving te choice of a wide
range of memories and external peripherals.
Up to four independent address windows may be defined (using register pairs ADDRSELx /
BUSCONx) to access different resources and bus characteristics. These address windows
are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2
overrides BUSCON1. All accesses to locations ncovered by these four address windows
are controlled by BUSCON0. No chip selesignals are provided, if needed they must be
generated through external glue logic
Bus arbitration, to share external resources with other bus masters, is not supported.
Connection of the slave controller to more than one master controller needs the addition of
glue logic. For bus arbitration policy, the ST10F276 user manual, where the EBC
automatically handle bus arbitration through dedicated pins, can be used as a reference.
For applications hich require less external memory space, the address space can be
restricted to 1 Mbyte, 256 Kbyte or to 64 Kbyte. Port 4 outputs all eight address lines if an
addresspace of 16 Mbytes is used, otherwise four, two or no address lines.
7.1
Controlling the external bus controller
A set of registers controls the function of EBC. General features like the use of pins (WR,
BHE), segmentation and internal memory mapping are controlled by the SYSCON register.
The properties of a bus cycle like length of ALE, external bus mode, read/write delay and
waitstates are controlled by BUSCON4...BUSCON0. This allows the use of memory
components or peripherals with different interfaces within the same system, while optimizing
access to each of them.
7.1.1
External bus controller registers
BUSCON0 (FF0Ch/86h)
SFR
Reset value: 0xx0
15
-
14
-
13
-
12
-
11
-
10
9
8
-
7
6
5
4
3
2
1
0
BUS
ACT4 CTL4
ALE
MTT RWD
C4
BTYP
MCTC
C4
RW
RW
RW
RW
-
RW RW
RW
RW
RW
RW
RW
RW
RW
RW
50/328
ST10F252M
External bus controller
BUSCON1 (FF14h/8Ah)
SFR
SFR
SFR
SFR
Reset value: 0000
15
-
14
-
13
-
12
-
11
-
10
9
8
-
7
6
5
4
3
2
1
0
BUS
ACT4 CTL4
ALE
MTT RWD
C4
C4
RW
RW
RW
RW
-
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
BUSCON2 (FF16h/8Bh)
Reset value: 0000
15
-
14
-
13
-
12
-
11
-
10
9
8
-
7
6
5
4
3
2
1
0
BUS
ACT4 CTL4
ALE
MTT RWD
C4
C4
RW
RW
RW
RW
-
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
BUSCON3 (FF18h/8Ch)
Reset value: 0000
15
-
14
-
13
-
12
-
11
-
10
9
8
-
7
6
5
4
3
2
1
0
BUS
ACT4 CTL4
ALE
MTT RWD
C4
C4
RW
RW
RW
RW
-
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
BUSCON4 (FF1Ah/8Dh)
Reset value: 0000
15
-
14
-
13
-
12
-
11
-
10
9
8
-
7
6
5
4
3
2
1
0
BUS
ACT4 CTL4
ALE
MTT RWD
C4
C4
RW
RW
RW
RW
-
RW RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 20. External bus controller funcons
Bit
Name
Function
‘0’: Bus not active
‘1’: Bus active
10
BUSACTx
ALE lengthening control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
9
ALECTL
External bus configuration
0 0: 8-bit demultiplexed
0 1: 8-bit multiplexed
6.7 BTYP
1 0: 16-bit Demultiplexed
1 1: 16-bit multiplexed
For BUSCON0 BTYP is defined via PORT0 during reset,
Memory Tristate Time Control
‘0’: 1 waitstates
5
4
MTTCx
‘1’: No waitstates
Read/write delay control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling edge of
ALE
RWDCX
‘1’: No read/write delay: activate command with falling edge of ALE
Memory cycle time control (number of memory cycle time wait states)
0 0 0 0: 15 waitstates (number = 15 -<MCTC>)
0.3 MCTC
. . .
1 1 1 1: no waitstates
51/328
External bus controller
ST10F252M
7.2
EA functionality
In ST10F252M, the EA pin is shared with V
supply pin. When main V is on and
DD
STBY
stable, V
can be temporary grounded: in stand-by mode, the logic that is powered by
STBY
V
(that is 12Kbyte portion of XRAM and stand-by voltage regulator), is powered by the
STBY
main V . This means that the EA pin can be driven low during reset, if requested, to
DD
configure the system to start from the external memory.
An appropriate external circuit must be provided to manage dynamically both the
functionalities associated with the pin: during reset and with stable V , the pin can be tied
DD
low, while after reset (or anyway before turning off the main V to enter stand-by mode) the
DD
V
supply is applied. Refer to Section 21.3 for more details.
STBY
Figure 10. EA/V
external circuit
STBY
4 - 5.5 Volt
V
EA / V
STBY
STBY
EA function
V
V
SS
SS
In Figure 10, a possible external circuit is represented. When selecting the resistance for
current limitation, ensure that the resistance does not disturb the stand-by mode when some
current (in the order of hundreds of μA) is provided to the device by V
pin of ST10F252M cannot become lower than 4.5 V.
; the voltage at the
STBY
To reduce the effect of the current consumption transients on V
pin (refer to I
in the
SB3
STBY
ElectricCharacteristics section), add an external capacitance which can filter any current
peaks, which could create potential problems of voltage drops if a very low power external
volage regulator is used. The external hardware must limit current peaks due to the
presence of the capacitance (when EA is used and the external bipolar is turned on, see
Figure 10).
52/328
ST10F252M
Internal Flash memory
8
Internal Flash memory
8.1
Overview
The on-chip Flash has one matrix module 256 Kbyte wide. This Flash is accessed from the
ST10 internal bus, hence it is also known as IFlash.
Figure 11. Flash modules structure
Control Section
IFlash
Flash Control
Registers
HV and Ref.
Generator
Bank 0: 256 Kbyte
Program Memory
+
Program/Erase
Controller
8 Kbyte Test-Flash
I-BUS Interf
The programming operations of the Flash are managed by an embedded Flash
program/erase controller (FPEC). The high voltages needed for program/erase operations
are internally generated.
The data bus is 32-bits wide for fetch accesses to IFlash, whereas it is 16-bits wide for read
accesses to the Flash control registers. Write accesses are possible only in the IFlash
control regists area.
8.2
Functional description
8.2.1
Structure
Table 21 below shows the address space reserved to the IFlash module (that is, ROMEN
set to 1 in the SYSCON register).
Table 21. Address space reserved for the Flash module
Description
Addresses
Size
IFlash sectors
Reserved area
0x00 0000 to 0x04 FFFF
0x05 0000 to 0x07 FFFF
0x08 0000 to 0x08 FFFF
256 Kbyte
Reserved
64 Kbyte
Registers and Flash internal reserved area
53/328
Internal Flash memory
ST10F252M
8.2.2
Modules structure
The IFlash module is composed of a bank (Bank0) of 256 Kbyte of program memory divided
into eight sectors (B0F0...B0F7). Bank0 contains a reserved sector named Test-Flash used
in bootstrap mode.
Addresses from 0x08 0000h to 0x08 FFFFh are reserved for the control register interface
and other internal service memory space used by the Flash program/erase controller.
The following tables shows the memory mapping of the Flash when it is accessed in read
mode (Table 22: Flash modules sectorization (read operations)), and when accessed in
write or erase mode (Table 23: Flash modules sectorization (write operations or with
ROMS1=’1’or Bootstrap mode)).
With this second mapping, the first four banks are remapped into code segment 1 (same as
obtained by setting bit ROMS1 in SYSCON register).
Table 22. Flash modules sectorization (read operations)
Size
Bank
Description
Address
(bytes)
Bank 0 Flash 0 (B0F0)
Bank 0 Flash 1 (B0F1)
Bank 0 Flash 2 (B0F2)
Bank 0 Flash 3 (B0F3)
Bank 0 Flash 4 (B0F4)
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
0x0000000 - 0x0000 1FFF
00000 2000 - 0x0000 3FFF
0x0000 4000 - 0x0000 5FFF
0x0000 6000 - 0x0000 7FFF
0x0001 8000 - 0x0001 FFFF
0x0002 0000 - 0x0002 FFFF
0x0003 0000 - 0x0003 FFFF
0x0004 0000 - 0x0004 FFFF
8 K
8 K
8 K
8 K
B0
32 K
64 K
64 K
64 K
Table 23. ash modules sectorization (write operations or with ROMS1=’1’or
Bootstrap mode)
Size
(bytes)
Bank
Description
Addresses
Bank 0 Test-Flash (B0TF)
Bank 0 Flash 0 (B0F0)
Bank 0 Flash 1 (B0F1)
Bank 0 Flash 2 (B0F2)
Bank 0 Flash 3 (B0F3)
Bank 0 Flash 4 (B0F4)
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
0x0000 0000 - 0x0000 1FFF
0x0001 0000 - 0x0001 1FFF
0x0001 2000 - 0x0001 3FFF
0x0001 4000 - 0x0001 5FFF
0x0001 6000 - 0x0001 7FFF
0x0001 8000 - 0x0001 FFFF
0x0002 0000 - 0x0002 FFFF
0x0003 0000 - 0x0003 FFFF
0x0004 0000 - 0x0004 FFFF
8 K
8 K
8 K
8 K
B0
8 K
32 K
64 K
64 K
64 K
54/328
ST10F252M
Internal Flash memory
Table 23 above refers to the configuration when bit ROMS1 of SYSCON register is set.
Refer to Chapter 24 for more details on bootstrap mode memory mapping during Bootstrap
mode. In particular, when Bootstrap mode is entered:
●
●
●
Test-Flash is seen and available for code fetches (address 00 0000h).
user I-Flash is available for read and write accesses.
write accesses must be made with addresses starting in segment 1 from 01 0000h,
whatever ROMS1 bit in SYSCON value.
●
read accesses are made in segment 0 or in segment 1 depending on ROMS1 value.
In bootstrap mode, ROMS1 = 0 by default, so the first 32 Kbytes of IFlash are mapped in
segment 0.
Example:
In default configuration, to program address 0, the user must put the value 01 0000h in the
FARL and FARH registers but to verify the content of the address 0, a read to 00 0000h
must be performed.
The next Table 24 shows the control register interface composition: this et of registers can
be addressed by the CPU.
Table 24. Control register interface
Size
(bytes) size
Bus
Name
Description
Addresses
FCR1-0
Flash control registers 1-0
Flash address registers
Flash error register
0x0008 0000 - 0x0008 0007
0x0008 0010 - 0x0008 0013
0x0008 0014 - 0x0008 0015
8
4
2
FAR
FER
Flash non-volatile protection I
register
FNVWPIR
0x0008 DFB0 - 0x0008 DFB1
0x0008 DFB4 - 0x0008 DFB5
0x0008 DFB8 - 0x0008 DFB9
0x0008 DFBC - 0x0008 DFBF
0x0000 EB50 - 0x0000 EB51
2
FNVWPIR-
Mirror
Flash non-volatile protection I
ister
2
2
4
2
16-bit
Flash non-volatile access
protection register 0
FNVAP0
FNVAPR1
FVTAU0
Flash non-volatile access
protection register 1
Flash volatile temporary access
unprotection register 0
8.2.3
Low power mode
The Flash module is automatically switched off when executing a PWRDN instruction. The
consumption is drastically reduced, but exiting this state can require a long time (t ).
PD
Recovery time from power-down mode for the Flash modules is anyway shorter than the
main oscillator start-up time. To avoid any problems in restarting to fetch code from the
Flash, it is important to size properly the external circuit on RPD pin.
Note:
PWRDN instruction must not be executed while a Flash program/erase operation is in
progress.
55/328
Internal Flash memory
ST10F252M
8.3
Write operation
The Flash module has one single register interface mapped in the memory space of the
IBus (08’0000h - 08’0015h). All the operations are enabled through four 16-bit control
registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit
registers are used to store Flash address and data for program operations (FARH/L and
FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible
with 8- and 16-bit instructions (since the IBUS operates in 16-bit mode for read/write
accesses to data).
Note:
The register that controls the Temporary Unprotection of the Flash is located on the XBus at
address 00 EB50h in the XMiscellaneous Register area.
Before accessing the IFlash module (and consequently the Flash register to be used for
program/erasing operations), the ROMEN bit in SYSCON register must be set.
Caution:
During a Flash write operation any attempt to read the Flash itself, that is under
modification, will output invalid data (software trap 009Bh). This means that the Flash is not
fetchable when a programming operation is active. The write operatiocommands must
be executed from another memory (internal RAM or external meory), as in ST10F269
device. In fact, due to IBus characteristics, it is not possible to erform a write operation on
IFlash, when fetching code from IFlash.
Direct addressing is not allowed for write accesses to IFlash Control Registers.
Warning: During a Write operation, when bit LOCK of FCR0 is set, it is
forbidden to writto the Flash Control Registers.
Power supply drop
If during a write operation the internal low voltage supply drops below a certain internal
voltage thresholany write operation running is suddenly interrupted and the module is
reset to Read mode. At following Power-on, the interrupted Flash write operation must be
repeatd.
8.4
Registers description
84.1
Flash control register 0 low (FCR0L)
The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High
(FCR0H) are used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is
seen by the user in Bootstrap mode only.
FCR0L (0x08 0000)
15 14 13
FCR
7
Reset value: 0000h
12
11
10
9
8
6
5
4
3
2
1
0
Reserved
-
LOCK Reserved BSY0 Res.
RO RO
-
-
56/328
ST10F252M
Internal Flash memory
Table 25. Flash control register 0 low
Bit
Name
Reserved
Function
These bits are left at their reset value (0).
Flash Registers Access Locked
15:5
When this bit is set, it means that the access to the Flash Control
Registers FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is
locked by the FPEC: any read access to the registers will output invalid
data (software trap 009Bh) and any write access will be ineffective.
LOCK bit is automatically set when the Flash bit WMS is set.
This is the only bit the user can always access to detect the status of
the Flash: once it is found low, the rest of FCR0L and all the other
Flash registers are accessible by the user as well.
4
LOCK
Note that FER content can be read when LOCK is low, but its content is
updated only when the BSY0 bit is reset.
3.2 Reserved
These bits are left at their reset value (0).
Bank 0 Busy (IFlash)
This bit indicates that a write operatios running on Bank 0 (IFlash). It
is automatically set when bit WMS is set. Setting Protection operation
sets bit BSY0 (since protection registers are in this Block). When this
bit is set, every read access o Bank 0 will output invalid data (software
trap 009Bh), while everwrite access to the Bank will be ignored. At
the end of the write operation or during a Program or Erase Suspend
this bit is autmaally reset and the Bank returns to read mode. After
a Program ase Resume this bit is automatically set again.
1
0
BSY
Reserved
This bit is left at its reset value (0).
8.4.2
Flash control register 0 high (FCR0H)
The Flash ContrRegister 0 High (FCR0H) together with the Flash Control Register 0 Low
(FCR0L) is ud to enable and to monitor all the write operations on the IFlash. The user
has no ccess in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is
seen by the user in Bootstrap mode only.
FCR0H (0x08 0002)
15 14 13
FCR
8
Reset value: 0000h
12
11
10
9
7
6
5
4
3
2
1
0
WMS SUSP WPG DWPG SER
Reserved
SPR
Reserved
RW RW RW RW RW
-
RW
-
57/328
Internal Flash memory
ST10F252M
Table 26. Flash control register 0 high
Bit
Name
Function
Write Mode Start
This bit must be set to start every write operation in the Flash module. At the end
of the write operation or during a Suspend, this bit is automatically reset. To
resume a suspended operation, this bit must be set again. It is forbidden to set
this bit if bit ERR of FER is high (the operation is not accepted). It is also
forbidden to start a new write (program or erase) operation (by setting WMS
high) when bit SUSP of FCR0 is high. Resetting this bit by software has no
effect.
15
WMS
Suspend
This bit must be set to suspend the current Program (Word or Double Word) or
Sector Erase operation in order to read data in one of the Sectors of the Bank
under modification or to program data in another Bank. The Suspend operation
resets the Flash Bank to normal read mode (automatically resetting bit BSY0).
When in Program Suspend, the Flash module accepts onthe following
operations: Read and Program Resume. When in EraSuspend the module
accepts only the following operations: Read, ErResume and Program (Word
or Double Word; Program operations cannot be suspended during Erase
Suspend). To resume a suspended operatin, the WMS bit must be set again,
together with the selection bit correspnding to the operation to resume (WPG,
DWPG, SER).
14
SUSP
Note: It is forbidden to start a new Write operation with bit SUSP already set.
Word Program
This bit must be set to select the Word (32 bits) Program operation in the Flash
module. The Word Program operation can be used to program 0s in place of 1s.
The Flash Address to be programmed must be written in the FARH/L registers,
while the Flash Data to be programmed must be written in the FDR0H/L
registers before starting the execution by setting bit WMS. WPG bit is
automatically reset at the end of the Word Program operation.
13
WPG
Double Word Program
This bit must be set to select the Double Word (64 bits) Program operation in the
Flash module. The Double Word Program operation can be used to program 0s
in place of 1s. The Flash Address in which to program (aligned with even words)
must be written in the FARH/L registers, while the two Flash Data words to be
programmed must be written in the FDR0H/L registers (even word) and
FDR1H/L registers (odd word) before starting the execution by setting bit WMS.
DWPG bit is automatically reset at the end of the Double Word Program
operation.
12
DWPG
Sector Erase
This bit must be set to select the Sector Erase operation in the Flash modules.
The Sector Erase operation can be used to erase all the Flash locations to value
0xFF. From 1 to all the sectors of the same Bank (excluded Test-Flash for Bank
B0) can be selected to be erased through bits BxFy of FCR1H/L registers before
starting the execution by setting bit WMS. It is not necessary to preprogram the
sectors to 0x00, because this is done automatically. SER bit is automatically
reset at the end of the Sector Erase operation.
11
SER
10:9 Reserved These bits are left at their reset value (0).
58/328
ST10F252M
Internal Flash memory
Table 26. Flash control register 0 high (continued)
Bit
Name
Function
Set protection.
This bit is set to select the set protection operation. The set protection operation
programs 0s in place of 1s in the Flash non volatile protection registers. The
Flash address in which to program is written in the FARH/L registers, while the
Flash data to be programmed is written in the FDR0H/L before starting the
execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER
if the address written in FARH/L is not in the range 0x08DFB0-0x08DFBF. This
bit is automatically reset at the end of the set protection operation.
8
SPR
7:0
Reserved These bits are left at their reset value (0).
8.4.3
Flash control register 1 low (FCR1L)
The Flash Control Register 1 Low (FCR1L), together with Flash Control Register 1 High
(FCR1H), is used to select the Sectors to Erase, or during any write opeation to monitor the
status of each Sector and Bank.
FCR1L (0x08 0004)
15 14 13
FCR
8
Reset value: 0000h
12
11
10
9
7
6
5
4
3
2
1
0
Reserved
-
B07 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0
RS RS RS RS RS RS RS RS
Table 27. Flash control register 1 low
Bit Name
Function
15:8 Reserved These bits are left at their reset value (0).
Bank 0 IFlash Sectors 7-0 Status
These bits must be set during a Sector Erase operation to select the sectors to
erase in Bank 0. Moreover, during any erase operation, these bits are
7:0
0F[7:0]
automatically set and give the status of the eight sectors of Bank 0 (B0F7-B0F0).
The meaning of B0Fy bit for Sector y of Bank 0 is given in Table 29. These bits
are automatically reset at the end of a write operation if no errors are detected.
8.4.4
Flash control register 1 high (FCR1H)
The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low
(FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the
status of each Sector and Bank.
FCR1H (0x08 0006)
15 14 13
FCR
8
Reset value: 0000h
12
11
10
9
7
6
5
4
3
2
1
0
Reserved
-
B0S
RS
Reserved
-
59/328
Internal Flash memory
ST10F252M
Table 28. Flash control register 1 high
Bit Name
Function
7:0 Reserved These bits are left at their reset value (0).
Bank 0 Status (IFlash)
During any erase operation, this bit is automatically modified and gives the status
of the Bank 0. The meaning of B0S bit is given in Table 29. This bit is
automatically reset at the end of an erase operation if no errors are detected.
8
B0S
15:9 Reserved These bits are left at their reset value (0).
During any erase operation, this bit is automatically set and gives the status of the Bank 0.
The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of an
erase operation if no errors are detected.
Table 29. Banks (BxS) and sectors (BxFy) status bits meaning
ERR SUSP
B0S = 1 meaning
Erase Error in Bank0
B0Fy = 1 meaning
1
0
0
-
Erase Errin Sector y of Bank0
ErasSuspended in Sector y of Bank0
Don’t care
1
0
Erase Suspended in Bank0
Don’t care
8.4.5
Flash data register 0 low (FDR0L)
During program operations, the Flash Address Registers (FARH/L) are used to store the
Flash address in which to program and the Flash Data Registers (FDR1H/L-FDR0H/L) are
used to store the Flash data to program.
FDR0L (0x08 0008)
15 14 3
FCR
8
Reset value: FFFFh
12
11
10
9
7
6
5
4
3
2
1
0
DIN15 DN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 30. Flash data register 0 low
Bit
Name
Function
Data Input 15:0
These bits must be written with the Data to program the Flash with the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
15:0 DIN[15:0]
60/328
ST10F252M
Internal Flash memory
8.4.6
Flash data register 0 high (FDR0H)
FDR0H (0x08 000A)
15 14 13
FCR
8
Reset value: FFFFh
12
11
10
9
7
6
5
4
3
2
1
0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 31. Flash data register 0 high
Bit
Name
Function
Data Input 31:16
These bits must be written with the Data to program the Flash with the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
15:0 DIN[31:16]
8.4.7
Flash data register 1 low (FDR1L)
FDR1L (0x08 000C)
15 14 13
FCR
Reset value: FFFFh
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 32. Flash data register 1 lo
Bit
Name
Function
Data Input 15:0
These bits must be written with the Data to program the Flash with the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
otection.
15:0 DIN[15:0]
8.4.8
Flash data register 1 high (FDR1H)
FDR1H (0x08 000E)
15 14 13
FCR
8
Reset value: FFFFh
12
11
10
9
7
6
5
4
3
2
1
0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 33. Flash data register 1 high
Bit
Name
Function
Data Input 31:16
These bits must be written with the Data to program the Flash with the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
15:0 DIN[31:16]
61/328
Internal Flash memory
ST10F252M
8.4.9
Flash address register low (FARL)
FARL (0x08 0010)
15 14 13
FCR
8
Reset value: 0000h
12
11
10
9
7
6
5
4
3
2
1
0
ADD15ADD14ADD13ADD12ADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 Reserved
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
-
Table 34. Flash address register low
Bit
Name
Function
Address 15:2
These bits must be written with the Address of the Flash location to program in the
following operations: Word Program (32-bit) and Double Word Program (64-bit). In
Double Word Program bit ADD2 must be written to ‘0’.
15:2 ADD[15:2]
1:0 Reserved These bits are left at their reset value (0).
8.4.10
Flash address register high (FARH)
FARH (0x08 0012)
15 14 13
FCR
8
Reset value: 0000h
12
11
10
9
7
6
5
4
3
2
1
0
ADD20 ADD19 ADD18 ADD17 ADD16
Reserved
-
RW RW RW RW RW
Table 35. Flash address register high
Bit Name
Function
15:5 Reserved These bits are left at their reset value (0).
Address 20:16
4:0 ADD[20:16]
These bits must be written with the Address of the Flash location to program in
the following operations: Word Program and Double Word Program.
8.4.11
Flash error register (FER)
The Flash Error register, as well as all the other Flash registers, can be read only once the
LOCK bit of register FCR0L is low. Nevertheless, the FER content is updated after
completion of the Flash operation, that is, when BSY0 is reset. Therefore, the FER content
can only be read once the LOCK and BSY0 bits are cleared.
FER (0x8 0014h)
15 14 13
FCR
8
Reset value: 0000h
12
Reserved
-
11
10
9
7
6
5
4
3
2
1
0
WPF RESERSEQER
Reserved
10ER PGER ERER ERR
RC RC RC
-
RC RC RC RC
62/328
ST10F252M
Internal Flash memory
Table 36. Flash error register
Bit Name
Function
15:9 Reserved These bits are left at their reset value (0).
Write Protection Flag
This bit is automatically set when trying to program or erase in a sector write
protected. In case of multiple Sector Erase, the not protected sectors are erased,
while the protected sectors are not erased and bit WPF is set. This bit has to be
software reset.
8
7
WPF
Resume Error
This bit is automatically set when a suspended Program or Erase operation is not
resumed correctly due to a protocol error. In this case the suspended operation is
aborted. This bit has to be software reset.
RESER
SEQER
Sequence Error
This bit is automatically set when the control registers (FCR1H/L-FCR0H/L,
FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to exeute a valid Write
Operation. In this case no Write Operation is executed. Thibit has to be
software reset.
6
5:4
3
Reserved These bits are left at their reset value (0).
1 over 0 Error
This bit is automatically set when trying to program at 1 bits previously set at 0
10ER
(this does not happen when progrmming the Protection bits). This error is not
due to a failure of the Flash ell, but only flags that the desired data has not been
written. This bit has tsoftware reset.
Program Error
This bit is automatically set when a Program error occurs during a Flash write
operation. This error is due to a real failure of a Flash cell, that can no more be
programmed. The word where this error occurred must be discarded. This bit has
to be software reset.
2
PGER
Erase Error
This bit is automatically set when an Erase error occurs during a Flash write
operation. This error is due to a real failure of a Flash cell, that can no more be
erased. This kind of error is fatal and the sector where it occurred must be
discarded. This bit has to be software reset.
1
0
ERER
ERR
Write Error
This bit is automatically set when an error occurs during a Flash write operation
or when a bad write operation setup is done. Once the error has been discovered
and understood, ERR bit must be software reset.
8.5
Protection strategy
The protection bits are stored in Non-Volatile Flash cells inside IFlash module, that are read
once at reset and stored in four Volatile registers. Before they are read from the Non-
Volatile cells, all the available protections are forced active during reset.
The protections can be programmed using the Set Protection operation (see Flash Control
Registers paragraph), that can be executed from all the internal or external memories
except from the Flash itself.
63/328
Internal Flash memory
ST10F252M
Two kind of protections are available: write protections to avoid unwanted writings and
access protections to avoid piracy. In next paragraphs all different level of protections are
shown, and architecture limitations are highlighted as well.
8.5.1
8.5.2
Protection registers
The four Non-Volatile Protection Registers are one time programmable for the user.
One register (FNVWPIR) is used to store the Write Protection fuses respectively for each
sector IFlash module. The other three registers (FNVAPR0 and FNVAPR1L/H) are used to
store the Access Protection fuses.
Flash non-volatile write protection I register (FNVWPIR)
FNVWPIR (0x08 DFB0)
15 14 13 12
NVR
8
Reset value: FFFFh
11
10
9
7
6
5
4
3
2
1
0
Reserved
-
W0P7W0P6W0P5W0P4W3W0P2W0P1W0P0
RW RW RW RW RW RW RW RW
Table 37. Flash non-volatile write protection I regiser
Bit Name Function
15:8 Reserved These bits are left at their reset value (F).
Write Protection BanSectors 7-0 (IFlash)
7:0
W0P[7:0]
These bits, if programmed at 0, disable any write access to the sectors of Bank 0
(IFlash)
8.5.3
Flash non-volatile access protection register 0 (FNVAPR0)
FNVAPR0 (0xDFB8)
15 4 13 12
NVR
8
Delivery value: ACFFh
11
10
9
7
6
5
4
3
2
1
0
DBGP ACCP
Reserved
-
RW RW
Table 38. Flash non-volatile access protection register 0
Bit Name Function
15:2 Reserved
Debug Protection
This bit, if erased at 1, can be used to by-pass all the protections using the Debug
features through the Test Interface. If programmed at 0, on the contrary, all the
debug features, the Test Interface and all the Flash Test modes are disabled. Even
STMicroelectronics will not be able to access the device to run any eventual failure
analysis.
1
0
DBGP
ACCP
Access Protection
This bit, if programmed at 0, disables any access (read/write) to data mapped
inside IFlash Module address space, unless the current instruction is fetched from
IFlash.
64/328
ST10F252M
Internal Flash memory
8.5.4
Flash non-volatile access protection register 1 low (FNVAPR1L)
FNVAPR1L (0x08 DFBC)
15 14 13 12
NVR
8
Delivery value: FFFFh
11
10
9
7
6
5
4
3
2
1
0
PDS15PDS14PDS13PDS12PDS11PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 39. Flash non-volatile access protection register 1 low
Bit
Name
Function
Protections Disable 15-0
If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP
is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP
have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit
PENx-1 has already been programmed at 0.
15:0 PDS[15:0]
8.5.5
Flash non-volatile access protection register 1 high (NVAPR1H)
FNVAPR1H (0x08 DFBE)
15 14 13 12
NVR
8
Delivery value: FFFFh
11
10
9
7
6
5
4
3
2
1
0
PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PE7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
RW RW RW RW RW RW RW RRW RW RW RW RW RW RW RW
Table 40. Flash non-volatile access protection register 1 high
Bit
Name
Function
Protections Enable 15-0
f bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit
CCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has
already been programmed at 0.
15:0 PEN[15:0]
8.5.6
XBus Flash volatile temporary access unprotection register (XFVTAUR0)
XFVTAUR0 (0x00 EB50)
15 14 13 12
NVR
8
Reset value: 0000h
11
10
9
7
6
5
4
3
2
1
0
Reserved
-
TAUB
RW
Table 41. XBus Flash volatile temporary access unprotection register
Bit Name Function
15:1 Reserved These bits are left at their reset value (0).
Temporary Access Unprotection bit
If this bit is set to 1, the Access Protection is temporary disabled.
0
TAUB
The fact that this bit can be written only while executing from IFlash guarantees
that only a code executed in IFlash can unprotect the IFlash when it is Access
Protected.
65/328
Internal Flash memory
ST10F252M
8.5.7
Access protection
The IFlash module has one level of access protection (access to data both in Reading and
Writing).
When bit ACCP of FNVAPR0 is programmed at 0 and bit TAUB in XFVTAUR0 is set at 0, the
IFlash module becomes access protected (data in the IFlash module can be read only if the
current execution is from the IFlash module itself).
Trying to read into the access protected Flash from internal RAM or external memories will
output a dummy data (software trap 009Bh).
When the Flash module is protected in access, data access through PEC transfers is also
forbidden. To read/write data through PEC in a protected Bank, first it is necessary to
temporarily unprotect the Flash module.
To enable Access Protection, the following sequence of operations is recommended:
●
●
●
●
●
execution from external memory or internal Rams
program TAUB bit at 1 in XFVTAUR0 register
program ACCP bit in FNVAPR0 to 0 using Set Protection operon
program TAUB bit at 0 in XFVTAUR0 register
Access Protection is active when both ACCP bit and TAUB bit are set to 0.
Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order
to analyze rejects. Protection can be permanentenabled again by programming bit PEN0
of FNVAPR1L. The action to disable and enable again Access Protections in a permanent
way can be executed a maximum of 1mes. To execute the above described operations,
the Flash has to be temporarily unprotected (see Section 8.5.9: Temporary unprotection).
Trying to write into the access protected Flash from internal RAM or external memories will
be unsuccessful. Trying to read into the access protected Flash from internal RAM or
external memories will output dummy data (software trap 0x009Bh).
When the Flash odule is protected in access, data access through PEC of a peripheral is
also forbiddeTo read/write data in PEC mode from/to a protected Bank, it is necessary to
first teorarily unprotect the Flash module.
Thfollowing table summarizes all possible Access Protection levels: In particular, it shows
what is possible and not possible to do when fetching from a memory (see fetch location
column) supposing all possible access protections are enabled.
Table 42. Summary of access protection level
Read XRAM or
External
Read IFlash /
Jump to IFlash Jump to XRAM
or External
Memory /
Read Flash
Registers
Write Flash
Registers
Fetch location
Memory
Fetching from IFlash
Fetching from IRAM
Fetching from XRAM
Yes / Yes
No / Yes
No / Yes
Yes / Yes
No / Yes
No / Yes
Yes
No
No
No
Yes / No
Yes / No
Fetching from external
memory
No / Yes
No / Yes
Yes / No
No
66/328
ST10F252M
Internal Flash memory
When the Access Protection is enabled, Flash registers can not be written, so no
program/erase operation can be run on IFlash. To enable the access to registers again, the
Temporary Access Unprotection procedure has to be followed (see Section 8.5.9).
8.5.8
8.5.9
Write protection
The Flash modules have one level of Write Protections: each Sector of each Bank of each
Flash Module can be Software Write Protected by programming at 0 the related bit W0Px in
FNVWPIRL register.
Temporary unprotection
Bits W0Px of FNVWPIRL can be temporarily unprotected by executing the Set Protection
operation and by writing 1 into these bits.
To restore the write protection bits it is necessary to reset the microcontroller or to execute a
Set Protection operation and write 0 into the desired bits.
In reality, when a temporary write unprotection operation is executed, tcorresponding
volatile register is written to 1, while the non-volatile registers bits priously written to 0 (for
a protection set operation), will continue to maintain the 0. For this reason, the User
software must be in charge to track the current write protection status (for instance using a
specific RAM area), it is not possible to deduce it by reading the non-volatile register content
(a temporary unprotection cannot be detected).
To temporarily unprotect the Flash when the Access Protection is active, it is necessary to
set to ‘1’ the bit TAUB in XFVTAUR0. Ts bt can be set to ‘1’ only while executing from
Flash: In this way only an instruction ecuted from Flash can unprotect the Flash itself.
To restore the Access Protection, it is necessary to reset the microcontroller or to write at 0
the bit TAUB in XFVTAUR0.
8.6
Write operation examples
The folwing examples represent each kind of Flash write operation.
Note:
Thwrite operation commands must be executed from another memory (internal RAM or
external memory), as in ST10F269 device. In fact, due to I-bus characteristics, it is not
possible to perform write operation in IFlash while fetching code from IFlash.
Direct addressing is not allowed for write accesses to IFlash control registers. This means
that both address and data for a writing operation must be loaded in one ST10 GPR register
(R0...R15).
A write operation on the I-bus is 16 bits wide.
Example: indirect addressing mode:
MOV RWm, #ADDRESS;
/*Load Add in RWm*/
/*Load Data in RWn*/
/*Indirect addressing*/
MOV RWn, #DATA;
MOV [RWm], RWn
;
Word program example: 32-bit word program of data 0xAAAAAAAA at address 0x015554.
FCR0H |= 0x2000;
/*Set WPG in FCR0H*/
FARL = 0x5554;
/*Load Add in FARL*/
67/328
Internal Flash memory
ST10F252M
FARH
= 0x0001;
/*Load Add in FARH*/
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Operation start*/
FDR0L
FDR0H
= 0xAAAA;
= 0xAAAA;
FCR0H |= 0x8000;
Double word program example: double word program (64-bit) of data 0x55AA55AA at
address 0x015558 and data 0xAA55AA55 at address 0x01555C.
FCR0H |= 0x1000;
/*Set DWPG*/
FARL
= 0x5558;
= 0x0001;
= 0x55AA;
= 0x55AA;
= 0xAA55;
= 0xAA55;
/*Load Add in FARL*/
/*Load Add in FARH*/
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Load Data in FDR1L*/
/*Load Data in FDR1H*/
/*Operation start*/
FARH
FDR0L
FDR0H
FDR1L
FDR1H
FCR0H |= 0x8000;
Note:
A double word program is always performed on the double wod aligned on a even word –
bit ADD2 of FARL is ignored.
Sector erase example: sector erase of sectors B0F1 and B0F0 of Bank0 in IFlash module.
FCR0H |= 0x0800;
FCR1H |= 0x0003;
FCR0H |= 0x8000;
/*Set SER in FCR0H*
/*Set B0FB0*/
/*Operation start*/
Suspend and resume example: word program, double word program, and sector erase
operations can be suspended in the following way.
FCR0H |= 0x4000;
/*Set SUSP in FCR0H*/
The operation cbe resumed in the following way.
FCR0H 0xBFFF;
/*Rst SUSP in FCR0H*/
FCR0H |= 0x8000;
/*Operation resume*/
Note:
The original set up of select operation bits in FCR0H/L must be restored before the
operation resume, otherwise the operation is aborted and bit RESER of FER is set.
Erase suspend, program and resume examples: a sector erase operation can be
suspended to program (word or double word) another sector.
Sector erase of sector B0F1 of Bank0 in IFlash module.
FCR0H |= 0x0800;
FCR1H |= 0x0002;
FCR0H |= 0x8000;
/*Set SER in FCR0H*/
/*Set B3F1*/
/*Operation start*/
Sector erase suspend.
FCR0H |= 0x4000;
do
/*Set SUSP in FCR0H*/
/*Loop to Wait WMS=0*/
/*Read FCR0H*/
{tmp = FCR0H;
} while (tmp & 0x8000);
68/328
ST10F252M
Internal Flash memory
Example: word program of data 0x5555AAAA at address 0x015554 in IFlash module.
FCR0H |= 0x2000;
/*Set WPG in FCR0H*/
/*Load Add in FARL*/
/*Load Add in FARH*/
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Operation start*/
FARL
= 0x5554;
= 0x000C;
= 0xAAAA;
= 0x5555;
FARH
FDR0L
FDR0H
FCR0H |= 0x8000;
Once the program operation is finished, the erase operation can be resumed in the following
way.
FCR0H &= 0xBFFF;
/*Rst SUSP in FCR0H*/
FCR0H |= 0x8000;
/*Operation resume*/
Note:
During the program operation in erase suspend, bits SER and SUSP remain high. A word or
double word program during erase suspend cannot be suspended.
Set protection example 1: enable write protection of sectors B0F3...B0F0 of Bank 0 in IFlash
module.
FCR0H |= 0x0100;
/*Set SPR in FCR0H*/
FARL
FARH
FDR0L
= 0xDFB4;
= 0x0008;
= 0xFFF0;
/*Load Add of register FNVWPIRL in FARL*/
/*Load Add of registr FNVWPIRL in FARH*/
/*Load Data in FDR0L*/
FCR0H |= 0x8000;
/*Operatitart*/
Set protection example 2: enable access and debug protection.
FVTUR
= 0x0001;
/*Set TAUB in FVTAUR0*/
FCR0H |= 0x0100;
/*Set SPR in FCR0H*/
FARL
FARH
FDR0L
= 0xDFB8
= 0x8;
= 0xFFFC;
/*Load Add of register FNVAPR0 in FARL*/
/*Load Add of register FNVAPR0 in FARH*/
/*Load Data in FDR0L*/
FCR0H |= 0x8000;
FVTUR = 0x0000;
/*Operation start*/
/*Set TAUB in FVTAUR0*/
Set protection example 3: permanently disable access and debug protection.
FVTUR
= 0x0001;
/*Set TAUB in FVTAUR0*/
FCR0H |= 0x0100;
/*Set SPR in FCR0H*/
FARL
FARH
FDR0L
= 0xDFBC;
= 0x000E;
= 0xFFFE;
/*Load Add of register FNVAPR1L in FARL*/
/*Load Add of register FNVAPR1L in FARH*/
/*Load Data in FDR0L for clearing PDS0*/
/*Operation start*/
FCR0H |= 0x8000;
Set protection example 4: permanently re-enable access and debug protection, after having
disabled them.
FVTUR = 0x0001;
/*Set TAUB in FVTAUR0*/
FCR0H |= 0x0100;
/*Set SPR in FCR0H*/
69/328
Internal Flash memory
ST10F252M
FARL
FARH
FDR0H
= 0xDFBC;
/*Load Add register FNVAPR1H in FARL*/
/*Load Add register FNVAPR1H in FARH*/
/*Load Data in FDR0H for clearing PEN0*/
/*Operation start*/
= 0x0008;
= 0xFFFE;
FCR0H |= 0x8000;
FVTUR = 0x0000;
/*Set TAUB in FVTAUR0*/
Note:
Disable and re-enable of access and debug protection in a permanently (as shown by
examples 3 and 4) can be done for a maximum of 16 times.
70/328
ST10F252M
Internal Flash memory
8.7
Write operation summary
In general, each write operation is started through a sequence of three steps:
1. The first instruction is used to select the desired operation by setting its corresponding
selection bit in the Flash Control Register 0.
2. The second step is the definition of the Address and Data for programming or the
Sectors or Banks to erase.
3. The last instruction is used to start the write operation, by setting the start bit WMS in
the FCR0.
Once selected, but not yet started, one operation can be canceled by resetting the operation
selection bit.
Available Flash Module Write Operations are summarized in the following Table 43.
Table 43. Flash write operations
Operation
Select bit
Address and data
Start bit
FARL/FARH
FDR0L/FR0H
Word program (32-bit)
WPG
WMS
FARL/FARH
FDR0L/FDR0H
FDR1L/FDR1H
Double word program (64-bit)
DWPG
WMS
Sector erase
SER
SPR
FCR1L/FCR1H
FDR0L/FDR0H
None
WMS
WMS
None
Set protection
Program/erase suspend
SUSP
Figure 12 shows the complete flow needed for a Write operation.
Figure 12. Write operation control flow
Start Write Operation
No
FCR0L.LOCK == 0?
Yes
Write Operation finished?
No
(Check related busy bit)
Yes
Check Error Status
Error:
Error handler, ...
No error:
Proceed with application
Re-start operation
71/328
Interrupt system
ST10F252M
9
Interrupt system
The interrupt response time for internal program execution is from 125 ns to 300 ns at
40 MHz CPU frequency.
The ST10F252M architecture supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be serviced by the interrupt controller or
by the peripheral event controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’
from the current CPU activity to perform a PEC service. A PEC service implies a single byte
or word data transfer between any two memory locations with an additional increment of
either the PEC source or the destination pointer. An individual PEC transfer counter is
implicitly decremented for each PEC service except when performing in the continuous
transfer mode. When this counter reaches zero, a standard interrupt is erformed to the
corresponding source related vector location. PEC services are verwell suited, for
example, for supporting the transmission or reception of blockof data. The ST10F252M
has eight PEC channels each of which offers such fast interrupt-driven data transfer
capabilities.
There is a separate control register, which contains an interrupt request flag, an interrupt
enable flag and an interrupt priority bit-field for eah of the possible interrupt sources. Via its
related register, each source can be programed to one of sixteen interrupt priority levels.
Once having been accepted by the Can interrupt service can only be interrupted by a
higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt sources has a dedicated vector location.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
9.1
Fast xternal interrupt
Fat external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge,
falling edge or both edges).
9.1.1
External interrupt source selection register (EXISEL)
Fast external interrupts may also have interrupt sources selected from other peripherals; for
example the CANx controller receive signal (CANx_RxD) can be used to interrupt the
2
system. The same is valid for I C interface serial clock line (SCL), and for real time clock.
This function is controlled using the external interrupt source selection register (EXISEL),
and allows to wake-up the system from interruptible power down having to reset the device.
72/328
ST10F252M
Interrupt system
External interrupt source selection register
External interrupt source selection register
(F1DA ED)
EXISEL
Reset value: 0000h
15
EXI7SS
RW
14
13
EXI6SS
RW
12
11
EXI5SS
RW
10
9
8
7
6
5
4
3
2
1
0
EXI4SS
RW
EXI3SS
RW
EXI2SS
RW
EXI1SS
RW
EXI0SS
RW
Table 44. External interrupt source selection register functions
Bit
Name
Function
External interrupt x source selection (x=7...0)
‘00’: Input from associated port 2 pin.
‘01’: Input from “alternate source”.
15.0 EXIxSS(7:0)
‘10’: Input from port 2 pin ORed with “alternate source”.
‘11’: Input from port 2 pin ANDed with “alternate ource”.
Table 45. EXIxSS interrupts
EXIxSS
Port 2 pin
Alternate Source
0
1
P2.8
CAN1_RxD
CA2_RxD
RTC_secIT
RTC_alarmIT
SCL
P4.5
P4.4
P2.9
2
P2.10
P2.11
P2.12
P2.13...15
Internal MUX
3
Internal MUX
4
P1.6
-
5...7
2
Not used (zero)
CAN and I C interrupt need some considerations, the following are general rules.
●
When a odule is not enabled, even though the interrupt source is enabled (see for
exmple EXIxSS=’01’), an event on the pin does not generate any request to the CPU.
●
CAN parallel mode is enabled only when both CAN modules are enabled (on the
contrary it has no effect).
EXxIN inputs are normally sampled interrupt inputs. However, the power down mode
circuitry uses them as level-sensitive inputs. An EXxIN (x = 7...0) interrupt enable bit (bit
CCxIE in the respective CCxIC register) needs not to be set to bring the device out of power
down mode.
If the Interrupt was enabled (bit CCxIE=’1’ in the respective CCxIC register) before entering
power down mode, the device executes the interrupt service routine, and then resumes
execution after the PWRDN instruction. If the interrupt was disabled, the device executes
the instruction following PWRDN instruction, and the interrupt request flag (bit CCxIR in the
respective CCxIC register) remains set until it is cleared by software.
In Table 46, all the possible pin configurations are summarized for CAN parallel mode. In the
table, the bit of XPERCON register are shown (used to enable/disable each module) and the
bit CANPAR of XMISC register used to enable/disable the CAN parallel mode. The table
73/328
Interrupt system
ST10F252M
shows when the wake-up interrupt can be generated by the two modules (providing that the
EXISEL register is properly set).
Table 46. CAN parallel mode pin configurations
CANPAR
CAN2EN
CAN1EN
Interrupt P4.5
Interrupt P4.4
x
x
x
0
1
0
0
1
1
1
0
1
0
1
1
No
No
No
Yes (CAN1)
No
Yes (CAN2)
Yes (CAN2)
No
Yes (CAN1)
Yes (CAN1/2)
Note:
For CAN1 (and CAN2 when parallel mode is set) the related interrupt control register is
CC8IC; for CAN2 the register is CC9IC, for I2C is CC12IC
9.1.2
External interrupt control register (EXICON)
The Power Down mode can be entered if enabled Fast External Interrupt pins (EXxIN pins,
Alternate Functions of Port 2 pins, with x = 7...0) are in their inactive level. This inactive level
is configured with the EXIxES bit field in the EXICON regiter.
External interrupt control register
External interrupt control register (F1CD EB)
15 14 13 12 11 10
XICON
Reset value: 0000h
9
8
7
6
5
4
3
2
1
0
EXI7ES
EXI6ES
EXI5ES
EXI4ES
EXI3ES
EXI2ES
EXI1ES
EXI0ES
RW
RW
RW
RW
RW
RW
RW
RW
Table 47. Exnal interrupt control register functions
Bit
Name
Function
External Interrupt x Edge Selection Field (x=7...0)
‘00’: Fast external interrupts disabled: standard mode. The EXxIN pin is
not taken into account for entering/exiting power down mode.
‘01’: Interrupt on positive edge (rising). Enter power down mode if
15.0
EXIxES(7:0)
EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
‘10’: Interrupt on negative edge (falling). Enter power down mode if
EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
‘11’: Interrupt on any edge (rising or falling). Always enter power down
mode, exit if EXxIN level changes.
2
While for CAN and I C the EXICON programming depends on the customer application
2
(even though inactive state of both CAN and I C protocols is the high level, so a new activity
on the bus can be detected by a falling edge observed at the related pins), for RTC the
internal hardware circuitry is such that the interrupts are generated on the positive edge, so
the EXICON register must be programmed accordingly.
2
Note:
The I C interface implements a input analog filter to avoid spurious spikes are assumed as
valid bus transitions. For this reason, a pulse on SCL line is long enough to be recognized
as valid pulse: this is in the range of 500 ns (minimum). All pulses shorter than 50 ns are
74/328
ST10F252M
Interrupt system
certainly filtered: a pulse longer than 50 ns but shorter than 500 ns could either trigger or not
trigger the exit from power down mode.
9.2
X-Peripheral interrupt
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some
constraints on the implementation of the new functionality. In particular, the additional X-
2
Peripherals SSC1, ASC1, I C, PWM1 and RTC need some resources to implement interrupt
and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt
management is proposed. In the next Figure 13, the principle is explained through a simple
diagram, which shows the basic structure replicated for each of the four X-interrupt available
vectors (XP0INT, XP1INT, XP2INT and XP3INT).
It is based on a set of 16-bit registers XIRxSEL (x = 0,1,2,3), divided in two portions each:
●
Byte High
Byte Low
XIRxSEL[15:8]
XIRxSEL[7:0]
Interrupt Enable bits
Interrupt Flag bits
●
When different sources submit an interrupt request, the enable bits yte High of XIRxSEL
register) define a mask which controls which sources will be aociated with the unique
available vector. If more than one source is enabled to issue the request, the service routine
will have to take care to identify the real event to be serviced. This can easily be done by
checking the flag bits (Byte Low of XIRxSEL register. Note that the flag bits can also
provide information about events which are not crently serviced by the interrupt controller
(since they are masked through the enable bits), allowing an effective software management
even if the related interrupt request caot e served: A periodic polling of the flag bits may
be implemented inside the user application.
Figure 13. X-interrupt basic structure
7
0
Flag[7:0]
XIRxSEL[7:0] (x = 0, 1, 2, 3)
IT Source 7
IT Source 6
IT Source 5
IT Source 4
IT Source 3
IT Source 2
IT Source 1
IT Source 0
XPxIC.IR (x = 0, 1, 2, 3)
Enable[7:0]
XIRxSEL[15:8] (x = 0, 1, 2, 3)
15
8
Table 48 summarizes the mapping of the different interrupt sources, which share the four
X-interrupt vectors.
75/328
Interrupt system
ST10F252M
Since the XIRxSEL registers are not bit addressable, another pair of registers (a pair for
each XIRxSEL) is provided to allow setting and clearing the bits of XIRxSEL without risking
overwriting requests arriving after reading the register and before writing it. These registers
are described in this section as well.
Table 48. X-Interrupt detailed mapping
Interrupt
CAN1 Interrupt
XP0INT
XP1INT
XP2INT
XP3INT
x
x
x
CAN2 Interrupt
I2C Receive
x
x
x
x
x
x
x
I2C Transmit
I2C Error
x
x
SSC1 Receive
SSC1 Transmit
SSC1 Error
x
x
x
x
x
x
ASC1 Receive
ASC1 Transmit
ASC1 Transmit Buffer
ASC1 Error
x
x
x
x
x
x
x
x
x
x
x
x
PLL Unlock / OWD
PWM1 Channel 3...0
x
9.3
Interrupt sources
Table 4shows all of the possible ST10F252M interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Table 49. Interrupt sources
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 0
CAPCOM Register 1
CAPCOM Register 2
CAPCOM Register 3
CAPCOM Register 4
CAPCOM Register 5
CAPCOM Register 6
CAPCOM Register 7
CAPCOM Register 8
CAPCOM Register 9
CC0IR
CC1IR
CC2IR
CC3IR
CC4IR
CC5IR
CC6IR
CC7IR
CC8IR
CC9IR
CC0IE
CC1IE
CC2IE
CC3IE
CC4IE
CC5IE
CC6IE
CC7IE
CC8IE
CC9IE
CC0INT
CC1INT
CC2INT
CC3INT
CC4INT
CC5INT
CC6INT
CC7INT
CC8INT
CC9INT
00’0040h
00’0044h
00’0048h
00’004Ch
00’0050h
00’0054h
00’0058h
00’005Ch
00’0060h
00’0064h
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
76/328
ST10F252M
Interrupt system
Table 49. Interrupt sources (continued)
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 10
CAPCOM Register 11
CAPCOM Register 12
CAPCOM Register 13
CAPCOM Register 14
CAPCOM Register 15
CAPCOM Register 16
CAPCOM Register 17
CAPCOM Register 18
CAPCOM Register 19
CAPCOM Register 20
CAPCOM Register 21
CAPCOM Register 22
CAPCOM Register 23
CAPCOM Register 24
CAPCOM Register 25
CAPCOM Register 26
CAPCOM Register 27
CAPCOM Register 28
CAPCOM Regist29
CAPCRegister 30
CAPCOM Register 31
CAPCOM Timer 0
CC10IR
CC11IR
CC12IR
CC13IR
CC14IR
CC15IR
CC16IR
CC17IR
CC18IR
CC19IR
CC20IR
CC21IR
CC22IR
CC23IR
CC24IR
CC25IR
CC26IR
CC27IR
CC28IR
CC29IR
CC30IR
CC31IR
T0IR
CC10IE
CC11IE
CC12IE
CC13IE
CC14IE
CC15IE
CC16IE
CC17IE
CC18IE
CC19IE
CC20IE
CC21IE
CC22IE
CC23IE
C24IE
CC25IE
CC26IE
CC27IE
CC28IE
CC29IE
CC30IE
CC31IE
T0IE
CC10INT
CC11INT
CC12INT
CC13INT
CC14INT
CC15INT
CC16INT
CC17INT
CC18INT
CC19INT
CC20IN
CC21INT
CC22INT
CC23INT
CC24INT
CC25INT
CC26INT
CC27INT
CC28INT
CC29INT
CC30INT
CC31INT
T0INT
00’0068h
00’006Ch
00’0070h
00’0074h
00’0078h
00’007Ch
00’00C0h
00’00C4h
00’00C8h
00’0CCh
00’00D0h
00’00D4h
00’00D8h
00’00DCh
00’00E0h
00’00E4h
00’00E8h
00’00ECh
00’00E0h
00’0110h
00’0114h
00’0118h
00’0080h
00’0084h
00’00F4h
00’00F8h
00’0088h
00’008Ch
00’0090h
00’0094h
00’0098h
00’009Ch
00’00A0h
00’00A4h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
44h
45h
46h
20h
21h
3Dh
3Eh
22h
23h
24h
25h
26h
27h
28h
29h
CAPCOM Timer 1
T1IR
T1IE
T1INT
CAPCOM Timer 7
T7IR
T7IE
T7INT
CAPCOM Timer 8
T8IR
T8IE
T8INT
GPT1 Timer 2
T2IR
T2IE
T2INT
GPT1 Timer 3
T3IR
T3IE
T3INT
GPT1 Timer 4
T4IR
T4IE
T4INT
GPT2 Timer 5
T5IR
T5IE
T5INT
GPT2 Timer 6
T6IR
T6IE
T6INT
GPT2 CAPREL Register
A/D Conversion Complete
A/D Overrun Error
CRIR
CRIE
CRINT
ADCIR
ADEIR
ADCIE
ADEIE
ADCINT
ADEINT
77/328
Interrupt system
Table 49. Interrupt sources (continued)
ST10F252M
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
ASC0 Transmit
ASC0 Transmit Buffer
ASC0 Receive
ASC0 Error
S0TIR
S0TBIR
S0RIR
S0EIR
SCTIR
SCRIR
SCEIR
PWMIR
XP0IR
XP1IR
XP2IR
XP3IR
S0TIE
S0TBIE
S0RIE
S0EIE
SCTIE
SCRIE
SCEIE
PWMIE
XP0IE
XP1IE
XP2IE
XP3IE
S0TINT
S0TBINT
S0RINT
S0EINT
SCTINT
SCRINT
SCEINT
PWMINT
XP0INT
XP1INT
XP2INT
XP3INT
00’00A8h
00’011Ch
00’00ACh
00’00B0h
00’00B4h
00’00B8h
00’00BCh
00’00FCh
00’0100h
00’04h
00’0108h
00’010Ch
2Ah
47h
2Bh
2Ch
2Dh
2Eh
2Fh
3Fh
40h
41h
42h
43h
SSC Transmit
SSC Receive
SSC Error
PWM Channel 0...3
See Section 9.2
Hardware traps are exceptions or error conditions that arise during run-time. They cause an
immediate non-maskable system reaction similao a standard interrupt service (branching
to a dedicated vector table location).
The occurrence of a hardware trap is ationally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
9.4
Exception and traps list
Table 5shows all of the possible exceptions or error conditions that can arise during run-
time.
Table 50. Trap priorities
Trap
flag
Trap
vector
Vector
location
Trap
number
Trap
Exception condition
priority(1)
Reset Functions:
Hardware Reset
Software Reset
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
00h
00h
00h
III
III
III
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008h
00’0010h
00’0018h
02h
04h
06h
II
II
II
Stack Underflow
78/328
ST10F252M
Interrupt system
Table 50. Trap priorities (continued)
Trap
Exception condition
flag
Trap
vector
Vector
location
Trap
number
Trap
priority(1)
Class B Hardware Traps:
Undefined Opcode
MAC Interruption
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLINA
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
I
I
I
I
I
I
ILLBUS
Reserved
[002Ch - 003Ch] [0Bh - 0Fh]
Any
Current
CPU
Priority
Software Traps
TRAP Instruction
Any
0000h – 01FCh
[00h - 7Fh]
in steps of 4h
1. - All the class B traps have the same trap number (and vector) and the same lower priority compared to the
class A traps and to the resets.
- Each class A trap has a dedicated trap number (and vector). They are prioritized in e second priority
level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.
79/328
Capture compare (CAPCOM) units
ST10F252M
10
Capture compare (CAPCOM) units
The ST10F252M has two 16 channel CAPCOM units. They support generation and control
of timing sequences on up to 32 channels with a maximum resolution of 200 ns at 40 MHz
CPU clock.
The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation (PMW), digital to analog (D/A) conversion,
software timing, or time recording relative to external events.
These two CAPCOM units are identical to the ones of the ST10F269 and ST10F27x, but,
due to 100-pins limitation in the ST10F252, the I/O capability is limited to 18 channels.
For CAPCOM1, 14 input-capture/output-compare channels with 4 only input-capture
channel for CAPCOM2.
The number of timer input lines has not changed, the T0IN input line is available for
CAPCOM1, T7IN input line timer for CAPCOM2.
All capture/compare registers and timers register are available, but sme of them are not
connected to external pins
80/328
ST10F252M
Capture compare (CAPCOM) units
Figure 14. SFR and port pins associated with CAPCOM units
81/328
General purpose timer unit
ST10F252M
11
General purpose timer unit
The general purpose timer (GPT) unit is a flexible multifunctional timer/counter structure
which is used for time related tasks such as event timing and counting, pulse width and duty
cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five
16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each
module may operate independently in several different modes, or may be concatenated with
another timer of the same module.
11.1
GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for
one of four basic modes of operation:
1. timer
2. gated timer
3. counter mode
4. incremental interface mode.
Although due to pins limitation in ST10F252 not all modes are available for each timer.
In timer mode, the input clock for a timer is derivfrom the CPU clock, divided by a
programmable prescaler, Each of the three timers T2, T3, T4 of the GPT1 module can be
configured in this mode.
In counter mode, the timer is clocked by reference to external events. Pulse width or duty
cycle measurement is supported in gated timer mode where the operation of a timer is
controlled by the ‘gate’ level on an external input pin. For these purposes, timers have one
associated port pin (TxIN) which serves as gate or clock input. Only T2 and T3 have such an
input pin associated in ST10F252, so gated timer and counter mode are not available for
timer T4.
The cot direction (up/down) for each timer is programmable only by software.
Functionality that dynamically changes direction by an external signal on a port pin is not
avilable on ST10F252. For the same reason, incremental interface mode is not available
for all the GPT1 timers (T2, T3, T4).
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-
flow/underflow. The state of this latch may be used internally to clock timers T2 and T4 for
measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or
capture registers for timer T3. When used as capture or reload registers, timers T2 and T4
are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at
their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4
triggered either by an external signal or by a selectable state transition of its toggle latch
T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state
transitions of T3OTL with the low and high times of a PWM signal, this signal can be
constantly generated without software intervention.
82/328
ST10F252M
General purpose timer unit
Figure 15. SFRs and port pins associated with timer block GPT1
Data Registers
Ports & Direction Control Alternate Functions
151413121110 9 8 7 6 5 4 3 2 1 0
151413121110 9 8 7 6 5 4 3 2 1 0
ODP3 E -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - Y Y - Y - - - -
- - Y Y - Y - - - -
- - Y Y - Y - - - -
T2 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
T3 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
T4 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
DP3
P3
-
-
Control Registers
Interrupt Control
151413121110 9 8 7 6 5 4 3 2 1 0
151413121110 9 8 7 6 5 4 3 2 1 0
T2CON Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
T3CON Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
T4CON Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
T2IC -
T3IC -
T4IC -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - Y Y Y Y Y Y Y Y
- - Y Y Y Y Y Y Y
- - Y Y Y Y Y Y Y
Y
-
E
:
:
:
Bit is linkd to a function
Bit has no function or is not implemented
Rister is in ESFR internal memory space
T2IN/P3.7
T3IN/P3.6
T3EUD/P3.4
ODP3 Port3 Open Drain Control Register
T2
T3
T4
GPT1 Timer 2 Register
GPT1 Timer 3 Register
GPT1 Timer 4 Register
DP3
Port3 Direction Control Registe
Port3 Data Register
P3
T2CON GPT1 Timer 2 Control Register
T3CON GPT1 Timer 3 Control Register
T4CON GPT1 Timer 4 Control Register
T2IC
T3IC
T4IC
GPT1 Timer 2 Interrupt Control Register
GPT1 Timer 3 Interrupt Control Register
GPT1 Timer 4 Interrupt Control Register
11.2
GPT2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock which is derived from the CPU clock via a programmable prescaler. The count
direction (up/down) for each timer is programmable by software. Concatenation of the timers
is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each
timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin
(T6OUT). The overflow/underflow of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL
register may capture the contents of timer T5 based on an external signal transition on the
corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture
procedure. This allows absolute time differences to be measured or pulse multiplication to
be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1
timer T3’s inputs T3IN and/or T3EUD.
Note:
In ST10F252, port pins to clock timers T5 and T6 with external signals and pins to control
counter direction are not available.
83/328
General purpose timer unit
ST10F252M
Figure 16. SFRs and port pins associated with timer block GPT2
Ports & Direction Control Alternate Functions Data Registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
ODP3 E -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- Y Y -
- Y Y -
- Y Y -
T5
T6
DP3
P3
-
-
CAPREL Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Interrupt Control
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Control Registers
T5IC
T6IC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- Y Y Y Y Y Y Y Y
- Y Y Y Y Y Y Y Y
- Y Y Y Y Y Y Y
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T5CON Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
T6CON Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
CRIC -
CAPIN/P3.2 T6OUT/P3.1
Y : Bit is lind to a function
-
: Bit has o function or is not implemented
E : Register is in ESFR internal memory space
T5
T6
GPT2 Timer 5 Register
GPT2 Timer 6 Register
ODP3 Port3 Open Drain Control Register
DP3
Port3 Direction Control Register
Port3 Data Register
CAPREL GPT2 Capture/Reload Register
P3
T5IC
T6IC
CRIC
GPT2 Timer 5 Interrupt Control Register
GPT2 Timer 6 Interrupt Control Register
GPT2 CAPREL Interrupt Control Register
T5CON GPT2 Timer 5 Control Register
T6CON GPT2 Timer 6 Control Register
84/328
ST10F252M
PWM modules
12
PWM modules
Two pulse width modulation modules are available on ST10F252M: standard PWM0 and
XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned
or center-aligned PWM. In addition, the PWM modules can generate PWM burst signals and
single shot outputs. Table 51 shows the PWM frequencies for different resolutions. The level
of the output signals is selectable and the PWM modules can generate interrupt requests.
Figure 17. Block diagram of PWM module
PPx Period Register *
Match
Comparator
*
Clock 1
Clock 2
PTx
Up/Down/
Clear Control
Input
Control
16-bit Up/Down Counter
Run
Match
Comparator
Shadow Register
Outpontrol
Write Control
POUTx
Enable
*
PWx Pulse Width Regr
User readable / writeable register
*
Table 51. PWM unit frequencies and resolutions at 40 MHz CPU clock
Mode 0
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU Clock/1
25ns
156.25 kHz
39.1 kHz
9.77 kHz
2.44Hz
610Hz
9.54Hz
CPU
Clock/64
1.6µs
2.44 kHz
610Hz
152.6Hz
38.15Hz
Mod1
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CU Clock/1
25ns
78.12 kHz
19.53 kHz
4.88 kHz
1.22 kHz
305.2Hz
CPU
Clock/64
1.6µs
1.22 kHz
305.17Hz
76.29Hz
19.07Hz
4.77Hz
85/328
Parallel ports
ST10F252M
13
Parallel ports
13.1
Introduction
To accept or generate single external control signals or parallel data, the ST10F252
provides up to 76 parallel I/O lines, organized into one 14-bit I/O port (Port 2), five 8-bit I/O
ports (PORT0 comprising P0H and P0L, PORT1 comprising P1H and P1L, and Port 4), one
12-bit I/O port (Port 3) and one 10-bit input port (Port 5).
These port lines may be used for general purpose input and output, controlled via software,
or may be used implicitly by ST10F252’s integrated peripherals or the external bus
controller.
All port lines are bit addressable and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers (except for Port 5). The I/O ports
are true bidirectional ports, which are switched to high impedance state when configured as
inputs. The output drivers of three I/O ports (2, 3, 4) can be configured pin by pin) for
push/pull operation or open-drain operation via control registers.
The logic level of a pin is clocked into the input latch once per ate time, regardless whether
the port is configured for input or output.
A write operation to a port pin configured as an input causes the value to be written into the
port output latch, while a read operation returns e latched state of the pin itself. A read-
modify-write operation reads the value of the pin, modifies it, and writes it back to the output
latch.
Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to
have the written value, since the output buffer is enabled. Reading this pin returns the value
of the output latch. A read-modify-write operation reads the value of the output latch,
modifies it, and writes it back to the output latch, thus also modifying the level at the pin.
Note:
A set of registers, mapped on XBUS, is implemented on ST10F252 to manage the data,
direction and open-drain mode for those pins where the XPWM, XASC and XSSC are
mappeThe standard port register bits for these pins are working when the X-peripherals
are not enabled (see XPERCON register); however, when the X-Peripherals are enabled,
the new registers take the control of the pins and the content if the standard registers is
ignored.
86/328
ST10F252M
Parallel ports
Figure 18. SFRs, XBUS registers and pins associated with the parallel ports
87/328
Parallel ports
ST10F252M
13.2
I/O’s special features
13.2.1
Open drain mode
Some of the I/O ports of ST10F252M support the open drain capability. This programmable
feature may be used with an external pull-up resistor, in order to provide an AND wired
logical function.
When open-drain mode is selected, the voltage on the pin must not exceed the V value to
DD
avoid injecting current through the diode, inherent in disabled upper transistor (turned off,
but still physically connected to the pin). This is taken into account especially during power-
on and power-off sequences (see stand-by mode entering procedure).
This feature is implemented for ports P2, P3, P4 (see Section 13.5, Section 13.6 and
Section 13.7 respectively) and is controlled through the respective Open Drain Control
Registers ODPx, for port P1 it’s implemented only when XSSC, XASC or XPWM are
enabled. Open Drain Control Registers allow the individual bit-wise selection of the open
drain mode for each port line. If the respective control bit ODPx.y is ‘0’ (default after reset),
the output driver is in the push/pull mode. If ODPx.y is ‘1’, the open drain configuration is
selected. Note that all ODPx registers are located in the ESFR pace.
Note:
When XPWM, XASC and XSSC are used (enabled through XPERCON) the open-drain
mode of the related pins is controlled by a set of new registers (XPWMPORT, XS1PORT,
XSSCPORT).
When XI2C is enabled (through XPERCON), the related pins of Port1 are automatically set
to open-drain mode.
Figure 19. Output drivers in push/pull mode and in open drain mode
External
Pull-up
Q
Q
Push-Pull Output Driver
Open Drain Output Driver
13.2.2
Input threshold control
The standard inputs of the ST10F252M determine the status of input signals according to
TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be
selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds
are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs
from toggling while the respective input signal level is near the thresholds.
Two port input control registers (PICON and XPICON) are used to select these thresholds
for each byte of the indicated ports: the 8-bit ports P4 is controlled by one bit while ports P0,
P1, P2, P3 and P5 are controlled by two bits each.
88/328
ST10F252M
Parallel ports
PICON (F1C4 / E2)
ESFR
7
Reset value: --00h
15
14
13
12
-
11
-
10
9
-
8
-
6
-
5
-
4
3
2
1
0
Reserved
-
P4LINP3HINP3LINP2HINP2LIN
RW RW RW RW RW
-
-
-
-
Table 52. Port input control register (PICON)
Bit
Name
Function
15:5
Reserved
Port x low byte input level selection
4:0
PxLIN
’0’: Pins Px.7...Px.0 switch on standard TTL input levels.
’1’: Pins Px.7...Px.0 switch on standard CMOS input levels.
XPICON (EB26)
XBUS
Reset value: --00h
15
14
13
12
-
11
10
9
-
8
-
7
6
5
4
3
2
1
0
Reserved
P5HIN LIN P1HIN P1LIN P0HIN P0LIN
RRW RW RW RW RW
-
-
-
-
-
-
-
Table 53. Additional port input control regier (XPICON)
Bit
Name
Function
15:6
Reserved
Port x high byte input level selection
5:0
PxHIN
’0’: Pins Px.15...Px.8 switch on standard TTL input levels.
’1’: Pins Px.15...Px.8 switch on standard CMOS input levels.
Note:
PICON is an ESR register, while XPICON is an XBUS register. XPICON is accessible only
after bit XMISCEN of XPERCON register and bit XPEN of SYSCON register have been set.
All options for individual direction and output mode control are available for each pin,
independent of the selected input threshold. The input hysteresis (variable, according to TTL
or CMOS selection) provides stable inputs from noisy or slowly changing external signals.
Figure 20. Hysteresis concept
Hysteresis
Input level
Bit state
13.2.3
Alternate port functions
Each port line has one (or more) associated programmable alternate input or output
functions. If an alternate output function of a pin is to be used, the direction of this pin must
be programmed for output (DPx.y=‘1’), except for some signals that are used directly after
reset and are configured automatically. Otherwise the pin remains in the high-impedance
89/328
Parallel ports
ST10F252M
state and is not affected by the alternate output function. The respective port latch should
hold a ‘1’, because its output is ANDed with the alternate output data (except for PWM
output signals).
If an alternate input function of a pin is used, the direction of the pin must be programmed
for input (DPx.y=‘0’) if an external device is driving the pin. The input direction is the default
after reset. If no external device is connected to the pin, however, the direction for this pin
can also be set to output. In this case, the pin reflects the state of the port output latch.
Thus, the alternate input function reads the value stored in the port output latch. This can be
used for testing purposes to allow a software trigger of an alternate input function by writing
to the port output latch.
On most of the port lines, user software is responsible for setting the proper direction when
using an alternate input or output function of a pin. This is done by setting or clearing the
direction control bit DPx.y of the pin before enabling the alternate function. There are port
lines, however, where the direction of the port line is switched automatically. For instance, in
the multiplexed external bus modes of PORT0, the direction must be switched several times
for an instruction fetch to output the addresses and to input the data. Obviously, this cannot
be done through instructions. In these cases, the direction of the port liis switched
automatically by hardware if the alternate function of such a pin is enabled. To determine the
appropriate level of the port output latches check how the alternate data output is combined
with the respective port latch output.
There is one basic structure for all port lines with onlan alternate input function. Port lines
with only an alternate output function, however, ve different structures due to the way the
direction of the pin is switched and depending on whether the pin is accessible by the user
software or not in the alternate functioode.
All port lines that are not used for these Alternate Functions may be used as general
purpose I/O lines. When using port pins for general purpose output, the initial output value
should be written to the port latch prior to enabling the output drivers, to avoid undesired
transitions on the output pins. This applies to single pins as well as to pin groups (see
examples below).
SINGLE_BIT:
BSET
P4.7
; Initial output level is “high”
; Switch on the output driver
; Initial output level is “high”
; Switch on the output drivers
BSET
DP4.7
BITGROUP:
BFLDH
BFLDH
P4, #24H, #24H
DP4, #24H, #24H
Note:
When using several BSET pairs to control more pins of one port, these pairs must be
separated by instructions, which do not reference the respective port.
13.3
PORT0
The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0,
respectively. Both halves of PORT0 can be written (for example, via a PEC transfer) without
affecting the other half.
90/328
ST10F252M
Parallel ports
P0L register
P0L register (FF00/80)
SFR
Reset value: --00h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
-
POL.7 POL.6 POL.5 POL.4 POL.3 POL.2 POL.1 POL.0
RW RW RW RW RW RW RW RW
P0H register
P0H register (FF02/81)
SFR
Reset value: --00h
15
14
13
12
11
reserved
-
10
9
8
7
6
5
4
3
2
1
0
POH. POH. POH. POH. POH. POH.
7
POH.1 POH.0
RW RW
6
5
4
3
2
RW
RW
RW
RW
RW
RW
Table 54. P0L and P0H registers functions
Bit
Name
Function
P0L 7.0
P0H 7.0
P0X.y
Port data register P0H or P0L bit y
If this port is used for general purpose I/O, the direction of each line can be configured via
the corresponding direction registers DP0H and DP0L.
DP0L register
DP0L register (F100/80)
15 14 13
ESFR
Reset value: --00h
12
11
10
9
8
7
6
5
4
3
2
1
0
DPOL DPOL DPOL DPOL DPOL DPOL DPOL. DPOL.
-
-
.7
.6
.5
.4
.3
.2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
DP0H gister
DPregister (F102/81)
ESFR
Reset value: --00h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DPOH DPOH DPOH DPOH DPOH DPOH DPOH. DPOH.
-
-
.7
.6
.5
.4
.3
.2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
Table 55. DP0L and DP0H registers functions
Bit
Name
Function
Port direction register DP0H or DP0L bit y
DP0L 7.0
DP0H 7.0
DP0X.y
‘0’: Port line P0X.y is an input (high-impedance)
‘1’: Port line P0X.y is an output
13.3.1
Alternate functions of PORT0
When an external bus is enabled, PORT0 is used as a data bus or an address and data bus,
when no additional ADC Channels (6) are selected.
91/328
Parallel ports
ST10F252M
An external 8-bit de-multiplexed bus only uses P0L, while P0H is free for I/O (provided that
no other bus mode is enabled).
PORT0 is also used to select the system start-up configuration. During reset, PORT0 is
configured to input and each line is held high through an internal pull-up device. Each line
can now be individually pulled to a low level (see the DC-level specifications in the
appropriate data sheets) through an external pull-down device. A default configuration is
selected when the respective PORT0 lines are at a high level. Through pulling individual
lines to a low level, this default can be changed according to the needs of the application.
The internal pull-up devices are designed such that an external pull-down resistors (see
Data Sheet specification) can be used to apply a correct low level. These external pull-down
resistors can remain connected to the PORT0 pins also during normal operation, however,
take care that they do not disturb the normal function of PORT0 (this may be the case, for
example, if the external resistor is too strong).
At the end of reset, the selected bus configuration is written to the BUSCON0 register. The
configuration of the high byte of PORT0, is copied into the special register RP0H. This read-
only register holds the selection for the number of chip selects and segment addresses.
Software can read this register to react to the selected configuration, if quired. When the
reset is terminated, the internal pull-up devices are switched off, and PORT0 is switched to
the appropriate operating mode.
During external accesses in multiplexed bus modes, PORT0 first outputs the 16-bit intra-
segment address as an alternate output function. PORT0 is then switched to high-
impedance input mode to read the incoming instction or data. In 8-bit data bus mode, two
memory cycles are required for word accesses, the first for the low byte and the second for
the high byte of the word. During write cles PORT0 outputs the data byte or word after
outputting the address. During external accesses in de-multiplexed bus modes, PORT0
reads the incoming instruction or data word or outputs the data byte or word.
Figure 21. PORT0 I/O and alternate functions
Alternatunction
a)
b)
c)
d)
D15
D14
D13
D12
D11
D10
D9
A15
A14
A13
A12
A11
A10
A9
AD15
AD14
AD13
AD12
AD11
AD10
AD9
P0H.7
P0H.6
P0H.5
P0H.4/AN15
P0H
P0H.3/AN14
P0H.2/AN13
P0H.1/AN12
P0H.0/AN11
P0L.7/AN10
P0L.6
D8
A8
AD8
PORT0
D7
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD7
D7
D6
D5
D4
D3
D2
D1
D0
D6
AD6
D5
AD5
P0L.5
D4
AD4
P0L.4
P0L
D3
AD3
P0L.3
D2
AD2
P0L.2
D1
AD1
P0L.1
D0
AD0
P0L.0
General Purpose
I/O and Analog Inputs
8-bit
Demux Bus
16-bit
Demux Bus
8-bit
MUX Bus
16-bit
MUX Bus
When an external bus mode is enabled, the direction of the port pin and the loading of data
into the port output latch are controlled by the bus controller hardware. The input of the port
output latch is disconnected from the internal bus and is switched to the line labeled
“Alternate Data Output” via a multiplexer. The alternate data can be the 16-bit intra-segment
address or the 8/16-bit data information. The incoming data on PORT0 is read on the line
“Alternate Data Input”. While an external bus mode is enabled, the user software should not
92/328
ST10F252M
Parallel ports
write to the port output latch, otherwise unpredictable results may occur. When the external
bus modes are disabled, the contents of the direction register last written becomes active.
Figure 22 shows the structure of a PORT0 pin.
Figure 22. Block diagram of a PORT0
Write DP0H.y / DP0L.y
Alternate
1
Direction
MUX
Direction
Latch
0
Read DP0H.y / DP0L.y
Alternate
Function
Enable
Alternate
Data
Output
Write P0H.y / P0L.y
1
P0H.y
P0L.y
Port Data
Output
MUX
Output
Buffer
Port Output
Latch
0
Read P0H.y / P0L.y
Clock
MUX
Input
Latch
0
y = 7...0
13.3.2
Disturb protection on analog inputs
A regiser is provided for additional disturb protection support on analog inputs for PORT0.
In articular, the register can disable both the digital input and output sections of the I/O
structure. To access this register the bit XMISCEN of register XPERCON and bit XPEN of
register SYSCON must be set.
93/328
Parallel ports
ST10F252M
Disturb protection register
Disturb protection register (EB36)
15 14 13 12
XP0DIDIS
Reset value: 0000h
11
10
9
8
7
6
-
5
4
3
2
1
0
-
-
-
XP1DI XP1DI XP1DI XP1DI XP1DI XP1DI
-
-
RW
RW
RW
RW
RW
RW
Table 56. Disturb protection register functions
Bit Name
Function
Port 1 Digital Disable register bit y
‘0’: Port line P0.y digital input and output are not disabled: the port pin
is defined through the corresponding bits of the standard registers
P0L/DP0L. General Purpose Input/Output functionality is available, as
well as the external memory interface functionality.
5.0 XP0DIDIS.y
‘1’: Port line P0.y digital input and output are disaled (necessary for
input leakage current reduction and to void undesired conflict
between output driver configuration ananalog input signal). Once this
bit is set, P0L/DP0L correspondinbits are no longer effective and the
external memory interface functionality is masked on the single bit.
Figure 23. Block diagram of input section oORT0L pin
Chel
Select
Analog
to Sample + Hold
Circuit
Switch
P0L,H.x/ANy
Read Port P0L,H.x Clock
XP0DIDIS.x
Input
Latch
Read
x = 7,0...4
y = 10...15
Buffer
94/328
ST10F252M
Parallel ports
Figure 24. Block diagram of a PORT0 pin
Write DP0H.7 / DP0L.y
“1”
1
MUX
0
Direction
Latch
Read DP0H.7 / DP0L.y
Alternate
Function
Enable
Alternate
Data
Output
Write P0H.7 / P0L.y
1
MUX
P0H.y
P0L.7
Port Data
Output
Output
Buffer
Port Output
Latch
0
Read P0H.7 / P0L.y
XP0DIDIS.y,5
Clock
1
MUX
0
Inut
Latch
y = 0...4
13.4
PORT1
The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1,
respectively. Either half of PORT1 can be written (for example, by a PEC transfer) without
effecting the other half.
P1L register
P1L register (FF04/82)
15 14 13
SFR
Reset value: --00h
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
P1L7 P1L6 P1L5 P1L4 P1L3 P1L2 P1L1 P1L0
RW
RW
RW
RW
RW
RW
RW
RW
P1H register
P1H register (FF06/83)
SFR
Reset value: --00h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
P1H7 P1H6 P1H5 P1H4 P1H3 P1H2 P1H1 P1H0
RW
RW
RW
RW
RW
RW
RW
RW
95/328
Parallel ports
ST10F252M
Table 57. P1L and P1H registers functions
Pin
Name
Function
P1L 7.0
P1R 7.0
P1X.y
Port data register P1H or P1L bit y
If PORT1 is used for general purpose I/O, the direction of each line can be configured via
the corresponding direction registers DP1H and DP1L.
DP1L register
DP1L register (F104/82)
15 14 13
ESFR
Reset value: --00h
12
11
10
9
8
7
6
5
4
3
2
1
0
DP1L. DP1L. DP1L. DP1L. DP1L. DP1L. DP1L. DP1L.
-
-
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
DP1H register
DP1H register (F106/83)
ESFR
Reset value: --00h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DP. DP1H. DP1H. DP1H. DP1H. DP1H. DP1H. DP1H.
-
-
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
Table 58. DP1L and DP1H registers functions
Bit
Name
Function
Port direction register DP1H or DP1L bit y
DP1L 7.0
DP1H 7.0
DP1X
‘0’: Port line P1X.y is an input (high-impedance)
‘1’: Port line P1X.y is an output
If PORT1 pins are used as alternate function for input/output of XPWM, XASC or XSSC
peripherals, the direction of each pins is configured by dedicated registers mapped in the X-
peripheral memory area, an open drain setting is also available for used port P1 pins.
Registers that are used for different alternate function are described in the following.
XSSCPORT
This register is enabled and visible only when bit XPEN of SYSCON is set, and bit XSSCEN
in XPERCON is also set. If not enabled, the standard P1H, DP1H registers are used to
configure pins P1H.1, P1H.2 and P1H.3; the open drain setting is not available.
XSSCPORT register
XSSCPORT register (E880)
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
XDP1
H.3.7
XP1 XDP1
XP1
H.1
XDP1
H.1
XOD
P1H.3
XP1
H.3
XOD
P1H.2
XOD
P1H.1
-
H.2
H.2.6
-
RW
RW
RW
RW
RW
RW
RW
RW
RW
96/328
ST10F252M
Parallel ports
Table 59. XSSCPORT register functions
Bit
Name
Function
Port open drain control register bit y (y = 1, 2, 3 only)
‘0’: Port line P1H.y output driver in push/pull mode
‘1’: Port line P1H.y output driver in open drain mode
8, 5, 2
7, 4, 1
6. 3. 0
XODP1H.y
XP1H.y
Port data register bit y (y = 1, 2, 3 only)
Port direction register bit y (y = 1, 2, 3 only)
‘0’: Port line P1H.y is an input (high-impedance)
‘1’: Port line P1H.y is an output
XDP1H.y
XS1PORT
This register is enabled and visible only when bit XPEN of SYSCON is set, and bit XASCEN
in XPERCON is also set. If not enabled, the standard P1L, DP1L registers are used to
configure pins P1L.4 and P1L.5; the open drain setting is not available.
XS1PORT register
XS1PORT register (E980)
15 14 13
Reset value: 0000h
12
11
10
9
8
7
6
5
4
3
2
1
0
XP1 XDP1
XP1
L.5
XDP1
L.5
XOD
P1L.4
XOD
P1L.5
Reserved
-
L.4
L.4.7
RW
RW
RW
RW
RW
RW
Table 60. XS1PORT register functions
Bit
Name
Function
Port open drain control register bit y (y = 4, 5 only)
‘0’: Port line P1L.y output driver in push/pull mode
‘1’: Port line P1L.y output driver in open drain mode
5, 2
4, 1
3, 0
XOD1L.y
XP1L.y
Port data register bit y (y = 4, 5 only)
Port direction register bit y (y = 4, 5 only)
‘0’: Port line P1L.y is an input (high-impedance)
‘1’: Port line P1L.y is an output
XDP1L.y
XPWMPORT
This register is enabled and visible only when bit XPEN of SYSCON is set, and bit
XPWMEN in XPERCON is also set. If not enabled, the standard P1L, DP1L registers are
used to configure pins P1L.0, P1L.1, P1L.2 and P1L.3; the open drain setting is not
available.
97/328
Parallel ports
ST10F252M
XPWPORT register
XPWNPORT register (EC80)
15 14 13 12
Reset value: 0000h
11
10
9
8
7
6
5
4
3
2
1
0
XP1 XDP1
XP1 XDP1
XP1 XDP1
XP1
L.0
XDP1
L.0
XOD
P1L.3
XOD
P1L.2
XOD
P1L.1
XOD
P1L.0
-
-
L.3
L.3
L.2
L.2.2
L.1
L.1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 61. XPWPORT register functions
Bit
Name
Function
Port open drain control register bit y (y = 0, 1, 2, 3 only)
‘0’: Port line P1L.y output driver in push/pull mode
‘1’: Port line P1L.y output driver in open drain mode
11, 8,
5, 2
XODP1L.y
10, 7,
4, 1
XP1L.y
Port data register bit y (y = 0, 1, 2, 3 only)
Port direction register bit y (y = 0, 1, 2, only)
‘0’: Port line P1L.y is an input (high-impedance)
‘1’: Port line P1L.y is an output
9, 6,
3, 0
XDP1L.y
13.4.1
Alternate functions of PORT1
When a de-multiplexed external bus is abled, PORT1 is used as address bus. De-
multiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used
for general purpose I/O.
Pins P1H.3...P1H.1 of PORT1 are also used for receive/transmit and clock lines of SSC1.
Pins P1L.7 and P1L.6 of PORT1 are also used for input/output lines of I2C.
Pins P1L.5 and L.4 of PORT1 are also used for receive, transmit lines of ASC1.
Pins P.3...P1L.0 of PORT1 are also used for output lines of PWM1.
The upper four pins of PORT1 (P1H.7...P1H.4) also serve as capture input lines for the
CAPCOM2 unit (CC27I...CC24I). As all other capture inputs, the capture input function of
pins P1H.7...P1H.4 can also be used as external interrupt inputs (83.34 ns sample rate at
48 MHz CPU clock).
During external accesses in de-multiplexed bus modes, PORT1 outputs the 16-bit
intra-segment address as an alternate output function.
During external accesses in multiplexed bus modes, when no BUSCON register selects a
de-multiplexed bus mode, PORT1 is not used and is available for general purpose I/O and
other alternate functions.
98/328
ST10F252M
Parallel ports
Figure 25. PORT1 I/O and alternate functions
Alternate Function
a)
b)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
P1H.7
P1H.6
P1H.5
P1H.4
CC27I
CC26I
CC25I
CC24I
SCLK
MTSR
MRST
P1H
P1H.3
P1H.2
P1H.1
P1H.0
PORT1
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
P1L.1
P1L.0
SDA
SCL
RxD
TxD
XPOUT3
XPOUT2
XPOUT1
XPOUT0
A4
A3
A2
A1
P1L
A0
8/16-bit
Demux bus
CAPCOM2 Capt.In
/XPWM/XSSC/XASC/I2C
General Purpose
Input/Output
When demultiplexed external bus mode is enabled, the direction of the port pin and the
loading of data into the port output latch are controlled by the bus controller hardware. The
input of the port output latch is disconnected from the internal bus and iwitched to the line
labeled “Demux Bus” via a multiplexer. The alternate data is the 16-intra-segment
address. While an external bus mode is enabled, the software does not write to the port
output latch, otherwise unpredictable results may occur. When external bus modes are
disabled, the contents of the direction register last written becomes active.
If one or more peripherals from XASC, I2C, XSSCXPWM (bit XPEN of SYSCON is set, and
associated bit to peripheral in XPERCON is set) are enabled, alternate functions for
demultiplexed bus cannot be used.
Figure 26. Block diagram of a PORT1 pin P1H.7...P1H.4
Write DP1H.y
1
“1”
MUX
Direction
Latch
0
Read DP1H.y / DP1L.y
DEMUX
BUS
Enable
DEMUX BUS
Output
Write P1H.y
1
P1H.y
Port Data
Output
MUX
Output
Buffer
Port Output
Latch
0
Read P1H.y
Clock
1
MUX
Input
Latch
0
(y = 7...4)
99/328
Parallel ports
Figure 27. Block diagram of pins P1H.3 ...P1H.1
ST10F252M
‘0’
0
MUX
1
I
n
t
e
r
n
a
l
Write DP1Hy
1
‘1’
0
MUX
MUX
0
Direction
Latch
1
Read DP1H.y
Write P1H.y
DEMUX BUS
Enable
B
u
s
DEMUX BUS
Data Output
1
MUX
0
MUX
Port Output
Latch
0
P1H.y
1
Output
Buffer
Read P1.y
1
MUX
&
SCLK1/MTSR1/MRST1
Data Output
Clock
0
Input
Latch
Write XODP1H.y
Open Drain
Latch
Read XODP1H..y
Write XDP1H.y
I
n
t
e
r
n
a
l
Direction
Latch
Read XDP1H.y
Write XP1H.y
XXPERCON(8)
XSSCEN
X
b
u
s
SCLK1/MTSR1/MRST1
Data Input
Port Output
Latch
Read XP1H.y
(y = 1...3)
100/328
ST10F252M
Parallel ports
Figure 28. Block diagram of pin P1L.6, P1.7
Open Drain
Write DP1L.y
1
MUX
‘1’
0
MUX
Direction
Latch
0
‘1’
1
Read DP1L.y
DEMUX BUS
Enable
I
n
t
e
r
n
a
l
Write P1L.y
DEMUX BUS
Data Output
1
MUX
0
MUX
Port Output
Latch
0
P1L.y
1
Read P1L.y
Output
Buffer
1
MUX
B
u
s
ock
0
Input
Latch
SDA/SCL
Data Output
XPERCON.9
(I2CEN)
SDA/SCL
Data Input
(y = 6,7)
101/328
Parallel ports
Figure 29. Block diagram of pins P1L.5
ST10F252M
Open Drain
‘0’
0
MUX
1
I
n
t
e
r
n
a
l
Write DP1.5
1
MUX
0
‘1’
0
MUX
1
Direction
Latch
Read DP1.5
Write P1.5
DEMUX BUS
Enable
B
u
s
DEMUX BUS
Data Output
1
MUX
0
MUX
Port Output
Latch
0
P1L.5
1
Output
Buffer
Read P1.5
1
MUX
&
RxD
Data Output
ck
0
Input
Latch
Write XODP1.5
Open Drain
Latch
Read XODP1.5
Write XDP1.5
I
n
t
e
r
n
a
l
Direction
Latch
Read XDP1.5
WP1.5
XPERCON(7)
XASC Enable
X
b
u
s
RxD
Data Input
Port Output
Latch
Read XP1.5
102/328
ST10F252M
Parallel ports
Figure 30. Block diagram of pins P1L.4
Open Drain
‘0’
0
MUX
1
I
n
t
e
r
n
a
l
Write DP1L.4
1
MUX
0
‘1’
0
MUX
1
Direction
Latch
Read DP1L.4
Write P1L.4
DEMUX BUS
Enable
B
u
s
DEMUX BUS
Data Output
1
MUX
0
MUX
Port Output
Latch
0
P1L.4
1
Output
Buffer
Read P1L.4
1
MUX
&
TxD
Data Output
ck
0
Input
Latch
Write XODP1L.4
Open Drain
Latch
Read XODP1L.4
Write XDP1L.4
I
n
t
e
r
n
a
l
Direction
Latch
Read XDP1L.4
WritL.4
XPERCON(7)
XASCEN
X
b
u
s
Port Output
Latch
Read XP1L.4
103/328
Parallel ports
Figure 31. Block diagram of pins P1L.3...P1L.0
ST10F252M
Open Drain
‘0’
0
MUX
1
I
n
t
e
r
n
a
l
Write DP1L.y
1
MUX
0
‘1’
0
MUX
1
Direction
Latch
Read DP1L.y
Write P1L.y
DEMUX BUS
Enable
B
u
s
DEMUX BUS
Data Output
1
MUX
0
MUX
Port Output
Latch
0
P1L.y
1
Output
Buffer
Read P1L.y
1
XPOUTy
Data Output
MUX
=1
k
0
EXOR
Input
Latch
Write XODP1L.y
Open Drain
Latch
Read XODP1L.y
Write XDP1L.y
I
n
t
e
r
n
a
l
Direction
Latch
Read XDP1L.y
Wri1L.y
XPERCON(6)
XPWMEN
X
b
u
s
Port Output
Latch
Read XP1L.y
(y = 0...3)
13.5
PORT2
If this 14-bit port is used for general purpose I/O, the direction of each line is configured by
the corresponding direction register DP2. Each port line can be switched into push/pull or
open drain mode by the open drain control register ODP2.
104/328
ST10F252M
Parallel ports
PORT2 register
PORT2 register (FFC0/E0)
SFR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9
RW RW RW RW RW RW RW
P2.8
RW
P2.7
RW
P2.6
RW
P2.5
RW
P2.4
RW
P2.3
RW
P2.2
RW
-
-
-
-
Table 62. PORT2 register functions
Bit
Name
Function
15.2 P2.y
Port data register P2 bit y
PORT2 direction register
PORT2 direction register (FFC2/E1)
SFR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DP2.1 DP2.1 DP2.1 DP2.1 DP2.1 DP2.1
DP2.9 DP2.8 DP2.7 DP2.6 DP2.5 DP2.4 DP2.3 DP2.2
RW RW RW RW RW RW RW RW
-
-
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
-
-
Table 63. PORT2 direction register functions
Bit
Name
Function
Port direction register DP2 bit y
15.2 DP2.y
‘0’: Port line P2.y is an input (high-impedance)
‘1’: Port line P2.y is an output
PORT2 open ain control register
PORT2 n drain control register (F1C2/E1)
ESFR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2. ODP2. ODP2 ODP2 ODP2 ODP2 ODP2 ODP2
-
-
. 15
RW
. 14
RW
.13
. 12
RW
. 11
RW
. 10
RW
9
8
.7
.6
.5
.4
.3
.2
RW
RW
RW
RW
RW
RW
RW
RW
RW
-
-
Table 64. PORT2 open drain control register functions
Bit
Name
Function
Port 2 open drain control register bit y
15.2
ODP2.y
‘0’: Port line P2.y output driver in push/pull mode
‘1’: Port line P2.y output driver in open drain mode
13.5.1
Alternate functions of PORT2
All PORT2 lines (P2.15 to P2.2) serve as capture inputs or compare outputs (CC15IO to
CC2IO) for the CAPCOM1 unit.
105/328
Parallel ports
ST10F252M
When a PORT2 line is used as a capture input, the state of the input latch, which represents
the state of the port pin, is directed to the CAPCOM unit via the line “Alternate Pin Data
Input”. If an external capture trigger signal is used, the direction of the respective pin is set
to input. If the direction is set to output, the state of the port output latch is read since the pin
represents the state of the output latch. This can be used to trigger a capture event through
software by setting or clearing the port latch. In the output configuration, no external device
may drive the pin, otherwise conflicts would occur.
When a PORT2 line is used as a compare output (compare modes 1 and 3), the compare
event (or the timer overflow in compare mode 3) directly effects the port output latch. In
compare mode 1, when a valid compare match occurs, the state of the port output latch is
read by the CAPCOM control hardware via the line “Alternate Latch Data Input”, inverted,
and written back to the latch via the line “Alternate Data Output”. The port output latch is
clocked by the signal “Compare Trigger” which is generated by the CAPCOM unit. In
compare mode 3, when a match occurs, the value '1' is written to the port output latch via
the line “Alternate Data Output”. When an overflow of the corresponding timer occurs, a '0' is
written to the port output latch. In both cases, the output latch is clocked by the signal
“Compare Trigger”. The direction of the pin is set to output by the user, herwise the pin will
be in the high-impedance state and will not reflect the state of the oput latch.
As can be seen from the port structure (Figure 33), the user software always has free
access to the port pin even when it is used as a compare utput. This is useful for setting up
the initial level of the pin when using compare mode 1 or the double-register mode. In these
modes, unlike in compare mode 3, the pin is not set to a specific value when a compare
match occurs but is toggled instead.
When the user software wants to writthe port pin at the same time a compare trigger
tries to clock the output latch, the write operation of the user software has priority. Each time
a CPU write access to the port output latch occurs, the input multiplexer of the port output
latch is switched to the line connected to the internal bus. The port output latch receives the
value from the internal bus and the hardware-triggered change is lost.
As all other capture inputs, the capture input function of pins P2.15...P2.0 can also be used
as external interpt inputs (83.34 ns sample rate at 48 MHz CPU clock).
The upr eight PORT2 lines (P2.15 to P2.8) also can serve as fast external Interrupt inputs
(EX7IN to EX0IN).
P2.15 also serves as the input for CAPCOM2 timer T7 (T7IN).
Table 65 summarizes the alternate functions of PORT2.
Table 65. PORT2 alternate functions
Pin Alternate function a)
Alternate function b)
Alternate function c)
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
CC2IO
CC3IO
CC4IO
CC5IO
CC6IO
CC7IO
CC8IO
CC9IO
-
-
-
-
-
-
-
-
-
-
EX0IN Fast Ext. Interrupt 0 Input -
EX1IN Fast Ext. Interrupt 1 Input -
106/328
ST10F252M
Parallel ports
Table 65. PORT2 alternate functions (continued)
Pin Alternate function a)
Alternate function b)
Alternate function c)
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
CC10IO
CC11IO
CC12IO
CC13IO
CC14IO
CC15IO
EX2IN Fast Ext. Interrupt 0 Input -
EX3IN Fast Ext. Interrupt 1 Input -
EX4IN Fast Ext. Interrupt 0 Input -
EX5IN Fast Ext. Interrupt 1 Input -
EX6IN Fast Ext. Interrupt 0 Input -
EX7IN Fast Ext. Interrupt 1 Input T7IN timer external count input
Figure 32. PORT2 I/O and alternate functions
Alternate Function
a)
b)
c)
T7IN
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
CC15IO
CC14IO
CC13IO
CC12IO
CC11IO
CC10IO
CC9IO
CC8IO
CC7IO
CC6IO
CC5IO
CC4IO
CC3IO
CC2IO
EX7IN
EX6IN
EX5IN
EX4IN
EX3IN
EX2IN
EX
EX0
P2.8
Port 2
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
No Pins
General Purpose
Input/Output
CAM1
Capt.Inp./p.Output
Fast External
Interrupt Input
CAPCOM2
Timer T7 Input
The pins of PORT2 combine internal bus data with alternate data output before the port
latch input.
107/328
Parallel ports
Figure 33. Block diagram of a PORT2 pin
ST10F252M
Write 0DP2.y
Open Drain
Latch
Read 0DP2.y
Write DP2.y
Direction
Latch
Read DP2.y
1
MUX
P2.y
CCyIO
EXxIN
Output
h
Alternate
Data
Output
Output
Buffer
0
≥ 1
Write Port P2.y
Compare Trigger
Read P2.y
Clock
1
0
MUX
Input
Latch
Alternate Data Input
Fast External Interrupt Input
x = 7...0
y = 15...2
13.6
PORT3
If this 12-bit port is used for general purpose I/O, the direction of each line can be configured
by the corresponding direction register DP3. Most port lines can be switched into push/pull
or open drain mode by the open drain control register ODP3 (pins P3.15 and P3.12 do not
support open drain mode). P3.4 function can be used if P34EN, bit 5 of XMISC register, is
set to 1, see Section 18.3.
108/328
ST10F252M
Parallel ports
PORT3 register
PORT3 register (FFC4/E2)
SFR
Reset value: 0000h
15
P3.15
RW
14
13
P3.13 P3. 12 P3. 11 P3. 10 P3.9
RW RW RW RW RW
12
11
10
9
8
7
6
5
-
4
P3.4
-
3
-
2
1
0
-
P3.8
RW
P3.7 P3.6
RW RW
P3.2
RW
P3.1
RW
P3.0
RW
-
-
-
Table 66. PORT3 register functions
Bit
Name
Function
15.0 P3.y
Port data register P3 bit y
PORT3 direction register
PORT3 direction register (FFC6/E3)
SFR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
DP3.4
-
2
1
0
DP3.1
5
DP3.1 DP3.1 DP3.1 DP3.1
3
-
DP3.9 DP3.8 DP3.7 DP3.6
-
-
-
-
DP3.2 DP3.1 DP3.0
2
1
0
RW
-
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 67. PORT3 direction register functions
Bit
Name
Function
Port direction register DP3 bit y
15.0 DP3.y
‘0’: Port line P3.y is an input (high-impedance)
‘1’: Port line P3.y is an output
PORT3 open ain control register
PORT3 n drain control register (F1C5/E3)
ESFR
Reset value: 0000h
15
-
14
-
13
12
-
11
10
9
8
7
6
5
-
4
3
2
1
0
ODP3.
13
ODP3. ODP3. ODP3. ODP3. ODP3. ODP3.
11
ODP3.
4
ODP3. ODP3. ODP3.
2
-
-
10
9
8
7
6
1
0
-
-
RW
-
RW
RW
RW
RW
RW
RW
-
-
RW
RW
RW
Table 68. PORT3 open drain control register functions
Bit Name Function
Port 3 open drain control register bit y
13.0 ODP3.y
‘0’: Port line P3.y output driver in push/pull mode
‘1’: Port line P3.y output driver in open drain mode
109/328
Parallel ports
ST10F252M
13.6.1
Alternate functions of PORT3
The pins of PORT3 serve for various functions which include external timer control lines, two
serial interfaces ASC0 and SSC0, the control lines BHE/WRH and CLKOUT.
Table 69. PORT3 alternative functions
PORT3
Name
Pin
P3.0
P3.1
T0IN
T6OUT
CAPIN
---
CAPCOM1 Timer 0 Count Input
Timer 6 Toggle Output
P3.2
GPT2 Capture Input
P3.3
No pin assigned!
P3.4
T3EUD
---
Timer 3 External Up/Down Input
No pin assigned!
P3.5
P3.6
T3IN
Timer 3 Count Input
P3.7
T2IN
Timer 2 Count Input
P3.8
MRST0
MTSR0
TxD0
RxD0
SSC0 Master Receive / Slave Transmit
SSC0 Master Transmit / Slave Receive
ASC0 Transmit Data Output
ASC0 Receive Data Input
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
BHE/WRH Byte High Enable / Write High Output
SCLK0
---
SSC0 Shift Clock Input/Out
No pin assigned!
CLKOUT
System Clock put (either prescaled or not through register CLKDIV)
Figure 34. PORT3 I/O and alternate functions
Alternate Function
a)
b)
CLKOUT
P3.15
No Pin
SCLK0
BHE
RxD0
TxD0
MTSR0
MRST0
T2IN
P3.13
P3.12
P3.11
P3.10
P3.9
P3.8
P3.7
WRH
Port 3
T3IN
P3.6
T3EUD
No Pins
CAPIN
T6OUT
T0IN
P3.2
P3.1
P3.0
General Purpose
Input/Output
The port structure of the PORT3 pins depends on their alternate function (see Figure 35).
When the on-chip peripheral associated with a PORT3 pin is configured to use the alternate
input function, it reads the input latch, which represents the state of the pin, via the line
labeled “Alternate Data Input”. PORT3 pins with alternate input functions are T0IN, T2IN,
T3IN , T3EUD and CAPIN.
When the on-chip peripheral associated with a PORT3 pin is configured to use the alternate
output function, its “Alternate Data Output” line is ANDed with the port output latch line.
When using these alternate functions, the user software must set the direction of the port
line to output (DP3.y=1) and set the port output latch (P3.y=1). Otherwise, the pin is in its
high-impedance state (when configured as input) or the pin is held at '0' (when the port
110/328
ST10F252M
Parallel ports
output latch is cleared). When the alternate output functions are not used, the “Alternate
Data Output” line is in its inactive state, which is a high level ('1'). PORT3 pins with alternate
output functions are: T6OUT, TxD0 and CLKOUT.
When the on-chip peripheral associated with a PORT3 pin is configured to use both the
alternate input and output function, the descriptions above apply to the respective current
operating mode. The direction must be set accordingly. PORT3 pins with alternate input and
output functions are: MTSR0, MRST0, RxD0, TxD0 and SCLK0.
Note:
Enabling the CLKOUT function automatically enables the P3.15 output driver. Setting bit
DP3.15 = ‘1’ is not required.
Figure 35. Block diagram of PORT3 pin with alternate input or alternate output
function
Write 0DP3.y
Open Drain
Latch
Read 0DP3.y
Write DP3.y
Direction
Latch
Read DP3.y
Alternate
Data Output
Write DP3.y
Port Data
Output
&
P3.y
Port Output
Latch
Output
Buffer
Read P3.y
Clock
1
MUX
Input
Latch
0
Alternate
Data
Input
y = 13, 11...0
Pin P3.12 (BHE/WRH) is another pin with an alternate output function, however, its structure
is slightly different (see Figure 36). After reset, the BHE or WRH function must be used
111/328
Parallel ports
ST10F252M
depending on the system start-up configuration. In either of these cases, it is not possible to
program port latches. Thus, the appropriate alternate function is selected automatically. If
BHE/WRH is not used in the system, this pin can be used for general purpose I/O by
disabling the alternate function (BYTDIS = ‘1’ / WRCFG=’0’).
Figure 36. Block diagram of pins P3.15 (CLKOUT) and P3.12 (BHE/WRH)
Write DP3.x
1
“1”
MUX
0
Direction
Latch
Read DP3.x
Alternate
Function
Enable
Write P3.x
Alternate
Data
Output
1
MUX
P3.12/BHE
P3.15/CLKOUT
Output
Buffer
Port Output
Latch
0
Read P3.x
Clock
1
0
MUX
Input
Latch
x = 15, 12
Note:
Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit
DP3.12 = ‘1’ is nt required.
13.7
PORT4
Port 4 is 8-bit port, it can be used for general purpose I/O, the direction of each line can be
configured via the corresponding direction register DP4.
PORT4 register
PORT4 register (FFC8/E4)
15 14 13 12
SFR
Reset value: --00h
11
10
9
8
7
6
5
4
3
2
1
0
-
-
P4.7
RW
P4.6
RW
P4.5
RW
P4.4
RW
P4.3
RW
P4.2
RW
P4.1
RW
P4.0
RW
Table 70. PORT4 register functions
Bit
Name
Function
7.0 P4.y
Port data register P4 bit y
112/328
ST10F252M
Parallel ports
PORT4 direction register
PORT4 direction register (FFCA/E5)
SFR
Reset value: --00h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
DP4.7 DP4.6 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4.0
RW
RW
RW
RW
RW
RW
RW
RW
Table 71. PORT4 direction register functions
Bit
Name
Function
Port direction register DP4 bit y
7.0
DP4.y
‘0’: Port line P4.y is an input (high-impedance)
‘1’: Port line P4.y is an output
For CAN configuration support (see Section 18), PORT4 has an open drain function,
controlled with the ODP4 register.
PORT4 open drain control register
PORT4 open drain control register (F1CA/E5)
15 14 13 12 11 10
ESFR
Reset value: --00h
9
8
7
6
5
4
3
2
1
0
ODODP4 ODP4 ODP4
-
-
-
-
.7
.6
.5
.4
RW
RW
RW
RW
Table 72. PORT4 open drain control register functions
Bit Name Function
Port 4 open drain control register bit y
‘0’: Port line P4.y output driver in push/pull mode
7.4 ODP4
‘1’: Port line P4.y output driver in open drain mode if P4.y is not a
segment address line output
Only bits 4, 5, 6 and 7 are implemented, all other bits are read as “0”.
Port 4 pins 0,1, 2, and 3 are connected to external pins 47-50 only if bit P7EN of XMISC
register is zero, that is its default value (see Section 18.3 for XMISC description).
13.7.1
Alternate functions of PORT4
During external bus cycles that use segmentation (that is, an address space above
64 Kbyte), a number of PORT4 pins may output the segment address lines. The number of
pins that is used for segment address output determines the external address space which
is directly accessible. The other pins of PORT4 may be used for general purpose I/O. If
segment address lines are selected, the alternate function of PORT4 may be necessary to
access, for example, external memory directly after reset. For this reason, PORT4 is
switched to this alternate function automatically.
The number of segment address lines is selected via PORT0 during reset. The selected
value can be read from bitfield SALSEL in register RP0H (read only) to, for example, check
the configuration during run time.
113/328
Parallel ports
ST10F252M
Devices with CAN interfaces use two pins of PORT4 to interface each CAN Module to an
external CAN transceiver. In this case, the number of possible segment address lines is
reduced.
Table 73 summarizes the alternate functions of PORT4 depending on the number of
selected segment address lines (coded via bitfield SALSEL).
Table 73. PORT4 alternate functions
Standard function
Alternate function
Alternate function
SALSEL=00 1 Mb
Alternate function
SALSEL=10 6 Mb
Pin
SALSEL=01 64 Kb SALSEL=11 256 Kb
P4.0 GPIO
Seg. Address A16
Seg. Address A17
GPIO
Seg. Address A16
Seg. Address A17
Seg. Address A18
Seg. Address A19
GPIO/CAN2_RxD
Seg. Address A16
Seg. Address A17
Seg. Address A18
Seg. Address A19
Seg. Address A20
P4.1 GPIO
P4.2 GPIO
P4.3 GPIO
GPIO
P4.4 GPIO/CAN2_RxD
GPIO/CAN2_RxD
P4.5 GPIO/CAN1-2_RxD GPIO/CAN1-2_RxD GPIO/CAN1-2_RxD Seg. Address A21
P4.6 GPIO/CAN1-2_TxD
P4.7 GPIO/CAN2_TxD
GPIO/CAN1-2_TxD
GPIO/CAN2_TxD
GPIO/CAN1-2_TxD
GPIO/CAN2_TxD
eg. Address A22
Seg. Address A23
Note:
When SALSEL=’10’, CAN1 and CAN2 cannot be used: it means that external memory has
higher priority on CAN alternate function. PORT4 I/O and alternate functions
Figure 37. PORT4 I/O and alternate functions
Alternate Function
b)
a)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port 4
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
CAN2_TxD
A23
A22
A21
A20
A19
A18
A17
A16
CAN1_TxD / CAN2_TxD
CAN1_RxD / CAN2_RxD
CAN2_RxD
General Purpose
Input/Output
114/328
ST10F252M
Parallel ports
Figure 38. Block diagram of pins P4.0 ... P4.3
Write DP4.y
1
“1”
MUX
0
Direction
Latch
Read DP4.y
Alternate
Function
Enable
Write P4.y
Alternate
Data
Output
1
MUX
P4.y
Output
Buffer
Port Output
Latch
0
Read P4.y
Clo
1
0
MUX
Input
Latch
y = 3...0
115/328
Parallel ports
ST10F252M
Figure 39. Block diagram of pin P4.4
Write ODP4.4
Open Drain
Latch
0
MUX
‘0’
1
Read ODP4.4
Write DP4.4
1
MUX
0
‘1’
Direction
0
Latch
MUX
‘0’
1
Read DP4.4
Write P4.4
Ext. Memory
Function
Enable
I
n
t
Ext. Memory
Data Output
1
MUX
e
r
P4.4
Port Output
Latch
0
n
a
l
Output
Buffer
Read P4.4
1
MUX
B
u
s
Clock
0
Input
Latch
XPERCON.1
(CAN2EN)
CAN2_R
Data Inp
&
0
MUX
P4.5
1
XPERCON.0
(CAN1EN)
&
XMISC.1
(CANPAR)
1. When SALSEL=’10’, that is 8-bit segment address lines are selected, P4.4 is dedicated to output the
address; any attempt to use CAN2 on P4.4 is masked
When CAN parallel mode is selected, CAN2_RxD is remapped on P4.5; this occurs only if CAN1 is also
enabled. If CAN1 is disabled, no remapping occurs.
116/328
ST10F252M
Parallel ports
Figure 40. Block diagram of pin P4.5
Write ODP4.5
Open Drain
Latch
0
MUX
‘0’
1
Read ODP4.5
Write DP4.5
1
‘1’
Direction
Latch
0
MUX
MUX
0
‘0’
1
Read DP4.5
Ext. Memory
Function
Enable
I
n
Write P4.5
Ext. Memory
Data Output
t
e
r
n
a
l
1
MUX
P4.5
Port Output
Latch
0
Output
Buffer
Read P4.5
1
MUX
B
u
s
C
0
Input
Latch
XPERCON.0
(CAN1EN)
CAN1_RxD
Data Input
&
&
1
MUX
0
CAN2_RxD
Data Input
P4.4
XPERCON.1
(CAN2EN)
&
XMISC.1
(CANPAR)
1. WheSALSEL=’10’, that is 8-bit segment address lines are selected, P4.5 is dedicated to output the
address; any attempt to use the CAN1 on P4.5 is masked.
When CAN parallel mode is selected, CAN2_RxD is remapped on P4.5; this occurs only if CAN1 is also
enabled. If CAN1 is disabled, no remapping occurs.
117/328
Parallel ports
Figure 41. Block diagram of pin P4.6
ST10F252M
Write ODP4.6
Open Drain
Latch
0
MUX
‘0’
1
Read ODP4.6
Write DP4.6
1
MUX
‘1’
Direction
Latch
0
MUX
0
‘1’
1
Read DP4.6
Write P4.6
Ext. Memory
Function
Enable
I
n
t
e
r
n
a
l
Ext. Memory
Data Output
1
Port Output
Latch
0
MUX
MUX
P4.6
0
Output
fer
1
Read P4.6
B
u
s
1
MUX
Clock
0
Input
Latch
CAN1_TxD
Data Output
0
MUX
&
1
CAN2_TxD
Data Output
XPERCON.0
(CAN1EN)
XPERCON.1
(CAN2EN)
&
XMISC.1
(CANPAR)
1. When SALSEL=’10’, that is 8-bit segment address lines are selected, P4.6 is dedicated to output the
address; any attpt to use the CAN1 on P4.6 is masked.
When CAN paral mode is selected, CAN2_TxD is remapped on P4.6: this occurs only if CAN1 is also
enabled. If CN1 is disabled, no remapping occurs.
118/328
ST10F252M
Parallel ports
Figure 42. Block diagram of pin P4.7
Write ODP4.7
Open Drain
Latch
0
MUX
‘0’
1
Read ODP4.7
Write DP4.7
1
MUX
0
‘1’
Direction
Latch
0
MUX
‘1’
1
Read DP4.7
Ext. Memory
Function
Enable
I
n
t
Write P4.7
Ext. Memory
Data Output
1
MUX
e
r
n
a
l
Port Output
Latch
0
MUX
P4.7
0
Output
Buffer
1
Read P4.7
1
MUX
B
u
s
Clock
0
Input
Latch
CAN2_TxD
Data Output
XPERCON.1
(CAN2EN
&
XMISC.1
(CANPAR)
1. When SALSEL=’10’, that is 8-bit segment address lines are selected, P4.7 is dedicated to output the
address; any attempt to use the CAN2 on P4.7 is masked.
When CAN parallel mode is selected, CAN2_TxD is remapped on P4.6: this occurs only if CAN1 is also
enabled. If CAN1 is disabled, no remapping occurs.
13.8
PORT7
PORT7 is a 4-bit bidirectional I/O port. This port is connected to pins 47-50 only if bit P7EN
of the XMISC register is set (see Section 18.3 for XMISC description). If it is used for
general purpose I/O, the direction of each line can be configured using the corresponding
direction register DP7. Each port line can be switched into push/pull or open drain mode by
the open drain control register ODP7.
119/328
Parallel ports
ST10F252M
PORT7 register
PORT7 register (FFD0/E8)
15 14 13 12
SFR
Reset value: --00h
11
10
9
8
7
-
6
-
5
-
4
-
3
2
1
0
Reserved
-
P7.3
RW
P7.2
RW
P7.1
RW
P7.0
RW
-
-
-
-
Table 74. PORT7 register functions
Bit
Name
Function
3.0
P7.y
Port data register P7 bit y
PORT7 direction register
PORT7 direction register (FFD2/E9)
SFR
Reset value: --00h
15
14
13
12
11
10
9
8
7
-
6
-
5
-
4
-
2
1
0
Reserved
-
DP7.3 DP7.2 DP7.1 DP7.0
-
-
-
-
RW
RW
RW
RW
Table 75. PORT7 direction register functions
Bit
Name
Function
Port direction register DP7 bit y
3.0
DP7.y
‘0’: Port line P7.y is an input (high-impedance)
‘1’: Port line P7.y is an output
PORT7 open ain control register
PORT7 n drain control register (F1D2/E9)
ESFR
Reset value: --00h
15
14
13
12
11
10
9
8
7
-
6
-
5
-
4
-
3
2
1
0
ODP7 ODP7 ODP7. ODP7.
.3
Reserved
-
.2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
Table 76. PORT7 open drain control register functions
Bit
Name
Function
Port 7 open drain control register bit y
3.0
ODP7.y
‘0’: Port line P7.y output driver in push/pull mode
‘1’: Port line P7.y output driver in open drain mode
13.8.1
Alternate functions of PORT7
The four lines of PORT7 (P7.3...P7.0) serve as outputs from the PWM module
(POUT3...POUT0). At these pins, the value of the respective port output latch is XORed with
the value of the PWM output rather than ANDed, as the other pins do. This permits the use
of the alternate output value either as it is (port latch holds a ‘0’) or invert its level at the pin
120/328
ST10F252M
Parallel ports
(port latch holds a ‘1’). The PWM outputs must be enabled via the respective PENx bits in
PWMCON1.
Table 77 summarizes the alternate functions of PORT7.
Table 77. PORT7 alternate functions
Pin
Name
Alternate function
P7.0
P7.1
P7.2
P7.3
POUT0 PWM0 channel 0 output
POUT1 PWM0 channel 1 output
POUT2 PWM0 channel 2 output
POUT3 PWM0 channel 3 output
Figure 43. PORT7 I/O and alternate functions
-
-
-
-
-
No Pins
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
POUT3
POUT2
POUT1
POUT0
P7.3
Port 7
P7.2
P7.1
General Purpose
Input/Output
PWM
The port structures of PORT7 differ in the way the output latches are connected to the
internal bus and to the pin driver (see Figure 44 and Figure 45).
Pins P7.3...P7.0 (POUT3...POUT0) XOR the alternate data output with the port latch output,
which permits thuse of the alternate data directly or inverted at the pin driver.
121/328
Parallel ports
Figure 44. Block diagram of PORT7 pins P7.3...P7.0
ST10F252M
Write 0DP7.y
Open Drain
Latch
Read 0DP7.y
Write DP7.y
Direction
Latch
Read DP7.y
Alternate
Data
Output
Write DP7.y
=1
Por
Outp
P7.y/POUTy
Port Output
Latch
Output
Buffer
EXOR
Read P7.y
Clock
1
MUX
Input
Latch
0
y = 3...0
13.9
PORT5
This 10-bit input port can only read data. There is no output latch and no direction register.
Data written to P5 is lost.
122/328
ST10F252M
Parallel ports
PORT5 register
PORT5 register (FFA2/D1)
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
P5.9
R
8
7
P5.7
R
6
P5.6
R
5
P5.5
R
4
P5.4
R
3
P5.3
R
2
P5.2
R
1
P5.1
R
0
P5.0
R
-
-
P5.8
R
Table 78. PORT5 register functions
Bit
Name
Function
Port data register P5 bit y (Read only)
9.0 P5.y
13.9.1
Alternate functions of PORT5
Each line of PORT5 is also connected to one of the multiplexers of the nalog to digital
converter (ADC). All port lines (P5.9...P5.0) can accept analog signa(AN9...AN0) that can
be converted by the ADC. No special programming is required or pins that shall be used as
analog inputs.
Table 79 summarizes the alternate functions of PORT5.
Table 79. PORT5 alternate functions
Port 5 Pin
lternate function
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.
P5.8
P5.9
Analog Input AN0
Analog Input AN1
Analog Input AN2
Analog Input AN3
Analog Input AN4
Anag Input AN5
Aalog Input AN6
Analog Input AN7
Analog Input AN8
Analog Input AN9
Figure 45. PORT5 I/O and alternate functions
Alternate Function
No Pins
P5.9
P5.8
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port 5
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
General Purpose
Input
A/D Converter
Input
123/328
Parallel ports
ST10F252M
PORT5 pins have a special port structure (see Figure 46), first because it is an input only
port, and second because the analog input channels are directly connected to the pins
rather than to the input latches.
13.9.2
Disturb protection on analog inputs
A register is provided for additional disturb protection support on analog inputs for PORT5.
PORT5 digital disable register
PORT5 disturb protection register (FFA4/D2)
SFR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 80. PORT5 digital disable register functions
Bit Name Function
PORT5 digital disable registr bit y
‘0’: Port line P5.y digital put is enabled (Schmitt trigger enabled)
15-0 P5DIDIS.y
‘1’: Port line P5.y digital input is disabled (Schmitt trigger disabled,
necessary fonpleakage current reduction)
Note:
This feature is currently not supported by the emulator.
Figure 46. Block diagram of a PORT5 pin
Channel
Select
Analog
Switch
to Sample + Hold
Circuit
P5.y/ANy
Read Port P5.y
Clock
P5DIDIS.y
Input
Latch
Read
Buffer
y = 15...0
124/328
ST10F252M
Analog / digital converter
14
Analog / digital converter
The ST10F252M provides an analog to digital converter (ADC) with 10-bit resolution and a
sample and hold circuit on-chip. A multiplexer selects between up to 10+6 analog input
channels (alternate functions of PORT5 and PORT0) either via software (fixed channel
modes) or automatically (auto scan modes works automatically among the 10 channels on
PORT5, or among the 8 channels on PORT0). An automatic self-calibration adjusts the
ADC module to process parameter variations at each reset event.
The accuracy is guaranteed with a total unadjusted error of + 2LSB on PORT5 and + 5 LSB
on PORT0 (+ 7 LSB when overload condition is applied). Refer to Section 27.7 for detailed
characteristics. The sample time (for loading the capacitors) and the conversion time is
programmable and can be adjusted by external circuitry.
To fulfill most requirements of embedded control applications, the ADC supports the
following conversion modes:
●
●
●
●
●
●
fixed channel single conversion
produces just one result from the selected channel
fixed channel continuous conversion
repeatedly converts the selected channel
auto scan single conversion
produces one result from each of a selected group of channels
auto scan continuous conversion
repeatedly converts the selected ouof channels
wait for ADDAT read mode
start a conversion automatically when the previous result is read
channel injection mode
insert the conversion of a specific channel into a group conversion (auto scan).
A set of SFRs and port pins provide access to control functions and results of the ADC.
125/328
Analog / digital converter
ST10F252M
Figure 47. SFRs, XBUS registers and port pins associated with the A/D converter
Ports & Direction Control Alternate Functions
Data Registers
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P5
-
-
-
-
-
-
-
-
-
-
-
-
Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y
ADDAT
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y
P5DIDIS
ADDAT2 E
AN0/P5.0... AN9/P5.9
Interrupt Control
15 14 13 12 11 10 9
8
-
7
Y
Y
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
15 14 13 12 11 10 9
8
-
7 6 5 4 3 2 1 0
DP0L
P0L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADCIC
ADEIC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y
-
-
-
-
-
-
-
-
-
-
-
-
Y Y Y Y Y
Y Y Y Y Y
DP0H
P0H
-
-
-
-
P5
Port5 Data Register
AN10/P0L.7... AN15/P0H.4
P5DIDIS Port5 Analog Inputs Disturb Protection Reter
DP0L
P0L
Port0L Direction Register
Port0L Data Register
Control Registers
DP0H
P0H
ADDAT
Port0H Direction Register
Port0H Data Regist
A/D Converter Reslt Register
15 14 13 12 11 10 9
8
7
6
-
5 4 3 2 1 0
ADCON
XMISC
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y Y Y
Y Y Y Y Y Y
ADDAT2 A/D ConverChannel Injection Result Register
ADCON
XMISC
ADCIC
A/D Converer Control Register
Misneous Register (XBUS)
A/D Converter Interrupt Control Register
(End of Conversion)
A/D Converter Interrupt Control Register
(Overrun Error / Channel Injection)
-
-
-
-
- - Y Y Y Y
Y
-
:
:
:
Bit is linked to a function
Bit has no function or is not implemented
Register is in ESFR internal memory space
IC
E
The external analog reference voltages V
and V
are fixed.
AREF
AGND
The sample time as well as the conversion time, is programmable, so that the ADC can be
adjusted to the internal resistances of the analog sources and/or the analog reference
voltage supply.
Figure 48. Analog to digital converter block diagram
ADCON
ADCIR
Conversion
Control
Interrupt
Requests
ADEIR
AN10-15
P0L.7-P0H.0,4
Result Reg. ADDAT
Result Reg. ADDAT2
10-Bit
Converter
MUX
16-1
S + H
AN9
P5.9
:
:
10
V
V
AGND
AREF
Analog
Input
Channels
:
:
AN0
P5.0
126/328
ST10F252M
Analog / digital converter
14.1
Mode selection and operation
The analog input channels AN0 to AN9 are alternate functions of PORT5 which is a 10-bit
input-only port. The PORT5 lines may either be used as analog or digital inputs. No special
action is required to configure the PORT5 lines as analog inputs. The additional register
P5DIDIS can be used to further protect the ADC input analog section by disabling the digital
input section. Refer to Section 13.9.2 for details on register P5DIDIS.
The functions of the A/D converter are controlled by the bit-addressable A/D Converter
Control Register ADCON.
Its bit fields specify the analog channel to be acted upon, the conversion mode, and also
reflect the status of the converter.
ADCON (FFA0h / D0h)
SFR
Reset Value: 0000h
15 14 13
12
11
10
9
8
7
6
5
4
3
2
1
0
AD
AD
AD
AD
AD
OFF
ADCTC
RW
ADSTC
RW
ADST
RW
ADM
RW
ADCH
RW
CRQ CIN WR BSY
RW RW RW
R
RW
Table 81. ADCON functions
Bit
Name
Fuction
15:14
13:12
11
ADCTC
ADSTC
ADCRQ
ADCIN
ADWR
ADC Conversion Time Control (1)
ADC Sample Time Control (1)
ADC Channection Request Flag
ADC Channel Injection Enable
ADC Wait for Read Control
10
9
ADC Busy Flag
‘1’: a conversion or calibration is active
8
7
ADBSY
ADST
ADC Start bit
ADC Disable
‘0’: Analog circuitry of A/D converter is on: it can be used properly
‘1’: Analog circuitry of A/D converter is turned off (no consumption): non
conversion possible
6
ADOFF
ADC Mode Selection
’0 0’: Fixed Channel Single Conversion
’0 1’: Fixed Channel Continuous Conversion
’1 0’: Auto Scan Single Conversion
5
ADM
’1 1’: Auto Scan Continuous Conversion
4:0
ADCH
ADC Analog Channel Input Selection
1. ADSTC and ADCTC control the conversion timing. Refer to Section 14.2 on page 134.
Bit field ADCH specifies the analog input channel which is to be converted (first channel of a
conversion sequence in auto scan modes). Bit field ADM selects the operating mode of the
ADC. A conversion (or a sequence) is started by setting bit ADST. Clearing ADST stops the
ADC after a specified operation which depends on the selected operating mode.
The busy flag (read-only) ADBSY is set, as long as a conversion is in progress. After reset,
this bit is set because the self-calibration is ongoing (duration of self-calibration depends on
127/328
Analog / digital converter
ST10F252M
CPU clock: it takes up to 40.629 1 clock pulses). The user software can poll this bit to
determine when the first conversion can be launched.
The result of a conversion is stored in the result register ADDAT, or in ADDAT2 for an
injected conversion.
Note:
Bit field CHNR of register ADDAT is loaded by the ADC to indicate, which channel the result
refers to. Bit field CHNR of register ADDAT2 is loaded by the CPU to select the analog
channel, which is to be injected.
ADDAT register
ADDAT register (FEA0/50)
SFR
Reset value: 0000h
15
14
CHNR
RW
13
12
11
10
-
9
8
7
6
5
4
3
2
1
0
-
ADRES
RW
-
-
ADDAT2 register
ADDAT2 register (F9A0/50)
SFR
Reset value: 0000h
15
14
13
12
11
10
-
9
8
7
6
5
4
3
2
1
0
CHNR
RW
-
ADRES
RW
-
-
Table 82. ADDAT and ADDAT2 regsters functions
Bit
Name
Function
15.12 CHNR
Channel number (4-bit, identifies the converted analog channel)
Analog to digital conversion result (10-bit)
9.0 ADRES
A conversion started by setting bit ADST to ‘1’. The busy flag ADBSY is set and the
converr selects and samples the input channel, which is specified by the channel selection
field ADCH in register ADCON. The sampled level is held internally during the conversion.
When the conversion of this channel is complete, the 10-bit result together with the number
of the converted channel is transferred into the result register ADDAT and the interrupt
request flag ADCIR is set. Field ADCH represents the channel of PORT5 (0h = channel 0,
1h = channel 1, ... , 9h = channel 9).
If bit ADST is reset via software while a conversion is in progress, the ADC stops after the
current conversion (fixed channel modes) or after the current conversion sequence (auto
scan modes).
Setting bit ADST, while a conversion is running, aborts this conversion and starts a new
conversion with the parameters specified in ADCON.
Note:
Abortion and restart (see above) are triggered by bit ADST changing from ‘0’ to ‘1’, that is,
ADST must be ‘0’ before being set.
While a conversion is in progress, the mode selection field ADM and the channel selection
field ADCH may be changed. ADM is evaluated after the current conversion. ADCH is
evaluated after the current conversion (fixed channel modes) or after the current conversion
sequence (auto scan modes).
128/328
ST10F252M
Analog / digital converter
14.1.1
Fixed channel conversion modes
These modes are selected by programming the mode selection field ADM in register
ADCON to ‘00’ (single conversion) or to ‘01’ (continuous conversion). After starting the
converter through bit ADST, the busy flag ADBSY is set and the channel specified in bit field
ADCH is converted. After the conversion is complete, the interrupt request flag ADCIR (bit 7
of ADCIC register; Section 14.3) is set.
●
In single conversion mode, the converter automatically stops and resets bits ADBSY
and ADST.
●
In continuous conversion mode, the converter automatically starts a new conversion of
the channel specified in ADCH. ADCIR is set after each completed conversion.
When bit ADST is reset by software while a conversion is in progress, the converter
completes the current conversion and then stops and resets bit ADBSY.
14.1.2
Auto scan conversion modes
These modes are selected by programming the mode selection field AM in register
ADCON to ‘10’ (single conversion) or to ‘11’ (continuous conversionAuto scan modes
automatically convert a sequence of analog channels, beginng with the channel specified
in bit field ADCH and ending with channel 0, without requiring software to change the
channel number. If the ADCH value is greater than 9h, the sequence starts converting the
nonexistent channel; this corresponds to an unpredictable result, since the input of ADC is
left floating.
After starting the converter through bit ADSthe busy flag ADBSY is set and the channel
specified in bit field ADCH is convertefter the conversion is complete, the interrupt
request flag ADCIR is set and the converter automatically starts a new conversion of the
next lower channel. ADCIR set after each completed conversion. After conversion of
channel 0 the current sequence is complete.
●
In single conversion mode the converter automatically stops and resets bits ADBSY
and ADST.
●
In continus conversion mode the converter automatically starts a new sequence
beinning with the conversion of the channel specified in ADCH.
When bit ADST is reset by software while a conversion is in progress, the converter
completes the current sequence (including conversion of channel 0) and then stops and
resets bit ADBSY.
129/328
Analog / digital converter
ST10F252M
Figure 49. Auto scan conversion mode example
#3
#2
Conversion
of Channel:
#1
#0
#3
#2
#2
#1
#0
#3
#x
#3
Write ADDAT
ADDAT Full
Generate Interrupt
Request
ADDAT Full;
Channel 0
Result Lost
Read of ADDAT;
Result of Channel:
#x
#3
#2
#1
#3
Overrun Error Interrupt Request
14.1.3
Wait for ADDAT read mode
If, in the default mode of the ADC, a previous conversion result has not been read out of
register ADDAT by the time a new conversion is comlete, the previous result in register
ADDAT is lost because it is overwritten by the nevalue and the analog to digital overrun
error interrupt request flag ADEIR (bit 7 of ADEIC register; see Section 14.3) is set.
To avoid error interrupts and the loss onversion results, especially when using
continuous conversion modes, the ADC can be switched to “Wait for ADDAT read mode” by
setting bit ADWR in register ADCON.
If the value in ADDAT has not been read by the time the current conversion is complete, the
new result is stored in a temporary buffer and the next conversion is suspended (ADST and
ADBSY remain st in the meantime but no end-of-conversion interrupt is generated). After
reading the pvious value from ADDAT, the temporary buffer is copied into ADDAT
(generng an ADCIR interrupt) and the suspended conversion is started. This mechanism
applies to both single and continuous conversion modes.
Note:
While in standard mode, continuous conversions are executed at a fixed rate (determined by
the conversion time), in “Wait for ADDAT read mode” there may be delays due to suspended
conversions. However, this only affects the conversions, if the CPU (or PEC) cannot keep
track with the conversion rate.
130/328
ST10F252M
Analog / digital converter
Figure 50. Wait for read mode example
Conversion
of Channel:
#2
#3
#1
#0
#3
Wait
Write ADDAT
ADDAT Full
#x
#3
#2
#1
#0
#3
Temp-Latch Full
#1
Hold Result in
Temp-Latch
Generate Interrupt
Request
Read of ADDAT;
Result of Channel:
#x
#3
#2
#1
#0
14.1.4
Channel injection mode
Channel injection mode allows the conversion of a specific analog channel (also while the
ADC is running in a continuous or auto scan mode) without changing the current operating
mode. After the conversion of this specific channel, the ADC continues with the original
operating mode.
Channel injection mode is enabled by ttinbit ADCIN in register ADCON and requires the
Wait for ADDAT read mode (ADWR=‘1The channel to be converted in this mode is
specified in bit field CHNR of register ADDAT2.
Note:
These four bits in ADDAT2 are not modified by the ADC, but only the ADRES bit field. Since
the channel number for an injected conversion is not buffered, bitfield CHNR of ADDAT2 is
never modified during the sample phase of an injected conversion, otherwise the input
multiplexer switces to the new channel. It is recommended to only change the channel
number with injected conversion running.
Figure 51. Channel injection example
Conveion
of Channel:
#x-1
#x
#x-2
#x-3
#x-4
#...
#x-2
Write ADDAT
ADDAT Full
#x+1
#x
#x-1
#x-3
#x-4
#x+1
#x
#x-1
#x-2
#x-3
#x-4
Read ADDAT
#y
Channel Injection
Request by CC31
Injected Conversion
of Channel #y
Write ADDAT2
ADDAT2 Full
Interrupt Request
ADEINT
Read ADDAT2
131/328
Analog / digital converter
ST10F252M
A channel injection can be triggered by set the channel injection request bit ADCRQ via
software.
Note:
While an injected conversion is in progress, no further channel injection request can be
triggered. The channel injection request flag ADCRQ remains set until the result of the
injected conversion is written to the ADDAT2 register.
If the converter was idle before the channel injection, and during the injected conversion the
converter is started by software for normal conversions, the channel injection is aborted,
and the converter starts in the selected mode (as described above). This can be avoided by
checking the busy bit ADBSY before starting a new operation.
After completing the current conversion (if any is in progress), the converter starts (injects)
the conversion of the specified channel. When the conversion of this channel is complete,
the result is placed into the alternate result register ADDAT2, and a channel injection
complete interrupt request is generated, which uses the interrupt request flag ADEIR (for
this reason the Wait for ADDAT read mode is required).
Note:
If the temporary data register used in Wait for ADDAT read mode is full, the respective next
conversion (standard or injected) is suspended. The temporary registean hold data for
ADDAT (from a standard conversion) or for ADDAT2 (from an injecteconversion).
132/328
ST10F252M
Analog / digital converter
Figure 52. Channel injection example with wait for read
#x-1
#x
#x-2
#x-3
#...
Conversion
of Channel:
Wait until
ADDAT2 is
read
Write ADDAT
ADDAT Full
#x+1
#x
#x-1
#x-2
#x-3
#x+1
#x
#x-1
#x-2
#x-3
Read ADDAT
#y
Channel Injection
Request by CC31
Injected Conversion
of Channel #y
Write ADDAT2
#y
#z
ADDAT2 Full
Interrupt
Request
ADEINT
#z
#y
Read ADDAT2
Temp-Latch Full
Conversion
of Channel:
#x-1
#x
#x-2
#x-3
#...
Write ADDAT
ADDAT Full
#x+1
#x
#x-1
#x-2
#x-3
#x+1
#x
#x-1
#y
#x-2
#x-3
Read ADDAT
Temp-Latch Full
Channel Injection
Request by CC31
Write ADDAT2
Wait until ADDAT2
is read
ADDAT2 Full
Interrupt Request
ADEINT
#y
Read ADDAT2
14.1.5
ADC power down (ADOFF)
Setting bit ADOFF in ADCON register, turns off the ADC and zeroes the static power
consumption related with ADC analog circuitry. If this bit is set during a conversion, the
command is ignored (even though the ADOFF bit is immediately set); only at the end of the
conversion (or sequence of conversions if SCAN mode was selected), is the ADC switched
off (as soon as the ADBSY bit is cleared).
When ADC is off (ADOFF bit set), setting bit ADST automatically wakes up the ADC and a
conversion starts; the accuracy is unfortunately not yet granted, since the analog circuitry
133/328
Analog / digital converter
ST10F252M
needs at least 50 µs to complete the power-up transient phase. Clear the ADOFF bit first,
and start the first conversion only after 50 µs.
Note:
If bit ADOFF is set and when ADST is also set, at the end of the conversion (or cycle of
conversions if SCAN mode is selected), the ADC is switched off (as soon as ADBSY is
cleared).
Turning off ADC consumption (setting bit ADOFF) should be done once the calibration is
completed (starts after every reset occurrence); if not, the calibration is stopped by setting
bit ADOFF and not restarted/completed when bit ADOFF is cleared again.
14.2
Conversion timing control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value in several successive steps, which correspond to the 10-bit resolution of the
ADC. During these steps the internal capacitances are repeatedly chard and discharged
via the V
pin.
AREF
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deer, depends on its internal resistance.
The time that the two different actions duriconversion take (sampling, and converting)
can be programmed within a certain re in the ST10F252M with respect to the CPU
clock. The absolute time that is consumed by the different conversion steps is independent
of the general speed of the controller. This allows the ADC of the ST10F252M to be
adjusted to the properties of the system.
●
Fast conversion can be achieved by programming the respective times to their
absolute possible minimum. This is preferable for scanning high frequency signals.
However, the internal resistance of analog source and analog supply must be
sufciently low.
●
High internal resistance can be achieved by programming the respective times to a
higher value, or the possible maximum. This is preferable when using analog sources
and supply with a high internal resistance to keep the current as low as possible. The
conversion rate in this case may be considerably lower.
The ADC input bandwidth is limited by the achievable accuracy. For example, supposing a
maximum error of 0.5LSB (2 mV) impacting the global TUE (TUE also depends on other
causes), in the worst case of temperature and process, the maximum frequency for a sine
wave analog signal is around 7.5 kHz. To reduce the effect of the input signal variation on
the accuracy down to 0.05LSB, the maximum input frequency of the sine wave is reduced to
800 Hz.
If a static signal is applied during the sampling phase, the series resistance is not greater
than 20 kΩ (this takes into account any possible input leakage). Do not connect any
capacitance on analog input pins to reduce the effect of charge partitioning (and consequent
voltage drop error) between the external and the internal capacitance. If an RC filter is
necessary, the external capacitance must be greater than 10 nF to minimize the accuracy
impact.
134/328
ST10F252M
Analog / digital converter
The conversion times are programmed via the upper four bits of register ADCON. Bit fields
ADCTC and ADSTC are used to define the basic conversion time and, in particular, the
partition between sample phase and comparison phases. The table below lists the possible
combinations. The timings refer to the unit TCL, where f
= 1/2TCL.
CPU
Table 83. ADC programming
ADCTC ADSTC
Sample
Comparison
Extra
Total conversion
00
00
00
00
11
11
11
11
10
10
10
10
00
01
10
11
00
01
10
11
00
01
10
11
TCL * 120
TCL * 140
TCL * 200
TCL * 400
TCL * 240
TCL * 280
TCL * 400
TCL * 800
TCL * 480
TCL * 560
TCL * 800
TCL * 1600
TCL * 240
TCL * 280
TCL * 280
TCL * 280
TCL * 480
TCL * 560
TCL * 560
TCL * 560
TCL * 960
TCL * 1120
TCL * 1120
TCL * 1120
TCL * 28
TCL * 16
TCL * 52
TCL * 44
TCL * 52
TCL * 28
TCL * 388
TCL * 436
TCL * 532
TCL * 724
TCL * 772
TCL * 868
TCL * 1060
TCL * 1444
TCL * 1540
TCL * 1732
TCL * 2116
TCL * 2884
TCL * 100
TCL * 52
TC* 100
TCL * 52
TCL * 196
TCL * 164
The complete conversion time includee conversion itself, the sample time and the time
required to transfer the digital value to the result register.
Note:
The total conversion time is compatible with the formula valid for ST10F269, while the
meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum
conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4.85 μs (see
ST10F269).
14.3
ADC interrupt control
At the end of each conversion, the interrupt request flag ADCIR in the interrupt control
register ADCIC is set. This end-of-conversion interrupt request may cause an interrupt to
vector ADCINT or it may trigger a PEC data transfer which reads the conversion result from
register ADDAT, for example, to store it in a table in the internal RAM for later evaluation.
The interrupt request flag ADEIR in the register ADEIC is set if either a conversion result
overwrites a previous value in register ADDAT (error interrupt in standard mode) or if the
result of an injected conversion has been stored in ADDAT2 (end-of-injected-conversion
interrupt). This interrupt request may be used to cause an interrupt to vector ADEINT or it
may trigger a PEC data transfer.
135/328
Analog / digital converter
ST10F252M
ADC interrupt control
ADCIC register (FF98/CC)
15 14 13 12
SFR
Reset value: --00h
11
10
9
8
7
6
5
4
3
2
1
0
ADC ADC
-
-
ILVL
RW
GLVL
RW
IR
IE
RW
RW
ADEIC register (FF9A/CD)
15 14 13 12
SFR
Reset value: --00h
11
10
9
8
7
6
5
4
3
2
1
0
ADE
IR
ADE
IE
-
-
ILVL
RW
GLVL
RW
RW
RW
Note:
Refer to the general interrupt control register description (Section 9.1.2) for an explanation
of the control fields.
14.4
Calibration
A full calibration sequence is performed after a reset. Thifull calibration lasts 40.629
1
CPU clock cycles. During this time, the busy flag ADSY is set to indicate the operation. It
compensates for any capacitance mismatch, so e calibration procedure does not need
any update during normal operation.
No conversion can be performed durihis time. The bit ADBSY can be polled to verify
when the calibration is over, and the module is able to start a conversion.
Since the calibration process writes repeatedly spurious conversion results to the ADDAT
register, at the end of the calibration, both ADCIR and ADEIR flags are set. For this reason,
before starting a conversion, the ADC initialization routine performs a dummy read of
ADDAT register and clears the two flags.
Note:
If ADDAT is nread before starting the first conversion and, for example, “wait for read
mode” entered (ADWR bit set), the ADC is stack waiting for the ADDAT read, since the
result of the current conversion cannot be immediately written to ADDAT, which contains the
results of the calibration (meaningless data).
136/328
ST10F252M
Programmable output clock divider
15
Programmable output clock divider
15.1
Functionality
A specific register mapped on the XBUS allows to choose the division factor on the
CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address
range.
XCLKOUTDIV (EB02h)
XBUS
8
Reset Value: - - 00h
15
14
13
12
11
-
10
-
9
-
7
6
5
4
3
2
1
0
-
-
-
-
-
DIV
RW
Table 84. CLKOUTDIV functions
Bit
Name
Function
Clock Divider setting
‘00h’: fCLKOUT = fCPU
‘01h’: fCLKOUT = fCPU / 2
‘02h’: fCLKOUT = fCPU / 3
‘03h’: fCLKOUT = fCPU / 4
7:0
DIV
:
‘FFh’: fCLKOfCPU / 256
When the CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default
the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN
of register SYSCON programs the clock prescaling factor. In this way, a prescaled value of
the CPU clock is output on P3.15.
When the CLOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15
does noutput any clock signal, even though the XCLKOUTDIV register is programmed.
137/328
Serial channels
ST10F252M
16
Serial channels
Serial communication with other microcontrollers, microprocessors, terminals or external
peripheral components is provided by up to four serial interfaces: two asynchronous /
synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial
channel (SSC0 and SSC1). Dedicated baudrate generators set up all standard baudrates
without the requirement of oscillator tuning. For transmission, reception and erroneous
reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A
more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and
SSC1 (XBUS mapped).
16.1
16.2
Asynchronous / synchronous serial interfaces
The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial
communication between the ST10F252M and other microcontrollers, mcroprocessors or
external peripherals.
ASCx in asynchronous mode
In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop
bits can be selected. Parity framing and overrun error detection is provided to increase the
reliability of data transfers. Transmission areception of data is double-buffered. Full-
duplex communication up to 1.25 Mba(at 40 MHz of f
) is supported in this mode.
CPU
Table 85. ASC asynchronous baudrates by reload value and deviation errors (f
= 40 MHz)
CPU
S0BRS = ‘0’, fCPU = 40 MHz
S0BRS = ‘1’, fCPU = 40 MHz
Reload value
Reload value
(hex)
Baudrate (baud) Deviation rror
Baudrate (baud) Deviation error
(hex)
1 250 000
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
600
0.0% / 0.0%
+1.5% / -7.0%
+1.5% / -3.0%
+1.7% / -1.4%
+0.2% / -1.4%
+0.2% / -0.6%
+0.2% / -0.2%
+0.2% / 0.0%
0.1% / 0.0%
0000 / 0000
000A / 000B
0015 / 0016
001F / 0020
0040 / 0041
0081 / 0082
0103 / 0104
0207 / 0208
0410 / 0411
0822 / 0823
1045 / 1046
1FE8 / 1FE9
833 333
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
600
0.0% / 0.0%
+6.3% / -7.0%
+6.3% / -0.8%
+3.3% / -1.4%
+0.9% / -1.4%
+0.9% / -0.2%
+0.4% / -0.2%
+0.1% / -0.2%
+0.1% / -0.1%
+0.1% / 0.0%
0.0% / 0.0%
0000 / 0000
0006 / 0007
000D / 000E
0014 / 0015
002A / 002B
0055 / 0056
00AC / 00AD
015A / 015B
02B5 / 02B6
056B / 056C
0AD8 / 0AD9
1FE8 / 1FE9
0.0% / 0.0%
300
0.0% / 0.0%
300
153
0.0% / 0.0%
102
0.0% / 0.0%
Note:
The deviation errors given in the Table 85 are rounded off. To avoid deviation errors use a
baudrate crystal (providing a multiple of the ASC0 sampling frequency).
138/328
ST10F252M
Serial channels
16.3
ASCx in synchronous mode
In synchronous mode, data is transmitted or received synchronously to a shift clock which is
generated by the ST10F252M. Half-duplex communication up to 5 Mbaud (at 40 MHz of
f
) is possible in this mode.
CPU
Table 86. ASC synchronous baudrates by reload value and deviation errors (f
= 40 MHz)
CPU
S0BRS = ‘0’, fCPU = 40 MHz
S0BRS = ‘1’, fCPU = 40 MHz
Reload value
Reload value
(hex)
Baudrate (baud) Deviation error
Baudrate (baud) Deviation error
(hex)
5 000 000
112 000
56 000
38 400
19 200
9 600
0.0% / 0.0%
+1.5% / -0.8%
+0.3% / -0.8%
+0.2% / -0.6%
+0.2% / -0.2%
+0.2% / 0.0%
+0.1% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0000 / 0000
002B / 002C
0058 / 0059
0081 / 0082
0103 / 0104
0207 / 0208
0410 / 0411
0822 / 0823
1045 / 1046
15B2 / 15B3
1FE8 / 1FE9
3 333 333
112 000
56 000
38 400
19 200
9 600
0.0% / 0.0%
+2.6% / -0.8%
+0.9% / -0.8%
+0.9% / -0.2%
+0.4% / -2%
+0% / -0.2%
+0.1% / -0.1%
+0.1% / 0.0%
0.0% / 0.0%
0000 / 0000
001C / 001D
003A / 003B
0055 / 0056
00AC / 00AD
015A / 015B
02B5 / 02B6
056B / 056C
0AD8 / 0AD9
15B2 / 15B3
1FFD / 1FFE
4 800
4 800
2 400
2 400
1 200
1 200
900
600
0.0% / 0.0%
612
407
0.0% / 0.0%
Note:
The deviation errors given in the Table 86 are rounded off. To avoid deviation errors use a
baudrate crystal (providing a multiple of the ASC0 sampling frequency).
16.4
High sped synchronous serial interfaces
The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible high-
speed serial communication between the ST10F252M and other microcontrollers,
microprocessors or external peripherals.
The SSCx supports full-duplex and half-duplex synchronous communication. The serial
clock signal can be generated by the SSCx itself (master mode) or be received from an
external master (slave mode). Data width, shift direction, clock polarity and phase are
programmable.
This allows communication with SPI-compatible devices. Transmission and reception of data
is double-buffered. A 16-bit baudrate generator provides the SSCx with a separate serial
clock signal. The serial channel SSCx has its own dedicated 16-bit baudrate generator with
16-bit reload capability, allowing baudrate generation independent from the timers.
Table 87 lists some possible baudrates against the required reload values and the resulting
bit times for the 40 MHz CPU clock. The maximum is limited to 8 Mbaud.
139/328
Serial channels
ST10F252M
Table 87. Synchronous baudrate and reload values (f
= 40 MHz)
CPU
Baudrate
Bit time
Reload value
Reserved
-
0000h
0001h
0002h
0003h
0007h
0013h
00C7h
07CFh
4E1Fh
FF4Eh
Can be used only with fCPU = 32 MHz (or lower)
-
6.6 Mbaud
5 Mbaud
150ns
200ns
400ns
1µs
2.5 Mbaud
1 Mbaud
100 Kbaud
10 Kbaud
1 Kbaud
10µs
100µs
1ms
306 baud
3.26ms
140/328
ST10F252M
I2C interface
2
17
I C interface
2
The integrated I C Bus Module handles the transmission and reception of frames over the
2
2
two-line SDA/SCL in accordance with the I C Bus specification. The I C Module can
operate in slave mode, in master mode or in multi-master mode. It can receive and transmit
data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s
2
(both Standard and Fast I C bus modes are supported).
The module can generate three different types of interrupt:
●
●
●
requests related to bus events, such as start or stop events, or arbitration lost
requests related to data transmission
requests related to data reception
These requests are issued to the interrupt controller by three different lines, and identified as
Error, Transmit, and Receive interrupt lines.
2
When the I C module is enabled by setting bit XI2CEN in XPERCON rester, pins P4.4 and
P4.7 (where SCL and SDA are respectively mapped as alternate fuions) are
automatically configured as bidirectional open-drain: the valuof the external pull-up
resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin
configuration.
2
When the I C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O
controlled by P4, DP4 and ODP4.
2
The speed of the I C interface can be ected between Standard mode (0 to 100 kHz) and
2
Fast I C mode (100 to 400 kHz).
141/328
CAN modules
ST10F252M
18
CAN modules
The two integrated CAN modules (CAN1 and CAN2) are identical and handle the
completely autonomous transmission and reception of CAN frames in accordance with the
CAN specification V2.0 part A and B (active).
These two CAN modules are different with respect to the ones implemented on ST10F269.
The new module is based on C-CAN module characteristics. The following system
resources are used to interface the module with the ST10 core:
●
●
●
Interrupt of CAN1 and CAN2 are connected to the XBUS interrupt lines: refer to
Section 18.2 for details.
Both CAN modules have to be selected, before the bit XPEN is set in SYSCON
register, by setting the proper bit in XPERCON register.
After reset, CAN1 is enabled by default (see the reset value of the XPERCON register).
The CAN2 is not enabled.
This peripheral uses the new clock gating feature.
Note:
When the clock is gated, no reset is raised once the EINIT inuction has been executed.
18.1
Memory and pin mapping
18.1.1
CAN1 mapping
Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 module access. The CAN1 is
enabled by setting bit XPEN of the SYSCON register and bit 0 of XPERCON register.
Accesses to the CAN module use demultiplexed addresses and a 16-bit data bus (only word
accesses are possible). Two wait states give an access time of 83.34 ns at 40 MHz CPU
clock. No tristate wait state is used.
After reset, CN1 is enabled by default (see the reset value of the XPERCON register). It is
availabon pins P4.5 and P4.6.
18.1.2
CAN2 mapping
Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 module access. The CAN2 is
enabled by setting bit XPEN of the SYSCON register and bit 1 of the XPERCON register.
Accesses to the CAN module use demultiplexed addresses and a 16-bit data bus (only word
accesses are possible). Two wait states give an access time of 83.34 ns at40 MHz CPU
clock. No tristate wait state is used.
After reset, CAN2 is disabled by default (see the reset value of the XPERCON register).
Once enabled, it is available on pins P4.4 and P4.7.
Note:
If one or both CAN modules are used, PORT4 cannot be programmed to output all 8
segment address lines. Thus, only 4 segment address lines can be used, reducing the
external memory space to 1 Mbyte.
142/328
ST10F252M
CAN modules
18.1.3
Register summary
Table 88 and Table 89 summarize the CAN modules register mapping
Table 88. CAN1 register mapping
Address
Description
Reset
00 EF00
00 EF02
00 EF04
00 EF06
00 EF08
00 EF0A
00 EF0C
00 EF10
00 EF12
00 EF14
00 EF16
00 EF18
00 EF1A
00 EF1C
00 EF1E
00 EF20
00 EF22
00 EF24
00 EF40
00 EF42
00 EF44
00 EF46
00 EF48
00 EF4A
00 EF4C
00 EF4E
00 EF50
00 EF52
00 EF54
00 EF80
00 EF82
00 EF90
CAN1: CAN Control Register
CAN1: Status Register
CAN1: Error Counter
0001
0000
0000
2301
0000
00x0
0000
0001
0000
FFFF
FFFF
0000
0000
0000
0000
0000
0000
0000
0001
0000
FFFF
FFFF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
CAN1: Bit Timing Register
CAN1: Interrupt Register
CAN1: Test Register
CAN1: BRP Extension Register
CAN1: IF1 Command Request
CAN1: IF1 Command Mask
CAN1: IF1 Mask 1
CAN1: IF1 Mask 2
CAN1: IF1 Arbitration 1
CAN1: IF1 Arbitration 2
CAN1: IF1 Message Cont
CAN1: IF1 Data A 1
CAN1: IF1 Data A 2
CAN1: IF1 Data B 1
CAN1: IF1 Data B 2
AN1: IF2 Command Request
CAN1: IF2 Command Mask
CAN1: IF2 Mask 1
CAN1: IF2 Mask 2
CAN1: IF2 Arbitration 1
CAN1: IF2 Arbitration 2
CAN1: IF2 Message Control
CAN1: IF2 Data A 1
CAN1: IF2 Data A 2
CAN1: IF2 Data B 1
CAN1: IF2 Data B 2
CAN1: Transmission Request 1
CAN1: Transmission Request 2
CAN1: New Data 1
143/328
CAN modules
Table 88. CAN1 register mapping (continued)
ST10F252M
Reset
Address
Description
00 EF92
00 EFA0
00 EFA2
00 EFB0
00 EFB2
CAN1: New Data 2
0000
0000
0000
0000
0000
CAN1: Interrupt Pending 1
CAN1: Interrupt Pending 2
CAN1: Message Valid 1
CAN1: Message Valid 2
Table 89. CAN2 register mapping
Address
Description
Reset
00 EE00
00 EE02
00 EE04
00 EE06
00 EE08
00 EE0A
00 EE0C
00 EE10
00 EE12
00 EE14
00 EE16
00 EE18
00 EE1A
00 EC
00 EE1E
00 EE20
00 EE22
00 EE24
00 EE40
00 EE42
00 EE44
00 EE46
00 EE48
00 EE4A
00 EE4C
00 EE4E
00 EE50
CAN2: CAN Control Register
CAN2: Status Register
CAN2: Error Counter
0001
0000
0000
2301
0000
00x0
0000
0001
0000
FFFF
FFFF
0000
0000
0000
0000
0000
0000
0000
0001
0000
FFFF
FFFF
0000
0000
0000
0000
0000
CAN2: Bit Timing Register
CAN2: Interrupt Register
CAN2: Test Register
CAN2: BRP Extension Register
CAN2: IF1 Command Request
CAN2: IF1 Command Mas
CAN2: IF1 Mask 1
CAN2: IF1 Mask 2
CAN2: IF1 Arbitration 1
C2: IF1 Arbitration 2
CAN2: IF1 Message Control
CAN2: IF1 Data A 1
CAN2: IF1 Data A 2
CAN2: IF1 Data B 1
CAN2: IF1 Data B 2
CAN2: IF2 Command Request
CAN2: IF2 Command Mask
CAN2: IF2 Mask 1
CAN2: IF2 Mask 2
CAN2: IF2 Arbitration 1
CAN2: IF2 Arbitration 2
CAN2: IF2 Message Control
CAN2: IF2 Data A 1
CAN2: IF2 Data A 2
144/328
ST10F252M
CAN modules
Reset
Table 89. CAN2 register mapping (continued)
Address
Description
00 EE52
00 EE54
00 EE80
00 EE82
00 EE90
00 EE92
00 EEA0
00 EEA2
00 EEB0
00 EEB2
CAN2: IF2 Data B 1
CAN2: IF2 Data B 2
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
CAN2: Transmission Request 1
CAN2: Transmission Request 2
CAN2: New Data 1
CAN2: New Data 2
CAN2: Interrupt Pending 1
CAN2: Interrupt Pending 2
CAN2: Message Valid 1
CAN2: Message Valid 2
18.2
Interrupt
Up to four interrupt control registers (XIRxSEL, x = 0, 1, 2, 3) are provided to select the
source of the XBUS interrupt. One line for each module is provided and linked differently to
one of the XPxIC registers (x = 0, 1, 2, 3). In particular, two interrupt lines are available on
the following interrupt vectors:
CAN1
XP0INT
XP3INT
•
•
CAN2
XP1INT
XP3INT
Refer to Section 9.2 for details.
When interruptibpower down mode is entered, both CAN1 and CAN2 lines can be used to
wake-up the vice from low power mode without resetting it, restarting the application from
where was stopped before the execution of PWRDN instruction.
Reer to Section 9.1.
18.3
Configuration support
It is possible that both CAN controllers are working on the same CAN bus, together
supporting up to 64 message objects. In this configuration, both receive signals and both
transmit signals are linked together when using the same CAN transceiver. This
configuration is supported by providing open drain outputs for the CAN1_TxD and
CAN2_TxD signals. The open drain function is controlled with the ODP4 register for PORT4.
In this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with
P4.7 (transmit lines configured to be configured as open-drain).
The user software can also internally map both CAN modules on the same pins P4.5 and
P4.6. In this way, P4.4 and P4.7 may be used as general purpose input and output lines.
This is possible by setting bit CANPAR of XMISC register. To access this register, set bit
XMISCEN of XPERCON register and bit XPEN of SYSCON register.
145/328
CAN modules
ST10F252M
Note:
CAN parallel mode is possible only if both CAN1 and CAN2 are enabled through the setting
of bits CAN1EN and CAN2EN in XPERCON register. If CAN1 is disabled, CAN2 remains on
P4.4/P4.7 even if bit CANPAR is set.
XMISC register
XMISC register (EB46h)
15 14 13
SFR
Reset value: 0000h
12
11
10
9
8
7
-
6
-
5
4
3
2
1
0
P34E
N
VREG CANC CANP
-
-
P7EN
RW
-
OFF
K2
AR
-
-
RW
RW
RW
RW
-
Table 90. XMISC register functions
Bit
Name
Function
Port pin P3.4 enable on Port pin P1H.0
5
P34EN
‘0’ pins 0 of Port1(P1H.0) is connected to externapin 89
‘1’ pins 4 of Port3 (P3.4) is connected external pin 89
Port 7[3:0] enable on Port4[3:0]
4
3
P7EN
‘0’ pins 3:0 of Port4 are connected to external pins 47-50
‘1’ pins 3:0 of Port7 are connected to external pins 47-50
Main Voltage Regulator disable in Power-Down mode
‘0’: On-chip in egulator is held active when Power-Down mode is
entered
VREGOFF
‘1’: On-chip Main Regulator is turned off when Power-Down mode is
entered
CAN Clock divider by 2 disable
‘0’: Clock provided to CAN modules is CPU clock divided by 2
(mandatory when fCPU is higher than 40MHz)
2
1
CANCK2
CANPAR
‘1’: Clock provided to CAN modules is directly CPU clock
CAN parallel mode selection
‘0’: CAN2 is mapped on P4.4/P4.7, while CAN1 is mapped on
P4.5/P4.6
‘1’: CAN1 and CAN2 are mapped in parallel on P4.5/P4.6. This is
effective only if both CAN1 and CAN2 are enabled through setting of
bits CAN1EN and CAN2EN in XPERCON register. If CAN1 is disabled,
CAN2 remains on P4.4/P4.7 even if bit CANPAR is set.
18.3.1
Configuration examples
Figure 53, Figure 54, Figure 55 and Figure 56 show different configuration examples, where
the two CAN controllers of the ST10F252M are working on the same CAN bus or on
different CAN busses.
Wired-OR connections to a CAN bus use open drain outputs as described above. A
wired-OR structure can be used for on-board data exchange between two or more controller
devices via one signal line. As no CAN transceiver is used in this case, the maximum wire
length is very limited (<< 1 m) and noise conditions must be considered.
146/328
ST10F252M
CAN modules
Finally, when only one bus is interfaced, the parallel mode for the two on-chip CAN modules
allows a doubling of the buffer capability and the saving two pins for other functionalities.
The receive lines are internally tied together, while the transmit lines from the two modules
are logically ANDed on the single pin. This assigns the active value to the pin as driven by
one of the two (for CAN protocol logic level ‘1’ is the inactive state, so the non-transmitting
CAN module, allows the other to drive the pin).
Figure 53. Connection to single CAN bus via separate CAN transceivers
XMISC.CANPAR = 0
CAN1
CAN2
RX
TX
RX
TX
P4.5
P4.6 P4.4
P4.7
CAN
Transceiver
CAN
Transceiver
CAN_H
CAN_L
CAN bus
Figure 54. Connection to single CAN bus vine common transceiver
XMISC.CANPAR = 0
CAN1
CAN2
RX
TX
RX
TX
+5V
P4.5
P4.6 P4.4
OD
P4.7
OD
2.7kΩ
CAN
Transceiver
CAN_H
CAN_L
CAN bus
OD = Open Drain Output
147/328
CAN modules
ST10F252M
Figure 55. Connection to two different CAN buses (for example, for gateway
application)
XMISC.CANPAR = 0
CAN1
CAN2
RX
TX
RX
TX
P4.5
P4.6 P4.4
P4.7
CAN
Transceiver
CAN
Transceiver
CAN_H
CAN_L
CAN_H
CAN_L
CAN bus 1
CAN bus 2
Figure 56. Connection to one CAN bus with internal parallel mode enabled
XMISC.CANPAR = 1
(Both CAN enabled)
CAN1
CAN2
RX
TX
RX
TX
P4.5
P4.6 P4.4
P4.7
CAN
Transceiver
CAN_H
CAN_L
CAN bus
18.4
Clock prescaling
In the register XMISC, there is also a bit (CANCK2) to modify the clock frequency driving
both the CAN modules. For architectural limitations of the CAN module, when the CPU
frequency is higher than 40 MHz, it is recommended to divide the CPU clock by two to each
CAN module. 20 MHz is sufficient for CAN module to produce the maximum baud rate
defined by the protocol standard. If, on the other hand, the CPU frequency can be reduced
to 8 MHz, thus providing the CAN module directly with the CPU clock and disabling the
prescaler factor, it is still possible to obtain the maximum CAN speed (1 Mbaud).
After reset, the prescaler is enabled so the CPU clock is divided by two and provided to the
CAN modules. According to the system clock frequency, the application can disable the
prescaler to obtain the required baud rate.
Refer to Section 18.3.1 for the description of the register XMISC.
148/328
ST10F252M
CAN modules
18.5
CAN module: functional overview
The C-CAN consists of the components (see Figure 57):
●
●
●
●
●
CAN core
message RAM
message handler
control registers
module interface.
The CAN core performs communication according to the CAN protocol version 2.0 parts A
and B. The bit rate can be programmed to values up to 1 MBit/s depending on the
technology used. For the connection to the physical layer, additional transceiver hardware is
required.
For communication on a CAN network, individual message objects are configured. The
message objects and identifier masks for acceptance filtering of received messages are
stored in the message RAM.
All functions concerning the handling of messages are implemented the message
handler. Those functions are the acceptance filtering, the traner of messages between the
CAN core and the message RAM, and the handling of transmission requests as well as the
generation of the module interrupt.
The register set of the C-CAN can be accessed drectly by an external CPU via the module
interface. These registers are used to control/configure the CAN core and the message
handler and to access the message RAM.
The module interfaces delivered with the C-CAN module can easily be replaced by a
customized module interface adapted to user requirements.
C-CAN implements the following features:
●
●
●
●
●
●
●
●
CAN protocol version 2.0 parts A and B
bit rates up 1 MBit/s
32 messge objects
each message object has its own identifier mask
programmable FIFO mode (concatenation of message objects)
maskable interrupt
disabled automatic retransmission mode for time triggered CAN applications
programmable loop-back mode for self-test operation.
149/328
CAN modules
ST10F252M
18.6
Block diagram
The design consists of the following functional blocks (see Figure 57):
●
CAN core
CAN protocol controller and Rx/Tx shift register for serial/parallel conversion of
messages.
●
●
●
Message RAM
Stores message objects and identifier masks.
Registers
All registers used to control and to configure the C-CAN module.
Message handler
State machine that controls the data transfer between the Rx/Tx shift register of the
CAN core and the message RAM as well as the generation of interrupts as
programmed in the control and configuration registers.
Figure 57. Block diagram of the C-CAN
CAN_TX CAN_RX
C-CAN
CAN Core
sage RAM
Registers
Module Interface
18.7
Operating modes
18.7.1
Software initialisation
Software initialization is started by setting the Init bit in the CAN control register, either by
software or by a hardware reset, or by going Bus_Off.
While Init is set, all message transfer from and to the CAN bus is stopped, the status of the
CAN bus output CAN_TX is recessive (HIGH). The counters of the EML are unchanged.
Setting Init does not change any configuration register.
150/328
ST10F252M
CAN modules
To initialize the CAN controller, the CPU has to set up the bit timing register and each
message object. If a message object is not needed, it is sufficient to set it’s MsgVal bit to not
valid. Otherwise, the whole message object has to be initialized.
Access to the bit timing register and to the BRP extension register for the configuration of
the bit timing is enabled when both bits Init and CCE in the CAN control register are set.
Resetting Init (by CPU only) finishes the software initialisation. Afterwards the bit stream
processor (BSP see Section 18.9.10) synchronizes itself to the data transfer on the CAN
bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (≡ Bus
Idle) before it can take part in bus activities and starts the message transfer.
The initialization of the message objects is independent of Init and can be done on the fly,
but the message objects should all be configured to particular identifiers or set to not valid
before the BSP starts the message transfer.
To change the configuration of a message object during normal operation, the CPU starts by
setting MsgVal to not valid. When the configuration is completed, MsgVal is set to valid
again.
18.7.2
CAN message transfer
Once the C-CAN is initialized and Init is reset to zero, the C-CAN’s CAN core synchronizes
itself to the CAN bus and starts the message transfer.
Received messages are stored into their appropte message objects if they pass the
message handler’s acceptance filtering. The whole message including all arbitration bits,
DLC and eight data bytes is stored inte message object. If the identifier mask is used,
the arbitration bits which are masked to “don’t care” may be overwritten in the message
object.
The CPU may read or write each message any time via the interface registers, the message
handler guarantees data consistency in case of concurrent accesses.
Messages to be ansmitted are updated by the CPU. If a permanent message object
(arbitration acontrol bits set up during configuration) exists for the message, only the data
bytes aupdated and then TxRqst bit with NewDat bit are set to start the transmission. If
several transmit messages are assigned to the same message object (when the number of
message objects is not sufficient), the whole message object has to be configured before
the transmission of this message is requested.
The transmission of any number of message objects may be requested at the same time,
they are transmitted subsequently according to their internal priority. Messages may be
updated or set to not valid at any time, even when their requested transmission is still
pending. The old data is discarded when a message is updated before its pending
transmission has started.
Depending on the configuration of the message object, the transmission of a message may
be requested autonomously by the reception of a remote frame with a matching identifier.
18.7.3
Disabled automatic retransmission
According to the CAN specification (see ISO11898, 6.3.3 Recovery Management), the C-
CAN provides means for automatic retransmission of frames that have lost arbitration or that
have been disturbed by errors during transmission. The frame transmission service is
confirmed to the user before the transmission is successfully completed. By default, this
151/328
CAN modules
ST10F252M
means that automatic retransmission is enabled. It can be disabled to enable the C-CAN to
work within a time triggered CAN (TTCAN, see ISO11898-1) environment.
The disabled automatic retransmission mode is enabled by programming bit DAR in the
CAN Control Register to one. In this operation mode, a programmer must consider the
different behavior of bits TxRqst and NewDat in the control registers of the message buffers:
●
when a transmission starts bit TxRqst of the respective message buffer is reset, while
bit NewDat remains set
●
when the transmission completed successfully bit NewDat is reset.
When a transmission fails (lost arbitration or error) bit NewDat remains set. To restart the
transmission the CPU has to set TxRqst back to one.
18.7.4
18.7.5
Test mode
The test mode is entered by setting bit Test in the CAN control register to one. In test mode
the bits Tx1, Tx0, LBack, Silent and Basic in the test register are writable. Bit Rx monitors
the state of pin CAN_RX and, therefore, is only readable. All test registr functions are
disabled when bit test is reset to zero.
Silent mode
The CAN core can be set in silent mode by programming the test register bit Silent to one.
In Silent mode, the C-CAN is able to receive valid data frames and valid remote frames, but
it sends only recessive bits on the CAN buand it cannot start a transmission. If the CAN
core is required to send a dominant bCK bit, overload flag, active error flag), the bit is
rerouted internally so that the CAN core monitors this dominant bit, although the CAN bus
may remain in recessive state. The silent mode can be used to analyze the traffic on a CAN
bus without affecting it by the transmission of dominant bits (acknowledge bits, error
frames). Figure 58 shows the connection of signals CAN_TX and CAN_RX to the CAN Core
in Silent Mode.
Figure 58. AN core in silent mode
CAN_TX CAN_RX
=1
C-CAN
•
•
Tx
Rx
CAN Core
In ISO 11898-1, the silent mode is called the bus monitoring mode.
18.7.6
Loop back mode
The CAN core can be set in loop back mode by programming the test register bit LBack to
one. In loop back mode, the CAN core treats its own transmitted messages as received
messages and stores them (if they pass acceptance filtering) into a receive buffer. Figure 59
shows the connection of signals CAN_TX and CAN_RX to the CAN core in loop back mode.
152/328
ST10F252M
CAN modules
Figure 59. CAN core in loop back mode
CAN_TX CAN_RX
C-CAN
•
•
Tx
Rx
CAN Core
This mode is provided for self-test functions. To be independent from external stimulation,
the CAN core ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a
data/remote frame) in loop back mode. In this mode the CAN core performs an internal
feedback from its Tx output to its Rx input. The actual value of the CAN_RX input pin is
disregarded by the CAN core. The transmitted messages can be monited at the CAN_TX
pin.
18.7.7
Loop back combined with silent mode
It is also possible to combine loop back mode and silent mode by programming bits LBack
and Silent to one at the same time. This mode cabe used for a “hot self test”, meaning the
C-CAN can be tested without affecting a running CAN system connected to the pins
CAN_TX and CAN_RX. In this mode, CAN_RX pin is disconnected from the CAN core
and the CAN_TX pin is held recessive. Figure 60 shows the connection of signals CAN_TX
and CAN_RX to the CAN core in case of the combination of loop back mode with silent
mode.
Figure 60. CAN core in loop back combined with silent mode
CAN_TX CAN_RX
C-CAN
=1
•
•
Tx
Rx
CAN Core
18.7.8
Basic mode
The CAN core can be set in basic mode by programming the test register bit Basic to one. In
this mode the C-CAN module runs without the message RAM.
The IF1 registers are used as transmit buffer. The transmission of the contents of the IF1
registers is requested by writing the Busy bit of the IF1 command request register to ‘1’. The
IF1 registers are locked while the Busy bit is set. The Busy bit indicates that the
transmission is pending.
153/328
CAN modules
ST10F252M
As soon the CAN bus is idle, the IF1 registers are loaded into the shift register of the CAN
core and the transmission is started. When the transmission has completed, the Busy bit is
reset and the locked IF1 registers are released.
A pending transmission can be aborted at any time by resetting the Busy bit in the IF1
command request register while the IF1 registers are locked. If the CPU has reset the Busy
bit, a possible retransmission in case of lost arbitration or in case of an error is disabled.
The IF2 registers are used as the receive buffer. After the reception of a message the
contents of the shift register is stored into the IF2 registers, without any acceptance filtering.
Additionally, the actual contents of the shift register can be monitored during the message
transfer. Each time a read message object is initiated by writing the Busy bit of the IF2
command request register to ‘1’, the contents of the shift register are stored into the IF2
registers.
In basic mode the evaluation of all message object related control and status bits and of the
control bits of the IFx command mask registers is turned off. The message number of the
command request registers is not evaluated. The NewDat and MsgLst bits of the IF2
message control register retain their function, DLC3-0 shows the receivd DLC, the other
control bits are read as ‘0’.
In basic mode the ready output CAN_WAIT_B is disabled (always ‘1’).
18.7.9
Software control of pin CAN_TX
Four output functions are available for the CAN transmit pin CAN_TX. Additionally to its
default function – the serial data output can drive the CAN sample point signal to monitor
CAN_Core’s bit timing and it can drive constant dominant or recessive values. The last two
functions, combined with the readable CAN receive pin CAN_RX, can be used to check the
CAN bus physical layer.
The output mode of pin CAN_TX is selected by programming the Test Register bits Tx1 and
Tx0 as described in Section 18.8.2.
The three tesunctions for pin CAN_TX interfere with all CAN protocol functions. CAN_TX
must beft in its default function when CAN message transfer or any of the test modes loop
back mode, silent mode, or basic mode are selected.
18.8
Programmer’s model
The C-CAN module allocates an address space of 256 bytes. The registers are organized
as 16-bit registers, with the high byte at the odd address and the low byte at the even
address.
The two sets of interface registers (IF1 and IF2) control the CPU access to the message
RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts
between CPU accesses and message reception/transmission.
Table 91. C-CAN register summary
Address
Name
Reset Value
0x0001
Note
CAN Base + 0x00
CAN Base + 0x02
CAN Base + 0x04
CAN Control Register
Status Register
Error Counter
0x0000
0x0000
read only
154/328
ST10F252M
CAN modules
Note
Table 91. C-CAN register summary (continued)
Address
Name
Reset Value
0x2301
CAN Base + 0x06
CAN Base + 0x08
CAN Base + 0x0A
CAN Base + 0x0C
CAN Base + 0x0E
CAN Base + 0x10
CAN Base + 0x12
CAN Base + 0x14
CAN Base + 0x16
CAN Base + 0x18
CAN Base + 0x1A
CAN Base + 0x1C
CAN Base + 0x1E
CAN Base + 0x20
CAN Base + 0x22
CAN Base + 0x24
Bit Timing Register
Interrupt Register
Test Register
write enabled by CCE
read only
0x0000
(1)
0x00 & 0br0000000
write enabled by Test
write enabled by CCE
BRP Extension Register 0x0000
(2)
— reserved
—
IF1 Command Request
IF1 Command Mask
IF1 Mask 1
0x0001
0x0000
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x000
x0000
0x0000
IF1 Mask 2
IF1 Arbitration 1
IF1 Arbitration 2
IF1 Message Control
IF1 Data A 1
IF1 Data A 2
IF1 Data B 1
IF1 Data B 2
(2)
CAN Base + 0x28 - 0x3E — reserved
CAN Base + 0x40 - 0x54 IF2 registers
CAN Base + 0x56 - 0x7E — reserved
—
see note (3)
same as IF1 registers
(2)
—
CAN Base + 0x80
Transmission Request 1 0x0000
Transmission Request 2 0x0000
read only
read only
CAN Base + 82
(2)
CAN Bse + 0x84 - 0x8E — reserved
—
CN Base + 0x90
CAN Base + 0x92
New Data 1
New Data 2
0x0000
0x0000
read only
read only
(2)
CAN Base + 0x94 - 0x9E — reserved
—
CAN Base + 0xA0
CAN Base + 0xA2
Interrupt Pending 1
Interrupt Pending 2
0x0000
0x0000
read only
read only
(2)
CAN Base + 0xA4 - 0xAE — reserved
—
CAN Base + 0xB0
CAN Base + 0xB2
Message Valid 1
Message Valid 2
0x0000
0x0000
read only
read only
(2)
CAN Base + 0xB4 - 0xBE — reserved
—
1. r signifies the actual value of the CAN_RX pin.
2. Reserved bits are read as ‘0’ except for IFx mask 2 register where they are read as ‘1’
3. The two sets of message interface registers - IF1 and IF2 - have identical functions.
155/328
CAN modules
ST10F252M
18.8.1
Hardware reset description
After hardware reset, the busoff state is reset and the output CAN_TX is set to recessive
(HIGH). The value 0x0001 (Init = ‘1’) in the CAN control register enables the software
initialisation. The C-CAN does not influence the CAN bus until the CPU resets Init to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM are undefined.
18.8.2
CAN protocol related registers
These registers are related to the CAN protocol controller in the CAN core. They control the
operating modes and the configuration of the CAN bit timing and provide status information.
CAN control register (addresses 0x01 and 0x00)
CAN control register
SFR
Reset value: xxxxh
15
R
14
R
13
R
12
11
10
R
9
8
7
6
5
4
3
2
1
0
reser
ed
reserved
Test
RW
CCE DAR
RW RW
EIE
RW
SIE
RW
IE
Init
RW
R
R
R
R
R
RW
Table 92. CAN control register (addresses 0x01 and 0x00) functions
Bit
Name
Function
Test mode eble
‘1’ Test mode
7
Test
CCE
DAR
‘0’ Normal operation.
Configuration change enable
6
5
‘1’ The CPU has write access to the bit timing register (while Init=1)
‘0’ The CPU has no write access to the bit timing register.
Disable automatic retransmission
‘1’ Automatic retransmission disabled
‘0’ Automatic retransmission of disturbed messages enabled.
Error interrupt enable
‘1’ Enabled - A change in the bits BOff or EWarn in the register
generates an interrupt
3
2
EIE
SIE
‘0’ Disabled - no error status interrupt is generated.
Status change interrupt enable
‘1’ Enabled - an interrupt is generated when a message transfer is
successfully completed or a CAN bus error is detected
‘0’ Disabled - no status change interrupt is generated.
156/328
ST10F252M
CAN modules
Table 92. CAN control register (addresses 0x01 and 0x00) functions (continued)
Bit
Name
Function
Module interrupt enable
‘1’ Enabled - interrupts set IRQ_B to LOW. IRQ_B remains LOW until
all pending interrupts are processed.
1
IE
‘0’ Disabled - module interrupt IRQ_B is always HIGH.
Initialization
0
INIT
‘1’ Initialization is started.
‘0’ Normal operation.
Note:
The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by
setting or resetting Init. If the device goes busoff, it sets Init of its own accord, stopping all
bus activities. Once Init has been cleared by the CPU, the device waits for 129 occurrences
of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operations. At the
end of the busoff recovery sequence, the error management counters are reset.
During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits
has been monitored, a Bit0Error code is written to the status rister, enabling the CPU to
readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to
monitor the proceeding of the busoff recovery sequence.
Status register (addresses 0x03 and 0x02)
Status register
FR
Reset value: xxxxh
15
R
14
R
13
R
12
11
R
10
R
9
8
7
6
5
4
3
2
1
0
reserved
BOff EWarn EPass RxOk TxOk
LEC
RW
R
R
R
R
R
R
R
RW
Table 93. Stas register (addresses 0x03 and 0x02) functions
Bit
Name
Function
Busoff status
7
BOff
‘1’ The CAN module is in busoff state
‘0’ The CAN module is not busoff.
Warning status
‘1’ At least one of the error counters in the EML has reached the error
warning limit of 96
6
5
EWarn
‘0’ Both error counters are below the error warning limit of 96.
Error passive
‘1’ The CAN core is in the error passive state as defined in the CAN
specification
EPass
‘0’ The CAN core is error active.
157/328
CAN modules
ST10F252M
Table 93. Status register (addresses 0x03 and 0x02) functions (continued)
Bit
Name
Function
Received a message successfully
‘1’ Since this bit was last reset (to zero) by the CPU, a message has
been successfully received (independently of the result of acceptance
filtering)
4
RxOk
TxOk
‘0’ Since this bit was last reset by the CPU, no message has been
successfully received. This bit is never reset by the CAN core.
Transmitted a message successfully
‘1’ Since this bit was last reset by the CPU, a message has been
successfully (error free and acknowledged by at least one other node)
transmitted.
3
‘0’ Since this bit was reset by the CPU, no message has been
successfully transmitted. This bit is never reset by the CAN core.
Last error code (type of the last error to occur on the CAN bus)
‘000’ No error
‘001’ Stuff error: more than five equal bis in a sequence have occurred
in a part of a received message where this is not allowed
‘010’ Form error: a fixed format prt of a received frame has the wrong
format
‘011’ AckError: the mesge this CAN core transmitted was not
acknowledged by another node
‘100’ Bit1Err: dng the transmission of a message (with the
exception oarbitration field), the device wanted to send a
recessive level (bit of logical value ‘1’), but the monitored bus value was
dominant
2.0 LEC
‘101’ Bit0Error: during the transmission of a message (or acknowledge
bit, or active error flag, or overload flag), the device wanted to send a
dominant level (data or identifier bit logical value ‘0’), but the monitored
Bus value was recessive. During busoff recovery this status is set each
time a sequence of 11 recessive bits has been monitored. This enables
the CPU to monitor the proceeding of the busoff recovery sequence
(indicating the bus is not stuck at dominant or continuously disturbed)
‘110’ CRCError: the CRC check sum was incorrect in the message
received, the CRC received for an incoming message does not match
with the calculated CRC for the received data
‘111’ unused: when the LEC shows the value ‘111’, no CAN bus event
is detected since the CPU wrote this value to the LEC.
The LEC field holds a code which indicates the type of the last error to occur on the CAN
bus. This field will be cleared to ‘0’ when a message has been transferred (reception or
transmission) without error. The unused code ‘111’ may be written by the CPU to check for
updates.
Status interrupts
A status interrupt is generated by bits BOff and EWarn (error Interrupt) or by RxOk, TxOk,
and LEC (status change interrupt) assuming that the corresponding enable bits in the CAN
control register are set. A change of bit EPass or a write to RxOk, TxOk, or LEC never
generates a status interrupt.
158/328
ST10F252M
CAN modules
Reading the status register clears the status interrupt value (8000h) in the interrupt register,
if it is pending.
Error counter (addresses 0x05 and 0x04)
Error counter register
SFR
Reset value: xxxxh
15
RP
R
14
13
12
11
REC6-0
R
10
9
8
7
6
5
4
3
TEC7-0
R
2
1
0
Table 94. Error counter (addresses 0x05 and 0x04) functions
Bit
Name
Function
Receive error passive
‘1’ The receive error counter has reached the error passive level as
defined in the CAN specification.
15
RP
‘0’ The receive error counter is below the errpassive level.
Receive error counter
14.8 REC6-0
7.0 TEC7-0
Actual state of the receive error counter. Values between 0 and 127.
Transmit error counter
Actual state of the transt error counter. Values between 0 and 255.
Bit timing register (addresses 0and 0x06)
Bit timing register
SFR
Reset value: xxxxh
15
14
13
TSeg2
RW
12
11
10
TSeg1
RW
9
8
7
6
5
4
3
2
1
0
SJW
RW
BRP
RW
R
Table 95. Bit timing register (addresses 0x07 and 0x06) functions
Bit
Name
Function
Time segment after the sample point
Valid values for TSeg2 are [0 to 7]. The actual interpretation by the
hardware of this value is such that one more than the value
programmed here is used.
14.12 TSeg2
Time segment before the sample point
Valid values for TSeg1 are [1 to15]. The actual interpretation by the
hardware of this value is such that one more than the value
programmed here is used.
11.8 TSeg1
159/328
CAN modules
ST10F252M
Table 95. Bit timing register (addresses 0x07 and 0x06) functions (continued)
Bit
Name
Function
(Re)synchronisation jump width
Valid programmed values are [0 to 3]. The actual interpretation by the
hardware of this value is such that one more than the value
programmed here is used.
7.6 SJW
Baud rate prescaler
The value by which the oscillator frequency is divided for generating
the bit time quantum. The bit time is built up from a multiple of this
quantum. Valid values for the baud rate prescaler are [0 to 63]. The
actual interpretation by the hardware of this value is such that one
more than the value programmed here is used.
5.0 BRP
Note:
With a CAN module clock of 8 MHz, the reset value of 0x2301 configures the C-CAN for a
bit rate of 500 kBit/s. The registers are only writable if bits CCE and Init in the CAN control
register are set.
Test register (addresses 0x0B and 0x0A)
Test register
SFR
Reset value: xxxxh
15
R
14
R
13
R
12
11
10
R
9
8
7
R
6
5
4
3
2
1
0
reserved
Tx1
RW
Tx0 LBack Silent Basic
RW RW RW RW
reserved
R
R
R
R
R
R
Table 96. Test register (addresses 0x0B and 0x0A) functions
Bit
Name
Function
Monitors the actual value of the CAN_RX Pin
‘1’ The CAN bus is recessive (CAN_RX = ‘1’)
‘0’ The CAN bus is dominant (CAN_RX = ‘0’).
7
Rx
Control of CAN_TX pin
‘00’ Reset value, CAN_TX is controlled by the CAN core
‘01’ Sample point can be monitored at CAN_TX pin
‘10’ CAN_TX pin drives a dominant (‘0’) value
‘11’ CAN_TX pin drives a recessive (‘1’) value.
6.5 Tx1 and Tx0
Loop back mode
4
3
2
LBack
Silent
Basic
‘1’ Loop back mode is enabled
‘0’ Loop back mode is disabled.
Silent mode
‘1’ The module is in silent mode
‘0’ Normal operation.
Basic mode
‘1’ F1 registers used as Tx buffer, IF2 registers used as Rx buffer
‘0’ Basic mode disabled.
Write access to the test register is enabled by setting bit Test in the CAN control register.
The different test functions may be combined, but Tx1-0 ≠ “00” disturbs message transfer.
160/328
ST10F252M
CAN modules
BRP extension register (addresses 0x0D and 0x0C)
BRP extension register
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BRPE
RW
R
R
R
R
R
R
R
R
R
R
R
R
Table 97. BRP extension register (addresses 0x0D and 0x0C) functions
Bit
Name
Function
Baud rate prescaler extension
By programming BRPE
3.0 BRPE
the baud rate prescaler can be extended to values up to 1023. The
actual interpretation by the hardware is that one more than the value
programmed by BRPE (MSBs) and BRP (LSBs) is used.
18.8.3
Message interface register sets
There are two sets of interface registers which are used tcontrol the CPU access to the
message RAM. The interface registers avoid conflicts between CPU access to the message
RAM and CAN message reception and transmisson by buffering the data to be transferred.
A complete message object or parts of the message object may be transferred between the
message RAM and the IFx message buffeegisters in one single transfer.
The function of the two interface register sets is identical (except for test mode Basic). They
can be used the way that one set of registers is used for data transfer to the message RAM
while the other set of registers is used for the data transfer from the message RAM, allowing
both processes to be interrupted by each other. Table 98 gives an overview of the two
interface register sets.
Each set of interface registers consists of message buffer registers controlled by their own
commad registers. The command mask register specifies the direction of the data transfer
and which parts of a message object are transferred. The command request register is used
to elect a message object in the message RAM as target or source for the transfer and to
start the action specified in the command mask register.
Table 98. IF1 and IF2 message interface register sets
Address
IF1 Register Set
Address
IF2 Register Set
CAN Base + 0x10 IF1 Command Request
CAN Base + 0x12 IF1 Command Mask
CAN Base + 0x14 IF1 Mask 1
CAN Base + 0x40 IF2 Command Request
CAN Base + 0x42 IF2 Command Mask
CAN Base + 0x44 IF2 Mask 1
CAN Base + 0x16 IF1 Mask 2
CAN Base + 0x46 IF2 Mask 2
CAN Base + 0x18 IF1 Arbitration 1
CAN Base + 0x1A IF1 Arbitration 2
CAN Base + 0x1C IF1 Message Control
CAN Base + 0x1E IF1 Data A 1
CAN Base + 0x20 IF1 Data A 2
CAN Base + 0x48 IF2 Arbitration 1
CAN Base + 0x4A IF2 Arbitration 2
CAN Base + 0x4C IF2 Message Control
CAN Base + 0x4E IF2 Data A 1
CAN Base + 0x50 IF2 Data A 2
161/328
CAN modules
ST10F252M
Table 98. IF1 and IF2 message interface register sets (continued)
Address IF1 Register Set Address IF2 Register Set
CAN Base + 0x22 IF1 Data B 1
CAN Base + 0x24 IF1 Data B 2
CAN Base + 0x52 IF2 Data B 1
CAN Base + 0x54 IF2 Data B 2
A message transfer is started as soon as the CPU has written the message number to the
command request register. With this write operation the Busy bit is automatically set to ‘1’.
After a wait time of 3 to 6 CAN clock periods, the transfer between the interface register and
the message RAM is completed and the Busy bit is set back to zero.
IFx command request registers
IF1 Command Request Register (addresses 0x11 & 0x10)
SFR
7
Reset value: xxxxh
15
Busy
R
14
13
12
11
10
reserved
R
9
8
R
8
6
R
6
5
4
3
2
1
0
Message Number
RW
R
R
R
R
R
R
IF2 Command Request Register (addresses 0x41 & 0x40)
SFR
7
Reset value: xxxxh
15
Busy
R
14
13
12
11
10
reserved
R
9
5
4
3
2
1
0
Message Number
RW
R
R
R
R
R
R
R
Table 99. IFx command request registers functions
Bit
Name
Function
Busy flag
15
Busy
‘1’ Set when writing to the IFx command request register
‘0’ Read/write action has finished.
Message number
‘0x01-0x20’
Valid message number, the message object in the message RAM is
selected for data transfer
5.0 Message Number
‘0x00’
Not a valid message number, interpreted as 0x20
‘0x21-0x3F’
Not a valid message number, interpreted as 0x01-0x1F.
Note:
When a message number that is not valid is written into the command request register, the
message number is transformed into a valid value and that message object is transferred.
The control bits of the IFx command mask register specify the transfer direction and select
which of the IFx message buffer registers are source or target of the data transfer.
162/328
ST10F252M
CAN modules
IFx command mask registers
IF1 Command Mask Register (addresses 0x13
& 0x12)
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TxRqs
t/
Contr ClrInt
WR/R
D
reserved
Mask
RW
Arb
RW
Data A Data B
ol
Pnd
NewD
at
R
R
R
R
R
R
R
9
R
8
RW
RW
RW
RW
RW
RW
IF2 Command Mask Register (addresses 0x43
& 0x42)
SFR
Reset value: xxxxh
15
14
13
12
11
10
7
6
5
4
3
2
1
0
TxRqs
t/
Contr ClrInt
WR/R
D
reserved
Mask
RW
Arb
RW
Data A Data B
ol
Pnd
NewD
at
R
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
Table 100. IFx command mask registers functions
Bit
Name
Function
Write/Read
‘1’ Write: transfer data fm the selected message buffer registers to
the message object addressed by the command request register
7
WR/RD
‘0’ Read: trer data from the message object addressed by the
command reest register into the selected message buffer registers.
The other bits of IFx command mask register have different functions depending on the
transfer direction.
Table 101. IFx command mask registers functions (direction - write)
Bit
Nae
Function
Access mask bits
6
Mask
‘1’ Transfer identifier mask + MDir + MXtd to message object
‘0’ Mask bits unchanged.
Access arbitration bits
5
Arb
‘1’ Transfer identifier + Dir + Xtd + MsgVal to message object
‘0’ Arbitration bits unchanged.
Access control bits
4
3
Control
‘1’ Transfer control bits to message object
‘0’ Control bits unchanged.
Clear interrupt pending bit
ClrIntPnd
When writing to a message object, this bit is ignored.
Access transmission request bit
‘1’ Set TxRqst bit
‘0’ TxRqst bit unchanged
2
TxRqst/NewDat
If a transmission is requested by programming bit TxRqst/NewDat in
the IFx command mask register, bit TxRqst in the IFx message control
register is ignored.
163/328
CAN modules
ST10F252M
Table 101. IFx command mask registers functions (direction - write) (continued)
Bit
Name
Function
Access data bytes 0-3
1
Data A
‘1’ Transfer data bytes 0-3 to message object
‘0’ Data bytes 0-3 unchanged.
Access data bytes 4-7
0
Data B
‘1’ Transfer data bytes 4-7 to message object
‘0’ Data bytes 4-7 unchanged.
Table 102. IFx command mask registers functions (direction - read)
Bit
Name
Function
Access mask bits
‘1’ Transfer identifier mask + MDir + MXtd to IFx message buffer
register
6
Mask
Arb
‘0’ Mask bits unchanged.
Access arbitration bits
‘1’ Transfer identifier + Dir + Xtd + MsgVal to IFx message buffer
register
5
‘0’ Arbitration bits unchanged.
Access control bits
4
3
Control
‘1’ Transfer cntrbits to IFx message buffer register
‘0’ Control bunchanged.
Clear interrupt pending bit
ClrIntPnd
‘1’ Clear IntPnd bit in the message object
‘0’ IntPnd bit remains unchanged
Access new data bit
‘1’ Clear NewDat bit in the message object
‘0’ NewDat bit remains unchanged.
2
TxRqst/NewDat
A read access to a Message Object can be combined with the reset of
the control bits IntPnd and NewDat. The values of these bits
transferred to the IFx Message Control Register always reflect the
status before resetting these bits.
Access data bytes 0-3
1
0
Data A
Data B
‘1’ Transfer data bytes 0-3 to IFx message buffer register
‘0’ Data Bytes 0-3 unchanged.
Access data bytes 4-7
‘1’ Transfer data bytes 4-7 to IFx message buffer register
‘0’ Data Bytes 4-7 unchanged
18.8.4
IFx message buffer registers
The bits of the message buffer registers mirror the message objects in the message RAM.
164/328
ST10F252M
CAN modules
IFx mask register
IF1 Mask 1 Register (addresses 0x15 & 0x14)
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Msk15-0
RW RW
RW
RW
R
RW
RW
RW
RW
9
RW
RW
5
RW
4
RW
3
RW
RW
RW
IF1 Mask 2 Register (addresses 0x17 & 0x16)
SFR
Reset value: xxxxh
15
14
13
12
11
10
8
7
6
2
1
0
reserv
ed
MXtd MDir
Msk28-16
RW
RW
RW
R
RW
RW
RW
RW
9
RW
8
RW
7
RW
5
RW
4
RW
RW
RW
RW
IF1 Mask 1 Register (addresses 0x45 & 0x44)
SFR
Reset value: xxxxh
15
14
13
12
11
10
6
2
1
0
Msk15-0
RW
RW
R
RW
RW
RW
RW
9
RW
RW
RW
RW
5
RW
4
RW
3
RW
RW
RW
IF1 Mask 2 Register (addresses 0x47 & 0x46)
SFR
Reset value: xxxxh
15
14
13
12
11
10
7
6
2
1
0
MXtd MDir
Msk28-16
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IFx arbitration registers
IF1 Arbitration 1 Regi(addresses 0x19 &
0x18)
SFR
Reset value: xxxxh
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID15-0
RW RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IF1 Arbitration 2 Register (addresses 0x1B &
0x1A)
SFR
Reset value: xxxxh
15
14
Xtd
RW
13
Dir
R
12
11
10
9
8
7
6
5
4
3
2
1
0
MsgV
al
ID28-16
RW
RW
RW
RW
RW
RW
RW
8
RW
7
RW
RW
RW
RW
RW
RW
IF2 Arbitration 1 Register (addresses 0x49 &
0x48)
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
6
5
4
3
2
1
0
ID15-0
RW RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
165/328
CAN modules
ST10F252M
IF2 Arbitration 2 Register (addresses 0x4B &
0x4A)
SFR
Reset value: xxxxh
15
14
Xtd
RW
13
Dir
R
12
11
10
9
8
7
6
5
4
3
2
1
0
MsgV
al
ID28-16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IFx message control registers
IF1 Message Control Register (addresses
0x1D & 0x1C)
SFR
Reset value: xxxxh
15
14
13
IntPnd
R
12
11
10
9
8
7
6
5
4
3
2
1
0
NewD MsgLs
at
UMas
k
reserv reserv reserv
ed
TxIE RxIE RmtEn TxRqst EoB
DLC3-0
t
ed
ed
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IF2 Message Control Register (addresses
0x4D & 0x4C)
SFR
Reset value: xxxxh
15
14
13
IntPnd
R
12
11
10
9
8
7
6
5
4
3
2
1
0
NewD MsgLs
at
UMas
k
reserv reserv reserv
ed
TxIE RxIE RmtEn TxRqst EoB
DLC3-0
t
ed
ed
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IFx Data A and Data B Registers
The data bytes of CAN messages are stored in the IFx Message Buffer Registers in the
order shown in Table 103.
Table 103. IFx Data A and Data B registers
[15:8]
[7:0]
IF1 Message Data A1 (addresses 0x1F & 0x1E)
IF1 Message Data A2 (addresses 0x21 & 0x20)
IF1 Message Data B1 (addresses 0x23 & 0x22)
IF1 Message Data B2 (addresses 0x25 & 0x24)
IF2 Message Data A1 (addresses 0x4F & 0x4E)
IF2 Message Data A2 (addresses 0x51 & 0x50)
IF2 Message Data B1 (addresses 0x53 & 0x52)
IF2 Message Data B2 (addresses 0x55 & 0x54)
Data(1)
Data(3)
Data(5)
Data(7)
Data(1)
Data(3)
Data(5)
Data(7)
Data(0)
Data(2)
Data(4)
Data(6)
Data(0)
Data(2)
Data(4)
Data(6)
In a CAN data frame, Data(0) is the first, Data(7) is the last byte to be transmitted or
received. In CAN’s serial bit stream, the MSB of each byte is transmitted first.
Message object in the message memory
There are 32 message objects in the message RAM. To avoid conflicts between CPU
access to the message RAM and CAN message reception and transmission, the CPU
cannot directly access the message objects, these accesses are handled via the IFx
interface registers.
166/328
ST10F252M
CAN modules
Figure 61 gives an overview of the two structures of a message object.
Figure 61. Structure of a message object in the message memory
Message Object
UMask
MsgVal
Msk28-0
ID28-0
MXtd
Xtd
MDir
Dir
EoB
NewDat
MsgLst RxIE
TxIE
IntPnd RmtEn TxRqst
DLC3-0 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7
Table 104. Message object functions
Bit Name
Function
Message valid
‘1’ The message object is configured and should be considered by the
message handler
‘0’ The message object is ignored by the message handler.
MsgVal
The CPU must reset the MsgVal bit of all unused message objects
during the initialization before it resets bit Init in te CAN control
register. This bit must also be reset before thdentifier Id28-0, the
control bits Xtd, Dir, or the Data Lengtode DLC3-0 are modified, or
if the message object is no longer required.
Use acceptance mask
‘1’ Use mask (Msk28-0, MXtd, and MDir) for acceptance filtering
‘0’ Mask ignored.
UMask
If the UMask bit iet to one, the message object’s mask bits have to
be programduring initialization of the message object before
MsgVal is set to one.
Message identifier
ID28-0
sk28-0
Xtd
ID28 - ID0 29-bit Identifier (“extended frame”).
ID28 - ID18 11-bit Identifier (“standard frame”).
Identifier mask
‘1’ The corresponding identifier bit is used for acceptance filtering
‘0’ The corresponding bit in the identifier of the message object cannot
inhibit the match in the acceptance filtering.
Extended identifier
‘1’ The 29-bit (“extended”) Identifier is used for this message object.
‘0’ The 11-bit (“standard”) Identifier is used for this message object.
Mask extended identifier
‘1’ The extended identifier bit (IDE) is used for acceptance filtering
‘0’ The extended identifier bit (IDE) has no effect on the acceptance
filtering.
MXtd
When 11-bit (“standard”) identifiers are used for a message object, the
identifiers of received data frames are written into bits ID28 to ID18. For
acceptance filtering, only these bits together with mask bits Msk28 to
Msk18 are considered.
167/328
CAN modules
ST10F252M
Table 104. Message object functions (continued)
Bit Name
Function
Message direction
‘1’ Direction = transmit: On TxRqst, the respective message object is
transmitted as a data frame. On reception of a remote frame with
matching identifier, the TxRqst bit of this message object is set (if
RmtEn = one)
Dir
‘0’ Direction = receive: On TxRqst, a remote frame with the identifier of
this message object is transmitted. On reception of a data frame with
matching identifier, that message is stored in this message object.
Mask message direction
‘1’ The message direction bit (Dir) is used for acceptance filtering
‘0’ The message direction bit (Dir) has no effect on the acceptance
filtering.
The arbitration registers ID28-0, Xtd, and Dir are used to define the
identifier and type of outgoing messages and are used (together with
the mask registers Msk28-0, MXtd, and MDiror acceptance filtering
of incoming messages. A received meage is stored into the valid
message object with matching identifier and Direction=receive (data
frame) or Direction=transmit (remte frame). Extended frames can be
stored only in message objets with Xtd = one, standard frames in
message objects with Xtd = zero. If a received message (data frame or
remote frame) matches ith more than one valid Message Object, it is
stored into that wthe lowest message number. For details see
Section 18.
MDir
End of buffer
‘1’ Single message object or last message object of a FIFO buffer
‘0’ Message object belongs to a FIFO buffer and is not the last
message object of that FIFO buffer.
EoB
This bit is used to concatenate two ore more message objects (up to
32) to build a FIFO buffer. For single message objects (not belonging to
a FIFO buffer) this bit is always be set to one. For details on the
concatenation of message objects see Section 18.9.7.
New data
‘1’ The message handler or the CPU has written new data into the data
portion of this message object
NewDat
‘0’ No new data has been written into the data portion of this message
object by the message handler since last time this flag was cleared by
the CPU.
Message lost (only valid for message objects with direction = receive)
‘1’ The message handler stored a new message into this object when
NewDat was still set, the CPU has lost a message
MsgLst
RxIE
‘0’ No message lost since last time this bit was reset by the CPU.
Receive interrupt enable
‘1’ IntPnd is set after a successful reception of a frame
‘0’ IntPnd is left unchanged after a successful reception of a frame.
168/328
ST10F252M
CAN modules
Table 104. Message object functions (continued)
Bit Name
Function
Transmit interrupt enable
‘1’ IntPnd is set after a successful transmission of a frame
TxIE
‘0’ IntPnd is left unchanged after the successful transmission of a
frame.
Interrupt pending
‘1’ This message object is the source of an interrupt. The interrupt
identifier in the interrupt register point to this message object if there is
no other interrupt source with higher priority
IntPnd
‘0’ This message object is not the source of an interrupt.
Remote enable
RmtEn
TxRqst
‘1’ At the reception of a remote frame, TxRqst is set
‘0’ At the reception of a remote frame, TxRqst is left unchanged.
Transmit request
‘1’ The transmission of this message object iequested and is not yet
done
‘0’ This message object is not waitng for transmission.
Data length code
‘0-8’ Data frame has 0-ata bytes.
‘9-15’ Data frame has 8 data bytes
The data lecode of a message object is defined the same as in all
the correspoing objects with the same identifier at other nodes.
When the message handler stores a data frame, it will write the DLC to
the value given by the received message.
Data 0 1st data byte of a CAN data frame
Data 1 2nd data byte of a CAN data frame
Data 2 3rd data byte of a CAN data frame
Data 3 4th data byte of a CAN data frame
Data 4 5th data byte of a CAN data frame
Data 5 6th data byte of a CAN data frame
Data 6 7th data byte of a CAN data frame
Data 7 8th data byte of a CAN data frame
DLC3
Byte Data 0 is the first data byte shifted into the shift register of the
CAN core during a reception, byte Data 7 is the last. When the
message handler stores a data frame, it writes all the eight data bytes
into a message object. If the data length code is less than 8, the
remaining bytes of the message object are overwritten by non specified
values.
18.8.5
Message Handler Registers
All Message Handler registers are read-only. Their contents (TxRqst, NewDat, IntPnd, and
MsgVal bits of each Message Object and the Interrupt Identifier) is status information
provided by the Message Handler FSM.
169/328
CAN modules
ST10F252M
Interrupt register (addresses 0x09 and 0x08)
Interrupt Register (addresses 0x09 & 0x08)
15 14 13 12 11 10
SFR
Reset value: xxxxh
9
8
7
6
5
4
3
2
1
0
IntId15-8
R
IntId7-0
R
Table 105. Interrupt register (addresses 0x09 and 0x08) functions
Bit Name Function
Interrupt identifier (the number indicates the source of the interrupt)
‘0x0000’ No interrupt is pending
‘0x0001-0x0020’ Number of message object which caused the
interrupt
15.0 IntId15-0
‘0x0021-0x7FFF’ unused
‘0x8000’ Status Interrupt
‘0x8001-0xFFFF’ unused.
If several interrupts are pending, the CAN interrupt register points to the pending interrupt
with the highest priority, disregarding their chronologial order. An interrupt remains pending
until the CPU has cleared it. If IntId is not 0x0000 nd IE is set, the interrupt line to the CPU,
IRQ_B, is active. The interrupt line remains active until IntId is back to value 0x0000 (the
cause of the interrupt is reset) or until s reset.
The status interrupt has the highest priority. Among the message interrupts, the message
object’ s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the message object’s IntPnd bit. The status
interrupt is cleared by reading the status register.
18.8.6
Transmissn request registers
Trsmission Request 1 Register (addresses
SFR
Reset value: xxxxh
0x81 & 0x80)
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
TxRqst16-9
R
TxRqst8-1
R
Transmission Request 2 Register (addresses
0x83 & 0x82)
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TxRqst32-25
R
TxRqst24-17
R
170/328
ST10F252M
CAN modules
Table 106. Transmission request register functions
Bit
Name
Function
Transmission request bits (of all message objects)
‘1’ The transmission of this message object is requested and is not yet
done
15.0 TxRqst32-1
‘0’ This message object is not waiting for transmission.
These registers hold the TxRqst bits of the 32 message objects. By reading out the TxRqst
bits, the CPU can check for which message object a transmission request is pending. The
TxRqst bit of a specific message object can be set/reset by the CPU via the IFx message
interface registers or by the message handler after reception of a remote frame or after a
successful transmission.
18.8.7
New data registers
New Data 1 Register (addresses 0x91 & 0x90)
15 14 13 12 11 10
SFR
Reset value: xxxxh
9
8
7
6
5
4
3
2
1
0
NewDat16-9
R
NewDat8-1
R
New Data 2 Register (addresses 0x93 & 0x92)
15 14 13 12 11 10
FR
Reset value: xxxxh
9
8
7
6
5
4
3
2
1
0
NewDat32-25
R
NewDat24-17
R
Table 107. Nedata register functions
Bit Name
Function
New data bits (of all message objects)
‘1’ The message handler or the CPU has written new data into the data
portion of this message object
15.0 NewDat32-1
‘0’ No new data has been written into the data portion of this message
object by the message handler since last time this flag was cleared by
the CPU.
These registers hold the NewDat bits of the 32 message objects. By reading out the NewDat
bits, the CPU can check for which message object the data portion is updated. The NewDat
bit of a specific message object can be set/reset by the CPU via the IFx message interface
registers or by the message handler after reception of a data frame or after a successful
transmission.
171/328
CAN modules
ST10F252M
18.8.8
Interrupt pending registers
Interrupt Pending 1 Register (addresses 0xA1
& 0xA0)
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IntPnd16-9
R
IntPnd8-1
R
Interrupt Pending 2 Register (addresses 0xA3
& 0xA2)
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IntPnd32-25
R
IntPnd24-17
R
Table 108. Interrupt pending register functions
Bit Name
Functio
Interrupt pending bits (of all message objects)
15.0 IntPnd32-1
‘1’ This message object is the source of an interrupt
‘0’ This message object is not the source of an interrupt.
These registers hold the IntPnd bits of the 32 message objects. By reading out the IntPnd
bits, the CPU can check for which mege object an interrupt is pending. The IntPnd bit of
a specific message object can be set/reset by the CPU via the IFx message interface
registers or by the message handler after reception or after a successful transmission of a
frame. This will also affect the value of IntId in the interrupt register.
18.8.9
Message valid registers
Message lid 1 Register (addresses 0xB1 &
0xB0)
SFR
Reset value: xxxxh
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MsgVal16-9
R
MsgVal8-1
R
Message Valid 2 Register (addresses 0xB3 &
0xB2)
SFR
Reset value: xxxxh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MsgVal32-25
R
MsgVal24-17
R
172/328
ST10F252M
CAN modules
Table 109. Message valid register functions
Bit Name
Function
Message valid bits (of all message objects)
‘1’ This message object is configured and should be considered by the
message handler
15.0 MsgVal32-1
‘0’ This message object is ignored by the message handler.
These registers hold the MsgVal bits of the 32 message objects. By reading out the MsgVal
bits, the CPU can check which message object is valid. The MsgVal bit of a specific
message object can be set/reset by the CPU via the IFx message interface registers.
18.9
CAN application
18.9.1
Management of message objects
The configuration of the message objects in the message RAM are (with the exception of
the bits MsgVal, NewDat, IntPnd, and TxRqst) not affected by esetting the chip. All the
message objects are initialized by the CPU or they are novalid (MsgVal = ‘0’); bit timing is
configured before the CPU clears the Init bit in the CAN control register.
The configuration of a message object is done bprogramming mask, arbitration, control
and data fields of one of the two interface register sets to the desired values. By writing to
the corresponding IFx command requregister, the IFx message buffer registers are
loaded into the addressed message object in the message RAM.
When the Init bit in the CAN control register is cleared, the CAN protocol controller state
machine of the CAN core and the message handler state machine control the C-CAN’s
internal data flow. Received messages that pass the acceptance filtering are stored into the
message RAM, messages with pending transmission request are loaded into the CAN
core’s shift regisr and are transmitted via the CAN bus.
The Creads received messages and updates messages to be transmitted via the IFx
interface registers. Depending on the configuration, the CPU is interrupted on certain CAN
message and CAN error events.
18.9.2
Message handler state machine
The message handler controls the data transfer between the Rx/Tx shift register of the CAN
core, the message RAM and the IFx registers.
The message handler FSM controls the following functions:
●
●
●
●
●
●
●
●
data transfer from IFx registers to the message RAM
data transfer from message RAM to the IFx registers
data transfer from shift register to the message RAM
data transfer from message RAM to shift register
data transfer from shift register to the acceptance filtering unit
scanning of message RAM for a matching message object
handling of TxRqst flags.
handling of interrupts.
173/328
CAN modules
ST10F252M
Data transfer from and to message RAM
When the CPU initiates a data transfer between the IFx registers and message RAM, the
message handler sets the Busy bit in the respective command register to ‘1’. After the
transfer has completed, the Busy bit is set back to ‘0’ (see Figure 62).
The respective command mask register specifies whether a complete message object or
only parts of it are transferred. Due to the structure of the message RAM it is not possible to
write single bits/bytes of one message object, it is always necessary to write a complete
message object into the message RAM. Therefore, the data transfer from the IFx registers
to the message RAM requires a read-modify-write cycle. First, those parts of the message
object that are not to be changed are read from the Message RAM and, then, the complete
contents of the message buffer registers are into the message object.
Figure 62. Data transfer between IFx registers and message RAM
START
No
Write Command Request Reister
Yes
Busy = 1
CAWAIT_B = 0
No
Yes
WR/RD = 1
Read Message Object to IFx
Write IFx to Message RAM
Read Message Object to IFx
Busy = 0
CAN_WAIT_B = 1
After the partial write of a message object, the message buffer registers that are not
selected in the command mask register are set to the actual contents of the selected
message object.
After the partial read of a message object, the message buffer registers that are not
selected in the command mask register are left unchanged.
174/328
ST10F252M
CAN modules
Transmission of messages
If the shift register of the CAN core cell is ready for loading and if there is no data transfer
between the IFx registers and message RAM, the MsgVal bits in the message valid register
TxRqst bits in the transmission request register are evaluated. The valid message object
with the highest priority pending transmission request is loaded into the shift register by the
message handler and the transmission is started. The message object’s NewDat bit is reset.
After a successful transmission and if no new data was written to the message object
(NewDat = ‘0’) since the start of the transmission, the TxRqst bit is reset. If TxIE is set,
IntPnd is set after a successful transmission. If the C-CAN has lost the arbitration or if an
error occurred during the transmission, the message is retransmitted as soon as the CAN
bus is free again. If, meanwhile, the transmission of a message with higher priority is
requested, the messages are transmitted in the order of their priority.
Acceptance filtering of received messages
When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming
message is completely shifted into the Rx/Tx shift register of the CAN re, the message
handler FSM starts the scanning of the message RAM for a matchinvalid message object.
To scan the message RAM for a matching message object, the acceptance filtering unit is
loaded with the arbitration bits from the CAN core shift reister. The arbitration and mask
fields (including MsgVal, UMask, NewDat, and EoB) of message object 1 are loaded into the
acceptance filtering unit and compared with the arbitration field from the shift register. This is
repeated with each following message object until a matching message object is found or
until the end of the message RAM is reach.
If a match occurs, the scanning is stopped and the message handler FSM proceeds
depending on the type of frame (data frame or remote frame) received.
Reception of data frame
The message handler FSM stores the message from the CAN core shift register into the
respective message object in the message RAM. Not only the data bytes, but all arbitration
bits and he data length code are stored into the corresponding message object. This is
implemented to keep the data bytes connected with the identifier even if arbitration mask
registers are used.
The NewDat bit is set to indicate that new data (not yet seen by the CPU) has been
received. The CPU resets NewDat when it reads the message object. If, at the time of the
reception, the NewDat bit was already set, MsgLst is set to indicate that the previous data
(supposedly not seen by the CPU) is lost. If the RxIE bit is set, the IntPnd bit is set, causing
the interrupt register to point to this message object.
The TxRqst bit of this message object is reset to prevent the transmission of a remote
frame, while the requested data frame has just been received.
Reception of remote frame
When a remote frame is received, three different configurations of the matching message
object have to be considered:
175/328
CAN modules
1. Dir = ‘1’ (direction = transmit), RmtEn = ‘1’, UMask = ‘1’ or ‘0’
ST10F252M
At the reception of a matching remote frame, the TxRqst bit of this message object is
set. The rest of the message object remains unchanged.
2. Dir = ‘1’ (direction = transmit), RmtEn = ‘0’, UMask = ‘0’
At the reception of a matching remote frame, the TxRqst bit of this message object
remains unchanged; the remote frame is ignored.
3. Dir = ‘1’ (direction = transmit), RmtEn = ‘0’, UMask = ‘1’
At the reception of a matching remote frame, the TxRqst bit of this message object is
reset. The arbitration and control field (Identifier + IDE + RTR + DLC) from the shift
register is stored into the message object in the message RAM and the NewDat bit of
this message object is set. The data field of the message object remains unchanged;
the remote frame is treated similar to a received data frame.
Receive/transmit priority
The receive/transmit priority for the message objects is attached to the message number.
Message object 1 has the highest priority, while message object 32 has the lowest priority. If
more than one transmission request is pending, they are serviced accorng to the priority of
the corresponding message object.
18.9.3
Configuration of a transmit object
Figure 63 shows how a transmit object is initialized.
Figure 63. Initialisation of a transmit oect
MsgVal Arb Data Mask EoB Dir NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst
1
appl. appl. appl.
1
1
0
0
0
appl.
0
appl.
0
The arbitration registers (ID28-0 and Xtd bit) are given by the application. They define the
identifier and typof the outgoing message. If an 11-bit identifier (“standard frame”) is used,
it is programd to ID28 - ID18, ID17 - ID0 can be disregarded.
If the TIE bit is set, the IntPnd bit is be set after a successful transmission of the message
obect.
If the RmtEn bit is set, a matching received remote frame causes the TxRqst bit to be set;
the remote frame is autonomously answered by a Data Frame.
The data registers (DLC3-0, Data0-7) are given by the application, TxRqst and RmtEn may
not be set before the data is valid.
The mask registers (Msk28-0, UMask, MXtd, and MDir bits) may be used (UMask=’1’) to
allow groups of remote frames with similar identifiers to set the TxRqst bit. For details see
Section 18.9.2, handle with care; the Dir bit should not be masked.
18.9.4
Updating a transmit object
The CPU may update the data bytes of a transmit object any time via the IFx interface
registers, neither MsgVal nor TxRqst need be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding
IFx Data A Register or IFx Data B Register have to be valid before the content of that
register is transferred to the message object. Either the CPU has to write all four bytes into
176/328
ST10F252M
CAN modules
the IFx data register or the message object is transferred to the IFx data register before the
CPU writes the new data bytes.
When only the (eight) data bytes are updated, first, 0x0087 is written to the command mask
register and, then, the number of the message object is written to the command request
register, concurrently updating the data bytes and setting TxRqst.
To prevent the reset of TxRqst at the end of a transmission that may already be in progress
while the data is updated, NewDat is set together with TxRqst. For details see
Section 18.9.2.
When NewDat is set together with TxRqst, NewDat is reset as soon as the new
transmission has started.
18.9.5
Configuration of a receive object
Figure 64 shows how a receive object is initialized.
Figure 64. Initialization of a receive object
MsgVal Arb Data Mask EoB Dir NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst
1
appl. appl. appl.
1
0
0
0
appl.
0
0
0
0
The arbitration registers (ID28-0 and Xtd bit) are ven by the application. They define the
identifier and type of accepted received messages. If an 11-bit Identifier (“standard frame”)
is used, it is programmed to ID28 - IDID17 - ID0 can then be disregarded. When a data
frame with an 11-bit Identifier is received, ID17 - ID0 is set to ‘0’.
If the RxIE bit is set, the IntPnd bit is set when a received data frame is accepted and stored
in the message object.
The data length code (DLC3-0) is given by the application. When the message handler
stores a data frae in the message object, it stores the received data length code and eight
data bytes. If e data length code is less than eight, the remaining bytes of the message
object e overwritten by non specified values.
Thmask registers (Msk28-0, UMask, MXtd, and MDir bits) may be used (UMask=’1’) to
allow groups of data frames with similar identifiers to be accepted. For details see
Section 18.9.2. The Dir bit should not be masked in typical applications.
1.9.6
Handling of received messages
The CPU may read a received message any time via the IFx interface registers, the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the command mask register and then writes the
number of the message object to the command request register. This combination transfers
the whole received message from the message RAM into the message buffer register.
Additionally, the bits NewDat and IntPnd are cleared in the message RAM (not in the
message buffer).
If the message object uses masks for acceptance filtering, the arbitration bits show which of
the matching messages has been received.
The actual value of NewDat shows whether a new message has been received since last
time this message object was read. The actual value of MsgLst shows whether more than
177/328
CAN modules
ST10F252M
one message has been received since last time this message object was read. MsgLst is
not automatically reset.
By a remote frame, the CPU may request another CAN node to provide new data for a
receive object. Setting the TxRqst bit of a receive object causes the transmission of a
remote frame with the receive object’s identifier. This remote frame triggers the other CAN
node to start the transmission of the matching data frame. If the matching data frame is
received before the remote frame could be transmitted, the TxRqst bit is automatically reset.
18.9.7
Configuration of a FIFO buffer
With the exception of the EoB bit, the configuration of receive objects belonging to a FIFO
buffer is the same as the configuration of a (single) receive object, see Section 18.9.5.
To concatenate two or more message objects into a FIFO buffer, the identifiers and masks
(if used) of these message objects have to be programmed to matching values. Due to the
implicit priority of the message objects, the message object with the lowest number will be
the first message object of the FIFO buffer. The EoB bit of all message objects of a FIFO
buffer except the last have to be programmed to zero. The EoB bits of te last message
object of a FIFO buffer is set to one, configuring it as the end of the bock.
18.9.8
Reception of messages with FIFO buffers
Received messages with identifiers matching to a FIFO buffer are stored into a message
object of this FIFO buffer starting with the messae object with the lowest message number.
When a message is stored into a mesge bject of a FIFO buffer, the NewDat bit of this
message object is set. By setting Newt while EoB is zero, the message object is locked
for further write accesses by the message handler until the CPU has written the NewDat bit
back to zero.
Messages are stored into a FIFO buffer until the last message object of this FIFO buffer is
reached. If none of the preceding message objects is released by writing NewDat to zero, all
further messagefor this FIFO buffer are written into the last message object of the FIFO
buffer and, thefore, overwrite previous messages.
Reading from a FIFO buffer
When the CPU transfers the contents of message object to the IFx message buffer registers
by writing its number to the IFx command request register, the corresponding command
mask register is programmed such that bits NewDat and IntPnd are reset to zero
(TxRqst/NewDat = ‘1’ and ClrIntPnd = ‘1’). The values of these bits in the message control
register always reflect the status before resetting the bits.
To assure the correct function of a FIFO buffer, the CPU reads out the message objects
starting at the FIFO Object with the lowest message number.
Figure 65 shows how a set of message objects which are concatenated to a FIFO buffer can
be handled by the CPU.
178/328
ST10F252M
CAN modules
Figure 65. CPU Handling of a FIFO Buffer
START
Message Interrupt
Read Interrupt Pointer
case Interrupt Pointer
else
0x8000h
0x0000h
END
Status Change
Interrupt Handling
MessageNum = Interrupt Pointer
Write MessageNum to IFx Command Request
(Read Message to IFx Registers,
Reset NewDat = 0,
Reset IntPnd = 0)
Read IFx MessControl
No
NewDat = 1
Yes
Read Data from IFx Data A,B
Yes
EoB = 1
No
MessageNum = MessageNum + 1
18.9.9
Handling of interrupts
If several interrupts are pending, the CAN interrupt register points to the pending interrupt
with the highest priority, disregarding their chronological order. An interrupt remains pending
until the CPU has cleared it.
The status interrupt has the highest priority. Among the message interrupts, the message
object’ s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the message object’s IntPnd bit. The status
interrupt is cleared by reading the status register.
179/328
CAN modules
ST10F252M
The interrupt identifier IntId in the interrupt register indicates the cause of the interrupt.
When no interrupt is pending, the register holds the value zero. If the value of the interrupt
register is not zero, there is an interrupt pending and, if IE is set, the interrupt line to the
CPU, IRQ_B, is active. The interrupt line remains active until the interrupt register is back to
value zero (the cause of the interrupt is reset) or until IE is reset.
The value 0x8000 indicates that an interrupt is pending because the CAN core has updated
(not necessarily changed) the status register (error interrupt or status interrupt). This
interrupt has the highest priority. The CPU can update (reset) the status bits RxOk, TxOk
and LEC, but a write access of the CPU to the status register can never generate or reset an
interrupt.
All other values indicate that the source of the interrupt is one of the message objects, IntId
points to the pending message interrupt with the highest interrupt priority.
The CPU controls whether a change of the status register may cause an interrupt (bits EIE
and SIE in the CAN control register) and whether the interrupt line becomes active when the
interrupt register is not zero (bit IE in the CAN control register). The interrupt register is
updated even when IE is reset.
The CPU has two possibilities to follow the source of a message interrupt. First it can follow
the IntId in the interrupt register and second it can poll the interupt pending register (see
Section 18.8.5).
An interrupt service routine reading the message thais the source of the interrupt may read
the message and reset the message object’s Intd at the same time (bit ClrIntPnd in the
command mask register). When IntPnd is cleared, the interrupt register points to the next
message object with a pending interru
18.9.10 Configuration of bit timing
Even if minor errors in the configuration of the CAN bit timing do not result in immediate
failure, the performance of a CAN network can be reduced significantly.
In many cases, e CAN bit synchronization amends a faulty configuration of the CAN bit
timing to such a degree that only an occasional error frame is generated. In the case of
arbitraton however, when two or more CAN nodes simultaneously try to transmit a frame, a
misplaced sample point may cause one of the transmitters to become error passive.
The analysis of such sporadic errors requires a detailed knowledge of the CAN bit
synchronization inside a CAN node and of the CAN nodes’ interaction on the CAN bus.
Bit time and bit rate
CAN supports bit rates in the range of lower than 1 kBit/s up to 1000 kBit/s. Each member of
the CAN network has its own clock generator, usually a quartz oscillator. The timing
parameter of the bit time (that is, the reciprocal of the bit rate) can be configured individually
for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator
periods (f ) may be different.
osc
The frequencies of these oscillators are not absolutely stable, small variations are caused
by changes in temperature or voltage and by deteriorating components. As long as the
variations remain inside a specific oscillator tolerance range (df), the CAN nodes are able to
compensate for the different bit rates by resynchronising to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see
Figure 66):
180/328
ST10F252M
CAN modules
1. the synchronization segment
2. the propagation time segment
3. the phase buffer segment 1
4. the phase buffer segment 2.
Each segment consists of a specific, programmable number of time quanta (see Table 110).
The length of the time quantum (t , which is the basic time unit of the bit time, is defined by
q)
the CAN controller’s system clock f
and the baud rate prescaler (BRP): t = BRP / f
.
sys
q
sys
The C-CAN’s system clock f is the frequency of its CAN module clock input.
sys
The synchronization segment, Sync_Seg, is that part of the bit time where edges of the
CAN bus level are expected to occur; the distance between an edge that occurs outside of
Sync_Seg and the Sync_Seg is called the phase error of that edge. The propagation time
segment, Prop_Seg, is intended to compensate for the physical delay times within the CAN
network. The phase buffer segments, Phase_Seg1 and Phase_Seg2, surround the sample
point. the (re-)synchronisation jump width (SJW) defines how far a resynchronisation may
move the sample point inside the limits defined by the phase buffer segments to
compensate for edge phase errors.
Figure 66. Bit timing
Nominal CAN Bit Time
Sync_
Seg
Prop_Seg
Phase_Se
Phase_Seg2
1 Time Quantum
( t
)
Sample Point
q
Table 110. Parameters of the CAN bit time
Parameter
Range
Remark
defines the length of the time quantum
BRP
[1 .. 32]
tq
Sync_Seg
Prop_Seg
Phase_Seg1
Phase_Seg2
SJW
1
fixed length, synchronisation of bus input to system clock
compensates for the physical delay times
tq
[1 .. 8]
[1 .. 8]
[1 .. 8]
[1 .. 4]
tq
tq
tq
tq
may be lengthened temporarily by synchronisation
may be shortened temporarily by synchronisation
may not be longer than either Phase Buffer Segment
This table describes the minimum programmable ranges required by the CAN protocol
A given bit rate may be met by different bit time configurations but, for the proper function of
the CAN network, the physical delay times and the oscillator’s tolerance range have to be
considered.
Propagation time segment
This part of the bit time is used to compensate physical delay times within the network.
These delay times consist of the signal propagation time on the bus and the internal delay
time of the CAN nodes.
181/328
CAN modules
ST10F252M
Any CAN node synchronized to the bit stream on the CAN bus is out of phase with the
transmitter of that bit stream, caused by the signal propagation time between the two nodes.
The CAN protocol’s non-destructive bitwise arbitration and the dominant acknowledge bit
provided by receivers of CAN messages require that a CAN node transmitting a bit stream
must also be able to receive dominant bits transmitted by other CAN nodes that are
synchronized to that bit stream. The example in Figure 67 shows the phase shift and
propagation times between two CAN nodes.
Figure 67. The propagation time segment
Sync_Seg
Prop_Seg
Phase_Seg1
Phase_Seg2
Node B
Node A
Delay A_to_B
Delay B_to_A
Delay A_to_B >= node output delay(A) + bus le delay(A→B) + node input delay(B)
Prop_Seg
Prop_Seg
>= Delay A_to_B + Delay o_A
>= 2 • [max(node oput delay+ bus line delay + node input delay)]
In this example, both nodes A and B are transmitters performing an arbitration for the CAN
bus. The node A has sent its start of frame bit less than one bit time earlier than node B,
therefore, node B has synchronized itself to the received edge from recessive to dominant.
Since node B has received this edge delay(A_to_B) after it has been transmitted, B’s bit
timing segments are shifted with regard to A. Node B sends an identifier with higher priority
and so it wins tharbitration at a specific identifier bit when it transmits a dominant bit while
node A transmits a recessive bit. The dominant bit transmitted by node B arrives at node A
after thdelay(B_to_A).
Due to oscillator tolerances, the actual position of node A’s sample point can be anywhere
inside the nominal range of node A’s phase buffer segments, so the bit transmitted by node
B must arrive at node A before the start of Phase_Seg1. This condition defines the length of
Prop_Seg.
If the edge from recessive to dominant transmitted by node B arrives at node A after the
start of Phase_Seg1, it could happen that node A samples a recessive bit instead of a
dominant bit, resulting in a bit error and the destruction of the current frame by an error flag.
The error occurs only when two nodes arbitrate for the CAN bus that have oscillators of
opposite ends of the tolerance range and that are separated by a long bus line; this is an
example of a minor error in the bit timing configuration (Prop_Seg too short) that causes
sporadic bus errors.
Some CAN implementations provide an optional three-sample mode The C-CAN does not.
In this mode, the CAN bus input signal passes a digital low-pass filter, using three samples
and a majority logic to determine the valid bit value. This results in an additional input delay
of 1 t , requiring a longer Prop_Seg.
q
182/328
ST10F252M
CAN modules
Phase buffer segments and synchronisation
The phase buffer segments (Phase_Seg1 and Phase_Seg2) and the synchronisation jump
width (SJW) are used to compensate for the oscillator tolerance. The phase buffer segments
may be lengthened or shortened by synchronisation.
Synchronizations occur on edges from recessive to dominant, their purpose is to control the
distance between edges and sample points.
Edges are detected by sampling the actual bus level in each time quantum and comparing it
with the bus level at the previous sample point. A synchronisation may be done only if a
recessive bit was sampled at the previous sample point and if the actual time quantum’s bus
level is dominant.
An edge is synchronous if it occurs inside of Sync_Seg, otherwise the distance between
edge and the end of Sync_Seg is the edge phase error, measured in time quanta. If the
edge occurs before Sync_Seg, the phase error is negative, else it is positive.
Two types of synchronisation exist: hard synchronisation and resynchronisation. A hard
synchronisation is done once at the start of a frame; inside a frame onlesynchronisations
occur.
●
Hard synchronisation
After a hard synchronisation, the bit time is restarted with the end of Sync_Seg,
regardless of the edge phase error. Thus hard snchronisation forces the edge which
has caused the hard synchronisation to lie wthin the synchronisation segment of the
restarted bit time.
●
Bit resynchronisation
Resynchronisation leads to a shortening or lengthening of the bit time such that the
position of the sample point is shifted with regard to the edge.
When the phase error of the edge which causes resynchronisation is positive,
Phase_Seg1 is lengthened. If the magnitude of the phase error is less than SJW,
Phase_Seg1 is lengthened by the magnitude of the phase error, else it is lengthened
by SJW.
When thphase error of the edge which causes resynchronisation is negative,
Pse_Seg2 is shortened. If the magnitude of the phase error is less than SJW,
Phase_Seg2 is shortened by the magnitude of the phase error, else it is shortened by
SJW.
When the magnitude of the phase error of the edge is less than or equal to the programmed
value of SJW, the results of hard synchronisation and resynchronisation are the same. If the
magnitude of the phase error is larger than SJW, the resynchronisation cannot compensate
the phase error completely, an error of (phase error - SJW) remains.
Only one synchronisation may be done between two sample points. The synchronisations
maintain a minimum distance between edges and sample points, giving the bus level time to
stabilize and filtering out spikes that are shorter than (Prop_Seg + Phase_Seg1).
Apart from noise spikes, most synchronisations are caused by arbitration. All nodes
synchronize “hard” on the edge transmitted by the “leading” transceiver that started
transmitting first, but due to propagation delay times, they cannot become ideally
synchronized. The “leading” transmitter does not necessarily win the arbitration, therefore
the receivers have to synchronize themselves to different transmitters that subsequently
“take the lead” and that are differently synchronized to the previously “leading” transmitter.
The same happens at the acknowledge field, where the transmitter and some of the
183/328
CAN modules
ST10F252M
receivers will have to synchronize to that receiver that “takes the lead” in the transmission of
the dominant acknowledge bit.
Synchronisations after the end of the arbitration are caused by oscillator tolerance, when the
differences in the oscillator’s clock periods of transmitter and receivers sum up during the
time between synchronisations (at most ten bits). These summarized differences may not
be longer than the SJW, limiting the oscillator’s tolerance range.
The examples in Figure 68 show how the phase buffer segments are used to compensate
for phase errors. There are three drawings of each two consecutive bit timings. The upper
drawing shows the synchronisation on a “late” edge, the lower drawing shows the
synchronisation on an “early” edge, and the middle drawing is the reference without
synchronisation.
Figure 68. Synchronisation on “late” and “early” edges
recessive
dominant
“late” Edge
Rx-Input
Sample-Point
Sample-Point
Sample-Point
Sample-Poi
Sample-Point
Sample-Point
recessive
dominant
“early” Edge
Prop_Seg Phase_Seg1
Rx-Input
Sync_Seg
Phase_Seg2
In the first example an edge from recessive to dominant occurs at the end of Prop_Seg. The
edge is “late” since it occurs after the Sync_Seg. Reacting to the “late” edge, Phase_Seg1 is
lengthened so that the distance from the edge to the sample point is the same as it would
have been from the Sync_Seg to the sample point if no edge had occurred. The phase error
of this “late” edge is less than SJW, so it is fully compensated and the edge from dominant
to recessive at the end of the bit, which is one nominal bit time long, occurs in the
Sync_Seg.
In the second example an edge from recessive to dominant occurs during Phase_Seg2. The
edge is “early” since it occurs before a Sync_Seg. Reacting to the “early” edge, Phase_Seg2
is shortened and Sync_Seg is omitted, so that the distance from the edge to the sample
point is the same as it would have been from an Sync_Seg to the sample point if no edge
had occurred. As in the previous example, the magnitude of this “early” edge’s phase error is
less than SJW, so it is fully compensated.
The phase buffer segments are lengthened or shortened temporarily only; at the next bit
time, the segments return to their nominal programmed values.
In these examples, the bit timing is seen from the point of view of the CAN implementation’s
state machine, where the bit time starts and ends at the sample points. The state machine
184/328
ST10F252M
CAN modules
omits Sync_Seg when synchronizing on an “early” edge because it cannot subsequently
redefine that time quantum of Phase_Seg2 where the edge occurs to be the Sync_Seg.
The examples in Figure 69 show how short dominant noise spikes are filtered by
synchronisations. In both examples the spike starts at the end of Prop_Seg and has the
length of (Prop_Seg + Phase_Seg1).
Figure 69. Filtering of short dominant spikes
recessive
dominant
Spike
Rx-Input
Sample-Point
Sample-Point
SJW ≥ Phase Error
recessive
dominant
Spike
Rx-Input
Sample-Point
Sample-Point
SJW < Phase Error
Sync_Seg
Prop_Seg
Phase_Seg1
Phase_Seg2
In the first example, the synchronisation jump width is greater than or equal to the phase
error of the spike’s edge from recessive to dominant. Therefore, the sample point is shifted
after the end of the spike; a recessive bus level is sampled.
In the seconxample, SJW is shorter than the phase error, so the sample point cannot be
shifted r enough; the dominant spike is sampled as actual bus level.
Oscillator tolerance range
The oscillator tolerance range was increased when the CAN protocol was developed from
version 1.1 to version 1.2 (version 1.0 was never implemented in silicon). The option to
synchronize on edges from dominant to recessive became obsolete, only edges from
recessive to dominant are considered for synchronisation. The protocol update to version
2.0 (A and B) had no influence on the oscillator tolerance.
The tolerance range df for an oscillator’s frequency f
around the nominal frequency f
nom
osc
with (1 – df) • fnom ≤fosc ≤(1 + df) • fnom depends on the proportions of Phase_Seg1,
Phase_Seg2, SJW, and the bit time. The maximum tolerance df is the defined by two
conditions (both must be met):
min(Phase_Seg1 , Phase_Seg2)
I:
df = -----------------------------------------------------------------------------------------------
2 ⋅ (13 ⋅ bit_time – Phase_Seg2)
SJW
II: df = ------------------------------------
20 ⋅ bit_time
185/328
CAN modules
ST10F252M
It has to be considered that SJW may not be larger than the smaller of the phase buffer
segments and that the propagation time segment limits that part of the bit time that may be
used for the phase buffer segments.
The combination Prop_Seg = 1 and Phase_Seg1 = Phase_Seg2 = SJW = 4 allows the
largest possible oscillator tolerance of 1.58%. This combination with a propagation time
segment of only 10% of the bit time is not suitable for short bit times; it can be used for bit
rates of up to 125 kBit/s (bit time = 8 μs) with a bus length of 40 m.
Configuration of the CAN protocol controller
In most CAN implementations and also in the C-CAN, the bit timing configuration is
programmed in two register bytes. The sum of Prop_Seg and Phase_Seg1 (as TSEG1) is
combined with Phase_Seg2 (as TSEG2) in one byte, SJW and BRP are combined in the
other byte (see Figure 70).
In these bit timing registers, the four components TSEG1, TSEG2, SJW, and BRP have to
be programmed to a numerical value that is one less than its functional value; so instead of
values in the range of [1...n], values in the range of [0...n-1] are programmed. That way, e.g.
SJW (functional range of [1...4]) is represented by only two bits.
Therefore the length of the bit time is (programmed values) [TSEG1 + TSEG2 + 3] t or
q
(functional values) [Sync_Seg + Prop_Seg + Phase_Seg+ Phase_Seg2] t .
q
Figure 70. Structure of the CAN Core’s CAN Protocol Controller
ConfiguratioBRP)
System Clock
ScaledClock (tq)
Baudrate
Control
Status
Prescaler
Sample_Point
Sampled_Bit
Sync_Mode
Bit
Receive_Data
TransData
Timing
Logic
Bit_to_send
Bus_Off
Received_Data_Bit
Send_Message
Control
Shift-Register
Received_Message
Next_Data_Bit
Configuration (TSEG1, TSEG2, SJW)
The data in the bit timing registers are the configuration input of the CAN protocol controller.
The baud rate prescaler (configured by BRP) defines the length of the time quantum, the
basic time unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW)
defines the number of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the sample point, and
occasional synchronizations are controlled by the BTL state machine, which is evaluated
once each time quantum. The rest of the CAN protocol controller, the bit stream processor
(BSP) state machine is evaluated once each bit time, at the sample point.
The shift register serializes the messages to be sent and parallelize received messages. Its
loading and shifting is controlled by the BSP.
186/328
ST10F252M
CAN modules
The BSP translates messages into frames and vice versa. It generates and discards the
enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC
code, performs the error management, and decides which type of synchronization is to be
used. It is evaluated at the sample point and processes the sampled bus input bit. The time
after the sample point that is needed to calculate the next bit to be sent (for example, data
bit, CRC bit, stuff bit, error flag, or idle) is called the information processing time (IPT).
The IPT is application specific but may not be longer than 2 t ; the C-CAN’s IPT is 0 t . Its
q
q
length is the lower limit of the programmed length of Phase_Seg2. For a synchronization,
Phase_Seg2 may be shortened to a value less than IPT, which does not affect bus timing.
Calculation of the bit timing parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time.
The resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta, the length of the time quantum t is defined
q
by the baud rate prescaler with t = (Baud Rate Prescaler)/f . Several combinations may
q
sys
lead to the desired bit time, allowing iterations of the following steps.
The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay
times measured in the system. A maximum bus length as well as a maximum node delay
has to be defined for expandible CAN bus systems. The rsulting time for Prop_Seg is
converted into time quanta (rounded up to the nearest integer multiple of t ).
q
The Sync_Seg is 1 t long (fixed), leaving (bit tim– Prop_Seg – 1) t for the two phase
q
q
buffer segments. If the number of remaining t is even, the phase buffer segments have the
q
same length, Phase_Seg2 = Phase_1, else Phase_Seg2 = Phase_Seg1 + 1.
The minimum nominal length of Phase_Seg2 must be considered as well. Phase_Seg2 may
not be shorter than the CAN controller’s information processing time, which is, depending on
the actual implementation, in the range of [0...2] t .
q
The length of the synchronization jump width is set to its maximum value, which is the
minimum of four nd Phase_Seg1.
The oscillator tolerance range necessary for the resulting configuration is calculated by the
formulae given in Section 18.9.10
If more than one configuration is possible, that configuration allowing the highest oscillator
tolerance range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same
bit rate. The calculation of the propagation time in the CAN network, based on the nodes
with the longest delay times, is done once for the whole network.
The CAN system’s oscillator tolerance range is limited by that node with the lowest tolerance
range.
The calculation may show that bus length or bit rate have to be decreased or that the
oscillator frequencies’ stability has to be increased in order to find a protocol compliant
configuration of the CAN bit timing.
The resulting configuration is written into the bit timing register:
(Phase_Seg2 - 1) and (Phase_Seg1 + Prop_Seg - 1) and (SynchronisationJumpWidth - 1)
and (Prescaler - 1).
187/328
CAN modules
ST10F252M
Example for bit timing at high baud rate
In this example, the frequency of CAN module clock is 10 MHz, BRP is 0, the bit rate is 1 MBit/s
.
t
100 ns = t
q
CAN_CLK
delay of bus driver
50
ns
ns
delay of receiver circuit 30
delay of bus line (40m) 220 ns
t
t
t
t
t
600 ns = 6 x t
Prop
q
q
100 ns = 1 x t
700 ns = t
SJW
+ t
SJW
TSeg1
TSeg2
Sync-Seg
Prop
200 ns = Information Processing Time + 1 • t
q
100 ns = 1 x t
q
bit time
1000 ns = t
+ t
+ t
Sync-Seg
TSeg1 TSeg
min (PB1 , B2)
2 ⋅ (13 ⋅ bit_time – PB2)
--------------------------------------------------------------------
tolerance for CAN clock 0.39 %
=
=
0.1μs
----------------------------------------------------------
2 ⋅ (13 ⋅ 1μs – 0.2μs)
In this example, the concatenated bit tie rameters are (2-1) & (7-1) & (1-1) & (1-1) ,
3
4
2
6
the bit timing register is programmed t0x1600.
Example for bit timing at low baud rate
In this example, the frequency of CAN module clock is 2 MHz, BRP is 1, the bit rate is 100 KBit/s.
t
1
μs = 2 x t
CAN_CLK
q
delay bus driver
elay of receiver circuit 80
delay of bus line (40m) 220 ns
200 ns
ns
t
t
t
t
t
1
μs = 1 x t
μs = 4 x t
Prop
q
4
SJW
q
5
μs = t
+ t
TSeg1
TSeg2
Sync-Seg
Prop
SJW
4
μs = Information Processing Time + 3 • t
q
1
μs = 1 x t
q
bit time
10
μs = t
+ t
+ t
Sync-Seg
TSeg1 TSeg2
min (PB1 , PB2)
2 ⋅ (13 ⋅ bit_time – PB2)
----------------------------------------------------------------------
tolerance for CAN clock 1.58 %
=
=
4μs
----------------------------------------------------------
2 ⋅ (13 ⋅ 10μs – 4μs)
In this example, the concatenated bit time parameters are (4-1) & (5-1) & (4-1) & (2-1) ,
3
4
2
6
the bit timing register is programmed to= 0x34C1.
188/328
ST10F252M
Watchdog timer
19
Watchdog timer
The watchdog timer is a fail-safe mechanism which prevents the microcontroller from
malfunctioning for long periods of time. The watchdog timer is always enabled after a reset
of the chip (just after PORT0 latching) and can only be disabled in the time interval until the
EINIT (end of initialization) instruction has been executed. Therefore, the chip’s start-up
procedure is always monitored. The software is designed to service the watchdog timer
before it overflows. If, due to hardware or software related failures, the software fails to do
so, the watchdog timer overflows and generates an internal hardware reset. It pulls the
RSTOUT pin low to allow external hardware components to be reset.
Each of the different reset sources is indicated in the WDTCON register. The indicated bits
are cleared with the EINIT instruction. It is, thus, possible to identify the reset during the
initialization phase. The mechanism only detects a failure on the internal 1.8V, not on the
external power supply (V ).
DD
WDTCON register
WDTCON register (FFAEh/D7h)
SFR
Reset value: 00xxh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SHW
R
WDTI
N
WDTREL
RW
Resered
-
PONR LHWR
SWR WDTR
R
R
R
R
R
RW
Table 111. WDTCON register functions
Bit
Name
Function
Watchdog timer input frequency selection
‘0’: Input frequency is fCPU/2.
0
WDTIN
‘1’: Input frequency is fCPU/128.
Watchdog timer reset indication flag
1
WDTR (1) (3)
Set by the watchdog timer on an overflow. Cleared by a hardware reset
or by the SRVWDT instruction.
Software reset indication flag
2
3
4
SWR (1)(3)
SHWR (1)(3)
LHWR (1)(3)
Set by the SRST execution. Cleared by the EINIT instruction.
Short hardware reset indication flag
Set by the input RSTIN. Cleared by the EINIT instruction.
Long hardware reset indication flag
Set by the input RSTIN. Cleared by the EINIT instruction.
Power-on (asynchronous) reset indication flag
5
PONR(1)(2)(3)
WDTREL
Set by the input RSTIN if a power-on condition has been detected.
Cleared by the EINIT instruction.
15:8
Watchdog timer reload value (for the high byte)
1. More than one reset indication flag may be set. After EINIT, all flags are cleared.
2. Power-on is detected when a ramp on internal 1.8V (generated by the on-chip voltage regulator) is
detected.
3. These bits cannot be directly modified by software.
189/328
Watchdog timer
ST10F252M
WDTR
Table 112. Reset flag settings
Reset Source
Power On Reset
PONR
LHWR
SHWR
SWR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Power On after a partial supply failure (see Note)
Long Hardware Reset
Short Hardware Reset
Software Reset
Watchdog Reset
X
Note:
PONR bit may not be set for short supply failure.
If a bi-directional reset is enabled and if the RSTIN pin is latched low after the end of the
internal reset sequence, a short hardware reset, a software reset or a watchdog reset
triggers a long hardware reset. Thus, reset indications flags are set to indicate a long
hardware reset.
190/328
ST10F252M
System reset
20
System reset
System reset initializes the device in a predefined state. There are many ways to activate a
reset state. The system start-up configuration is different for each case as shown in
Table 113. The reset history is flagged inside WDTCON register (see also Chapter 19 for
additional details).
Table 113. Reset event definition
RPD
Reset Source
Flag
Conditions
Status
Power-on reset
PONR
Low
Low
Power-on
(1)
Asynchronous hardware reset
tRSTIN >
LHWR
SHWR
Synchronous long hardware
reset
tRSTIN > (1032 + 12) TCL + max(4 TCL,
500ns)
High
High
tRSTIN > max(4 TCL500ns)
Synchronous short hardware
reset (2)
tRSTIN ≤(1032 + 12) TCL + max(4 TCL,
500ns)
(3)
(3)
Watchdog timer reset
Software reset
WDTR
SWR
WDT overflow
SRST instruction execution
1. RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of PORT0.
2. See Section 20.1 for more details on minimrest pulse duration.
3. The RPD status has no influence unless bidirectional reset is activated (bit BDRSTEN in SYSCON): RPD low inhibits the
bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to Section 20.4, Section 20.5 and
Section 20.6).
20.1
Input filter
On RSN input pin, there is an on-chip RC filter. This filter is sized to filter all the spikes
shorter than 50 ns. A valid pulse must be longer than 500 ns before the ST10 recognizes a
reset command. Between 50 ns and 500 ns a pulse can either be filtered or recognized as
valid, depending on the operating conditions and process variations.
For this reason all minimum durations, mentioned in this chapter for the different kind of
reset events, should be carefully evaluated taking into account of the above requirements.
In particular, for short hardware reset, where only 4 TCL is specified as minimum input reset
pulse duration, the operating frequency is a key factor. For example:
●
for a CPU clock of 40 MHz, 4 TCL is 50 ns, so it would be filtered; in this case the
minimum becomes the one imposed by the filter (that is 500 ns)
●
for a CPU clock of 4 MHz, 4 TCL is 500 ns; in this case the minimum from the formula
is coherent with the limit imposed by the filter.
191/328
System reset
ST10F252M
20.2
Asynchronous reset
An asynchronous reset is triggered when RSTIN pin is pulled low while the RPD pin is low.
The ST10F252M is immediately (after the input filter delay) forced in reset default state. It
pulls low the RSTOUT pin, it cancels pending internal hold states if any, it aborts all
internal/external bus cycles, it switches buses (data, address and control signals) and I/O
pin drivers to high-impedance, it pulls high PORT0 pins.
Note:
If an asynchronous reset occurs during a read or write phase in internal memories, the
content of the memory itself could be corrupted. To avoid this, synchronous reset use is
strongly recommended.
Power-on reset
Asynchronous reset must be used during the power-on of the device. Depending on crystal
or resonator frequency, the on-chip oscillator needs about 1 ms to 10 ms to stabilize (refer to
Section 27.8.2), with an already stable V . The logic of the ST10F252M does not need a
DD
stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on
conditions. To ensure a proper reset sequence, the RSTIN pin and the PD pin must be
held at low level until the device clock signal is stabilized and the systm configuration value
on PORT0 is settled.
At power-on it is important to consider some additional constraints introduced by the
start-up phase of the different embedded modules.
In particular the on-chip voltage regulator needs at least 1 ms to stabilize the internal 1.8 V
for the core logic – this time is computed frm when the external reference (V ) becomes
DD
stable (inside specification range, that least 4.5 V). This is a constraint for the
application hardware (external voltage regulator). The RSTIN pin assertion should be
extended to guarantee the voltage regulator stabilization.
A second constraint is imposed by the embedded Flash. When booting from internal
memory, starting from the release of RSTIN, it needs a maximum of 1 ms for its initialization;
before that, the iternal reset (RST signal) is not released, so the CPU does not start code
execution in ernal memory.
Note:
This is ot true if external memory is used (pin EA held low during reset phase). In this case,
once RSTIN pin is released, and after few CPU clock pulses (filter delay plus 3...8 TCL), the
internal reset signal RST is released, so the code execution can start immediately. Access
to the data in internal Flash is forbidden before its initialization phase is completed; an
attempted access during the start-up phase returns FFFFh (just at the beginning), while
later 009Bh (an illegal opcode trap is generated).
At power-on, the RSTIN pin is tied low for a minimum time that includes also the start-up
time of the main oscillator (t
= 1 ms for resonator, 10 ms for crystal) and PLL
STUP
synchronization time (t
= 200 µs). This means that, if the internal Flash is used, the
PSUP
RSTIN pin could be released before the main oscillator and PLL are stable to recover some
time in the start-up phase (Flash initialization only needs stable V , but does not need
18
stable system clock since an internal dedicated oscillator is used).
192/328
ST10F252M
System reset
Warning: It is recommended to provide the external hardware with a
current limitation circuitry. This is necessary to avoid
permanent damage to the device during the power-on
transient, when the capacitance on V pin is charged. For
18
the on-chip voltage regulator functionality, 10 nF is sufficient.
However, a maximum of 100 nF on the V pin should not
18
generate problems of over-current (higher value is allowed if
current is limited by the external hardware). External current
limitation is also recommended to avoid risk of damage in the
event of a temporary short between V and ground. The
18
internal 1.8V drivers are sized to drive currents of several
tens of Amperes, so the current should be limited by the
external hardware. The limit of current is imposed by power
dissipation considerations (refer to Section 27.3 for details).
In the next Figure 71 and 72 Asynchronous Power-on timing diagramare shown,
respectively with boot from internal or external memory, highlihting the reset phase
extension introduced by the embedded Flash module when selected.
193/328
System reset
ST10F252M
Figure 71. Asynchronous power-on RESET (EA=1)
≤1.2 ms (for resonator oscillation + PLL stabilization)
≤10.2 ms (for crystal oscillation + PLL stabilization)
≥ 1 ms (for on-chip VREG stabilization)
V
V
DD
18
≤2 TCL
...
XTAL1
RPD
RSTIN
≥ 50 ns
≤500 ns
RSTF
(After Filter)
3..4 TCL
transparent
not t.
not t.
not t.
P0[15:13]
P0[12:2]
P0[1:0]
transparent
ot transparent
not t.
7 TCL
IBUS-CS
(Internal)
≤1 ms
FLARST
RST
Latching point of Port0 for
system start-up configuration
194/328
ST10F252M
System reset
Figure 72. Asynchronous power-on RESET (EA=0)
≥ 1.2 ms (for resonator oscillation + PLL stabilization)
≥ 10.2 ms (for crystal oscillation + PLL stabilization)
≥ 1 ms (for on-chip VREG stabilization)
V
V
DD
(1)
3..8 TCL
18
...
XTAL1
RPD
RSTIN
≥ 50 ns
≤500 ns
RSTF
(After Filter)
34 TCL
transparent
transparent
P0[15:13]
P0[12:2]
P0[1:0]
ALE
not t.
not t.
not transparent
not t.
8 TCL
RST
Latching point of Port0 for
system start-up configuration
1. 3 to 8 TCL depending on clock source selection.
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the
application. It may be triggered by the hardware of the application. Internal hardware logic
and application circuitry are described in Section 20.7 and Figure 84, Figure 85 and
Figure 86. It occurs when RSTIN is low and RPD is detected (or becomes) low as well.
195/328
System reset
Figure 73. Asynchronous hardware RESET (EA=1)
ST10F252M
(1)
≤2 TCL
RPD
≥ 50 ns
≤500 ns
RSTIN
≥ 50 ns
≤500 ns
RSTF
(After Filter)
3..4 TCL
transparent
transparent
not t.
P0[15:13]
P0[12:2]
P0[1:0]
not transparent
not t.
not t.
not t.
not transparent
not transparent
7 TCL
IBUS-CS
(internal)
≤1 ms
FLARST
RST
Latching point of Port0 for
system start-up configuration
1. Longer than Portsettling time + PLL synchronization (if needed, that is P0(15:13) changed)
Longer than 500to take into account of Input Filter on RSTIN pin
196/328
ST10F252M
System reset
Figure 74. Asynchronous hardware RESET (EA=0)
(1)
(2)
3..8 TCL
RPD
≥ 50 ns
≤500 ns
RSTIN
≥ 50 ns
≤500 ns
RSTF
(After Filter)
3..4 TCL
transparent
transparent
P0[15:13]
P0[12:2]
P0[1:0]
ALE
not transparent
not transparent
not t.
not.
not t.
not transparent
8 TCL
RST
Latching point of Port0 for
system start-up configuration
1. Longer than Portsettling time + PLL synchronization (if needed, that is P0(15:13) changed)
Longer than 500to take into account of Input Filter on RSTIN pin
2. 3 to 8 TCL depending on clock source selection.
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts. As already mentioned, if internal
Flash is used, the restarting occurs after the embedded Flash initialization routine is
completed. The system configuration is latched from PORT0: ALE, RD and WR/WRL pins
are driven to their inactive level. The ST10F252M starts program execution from memory
location 00'0000h in code segment 0. This starting location will typically points to the
general initialization routine. The timing of asynchronous hardware reset sequence are
summarized in Figure 73 and Figure 74.
20.3
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (two periods of CPU clock): refer also to Section 20.1 for
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
197/328
System reset
ST10F252M
cancelled and the current internal access cycle if any is completed. The external bus cycle
is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
register was previously set by software. This bit is always cleared on power-on or after a
reset sequence.
Short and long synchronous reset
Once the first maximum 16 TCL are elapsed (4+12 TCL), the internal reset sequence starts.
It is 1024 TCL cycles long. At the end of the sequence and after another 8 TCL, the level of
RSTIN is sampled (after the filter, see RSTF in the drawings). If it is already at high level,
only a short reset is flagged (refer to Chapter 19 for details on reset flags); if it is recognized
as still low, a long reset is flagged. The major difference between long and short reset is that
during the long reset, P0(15:13) also becomes transparent, so it is possible to change the
clock options.
WARNING:
Warning: For a short pulse on RSTIN pin and when bidirectional reset
is enabled, the RSTIN pin is held low by he internal circuitry.
At the end of the 1024 TCL cycles, the RTSIN pin is released
but, due to the presence of the inpuanalog filter, the internal
input reset signal (RSTF in the drawings) is released later
(from 50 to 500 ns). This deay is in parallel with the
additional 8 TCL, at the end of which the internal input reset
line (RSTF) is samleto decide if the reset event is short or
long. In particular
The same behavior occurs also when unidirectional reset is
selected and RSTIN pin is held low till the end of the internal
sequence (exactly 1024 TCL + max 16 TCL) and released
exactly at that time.
●
●
if 8 TCL > 500 ns (F
if 8 TCL < 500 ns (F
< 8 MHz), the reset event is always recognized as Short
> 8MHz), the reset event could be recognized either as Short
CPU
CPU
or Long, depending on the real filter delay (between 50 and 500 ns) and the CPU
frequency (RSTF sampled high means Short reset, RSTF sampled low means Long
reset). Note that in case a Long reset is recognized, once the 8 TCL are elapsed, the
P0(15:13) pins becomes transparent, so the system clock can be re-configured. The
port returns not transparent 3-4 TCL after the internal RSTF signal becomes high.
The same behavior just described, occurs also when unidirectional reset is selected and
RSTIN pin is held low till the end of the internal sequence (exactly 1024TCL + max 16 TCL)
and released exactly at that time.
Note:
When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be
recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns);
so it might happen that a short reset pulse is not filtered by the analog input filter, but on the
other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would
generate a Flash reset but not a system reset. In this condition, the Flash answers always
with FFFFh, which leads to an illegal opcode and consequently a trap event is generated.
198/328
ST10F252M
System reset
Exit from synchronous reset state
The reset sequence is extended until RSTIN level becomes high. Moreover, it is internally
prolonged by the Flash initialization when EA=1 (internal memory selected). Then, the code
execution restarts. The system configuration is latched from PORT0, and ALE, RD and
WR/WRL pins are driven to their inactive level. The ST10F252M starts program execution
from memory location 00'0000h in code segment 0. This starting location will typically points
to the general initialization routine. Timing of synchronous reset sequence is summarized in
Figure 75 and Figure 76 where a Short reset event is shown, with particular emphasis on
the fact that it can degenerate into Long reset: the two figures show the behavior when
booting from internal or external memory respectively. Figure 77 and 78 report the timing of
a typical synchronous Long reset, again when booting from internal or external memory.
Synchronous reset and RPD pin
Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a
Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance
(if any) on the RPD pin is slowly discharged through the internal weak pull-down. If the
voltage level on the RPD pin reaches the input low threshold (approximtely 2.5 V), the
reset event becomes immediately asynchronous. In case of hadware reset (short or long)
the situation goes immediately to the one illustrated in Figure 73. There is no effect if RPD
comes again above the input threshold: the asynchronous reset is completed coherently. To
correctly complete a synchronous reset, the value of he capacitance should be big enough
to maintain a sufficiently high voltage on the RPD pin for the duration of the internal reset
sequence.
For a Software or Watchdog reset evean active synchronous reset is completed
regardless of the RPD status.
It is important to highlight that the signal that makes RPD status transparent under reset is
the internal RSTF (after the noise filter).
199/328
System reset
Figure 75. Synchronous short / long hardware RESET (EA=1)
ST10F252M
(4)
≤4 TCL
≤12 TCL
< 1032 TCL
(1)
(3)
RSTIN
≥ 50 ns
≤500 ns
≥ 50 ns
≤500 ns
≥ 50 ns
≤500 ns
≤2 TCL
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
not transparent
not t.
transparent
not t.
not t.
not transparent
TCL
IBUS-CS
(Internal)
≤1 ms
FLARST
RST
1024 TCL
8 CL
At this time RSTF is sampled HIGH or LOW
so it is SHORT or LONG reset
RSTOUT
RPD
(2)
V
> 2.5V Asynchronous Reset not entered
RPD
200µA Discharge
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software.
Bit BDRSTEN is cleared after reset.
4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1)
200/328
ST10F252M
System reset
Figure 76. Synchronous short / long hardware RESET (EA=0)
(5)
≤4 TCL
≤12 TCL
< 1032 TCL
(1)
(4)
RSTIN
≥ 50 ns
≤500 ns
≥ 50 ns
≤500 ns
≥ 50 ns
≤500 ns
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
ALE
not transparent
not t.
transparent
not t.
not
not transparent
)
3..8 T
8 TCL
1024 TCL
8 CL
RST
At this time RSTF is sampled HIGH or LOW
so it is SHORT or LONG reset
RSTOUT
RPD
(2)
V
> 2.5V Asynchronous Reset not entered
RPD
200µA Discharge
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered.
3. 3 to 8 TCL depending on clock source selection.
4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit
BDRSTEN is cleared after reset.
5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1).
201/328
System reset
Figure 77. Synchronous long hardware RESET (EA=1)
ST10F252M
(2)
≤4 TCL
≤12 TCL
1024+8 TCL
RSTIN
≥ 50 ns
≤500 ns
≥ 50 ns
≥ 50 ns
≤500 ns
≤2 TCL
≤500 ns
RSTF
(After Filter)
3..4 TCL
transparent
P0[15:13]
P0[12:2]
P0[1:0]
not transparent
not t.
not t.
transparent
not t.
not t.
not transparent
TCL
IBUS-CS
(Internal)
≤1 ms
FLARST
RST
1024+8 TCL
At this time RSTF is sampled LOW
so it is definitely LONG reset
RSTOUT
RPD
(1)
V
> 2.5V Asynchronous Reset not entered
RPD
200µA Discharge
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered. Even if RPD returns above the
threshold, the reset is definitively taken as asynchronous.
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1).
202/328
ST10F252M
System reset
Figure 78. Synchronous long hardware RESET (EA=0)
(2)
4 TCL
12 TCL
1024+8 TCL
RSTIN
≥ 50 ns
≤500 ns
≥ 50 ns
≥ 50 ns
≤500 ns
≤500 ns
RSTF
(After Filter)
3..4 TCL
transparent
P0[15:13]
P0[12:2]
P0[1:0]
ALE
not transparent
not t.
transparent
not t.
not
not transparent
)
3..8 TC
8 TCL
1024+8 TCL
RST
At this time RSTF is sampled LOW
so it is LONG reset
RSTOUT
RPD
(1)
V
> 2.5V Asynchronous Reset not entered
RPD
200 µA Discharge
1. f during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered.
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1).
3. 3 to 8 TCL depending on clock source selection.
20.4
Software reset
A software reset sequence can be triggered at any time by the protected SRST (software
reset) instruction. This instruction can be deliberately executed within a program, for
example, to leave bootstrap loader mode, or on a hardware trap that reveals system failure.
On execution of the SRST instruction, the internal reset sequence is started. The
microcontroller behavior is the same as for a synchronous short reset, except that only bits
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (that is written at ‘1’).
A Software reset is always taken as synchronous. There is no influence on Software reset
behavior with RPD status. In case a bidirectional reset is selected, a Software reset event
203/328
System reset
ST10F252M
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional reset is selected.
Refer to Figure 79 and Figure 80 for unidirectional software reset timing, and to Figure 81,
Figure 82 and Figure 83 for bidirectional.
20.5
Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly
during program execution, it overflows and triggers the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after
the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always synchronous. There is no influence on Watchdog reset behavior
with RPD status. In case a Bidirectional reset is selected, a Watchdog reset event pulls
RSTIN pin low; this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low
even though bidirectional reset is selected.
Refer to Figure 79 and Figure 80 for unidirtional SW reset timing, and to Figure 81,
Figure 82 and Figure 83 for bidirectio
Figure 79. SW / WDT unidirectional RESET (EA=1)
RSTIN
≤2 TCL
P0[15
P0[12:8]
not transparent
transparent
not t.
not t.
P0[7:2]
P0[1:0]
not transparent
not transparent
7 TCL
IBUS-CS
(Internal)
≤1 ms
FLARST
RST
1024 TCL
RSTOUT
204/328
ST10F252M
System reset
Figure 80. SW / WDT unidirectional RESET (EA=0)
RSTIN
P0[15:13]
P0[12:8]
not transparent
transparent
not t.
not transparent
not transparent
P0[7:2]
P0[1:0]
not t.
8 TCL
ALE
1024 TCL
RST
RSTOUT
20.6
Bidirectional Reset
As shown in the previous sections, the RSTOUT pin is driven active (low level) at the
beginning of any eset sequence (synchronous/asynchronous hardware, software and
watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization
routine, until the protected EINIT instruction (end of initialization) is completed.
The Bidirectional reset function is useful when external devices require a reset signal but
cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It
is, for instance, the case of external memory running initialization routine before the
execution of EINIT instruction.
Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It
only can be enabled during the initialization routine, before EINIT instruction is completed.
When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal,
for the duration of the internal reset sequence (synchronous/asynchronous hardware,
synchronous software and synchronous watchdog timer resets). At the end of the internal
reset sequence (1024 TCL) the pull down is released and the following may occur.
●
After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low
8 TCL periods after the internal reset sequence completion (refer to Figure 75 and
Figure 76), the Short reset becomes a Long reset. Otherwise, if RSTF is sampled high
the device simply exits reset state.
●
After a Software or Watchdog Bidirectional reset, the device exits from reset. If RSTF
remains still low for at least 4 TCL periods (minimum time to recognize a Short
205/328
System reset
ST10F252M
hardware reset) after the reset exiting (refer to Figure 81 and 82), the Software or
Watchdog reset become a Short Hardware reset. On the contrary, if RSTF remains low
for less than 4 TCL, the device simply exits reset state.
The Bidirectional reset is not effective in case RPD is held low, when a Software or
Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset
event is active and RPD becomes low, the RSTIN pin is immediately released, while the
internal reset sequence is completed regardless of RPD status change (1024 TCL).
Note:
The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of
SYSCON is cleared). To be activated again it must be enabled during the initialization
routine.
WDTCON flags
Similar to what is highlighted in the previous section, when discussing Short reset and the
degeneration into Long reset, comparable situations may occur when Bidirectional reset is
enabled. The presence of the internal filter on RSTIN pin introduces a delay: When RSTIN is
released, the internal signal after the filter (see RSTF in the drawings) idelayed, so it
remains still active (low) for a while. It means that depending on the ternal clock speed, a
short reset may be recognized as a long reset: The WDTCON ags are set accordingly.
Moreover, when either Software or Watchdog bidirectionareset events occur, when the
RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal
(after the filter) remains low for a while, and depending on the clock frequency it is
recognized high or low. If the RSTF signal is recognized low for at least another 4 TCL after
the completion of the internal sequence, a rdware reset sequence starts, and WDTCON
flags this last event, masking the prevone (software or watchdog reset). Typically, a
short hardware reset is recognized, unless the RSTIN pin (and consequently internal signal
RSTF) is held sufficiently low by the external hardware to inject a long hardware reset. After
this occurrence, the initialization routine is not able to recognize a software or watchdog
bidirectional reset event, since a different source is flagged inside WDTCON register. This
phenomenon does not occur when internal Flash is selected during reset (EA = 1), since the
initialization of tFlash extends the internal reset duration well beyond the filter delay.
The neFigure 81, 82 and 83 summarize the timing for Software and Watchdog Timer
Bidirectional reset events. In particular, Figure 83 shows the degeneration into Hardware
reset.
206/328
ST10F252M
System reset
Figure 81. SW / WDT bidirectional RESET (EA=1)
RSTIN
≥ 50 ns
≤500 ns
≥ 50 ns
≤500 ns
RSTF
(After Filter)
P0[15:13]
P0[12:8]
not transparent
transparent
not t.
not t.
P0[7:2]
P0[1:0]
not transparent
not transparent
≤2 TCL
7 TCL
IBUS-CS
(Internal)
4 TCL
≤1 ms
FLARST
1024 TCL
RST
RSTOUT
Figure 82. SW / WDT bidirectional RESET (EA=0)
RSTIN
≥ 50 ns
≤500 ns
≥ 50 ns
≤500 ns
STF
(After Filter)
P0[15:13]
P0[12:8]
P0[7:2]
P0[1:0]
ALE
not transparent
transparent
not t.
not transparent
not transparent
not t.
8 TCL
4 TCL
1024 TCL
RST
At this time RSTF is already HIGH
so SW or WDT Reset is exited and flagged in WDTCON
(no new HW reset is generated)
RSTOUT
207/328
System reset
Figure 83. SW / WDT bidirectional RESET (EA=0)
ST10F252M
RSTIN
≥ 50 ns
≤500 ns
≥ 50 ns
≤500 ns
RSTF
(After Filter)
P0[15:13]
P0[12:8]
not transparent
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
ALE
not transparent
n
4 TCL
1024 TCL
RST
RSTF remains LOW for more than 4 TCL
so new HW Reset is entered and flagged
in WDTCON register
RSTOUT
20.7
Reset circutry
Internareset circuitry is described in Figure 86. The RSTIN pin provides an internal pull-up
resistor of 50 kΩ to 250 kΩ (the minimum reset time must be calculated using the lowest
value).
It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output
internal reset state signal (synchronous reset, watchdog timer reset or software reset).
This bidirectional reset function is useful in applications where external devices require a
reset signal but cannot be connected to RSTOUT pin.
This is the case of an external memory running codes before EINIT (end of initialization)
instruction is executed. RSTOUT pin is pulled high only when EINIT is executed.
The RPD pin provides an internal weak pull-down resistor which discharges external
capacitor at a typical rate of 200 µA. If bit PWDCFG of SYSCON register is set, an internal
pull-up resistor is activated at the end of the reset sequence. This pull-up charges any
capacitor connected on RPD pin.
The simplest way to reset the ST10F252M is to insert a capacitor C1 between RSTIN pin
and V , and a capacitor between RPD pin and V (C0) with a pull-up resistor R0 between
SS
SS
RPD pin and V . The input RSTIN provides an internal pull-up device equalling a resistor of
DD
50 kΩ to 250 kΩ (the minimum reset time must be determined by the lowest value). Select a
208/328
ST10F252M
System reset
value of C1 that produces a sufficient discharge time to permit the internal or external
oscillator and/or internal PLL and the on-chip voltage regulator to stabilize.
To ensure correct power-up reset with controlled supply current consumption, specially if the
clock signal requires a long period of time to stabilize, an asynchronous hardware reset is
required during power-up. For this reason, it is recommended to connect the external R0-C0
circuit, shown in Figure 84, to the RPD pin. On power-up, the logical low level on the RPD
pin forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-
up R0 will then charges the capacitor C0. Note that an internal pull-down device on RPD pin
is turned on when RSTIN pin is low and causes the external capacitor (C0) to begin
discharging at a typical rate of 100-200 µA. With this mechanism, after power-up reset,
short low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is
asserted longer than the time needed for C0 to be discharged by the internal pull-down
device, the device is forced in an asynchronous reset. This mechanism insures recovery
from very catastrophic failure.
Figure 84. Minimum external reset circuitry
RSTOUT
RSTIN
External Hardwa
+
a) Hardware
Reset
C1
V
CC
b) For Power-up
Reset
(and Interruptible
Power Down
mode)
R0
C0
RPD
+
ST10F252M
The minimum reset circuit of Figure 84 is not adequate when the RSTIN pin is driven from
the ST10F252M itself during software or watchdog triggered resets, because of the
capacitor C1 that keeps the voltage on RSTIN pin above V after the end of the internal
IL
reset sequence, and, thus will triggers an asynchronous reset sequence.
Figure 85 shows an example of a reset circuit. In this example, an R1-C1 external circuit is
only used to generate power-up or manual reset, and the R0-C0 circuit on RPD is used for
power-up reset and to exit from power down mode. Diode D1 creates a wired-OR gate
connection to the reset pin and may be replaced by open-collector Schmitt trigger buffer.
Diode D2 provides a faster cycle time for repetitive power-on resets.
R2 is an optional pull-up for faster recovery and correct biasing of TTL open collector
drivers.
209/328
System reset
Figure 85. System reset circuit
ST10F252M
V
DD
V
DD
R2
External Hardware
R1
C1
D2
RSTIN
+
V
+
D1
DD
External
Reset Source
o.d.
R0
C0
Open Drain Inverter
RPD
ST10F252M
Figure 86. Internal (simplified) reset circuitry
EINIT Instruction
Clr
Q
RSTOUT
Set
Reset State
Machine
Clock
V
DD
SRST instruction
watchdog overflow
Trigger
Clr
Internal
reset
signal
RSTIN
BDRSTEN
(512 CPU Clock Cycles)
Reset sequence
V
DD
Asynchronous
Reset
RPD
From / to Exit
powerdown
circuit
Weak pulldown
(~200µA)
210/328
ST10F252M
System reset
20.8
Reset summary
Table 114 summarizes the different reset events.
Table 114. Reset events summary
Event
RSTIN
WDTCON Flags
min
max
1 ms (VREG)
1.2 ms (Reson. +
PLL)
10.2 ms (Crystal +
PLL)
Asynch
.
0
0
0
1
N
N
-
-
1
1
1
1
1
1
1
1
0
0
Power-on Reset
Asynch
.
1ms (VREG)
1
x
x
x
x
FORBIDDEN
Y
NOT APPLICABE
-
Asynch
.
0
0
0
0
1
1
0
1
0
1
0
N
N
Y
Y
N
N
500ns
500ns
5s
500ns
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Asynch
.
-
-
-
Hardware Reset
(Asynchronous)(1)
Asynch
.
Asynch
.
1032 + 12 TCL +
max(4 TCL, 500ns)
Synch. max (4 TCL, 500ns)
Synch. max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
Short Hardware
Reset
1032 + 12 TCL +
max(4 TCL, 500ns)
max (4 TCL, 500ns)
Synch.
1
1
0
1
Y
Y
0
0
0
0
1
1
1
1
0
0
(Synchroous) 1
Activated by internal logic for 1024TCL
1032 + 12 TCL +
max (4 TCL, 500ns)
max(4 TCL, 500ns)
Synch.
Activated by internal logic for 1024 TCL
211/328
System reset
ST10F252M
Table 114. Reset events summary (continued)
RSTIN
WDTCON Flags
Event
min
1032 + 12 TCL +
max
1
1
0
1
N
N
Synch.
Synch.
-
-
-
0
0
1
1
1
1
1
1
0
0
max(4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
Long Hardware
Reset
(Synchronous)
1032 + 12 TCL +
max(4 TCL, 500ns)
1
1
0
1
Y
Y
Synch.
Synch.
0
0
1
1
1
1
1
1
0
0
Activated by internal logic only for 1024 TCL
1032 + 12 TCL +
max(4 TCL, 500ns)
-
Activated by internal logic only for 1024 TCL
Not activated
x
x
0
1
x
x
0
1
0
0
1
1
0
0
1
1
N
N
Y
Y
N
N
Y
Y
Synch.
Synch.
Synch.
Synch.
Synch.
Synch.
Synch.
Synch.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
Not activated
Software Reset (2)
Watchdog Reset (2)
Not activated
Activated by interl logic for 1024 TCL
Not activated
Not activated
Not activated
Activated by internal logic for 1024 TCL
1. It can degenerate into a long hardware reset and consequently differently flagged (see Figure 20.3 for details).
2. When Bidirectional is active (anith RPD=0), it can be followed by a short hardware reset and consequently differently
flagged (see Section 20.3 for detals).
The stat-up configurations are selected on reset sequences as described in Table 115.
It describes what is the system configuration latched on PORT0 in the six different reset
modes.
Table 5. PORT0 latched configuration for the different reset events
PORT0
X : Pin is sampled
- : Pin is not sampled
Sample event
Software Reset
Watchdog Reset
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
212/328
ST10F252M
System reset
Table 115. PORT0 latched configuration for the different reset events (continued)
PORT0
X : Pin is sampled
- : Pin is not sampled
Sample event
Synchronous Short Hardware Reset
Synchronous Long Hardware Reset
Asynchronous Hardware Reset
Asynchronous Power-On Reset
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
213/328
Power reduction modes
ST10F252M
21
Power reduction modes
Several different power reduction modes with different levels of power reduction have been
implemented in the ST10F252M, which may be entered under software and/or hardware
control.
In idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode
can be terminated by any reset or interrupt request.
In power down mode both the CPU and the peripherals are stopped. Power down mode can
be configured by software to be terminated only by a hardware reset, by a transition on
enabled fast external interrupt pins, by an interrupt generated by the real time clock, by an
2
interrupt generated by the activity on CAN and I C module interfaces.
Note:
All external bus actions are completed before idle or power down mode is entered.
To use the real time clock when the device is in power down mode a reference clock is
needed (XTAL1 / XTAL2 pins). In this case, the main oscillator is not stopped when power
down is entered, and the real time clock continues to work using the main oscillator clock
signal as reference.
Stand-by mode is achieved by turning off the main power supply (V ) while V
remains
STBY
DD
the only active supply for the device. In this condition, the V
pin provides the supply to a
STBY
portion of the XRAM (the stand-by RAM, 16 Kbyte in this device) through a dedicated
on-chip low power voltage regulator; the content f this RAM can be retained and is
available at next system start-up.
Note:
V
is always powered in the range 4.5-5.5 Volt.
STBY
An exception for the V
value is allowed when RSTIN pin is held low and the main V is
DD
STBY
on – this drives pin EA (mapped together with V
) and configures the access to external
STBY
memory. After the RSTIN pin is released, V
supply voltage.
returns high to be used as the V
STBY
STBY
The real time clock cannot be used in stand-by-mode. Turning off the main power supply
(V ) othe device, stop the main oscillator circuitry working. Standard power down mode
DD
must be used to continue operating the real time clock (RTC).
21.1
21.2
Idle mode
This mode is exactly the same as for the ST10F168 or the ST10F269.
In idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode
can be terminated by any reset or interrupt request. Any operation, required by the interrupt
is completed and the CPU returns to normal operation.
Power down mode
To further reduce the power consumption the microcontroller can be switched to power
down mode. Clocking of all internal blocks is stopped, the contents of the internal RAM,
however, are preserved through the voltage supplied via the V pins (and the on-chip
DD
voltage regulator). The watchdog timer is also stopped in power down mode. The only
exception could be the real time clock, if appropriately programmed, and the oscillator circuit
as a consequence (the main oscillator).
214/328
ST10F252M
Power reduction modes
When the ST10F252M is in power-down mode, its on-chip voltage regulator remains on by
default. To further reduce the consumption, it can be put in its power-saving mode; the
low-power voltage regulator delivers about 1.65 V to supply the core logic. It is mandatory
not to reduce the V during power down mode – it must be always in the range 5V 10%
DD
when in power down mode. Before executing the PWRDN instruction, bit 3 of the XMISC
register is set to turn off the main voltage regulator when power down is entered.
XMISC register
XMISC register (EB46h)
15 14 13
SFR
Reset value: 0000h
12
11
10
-
9
8
7
6
5
4
3
2
1
0
VREG CANC CANP
P7EN
-
OFF
K2
AR
-
RRW RRW RRW RRW
-
Table 116. XMISC register functions
Bit
Name
Function
Connect PORT7 to pins
4
P7EN
‘0’: Ports P4.0-P4.3 are connecteto pins 47-50 (default configuration).
‘1’: Ports P7.0-P7.3 are conected to pins 47-50
Main voltage regulator able in power-down mode
‘0’: On-chip main egulator is held active when power-down mode is
entered
3
2
VREGOFF
CANCK2
‘1’: On-chip main regulator is turned off when power-down mode is
entered
CAN clock divider by 2 disable
‘0’: Clock provided to CAN modules is CPU clock divided by two
(mandatory when fCPU is higher than 40 MHz)
‘1’: Clock provided to CAN modules is directly CPU clock
CAN parallel mode selection
‘0’: CAN2 is mapped on P4.4/P4.7, while CAN1 is mapped on
P4.5/P4.6
1
CANPAR
‘1’: CAN1 and CAN2 are mapped in parallel on P4.5/P4.6. This is
effective only if both CAN1 and CAN2 are enabled through setting of
bits CAN1EN and CAN2EN in XPERCON register. If CAN1 is disabled,
CAN2 remains on P4.4/P4.7 even if bit CANPAR is set.
The ST10F252M provides two different operating power down modes:
●
protected power down mode
●
interruptible power down mode.
The power down operating mode is selected by the bit PWDCFG in SYSCON register.
215/328
Power reduction modes
ST10F252M
SYSCON register
SYSCON register (FF12h/89h)
SFR
Reset value: 0xx0h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
RRW RRW RRW RRW RRW RRW RRW RRW RRW RRW RRW RRW RRW
Table 117. SYSCON PWDCFG functions
Bit
Name
Function
Power down mode configuration control
‘0’: Power down mode can only be entered during PWRDN instruction
execution if NMI pin is low, otherwise the instruction has no effect. To
exit power down mode, an external reset must be provided by asserting
the RSTIN pin.
‘1’: Power down mode can only be entered durinPWRDN instruction
execution if all enabled fast external interrupt XxIN) pins are in their
inactive level. Exiting this mode can be done by asserting one enabled
EXxIN pin and/or by an interrupt coming from the real time clock (if
running), and/or by an interrupt coming from CAN1/CAN2/I2C serial
interfaces and/or by asserting RSTIN pin.
5
PWDCFG
Note:
The SYSCON register cannot be changed after execution of the EINIT instruction.
21.2.1
Protected power down mode
This mode is selected by clearing the bit PWDCFG in register SYSCON to ‘0’.
In this mode, the power down mode can only be entered if the NMI (non maskable interrupt)
pin is externally pulled low while the PWRDN instruction is executed.
This feature cn be used in conjunction with an external power failure signal which pulls the
NMI piow when a power failure is imminent. The microcontroller enters the NMI trap
routine which can save the internal state into RAM. After the internal state has been saved,
the trap routine may set a flag or write a certain bit pattern into specific RAM locations and
then execute the PWRDN instruction. If the NMI pin is still low at this time, power down
mode is entered, otherwise program execution continues. During power down, the voltage
delivered by the on-chip voltage regulator automatically lowers the internal logic supply
down to about 1.65 V, saving the power while the contents of the internal RAM and all
registers are still preserved.
Exiting power down mode
In this mode, the only way to exit power down mode is with an external hardware reset.
The initialization routine (executed upon reset) can check the identification flag (see
WDTCON - Chapter 19) or bit pattern within RAM to determine whether the controller was
initially switched on, or whether it was properly restarted from power down mode.
216/328
ST10F252M
Power reduction modes
21.2.2
Interruptible power down mode
This mode is selected by setting the bit PWDCFG in register SYSCON to ‘1’.
In this mode, the power down mode can be entered if the fast external interrupt pins (EXxIN
pins, alternate functions of PORT2 pins, with x = 7...0) are in their inactive level. This
inactive level is configured with the EXIxES bit field in the EXICON register
Figure 87. EXICON register
EXICON register (F1C0h/E0)
ESFR
Reset value: 0000h
15 14 13 12
11
10
9
8
7
6
5
4
3
2
1
0
EXI7ES
EXI6ES
EXI5ES
EXI4ES
EXI3ES
EXI2ES
EXI1ES
EXI0ES
RRW
RRW
RRW
RRW
RRW
RRW
RRW
RRW
Table 118. EXICON register functions
Bit Name
Function
External interrupt x edge selection fiel(x=7...0)
‘00’: Fast external interrupts disabed: standard mode. EXxIN pin not
taken into account for entering or exiting power down mode.
‘01’: Interrupt on positive edge (rising). Enter power down mode if
15.0 EXIxES (x=7...0)
EXiIN = ‘0’, exit if EXxIN ‘1’ (referred as ‘high’ active level)
‘10’: Interrupt on gative edge (falling). Enter power down mode if
EXiIN = ‘1’, if EXxIN = ‘0’ (referred as ‘low’ active level)
‘11’: Interrupt on any edge (rising or falling). Always enter power down
mode, exit if EXxIN level changed.
Exiting power down mode
When interruptible power down mode is entered, the CPU and peripheral clocks are frozen,
and the oscillatoand PLL are stopped (when RTC is disabled, so there is no need for a
clock reference). Interruptible power down mode can be exited by either asserting RSTIN or
one of the enabled EXxIN pin (fast external interrupt). If the real time clock module needs to
be unning during power down, the main oscillator is not stopped. The PLL, on the contrary
is switched off.
If power down mode is exited by a hardware RESET, the RSTIN pin must be held low until
the oscillator (if not already running for real time clock operation) and PLL have restarted
and stabilized.
EXxIN inputs are normally sampled interrupt inputs. However, the power down mode
circuitry uses them as level-sensitive inputs. An EXxIN (x = 7...0) interrupt enable bit (bit
CCxIE in respective CCxIC register) needs not to be set to bring the device out of power
down mode.
To guarantee stabilization time before restart the operation when exiting from power down
(especially if the main oscillator was stopped – typically when the real time clock module is
not used), an external RC circuit must be connected to RPD pin (return from power down),
as shown in the Figure 88.
217/328
Power reduction modes
Figure 88. RPD pin: external circuit to exit power down
ST10F252M
VDD
R1 220k - 1M Ohm (typ)
RPD
+
C1 1µF (typ)
ST10F252M
To exit power down mode with external interrupt, an EXxIN pin has to be asserted for at
least 40 ns (x = 7...0). This signal enables the internal main oscillator (if not already running)
and PLL circuitry, and also turns on the internal weak pull-down on RPD in (see Figure 89).
The discharging of the external capacitor provides a delay that allowhe oscillator and PLL
circuits to stabilize before the internal CPU and peripheral clos are enabled. When the
voltage on RPD pin drops below the threshold voltage (about 2.5 V), the Schmitt trigger
clears Q2 flip-flop, thus enabling the CPU and peripheral clocks, and the device resumes
code execution.
If the Interrupt was enabled (bit CCxIE=’1’ in the respective CCxIC register) before entering
power down mode, the device executes the terrupt service routine, and resumes execution
after the PWRDN instruction (see notlow). If the interrupt was disabled, the device
executes the instruction following PWRDN instruction, and the interrupt request flag (bit
CCxIR in the respective CCxIC register) remains set until it is cleared by software.
Note:
Due to internal pipeline, the instruction that follows the PWRDN instruction is executed
before the CPU performs a call of the interrupt service routine when exiting power down
mode.
Figure 9. Simplified power down exit circuitry
V
DD
stop PLL
D
Q
Q
stop oscillator
V
Q1
cd
DD
Enter
power down
exit_pwrd
Pull-Up
RPD
Weak pull-down
(~ 200 µA)
External
interrupt
Reset
V
DD
en_clk_n
D
Q
Q
CPU and peripherals clocks
Q2
cd
system clock
218/328
ST10F252M
Power reduction modes
2
Exiting from interruptible power down is also possible through the CAN receive lines and I C
Serial Clock line (if properly enabled through CC8IC and CC9IC registers), an activity on
pins P4.5 and P4.4 is interpreted as a fast external interrupt event able to wake-up the
device. For more details refers also to Section 9.1.
Figure 90. Power down exit sequence using an external interrupt (PLL x 2)
XTAL1
CPU clk
Power Down Signal
(Internal)
External
Interrupt
RPD
~ 2.5 V
ExitPwrd
(Internal)
Delay for osillator / PLL
abilization
21.2.3
Real time clock and power don mode
If the real time clock is running (RTOFF bit of RTCCON register cleared), when PWRDN
instruction is executed, the oscillator circuit which is providing the reference to the counter is
not stopped.
21.3
Stand-by mode
In Stan-by mode, the RAM array is maintained powered through the dedicated pin V
STBY
when ST10F252M main power supply (V ) is turned off.
DD
To enter stand-by mode it is mandatory to hold the device under reset; once the device is
under reset, the RAM is disabled (see XRAM2EN and XRAM1EN bits of XPERCON
register), and its digital interface is frozen to avoid any kind of data corruption. It is then
possible to turn off the main V provided that V
is on.
DD
STBY
A dedicated embedded low-power voltage regulator is implemented to generate the internal
low voltage supply (about 1.65 V in stand-by mode) to bias all those circuits that remain
active: XRAM2 (12Kbytes).
In normal running mode (that is when main V is on), the V
pin can be tied to V
SS
DD
STBY
during reset to exercise the EA functionality associated with the same pin; the voltage
supply for the circuitries which are usually biased with V (see in particular the low-
STBY
power oscillator used in conjunction with real time clock module), is granted by the active
main V
.
DD
Stand-by mode can generate problems associated with the use of different power supplies
in CMOS systems. Pay particular attention when the ST10F252M I/O lines are interfaced
with other external CMOS integrated circuits. If V of ST10F252M becomes (for example
DD
219/328
Power reduction modes
ST10F252M
in stand-by mode) lower than the output level forced by the I/O lines of these external
integrated circuits, the ST10F252M could be directly powered through the inherent diode
existing on ST10F252M output driver circuitry. The same is valid for ST10F252M interfaced
to active or inactive communication buses during stand-by mode: current injection can be
generated through the inherent diode. Furthermore, the sequence of turning on/off of the
different voltage could be critical for the system (not only for the ST10F252M device). The
device stand-by mode current (I
) may vary while V to V
(and vice versa)
STBY
DD
STBY
transition occurs. Some current flows between V and V
pins. System noise on both
DD
STBY
V
and V
can contribute to increase this phenomenon.
DD
STBY
21.3.1
Entering stand-by mode
To enter stand-by mode XRAM2EN and XRAM1EN bits in the XPERCON register must be
cleared (this bit is automatically reset by any kind of RESET event, see Chapter 20); this
immediately freezes the RAM interface, avoiding any data corruption. As a consequence of
a RESET event, the RAM power supply is switched to the internal low-voltage supply, V
18SB
(derived from V
through the low-power voltage regulator). The RAM interface remains
STBY
frozen until the bits XRAM1EN and XRAM2EN are set again by softwarnitialization routine
(at next exit from main V power-on reset sequence).
DD
Since V is falling (as a consequence of V turning off), it can happen that the XRAM2EN
18
DD
bit is no longer able to guarantee its content (logic “0”), as the XPERCON register is
powered by the internal V . This does not generate any problem, because the Stand-by
18
mode dedicated switching circuit continues to corm the freezing of the RAM interface,
irrespective the XRAM2EN bit content. The XRAM2EN bit status is considered again when
internal V comes back over internal nd-by reference V
.
18
18SB
If internal V becomes lower than the internal stand-by reference (V
) of about 0.3-
18
18SB
0.45V with bit XRAM2EN set, the RAM supply switching circuit is not active. If there is a
temporary drop on internal V voltage versus internal V during normal code execution,
18
18SB
no spurious stand-by mode switching can occur (the RAM is not frozen and can still be
accessed).
The ST10F2M core module, generating the RAM control signals, is powered by the
internasupply. During turning off, these control signals follow the V , while RAM is
18
18
switched to the V
internal reference. It could happen that a high level of RAM write
18SB
strobe from ST10F252M core (active low signal) is low enough to be recognized as a logic
“0” by the RAM interface (due to V lower than V ); the bus status could contain a valid
18
18SB
address for the RAM and an unwanted data corruption could occur. For this reason, an extra
interface, powered by the switched supply, is used to prevent the RAM from this kind of
potential corruption mechanism.
Warning: During power-off phase, it is important that the external
hardware maintains a stable ground level on RSTIN pin,
without any glitch, to avoid spurious exiting from reset status
with unstable power supply.
220/328
ST10F252M
Power reduction modes
21.3.2
Exiting stand-by mode
After the system has entered the stand-by mode, the procedure to exit this mode consists of
a standard power-on sequence, with the only difference that the RAM is already powered
through the V
internal reference (derived from V
pin external voltage).
18SB
STBY
Hold the device under RESET (RSTIN pin forced low) until external V voltage pin is
DD
stable. Even though, at the very beginning of the power-on phase, the device is maintained
under reset by the internal low voltage detector circuit (implemented inside the main voltage
regulator) until the internal V becomes higher than about 1.0V, there is no warranty that
18
the device stays under reset status if RSTIN is at high level during power ramp up. So, it is
important the external hardware is able to guarantee a stable ground level on RSTIN along
the power-on phase, without any temporary glitch.
The external hardware is responsible to drive the RSTIN pin low until V is stable, even
DD
though the internal LVD is active. It is requested an additional time (at least 1 ms) to allow
internal voltage regulator stabilization before releasing the RSTIN pin; this is necessary
since the internal Flash has to begin its initialization phase (starting when RSTIN pin is
released) with an already stable V .
18
Once the internal reset signal goes low, the RAM (still frozen) ower supply is switched to
the main V .
18
At this time, everything becomes stable, and the execution of the initialization routines can
start: XRAM1EN and XRAM2EN bit can be set, enabling the RAM.
21.3.3
Real time clock and stand-by moe
When stand-by mode is entered (turning off the main supply V ), the real time clock
DD
counting stops running. This is because the main oscillator is used as reference for the
counter. As the main oscillator powered by V , once this is switched off, the oscillator
DD
stops.
221/328
Real time clock
ST10F252M
22
Real time clock
The Real Time Clock is an independent timer, in which the clock is derived directly from the
clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator)
so that it can continue running even in Idle or Power-down modes (if so enabled). Registers
access is implemented onto the XBUS. This module is designed with the following
characteristics:
●
generation of the current time and date for the system
●
cyclic time based interrupt, on Port2 external interrupts every “RTC basic clock tick”
and after n ’RTC basic clock ticks’ (n is programmable) if enabled
●
●
58-bit timer for long term measurement
capability to exit the ST10 chip from Power-down mode (if PWDCFG of SYSCON set)
after a programmed delay
Note:
When the clock is gated, no reset is raised after the EINIT instruction has been executed.
The RTC consists of a chain of programmable counters made of twmain blocks. The first
block is a prescaler which generates a basic reference clock (example, a one second
period clock). This basic reference clock includes a fixed prescaler divider (1/64) and two
programmable dividers: RTCPH (RTC prescaler high – 4-bits) and RTCPL (RTC prescaler
low – 16-bits). The second block, which uses TRCLK s an input clock, comprises two 16-bit
programmable counters, RTCH and RTCL, that ay be initialized to the current system
time. This system time is increased at the TRCLK rate and compared with a programmable
date to generate an alarm via an intert rquest (RTC_alarmIT), if enabled in the RTC
control register.
If enabled in the RTC control register, the RTC generates an interrupt request (RTC_SecIT)
every TRCLK period.
RTC_SecIT and RTC_alarmIT can trigger a fast external interrupt via EXISEL register of
PORT2 and wakthe ST10 chip if it is in power down mode (refer to Section 9.2 for details).
Another functn, implemented in the RTC, is to switch off the main on-chip oscillator if the
ST10 eers the power down mode, so that the chip can be fully switched off (if the RTC is
disabled).
At power on and after reset, the main oscillator drives the RTC counter, and since it is
powered by the main power supply, it cannot be maintained running in stand-by mode, while
in power down mode the main oscillator is maintained running to provide the reference to
the RTC module (if not disabled).
222/328
ST10F252M
Real time clock
Figure 91. SFRs associated with the RTC
Interrupt Control
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y Y Y Y
Y Y Y Y
-
-
-
-
-
-
-
-
-
-
-
-
-
- - - Y Y Y Y Y Y Y Y
EXISEL
EXICON
E
E
CCxIC
EXISEL External Interrupt Source Selection register (Port2)
EXICON External Interrupt Control register (Port2)
CCxIC CAPCOM1 Interrupt Control registers (x = 10, 11)
Y
-
E
:
:
:
Bit is linked to a function
Bit has no function or is not implemented
Register is in ESFR internal memory space
Figure 92. RTC block diagram
RTC_SecIT
RTC_alarmIT
OSC_CLK
OSC_STOP
RTCCON
alarmIT
SecIT
RTCAH
RTCAL
RTCPH
RTCPL
RTCDL
reload
=
RTCH
RTCDH
/64
RTCL
programmable 32 bits counter
programmable 20 bits divider
22.1
RTC registers
22.1.1
RTCCON: RTC control register
The functions of the RTC are controlled by the bit-addressable RTC control register
RTCCON. If the RTOFF bit is set, the RTC dividers and counters clocks are disabled and
registers can be written; when the ST10 chip enters power down mode the clock oscillators
(both main and low-power) are switched off. The RTC has two interrupt sources, one is
triggered every second, the other one is the alarm. RTCCON includes an interrupt request
223/328
Real time clock
ST10F252M
flag and an interrupt enable bit for each of them. This register is read and written via the
XBUS.
RTC control register
RTCCON register (ED00h)
ESFR
Reset value: 000uh
15
14
13
12
11
10
9
-
8
-
7
6
-
5
-
4
-
3
2
1
0
RTCO
FF
RTAE
N
RTSE
N
-
-
RTAIR
RTSIR
-
-
RRW
-
-
-
RRW RRW RRW RRW
Table 119. RTC control register functions
Bit
Name
Function
RTC switch off bit
‘0’: clock oscillator and RTC keep on running even if ST10 in power
down mode.
7
RTCOFF
‘1’: clock oscillator is switched off when ST10 enters power down
mode. Setting this bit, RTC dividers and counters are stopped and
registers can be written.
RTC alarm interrupt enable
3
2
1
0
RTAEN
RTAIR
RTSEN
RTSIR
‘0’: RTC_alarmIT is dised.
‘1’: RTC_alarmIT is enabled, it is generated every n seconds.
RTC alarm rupt request flag (when the alarm is triggered)
‘0’: the bit was reset less than n seconds ago.
‘1’: the interrupt was triggered.
RTC second interrupt enable
‘0’: RTC_SecIT is disabled.
‘1’: RTC_SecIT is enabled, it is generated every second.
RTC second interrupt request flag (every second)
‘0’: the bit was reset less than a second ago.
‘1’: the interrupt was triggered.
Note:
All the bits of RTCCON are active high.
The two RTC Interrupt request lines are connected to PORT2 to trigger an external interrupt
that wakes the chip up if in power down mode.
All the RTC registers are not bit addressable. To clear the RTC interrupt request flags (bit 0
and bit 2 of the RTCCON register) it is necessary to write a ‘1’ to the corresponding bit of the
RTCCON register.
22.1.2
RTC prescaler divider loaded value registers
The 20 bit programmable prescaler divider is loaded by two registers. The divisor 4 MSBs
are stored into RTCPH and the 16 LSBs in RTCPL. These registers are not reset to keep the
system clock. They are write protected by bit RTOFF of RTCCON register, write operation is
allowed if RTOFF is set.
224/328
ST10F252M
Real time clock
RTC prescaler register
RTCCPL register (ED06h)
ESFR
Reset value: uuuuh
15
14
13
12
11
10
10
9
9
8
8
7
6
6
5
5
4
4
3
3
2
2
1
0
RTCPL
RRW
RTCCPH register (ED08h)
15 14 13 12
ESFR
Reset value: uuuuh
11
7
1
0
RTCPH
RRW
Figure 93. RTC prescaler register function
15 14 13 12 11 10
3
2
1
0
9
8
7
6
5
4
3
2
1
0
RTCPH
RTCPL
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
20 bits word divider
The value stored into RTCPH, RTCPL caed RTCP (coded on 20 bits). The dividing ratio
of the prescaler divider is:
ratio = 64 x (RTCP)
The minimum value which can be set in RTCPL is 0002h.
22.1.3
RTC prescaler divider current value registers
Every priod of TRCLK the dividers are reloaded with the value stored in RTCPH and
RTCPL registers. To get an accurate time measurement, it is possible to access the internal
vae of the dividers, reading the registers RTCDH, RTCDL. These registers are read only.
When any bit changed in the programmable prescaler divider, the new internal value is
loaded in the registers.
RTC prescaler divider register
RTCCDL register (ED0Ah)
15 14 13 12
ESFR
Reset value: uuuuh
11
10
9
8
7
6
5
4
3
2
1
0
RTCDL
R
RTCCDH register (ED0Ch)
15 14 13 12
ESFR
Reset value: uuuuh
11
10
9
8
7
6
5
4
3
2
1
0
RTCDH
R
Note:
These registers are not reset, and are read only.
225/328
Real time clock
ST10F252M
The divider works as a decrement operator. When the internal value reaches 0001h, the
second interrupt is generated. When the next decrement occurs (which would set the divider
register to the value 0000h), the 20-bit word stored in RTCPH, RTCPL registers is loaded in
the divider. The minimum value which can be programmed in RTCPL is 0002h; if 0001h
were set, just one second interrupt would be generated, since the divider would stay fixed at
the value 0001h forever (a successive second interrupt cannot occur).
Figure 94. RTC prescaler divider register functions
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RTCDH
RTCDL
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
20 bits word internal value of the prescaler divider
The bits 15 down to 4 of RTCPH and RTCDH are not used. When reading, the return value
of these bits is zero.
22.1.4
RTC programmable counter registers
The RTC has two 16-bit programmable couers whose count rate is based on the 1 second
time reference. These counters can bed as a system clock as the clock oscillator can be
working even in power down mode (either the main or the low power on-chip oscillator) if bit
RTOFF of RTCCON register is reset. To keep this system clock, the counters are not reset
with any system reset; the only way to force their value is to write them via the XBUS.
These counters are write protected. The bit RTOFF of the RTCCON register must be set
(RTC dividers and counters are stopped) to enable a write operation on RTCH or RTCL.
A write operaton on RTCH or RTCL register loads directly the corresponding counter. When
readingthe current value in the counter (system date) is returned.
The counters are kept on running while at least one clock oscillator is working (either the
main or the low-power on-chip oscillator).
RTC programmable counter register
RTCL register (ED0Eh)
15 14 13
ESFR
Reset value: uuuuh
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCL
RW
RTH register (ED10h)
15 14 13
ESFR
Reset value: uuuuh
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCH
RW
Note:
These registers are not reset.
226/328
ST10F252M
Real time clock
22.1.5
RTC alarm registers
When the programmable counters reach the 32 bits value stored into RTCAH & RTCAL
registers an alarm is triggered and the interrupt request RTAIR is generated. These
registers are not protected.
RTC alarm register
RTCAL register (ED12h)
15 14 13
ESFR
Reset value: uuuuh
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCAL
RW
RTCAH register (ED14h)
15 14 13
ESFR
Reset value: uuuuh
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCAH
RW
Note:
These registers are not reset.
22.2
Programming the RTC
RTC interrupt request signals are connected to PORT2, pin 10 (RTCSI) and pin 11 (RTCAI).
EXICON ESFR controls the external interrupt edge selection; RTC interrupt requests are
rising edge active.
RTC external interrupt control register
EXICON register C0h/E0)
15 4 13 12
ESFR
Reset value: 0000h
11
10
9
8
7
6
5
4
3
2
1
0
EXI7ES
EXI6ES
EXI5ES
EXI4ES
EXI3ES
EXI2ES
EXI1ES
EXI0ES
RW
Table 120. RTC external interrupt control register functions
Bit Name Function
External interrupt x edge selection field (x=7...0)
‘00’: Fast external interrupts disabled: standard mode. EXxIN pin not
taken into account for entering or exiting power down mode.
‘01’: Interrupt on positive edge (rising). Enter power down mode if
15.0 EXIxES (x=7...0)
EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
‘10’: Interrupt on negative edge (falling). Enter power down mode if
EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
‘11’: Interrupt on any edge (rising or falling). Always enter power down
mode, exit if EXxIN level changed.
227/328
Real time clock
ST10F252M
Note:
EXI2ES and EXI3ES must be configured as “01b” because RTC interrupt request lines are
rising edge.
Alarm interrupt request line (RTCAI) is linked with EXI3ES; timed interrupt request (RTCSI)
is linked with EXI2ES.
EXISEL ESFR enables the Port2 alternate sources. RTC interrupts are alternate sources 2
and 3.
RTC external interrupt select register
EXISEL register (F1DAh/ED)
15 14 13 12
ESFR
Reset value: 0000h
11
10
9
8
7
6
5
4
3
2
1
0
EXI7SS
EXI6SS
EXI5SS
EXI4SS
EXI3SS
EXI2SS
EXI1SS
EXI0SS
RW
Table 121. RTC external interrupt select register functions
Bit Name Functi
External Interrupt x Source Selecton (x=7...0)
‘00’: Input from associated PORT2 pin
‘01’: Input from “alternate source”. (Advised configuration)
15.0 EXIxSS (x=7...0)
‘10’: Input from PORT2 pin ORed with “alternate source”. (Advised
configuration)
‘11’: Input frPORT2 pin ANDed with “alternate source”.
Interrupt control registers are common with the CAPCOM1 Unit: CC10IC (RTCSI) and
CC11IC (RTCAI).
RTC/CAPCOM interrupt control registers
CCxIC rester (FF8Ch/C6h, FF8Eh/C7h)
114 13 12 11
SFR
Reset value: --00h
10
9
8
7
6
5
4
3
2
1
0
-
CCxIR CCxIE
CCxINT
-
RW
RW
RW
Table 122. RTC/CAPCOM interrupt control requests
Source of interrupt or
Request flag
Enable flag
Interrupt vector Vector location
PEC service request
CAPCOM Register 10
CAPCOM Register 11
CC10IR
CC11IR
CC10IE
CC11IE
CC10INT
CC11INT
00’0068h
00’006Ch
228/328
ST10F252M
System start-up configuration
23
System start-up configuration
RP0H is a 8-bit ESFR loaded at reset with the value read on port P0H. Pull-up resistors are
active on each port P0H pin during reset, leading to RP0H = “FFh”, by default.
Figure 95. PORT0 configuration during Reset
Port 0
H.7 H.6 H.5 H.4 H.3 H.2 H.1 H.0 L.7 L.6 L.5 L.4 L.3 L.2 L.1 L.0
WRC
CLKCFG
SALSEL
-
BUSTYP
BSL
Res. ADP EMU
RP0H
CLKCFG
WRC
SALSEL
-
Bootstrap Loader
Internal Control Logic
Clock
Generator
Port 4
Logic
2
EA / VSTBY
P0L.7
P0L.7
SYSCON
BUSCON0
ALE
CTL0
BUS
ACT0
BTYP
BYTDIS
WRCFG
9
7
10
9
7
6
229/328
System start-up configuration
ST10F252M
Start up configuration register
RPOH register (F108h/84h)
14 13 12 11
ESFR
Reset value: --xxh
15
10
9
8
7
6
5
4
3
2
1
0
-
CLKSEL
RO
SALSEL
RO
-
WRC
RO
Table 123. Start up configuration register functions
Bit Name Function
System Clock Selection
‘000’:
‘001’:
‘010’:
‘011’:
‘100’:
‘101’:
‘110’:
‘111’:
fCPU = 16 * fOSC
fCPU = 0.5 * fOSC
fCPU = 10 * fOSC
fU = fOSC
U = 5 * fOSC
fCPU = 8 * fOSC
fCPU = 3 * fOSC
fCPU = 4 * fOSC
7.5 CLKSEL
Segment Address Line Seletion (Number of active segment address
outputs)
0 0: 4-bit segment address: A19...A16
4.3 SALSEL
0 1: No segnt dress lines at all
1 0: 8-bit seent address: A23...A16
1 1: 2-bit segment address: A17...A16 (Default without pull-downs)
Write Configuration Control
0
WRC
‘0’: Pins WR acts as WRL, pin BHE acts as WRH
‘1’: Pins WR and BHE retain their normal function
Note:
RP0H(7:5) biare loaded only during a long hardware reset.
230/328
ST10F252M
Bootstrap loader
24
Bootstrap loader
ST10F252M has an ST10 standard bootstrap mode that supports bootstrap via UART or
CAN.
24.1
Selection between user-code or standard bootstrap
The selection between user-code or standard bootstrap is made by special combinations on
PORT0L[5...4] during the time the reset configuration is latched from PORT0.
Bootstrap mode is triggered with a special combination set on PORT0L[5...4]. These
signals, as are other configuration signals, are latched on the rising edge of RSTIN pin.
●
Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) selects the normal mode and
selects the user Flash to be mapped from address 00’0000h.
●
Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) selects the ST10 standard
bootstrap mode (user Flash is remapped at address 01’0000h and test Flash is
mapped at address 00’0000h).
Table 124. ST10F252M boot mode selection
P0.5
P0.4
ST0 decoding
1
1
0
1
0
x
No test mode: user Flash mapped at 00’0000h
Standard Bootstloder: User Flash mapped from 01’0000h
Reserved
24.2
Standard bootstrap loader
The built-in bootrap loader (BSL) of the ST10F252M provides a mechanism to load the
startup program, which is executed after reset, via the serial interface. In this case, no
externa(ROM) memory or internal ROM is required for the initialization code starting at
location 00’000oh. The bootstrap loader moves code and data into the internal RAM but it is
also possible to transfer data via the serial interface into an external RAM using a second
level loader routine. ROM memory (internal or external) is not necessary. However, it may be
used to provide lookup tables or may provide “core-code”, that is, a set of general-purpose
subroutines, for example, for I/O operations, number crunching, system initialization, etc.
The bootstrap loader may be used to load the complete application software into ROMless
systems, it may load temporary software into complete systems for testing or calibration, it
may also be used to load a programming routine for Flash devices.
The BSL mechanism may be used for standard system startup as well as only for special
occasions like system maintenance (firmware update) or end-of-line programming or
testing.
24.2.1
Entering the standard bootstrap loader
As with the old ST10 bootstrap mode, the ST10F252M enters BSL mode, if pin P0L.4 is
sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is
231/328
Bootstrap loader
ST10F252M
activated independently of the selected bus mode. The bootstrap loader code is stored in a
special test Flash; no part of the standard of the Flash memory area is required for this.
After entering BSL mode and the respective initialization, the ST10F252M scans the RxD0
line and the CAN1_RxD line to receive either a valid dominant bit from CAN interface, or a
start condition from UART line.
●
Start condition on UART RxD
ST10F252M starts standard bootstrap loader. This bootstrap loader is identical to other
ST10 devices (example: ST10F269, ST10F168). See Section 24.3 for details.
●
Valid dominant bit on CAN1 RxD
ST10F252M start bootstrapping via CAN; the bootstrapping method is new and is
described in Section 24.4. Figure 96 shows the program flow of the new bootstrap
loader. It illustrates clearly how the new functionalities are implemented:
–
UART: UART has priority over CAN after a falling edge on CAN1_RxD till the 1st
valid rising edge on CAN1_RxD
–
CAN: pulses on CAN1_RxD shorter than 20*CPU-cycles are filtered.
232/328
ST10F252M
Bootstrap loader
Figure 96. ST10F252M new bootstrap loader program flow
START
No
No
Falling-edge on
UART0 RxD?
Falling-edge on
CAN1 RxD?
UART BOOT
Start Timer PT0
UART RxD = 0?
Start Timer T6
Yes
No
UART0 RxD = 1?
No
No
Stop Timer T6
Initialize UART
Send Acknowledge
CAN1 RxD = 1?
PT0 > 20?
Address = FA40h
No
Glitch on CRxD
CAN BOOT
byte Received?
Count = 1
Stop Timer PT0
Clear Timer PT0
[Address] = S0RBUF
Address = Address + 1
No
CAN RxD = 0?
No
Address = FA60h?
No
No
No
CN1 RxD = 1?
Count += 1
Message Received?
[Address] = MO15_data0
Address = Address + 1
Count = 5?
No
Address = FAC0h?
Stop Timer PT0
Initialize CAN
Address = FA40h
UART BOOT
CAN BOOT
Jump to Address FA40h
2.2.2
ST10 configuration in BSL
When the ST10F252M has entered BSL mode, the following configuration is automatically
set (values that deviate from the normal reset values, are marked):
Table 125. Register configuration in BSL
Register
Watchdog Timer:
Value
Notes
Disabled
XPEN bit set for Bootstrap via
CAN or Alternate Boot Mode
(1)
Register SYSCON:
0404h
Context Pointer CP:
Register STKUN:
FA00h
FC00h
233/328
Bootstrap loader
Table 125. Register configuration in BSL (continued)
ST10F252M
Register
Stack Pointer SP:
Value
Notes
FA40h
Register STKOV:
FA00h
acc. to startup
Register BUSCON0:
configuration (2)
Register S0CON:
Register S0BG:
8011h
Initialized only if Bootstrap via UART
acc. to ‘00’ byte Initialized only if Bootstrap via UART
P3.10 / TXD0:
‘1’
‘1’
Initialized only if Bootstrap via UART
Initialized only if Bootstrap via UART
Initialized only if Bootstrap via CAN
DP3.10:
CAN Status/Control register:
CAN Bit Timing Register:
0000h
acc. to ‘0’ frame Initialized only if Bootstrap via CAN
XRAM1-2, XFlash, CAN1 nd XMISC enabled.
XPERCON:
042Dh
Initialized only if Bootap via CAN
Initialized only iBootstrap via CAN
Initialized only if Bootstrap via CAN
P4.6 / CAN1_TxD:
DP4.6:
‘1’
‘1’
1. In bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
level. BYTDIS, bit 9 of SYSCON, is set according to dats width selection via PORT0 configuration.
2. BUSCON0 is initialized with 0000h, external bus abled, if pin EA is high during reset. If pin EA is low
during reset, BUSACT0, bit 10, and ALECTbit , are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set accoro Port0 configuration.
Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading
sequence is not time limited. Depending on the serial link (UART or CAN), the pin TxD0 or
CAN1_TxD is configured as output, so the ST10F252M can return an acknowledge. Even if
the internal IFlash is enabled, no code can be executed out of it.
24.2.3
Booting stps
As Figure 97 shows, booting ST10F252M with the boot loader code occurs in a minimum of
four steps.
1. The ST10F252M is reset with P0L.4 low.
2. The internal new bootstrap code runs on the ST10 and a first level user code is
downloaded from the external device using the selected serial link (UART or CAN). The
bootstrap code is contained in the ST10F252M test Flash and is automatically run
when ST10F252M is reset with P0L.4 low. After loading a preselected number of bytes,
ST10F252M begins executing the downloaded program.
3. The first level user code run on ST10F252M. Typically, this first level user code is
another loader that is used to download the application software into the ST10F252M.
4. The loaded application software is now running.
234/328
ST10F252M
Bootstrap loader
Figure 97. Booting steps for ST10F252M
External device
External device
Step1
Entering bootstrap
ST10F252M
Download
1st level user code
ST10F252M
Run Bootstrap Code
from Test-Flash
Step2
Loading 1st level user code
Download
Application
External device
External device
Step3
Loading the application
and exiting BSL
ST10F252M
Rst level Code
m DPRAM @FA40h
Step4
ST10F252M
Run Application Code
24.2.4
Hardware to activate BSL
The hardware that activates the BSL during reset may be a simple pull-down resistor on
P0L.4 for systems that use this feature upon every hardware reset. Alternatively, use a
switchable solution (via jumper or an external signal) for systems that only temporarily use
the bootstrap loaer.
Note:
CAN alternatfunction on PORT4 lines is not activated if the user has selected eight
addressegments (PORT4 pins have three functions: I/O-port, address-segment, CAN).
Boot via CAN requires that four address segments or less are selected.
Figure 98. Hardware provisions to activate BSL
External
Signal
Normal Boot
P0L.4
P0L.4
BSL
R
P0L.4
8kΩ max.
R
P0L.4
8kΩ max.
Circuit 2
Circuit 1
235/328
Bootstrap loader
ST10F252M
24.2.5
Memory configuration in bootstrap loader mode
The configuration (that is, the accessibility) of the ST10F252M’s memory areas after reset in
bootstrap loader mode differs from the standard case. Pin EA is evaluated when BSL mode
is selected to enable or not the external bus:
●
if EA = 1, the external bus is disabled (BUSACT0 = 0 in BUSCON0 register)
if EA = 0, the external bus is enabled (BUSACT0 = 1 in BUSCON0 register)
●
Moreover, while in BSL mode, accesses to the internal Flash area are partly redirected:
●
●
●
all code accesses are made from the special test Flash seen in the range 00’0000h to
00’01FFFh
user IFlash is only available for read and write accesses (test Flash can neither be read
nor written)
write accesses must be made with addresses starting in segment 1 from 01'0000h,
whatever the value of ROMS1 bit in SYSCON register
●
●
read accesses are made in segment 0 or in segment 1 depending of ROMS1 value
in BSL mode by default, ROMS1=0 so the first 32 Kbytes of IFlash re mapped in
segment 0.
For example: in the default configuration, to program address 0, the user software must put
the value 01'0000h in the FARL and FARH registers but, to verify the content of the address
0, a read to 00'0000h must be performed.
Figure 99. Memory configuration in bootstrap loader mode
16 Mbytes
16 Mbytes
16 Mbytes
access to
external
bus
access to
external
bus
Depends on
reset config.
(EA, P0)
enabled
disabled
1
0
1
0
1
0
int.
RAM
int.
RAM
int.
RAM
access to
int. Flash
enabled
access to
int. Flash
enabled
Depends on
reset config.
BSL mode active
EA pin
Yes (P0L.4=’0’)
Yes (P0L.4=’0’)
No (P0L.4=’1’)
high
low
according to application
User IFlash access
Code fetch from inter-
nal Flash area
Test-Flash access
User IFlash access
Test-Flash access
User IFlash access
Data fetch from inter-
nal Flash area
User IFlash access
Note:
As long as ST10F252M is in BSL, the user software should not try to execute code from the
internal IFlash as the fetches are redirected to the test Flash.
236/328
ST10F252M
Bootstrap loader
24.2.6
Loading the start-up code
After the serial link initialization sequence, the BSL enters a loop to receive 32 bytes (boot
via UART) or 128 bytes (boot via CAN).
These bytes are stored sequentially into ST10F252M dual-port RAM from location
00’FA40h.
To execute the loaded code, the BSL jumps to location 00’FA40h. The bootstrap sequence
running from the test Flash is now terminated but the microcontroller remains in BSL mode.
Most probably, the initially loaded routine (the first level user code) will load additional code
and data. This first level user code may use the pre-initialized interface (UART or CAN) to
receive data, a second level of code, and store it in arbitrary user-defined locations.
This second level of code may be the final application code. It may also be another, more
sophisticated, loader routine that adds a transmission protocol to enhance the integrity of
the loaded code or data. It may also contain a code sequence to change the system
configuration and enable the bus interface to store the received data into external memory.
In all cases, the ST10F252M still runs in BSL mode, that is, with the watchdog timer
disabled and limited access to the internal IFlash area.
24.2.7
Exiting bootstrap loader mode
To execute a program in normal mode, the BSL mode must be terminated. The ST10F252M
exits BSL mode upon a software reset (level on P0L.4 is ignored) or a hardware reset (P0L.4
must be high). After the reset, the ST10F2M starts executing from location 00’0000h of
the internal Flash (user Flash) or the ernal memory, as programmed via pin EA.
Note:
If a bidirectional software reset is executed and external memory boot is selected (EA=0), a
degeneration of the software reset event into a hardware reset can occur (refer to
Section 20.6 for details). This would imply that P0L.4 becomes transparent so, to exit from
bootstrap mode, it is necessary to release pin P0L.4 (it is no longer ignored).
24.2.8
Hardware requirements
Although the new bootstrap loader has been designed to be compatible with the old
bootstrap loader, there are few hardware requirements related with the new bootstrap
loader:
●
external bus configuration needs to use four segment address lines or less to keep
CAN I/O available
●
use of CAN pins (P4.5 and P4.6): even in bootstrap via UART, pin P4.5 (CAN1_RxD)
can not be used as port output but only as input; pin P4.6 (CAN1_TxD) can be used as
input or output only if bootstrap via UART is needed
●
level on UART RxD and CAN1_RxD during the bootstrap phase (see Figure 97 - Step
2) must be 1 (an external pull-up is recommended).
237/328
Bootstrap loader
ST10F252M
24.3
Standard bootstrap with UART (RS232 or K-Line)
24.3.1
Features
ST10F252M bootstrap via UART has the same overall behavior as the old ST10 bootstrap
via UART:
●
same bootstrapping steps
●
same bootstrap method: analyze the timing of a predefined byte, send back an
acknowledge byte, load a fixed number of bytes and run them
●
same functionalities: boot with different crystals and PLL ratios.
Figure 100. UART bootstrap loader sequence
RSTIN
P0L.4
(1)
(2)
(4)
RxD0
(3)
TxD0
(5
CSP:IP
32 bytes
user software
(6)
Int. Boot ROM / Test-Flash BSL-routine
1. BSL initialization time, > 2ms @ fCPU = 20 MHz.
2. Zero byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host.
3. Acknowledge byte, sent by ST10F252M
4. 32 bytes of code / data, sent by host.
5. Caution: TxD0 is only driven a certain time after reception of the zero byte (2.5ms @ fCPU = 20 MHz).
6. Internal Boot ROM / test-Flash.
24.3.2
Entering bootstrap via UART
The ST10F252M enters BSL mode if pin P0L.4 is sampled low at the end of a hardware
reset. In this case, the built-in bootstrap loader is activated independently of the selected
bus mode. The bootstrap loader code is stored in a special test Flash, no part of the
standard mask ROM or Flash memory area is required for this.
After entering BSL mode and the respective initialization, the ST10F252M scans the RxD0
line to receive a zero byte, that is, one start bit, eight ‘0’ data bits and one stop bit. From the
duration of this zero byte, it calculates the corresponding baud rate factor with respect to the
current CPU clock, initializes the serial interface, ASC0, accordingly and switches pin TxD0
238/328
ST10F252M
Bootstrap loader
to output. Using this baud rate, an acknowledge byte is returned to the host that provides the
loaded data.
The acknowledge byte is D5h for the ST10F252M.
24.3.3
ST10 configuration in UART BSL (RS232 or K-Line)
When the ST10F252M has entered BSL mode on UART, the following configuration is
automatically set (values that deviate from the normal reset values, are marked):
Table 126. Register configuration in UART BSL
Register
Watchdog Timer:
Value
Notes
Disabled
(1)
Register SYSCON:
Context Pointer CP:
Register STKUN:
Stack Pointer SP:
Register STKOV:
Register S0CON:
Register BUSCON0:
Register S0BG:
P3.10 / TXD0:
0400h
FA00h
FA00h
FA40h
FC00h
8011h
acc. to startup couration(2)
acc. ‘00’ byte
‘1’
‘1’
DP3.10:
1. In bootstrap modes (standard or alternate), ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via PORT0 configuration.
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low
during reset, BUACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP ield, bit 7 and 6, is set according to PORT0 configuration.
Other tan after a normal reset, the watchdog timer is disabled so the bootstrap loading
sequence is not time limited. Pin TxD0 is configured as output, so the ST10F252M can
return the acknowledge byte. Even if the internal IFlash is enabled, no code can be
executed from it.
2.3.4
Loading the start-up code
After sending the acknowledge byte, the BSL enters a loop to receive 32 bytes via ASC0.
These bytes are stored sequentially into locations 00’FA40h through 00’FA5Fh of the
internal RAM. So up to 16 instructions may be placed into the RAM area. To execute the
loaded code, the BSL jumps to location 00’FA40h, that is, the first loaded instruction. The
bootstrap loading sequence is now terminated but the ST10F252M remains in BSL mode.
Most probably, the initially loaded routine will load additional code or data, as an average
application is likely to require substantially more than 16 instructions. This second receive
loop may directly use the pre-initialized interface ASC0 to receive data and store it to
arbitrary user-defined locations.
This second level of loaded code may be the final application code. It may also be another,
more sophisticated, loader routine that adds a transmission protocol to enhance the integrity
239/328
Bootstrap loader
ST10F252M
of the loaded code or data. It may also contain a code sequence to change the system
configuration and enable the bus interface to store the received data into external memory.
This process may go through several iterations or may directly execute the final application.
In all cases the ST10F252M still runs in BSL mode, that is, with the watchdog timer disabled
and limited access to the internal Flash area. All code fetches from the IFlash area
(01’0000h...08’FFFFh, if mapped to segment 1) are redirected to the special test Flash.
Data read operations access the internal Flash of the ST10F252M, if any is available, but
will return undefined data on ROM-less devices.
24.3.5
Choosing the baud rate for the BSL via UART
The calculation of the serial baud rate for ASC0 from the length of the first zero byte that is
received allows the operation of the bootstrap loader of the ST10F252M with a wide range
of baud rates. However, the upper and lower limits have to be kept, to insure proper data
transfer.
f
CPU
---------------------------------------------
B
=
ST10F252M
32 ⋅ (S0BRL + 1)
The ST10F252M uses timer T6 to measure the length of the initial zero byte. The
quantization uncertainty of this measurement implies the first deviation from the real baud
rate, the next deviation is implied by the computation of the S0BRL reload value from the
timer contents. The formula below shows the asciation:
f
9
CPU
T6 6
-- ---------------
S0BRL = -----
,
T6 =
⋅
4 B
Host
For a correct data transfer from the host to the ST10F252M the maximum deviation between
the internal initialized baudrate for ASC0 and the real baud rate of the host should be below
2.5%. The deviation (F , in percent) between host baud rate and ST10F252M baud rate can
B
be calculated via the formula below
B
– B
Host
Contr
F
=
⋅
100 %
F
≤2.5
%
B
---------------------------------------
,
B
B
Contr
Note:
Fuction (F ) does not consider the tolerances of oscillators and other devices supporting
B
the serial communication.
This baud rate deviation is a nonlinear function depending on the CPU clock and the baud
rate of the host. The maxima of the function (F ) increases with the host baud rate due to
B
the smaller baud rate pre-scaler factors and the implied higher quantization error (see
Figure 101).
Figure 101. Baudrate deviation between host and ST10F252M
I
F
B
2.5%
B
B
B
HOST
Low
High
II
240/328
ST10F252M
Bootstrap loader
The minimum baud rate (B
in Figure 101) is determined by the maximum count capacity
Low
of timer T6, when measuring the zero byte, that is, it depends on the CPU clock. Using the
16
maximum T6 count 2 in the formula the minimum baud rate can be calculated. The lowest
standard baudrate in this case would be 1200 baud. Baudrates below B
to overflow. In this case, ASC0 cannot be initialized properly.
would cause T6
Low
The maximum baudrate (B
in Figure 101) is the highest baudrate where the deviation
High
still does not exceed the limit, that is, all baudrates between B
and B
are below the
Low
High
deviation limit. The maximum standard baudrate that fulfills this requirement is 19200 baud.
Higher baud rates, however, may be used as long as the actual deviation does not exceed
the limit. A certain baudrate (marked I) in the figure) may for example, violate the deviation
limit, while an even higher baudrate (marked II) in the figure) stays very well below it. This
depends on the host interface.
24.4
Standard bootstrap with CAN
24.4.1
Features
The bootstrap via CAN has the same overall behavior as the bootstrap via UART:
●
same bootstrapping steps
●
same bootstrap method: analyze the timing of a predefined frame, send back an
acknowledge frame but only on request, loaa fixed number of bytes and run
●
same functionalities: boot with differecrystals and PLL ratios.
Figure 102. CAN bootstrap loader sequence
RSTIN
P0L.4
(1)
(2)
(4)
CAN1_RxD
(3)
CAN1_TxD
(5)
CSP:IP
128 bytes
user software
(6)
Int. Boot ROM / Test-Flash BSL-routine
1. BSL initialization time, > 2ms @ fCPU = 20 MHz.
2. Zero frame (CAN message: standard ID = 0, DLC = 0), sent by host.
3. CAN message (standard ID = 0xE6, DLC = 3, Data0 = 0xD5, Data1-Data2 = IDCHIP_low-high), sent by
ST10F252M on request
4. 128 bytes of code / data, sent by host.
5. Caution: CAN1_TxD is only driven a certain time after reception of the zero byte (2.5ms @ fCPU = 20 MHz).
6. Internal Boot ROM / Test-Flash.
241/328
Bootstrap loader
ST10F252M
The Bootstrap Loader may be used to load the complete application software into ROM-less
systems, it may load temporary software into complete systems for testing or calibration, it
may also be used to load a programming routine for Flash devices.
The BSL mechanism may be used for standard system start-up as well as only for special
occasions like system maintenance (firmware update) or end-of-line programming or
testing.
24.4.2
Entering the CAN bootstrap loader (BSL)
The ST10F252M enters BSL mode, if pin P0L.4 is sampled low at the end of a hardware
reset. In this case, the built-in bootstrap loader is activated independently of the selected
bus mode. The bootstrap loader code is stored in a special test Flash, no part of the
standard mask ROM or Flash memory area is required for this.
After entering BSL mode and completing the initialization, the ST10F252M scans the
CAN1_TxD line to receive the following initialization frame:
●
standard identifier = 0x0
DLC = 0x0.
●
As all the bits to be transmitted are dominant bits, a succession of five dominant bits and
one stuff bit on the CAN network is used. From the duration of this frame, it calculates the
corresponding baud rate factor with respect to the current CPU clock, initializes the CAN1
interface accordingly, switches pin CAN1_TxD to output and enables the CAN1 interface to
take part in the network communication. Using ths baud rate, a message object is
configured to send an acknowledge frame. he ST10F252M does not send this message
object but the host can request it by sng a remote frame.
The acknowledge frame is the following for the ST10F252M:
●
●
●
●
●
standard identifier = 0xE6
DLC = 0x3
Data0 = 0xD5, that is, generic acknowledge of the ST10 devices
Data1 = CHIP least significant byte
Da2 = IDCHIP most significant byte
For the ST10F252M, IDCHIP = 0FCXh.
Note:
Two behaviors can be distinguished in the acknowledging of the ST10 to the host. If the host
is behaving according to the CAN protocol, as at the beginning, the ST10 CAN is not
configured, the host is alone on the CAN network and will not get any acknowledgement. It
automatically resends the zero frame. As soon as the ST10 CAN is configured, it
acknowledges the zero frame. The “acknowledge frame” with identifier 0xE6 is configured,
but the transmit request is not set. The host can request this frame to be sent and, therefore,
get the IDCHIP by sending a remote frame.
As the IDCHIP is sent in the acknowledge frame, the Flash programming software can now
know immediately the exact type of device to be programmed.
24.4.3
ST10 configuration in CAN BSL
When the ST10F252M enters BSL mode via CAN, the following configuration is
automatically set (values that deviate from the normal reset values, are marked):
242/328
ST10F252M
Bootstrap loader
Notes
Figure 103. Register configuration in CAN BSL
Register
Watchdog Timer:
Value
Disabled
XRAM1-2, CAN1, XFlash and
XMISC enabled
XPERCON:
042Dh
(1)
SYSCON:
0404h
XPEN bit set
Context Pointer CP:
Register STKUN:
Stack Pointer SP:
Register STKOV:
FA00h
FA00h
FA40h
FC00h
according to start-up
configuration (2)
BUSCON0:
CAN1 Status/Control Register:
CAN1 Bit Timing Register:
0000h
according to ‘Zero’
frame
P4.6 / CAN1_TxD:
DP4.6:
‘1’
‘1’
1. In bootstrap modes (standard or alternate), ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
level. BYTDIS, bit 9 of SYSCON, is set according o data bus width selection via PORT0 configuration.
2. BUSCON0 is initialized with 0000h, externdisabled, if pin EA is high during reset. If pin EA is low
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set according to PORT0 configuration.
The watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin
CAN1_TxD is configured as output, so the ST10F252M can return the identification frame.
Even if the internal Flash is enabled, no code can be executed from it.
24.4.4
Loading thstartup code via CAN
After sending the acknowledge byte the BSL enters a loop to receive 128 bytes via CAN1.
Hint: the number of bytes loaded when booting via the CAN interface has been extended to
128 bytes to allow the re-configuration of the CAN bit timing register with the best timings
(synchronization window, ...). This can be achieved by the following sequence of
instructions:
ReconfigureBaudRate:
MOV R1,#041h
MOV DPP3:0EF00h,R1
MOV R1,#01600h
; Put CAN in Init, enable Configuration Change
; 1MBaud at Fcpu = 20 MHz
MOV DPP3:0EF06h,R1
These 128 bytes are stored sequentially into locations 00’FA40h through 00’FABFh of the
internal RAM (DPRAM). Up to 64 instructions may be placed into the RAM area. To execute
the loaded code, the BSL jumps to location 00’FA40h, that is, the first loaded instruction.
The bootstrap loading sequence is now terminated but the ST10F252M remains in BSL
mode. Most probably, the initially loaded routine loads additional code or data, as an
average application is likely to require substantially more than 64 instructions. This second
243/328
Bootstrap loader
ST10F252M
receive loop may directly use the pre-initialized CAN interface to receive data and store it in
arbitrary user-defined locations.
This second level of loaded code may be the final application code. It may also be another,
more sophisticated, loader routine that adds a transmission protocol to enhance the integrity
of the loaded code or data. It may also contain a code sequence to change the system
configuration and enable the bus interface to store the received data into external memory.
This process may go through several iterations or may directly execute the final application.
In all cases, the ST10F252M still runs in BSL mode, that is, with the watchdog timer
disabled and limited access to the internal Flash area. All code fetches from the internal
Flash area (01’0000h to 08’FFFFh) are redirected to the special test Flash. Data fetches
access the internal Flash of the ST10F252M, if any is available, but return undefined data
on ROM-less devices.
24.4.5
Choosing the baud rate for the BSL via CAN
The bootstrap via CAN acts in the same way than the UART bootstrap mode. When the
ST10F252M is started in BSL mode, it polls the RxD0 and CAN1_RxD es. On polling a
low level on one of these lines, a timer is launched that is stopped whn the line gets back to
high level.
For CAN communication, the algorithm is made to receive a zero frame, that is, a standard
identifier is 0x0, DLC is 0. This frame will produce thfollowing levels: 5D, 1R, 5D, 1R, 5D,
1R, 5D, 1R, 5D, 1R, 4D, 1R, 1D, 11R. The algorim runs the timer until the detection of the
fifth recessive bit. This calculates the bit timing over the duration of 29 bits; this minimizes
the error introduced by the polling.
Figure 104. Bit rate measurement over a predefined zero-frame
Start
Stuff bit
Stuff bit
Stuff bit
Stuff bit
........
Measured Time
Error induced by the polling
The code used for the polling is as follows:
WaitCom:
JNB
JB
P4.5,CAN_Boot
P3.11,WaitCom
T6R
; if SOF detected on CAN, then go to CAN loader
; Wait for start bit at RXD0
; Start Timer T6
BSET
....
CAN_Boot:
BSET
PWMCON0.0
; Start PWM Timer0
; (resolution is 1 CPU clk cycle)
244/328
ST10F252M
Bootstrap loader
JMPR
cc_UC,WaitRecessiveBi
t
WaitDominantBit:
JB
P4.5,WaitDominantBit ; wait for end of stuff bit
WaitRecessiveBit:
JNB
P4.5,WaitRecessiveBit; wait for 1st dominant bit = Stuff bit
R1,#5 ; Test if 5th stuff bit detected
cc_NE,WaitDominantBit; No, go back to count more
PWMCON.0 ; Stop timer
CMPI1
JMPR
BCLR
; here the 5th stuff bit is detected:
; PT0 = 29 Bit_Time (25D and 4R)
Therefore, the maximum error at the detection of the communication on CAN pin is:
(1 not taken + 1 taken jumps) + 1 taken jump + 1 bit set: (6) + 6 CPU clock cycles
The error at the detection for the fifth recessive bit is:
(1 taken jump) + 1 not taken jump + 1 compare + 1 bit clear: (4) + CPU cycles
In the worst case, the induced error is of six CPU clock cycles. So the polling could induce
an error of six timer ticks.
Error induced by the bit rate calculation
The code used for the polling is as follows:
WaitCom:
JNB
P4.5,CAN_Boot
; if SOF detected on CAN,
; then go to CAN loader
JB
P3.11,WaitCom
T6R
; Wait for start bit at RxD0
; Start Timer T6
BSET
....
CA_Boot:
BSET
PWMCON0.0
; Start PWM Timer0
; (resolution is 1 CPU clk cycle)
JMPR
cc_UC,WaitRecessiveBit
WaitDominantBit:
JB P4.5,WaitDominantBit ; wait for end of stuff bit
WaitRecessiveBit:
JNB
P4.5,WaitRecessiveBit ; wait for 1st dominant bit = Stuff bit
R1,#5 ; Test if 5th stuff bit detected
cc_NE,WaitDominantBit ; No, go back to count more
CMPI1
JMPR
BCLR
PWMCON.0
; Stop timer
; here the 5th stuff bit is detected:
; PT0 = 29 Bit_Time (25D and 4R)
Therefore, the maximum error at the detection of the communication on CAN pin is:
(1 not taken + 1 taken jumps) + 1 taken jump + 1 bit set: (6) + 6 CPU clock cycles
245/328
Bootstrap loader
ST10F252M
The error at the detection for the fifth recessive bit is:
(1 taken jump) + 1 not taken jump + 1 compare + 1 bit clear: (4) + 6 CPU cycles
In the worst case the induced error is of six CPU clock cycles. So the polling could induce an
error of six timer ticks.
Error induced by the baud rate calculation
The content of the timer PT0 counter corresponds to 29 bit times. This gives the following
equation:
PT0 = 58 × (BRP + 1) × (1 + Tseg1 + Tseg2)
where BRP, Tseg1 and Tseg2 are the fields of the CAN bit timing register.
The CAN protocol specification recommends the implementation of a bit time that has at
least 8 time quantum (tq). This recommendation applies here. The maximum bit time length
is 25 tq. To have good precision, the target has the smallest bit rate prescaler (BRP) and the
maximum number of tq in a bit time.
This gives the following ranges for PT0 according to BRP:
8 ≤1 + Tseg1 + Tseg2 ≤25
464 × (1 + BRP) ≤PT0 ≤1450 × (1 + BRP)
Table 127. Ranges of timer contents in function of BRP value
BRP
PT0_min
PT0_max
Comments
0
1
464
1451
2901
4351
5801
7251
..
50
2900
4350
5800
7250
8700
..
2
3
4
5
..
43
44
45
..
20416
20880
21344
..
63800
65250
66700
..
Possible Timer overflow
63
X
X
The error from the measurement of the 29 bits is:
e = 6 / [PT0]
1
It is a maximum for the smallest BRP value and the smallest number of ticks in PT0.
Therefore:
e
= 1.29%
1 Max
To have better precision, the target is to have the smallest BRP so that the time quantum is
the smallest possible. Thus an error on the calculation of time quanta in a bit time is
246/328
ST10F252M
Bootstrap loader
minimized. To do so, the value of PT0 is divided in ranges of 1450 ticks. In the algorithm,
PT0 is divided by 1451 and the result is BRP.
The calculated BRP value is used to divide PT0 to have the value of (1 + Tseg1 + Tseg2). A
table is generated to set the values for Tseg1 and Tseg2 according to the value of (1 +
Tseg1 + Tseg2). These values of Tseg1 and Tseg2 are chosen to reach a sample point
between 70% and 80% of the bit time.
During the calculation of (1 + Tseg1 + Tseg2), an error e can be introduced by the division.
2
This error is a maximum of one time quantum.
To compensate any possible error on bit rate, the (re)synchronization jump width is fixed at
two time quanta.
24.4.6
How to compute the baud rate error
Considering the following conditions, the error is calculated as example.
●
CPU frequency: 20 MHz
target bit rate: 1 Mbit/s
●
In these conditions, the content of PT0 timer for 29 Bit should e:
29 × 20× 106
29 × Fcpu
---------------------------
[PT0] =
= --------------------------------- = 580
1× 106
BitRate
Therefore:
This gives:
574 < [PT586
●
BRP = 0
tq = 100 ns
●
Computation of + Tseg1 + Tseg2 from the equation:
[PT0] = 58 × (1 + BRP) × (1 + Tseg1 + Tseg2)
Thus:
574
58
586
58
---------
9 =
≤1 + Tseg1 + Tseg2 ≤--------- = 10
In the algorithm, a rounding to the superior value is made if the remainder of the division is
greater than half of the divisor. Here it would have been the case if the PT0 content was 574.
Thus in this example it results 1+Tseg1+Tseg2 = 10, giving a bit time of exactly 1μs and,
thus, no error in bit rate.
Note:
Note:
In most cases (24 MHz, 32 MHz, 40 MHz of CPU frequency and 125, 250, 500 or 1 Mb/s of
bit rate), there is no error. However, it is better to check the error with the real application
parameters.
The content of the Bit Timing register is: 0x1640. This gives a sample point at 80%.
The (re)synchronization jump width is fixed at two time quanta.
247/328
Bootstrap loader
ST10F252M
24.4.7
Bootstrap via CAN
After the bootstrap phase, the ST10F252 CAN module is configured as follow:
●
●
●
the pin P4.6 is configured as output (the latch value is ‘1’ = recessive) to assume
CAN1_TxD function.
the MO2 is configured to output the acknowledge of the bootstrap with the standard
identifier 0xE6, a DLC of 3 and Data0 = 0xD5, Data1 and 2 = IDCHIP.
The MO1 is configured to receive messages with the standard identifier 0x5; its
acceptance mask is set so that all bits match – the DLC received is not checked; the
ST10 expects only 1 byte of data at a time.
No other message is sent by the ST10F252M after the acknowledge.
Note:
The CAN boot waits for 128 byte of data instead of 32 (see UART boot). This is done in
order to allow the user to reconfigure the CAN bitrate as soon as possible.
24.5
Comparing the old and the new bootstrap loader
Table 128 and 129 summarize the differences between the olST10 (boot via UART only)
bootstrap and the new one (boot via UART or CAN).
24.5.1
Software aspects
Table 128 summarizes the software differences.
Table 128. Software topics summ
Old bootstrap loader
New bootstrap loader
Comments
for compatibility between boot
via UART and boot via CAN1,
please avoid loading the
application software in the
00’FA60h/00’FABFh range
uses only 32 bytes in Dual-Port uses up to 128 bytes in Dual-
RAM from 00’FA40h
Port RAM from 00’FA40h
load 32 bytes from UART (boot same files can be used for boot
load 32 bytes from UART
via UART mode)
via UART.
user selected Xperipherals can
user can change the
be enabled during boot (step 3 Xperipherals selection is fixed.
or step 4)
Xperipherals selections through
a specific code.
As the CAN1 is needed, the XPERCON register is configured by the bootstrap loader code
and bit XPEN of SYSCON is set. As long as the EINIT instruction is not executed (and it is
not in the bootstrap loader code), the settings can be modified. Perform the following steps
to do this:
●
disable the XPeripherals by clearing XPEN in SYSCON register; this part of code must
not be located in XRAM as it will be disabled
●
●
enabled the required XPeripherals by writing the correct value in XPERCON register
set XPEN bit in SYSCON.
248/328
ST10F252M
Bootstrap loader
24.5.2
Hardware aspects
Although the new bootstrap loader has been designed to be compatible with the old
bootstrap loader, there are few hardware requirements with the new bootstrap loader. These
are summarized in Table 129.
Table 129. Hardware topics summary
Actual bootstrap loader
New bootstrap loader
Comments
P4.5 and P4.6 cannot be used
as user output in BSL mode, but
only as CAN1 alternate pins or
inputs or address-segments
P4.5 and P4.6 can be used as
output in BSL mode
level on CAN1_RxD can change level on CAN1_RxD must be
during boot step2 stable at ‘1’ during boot step2
external pull-up on P4.5 needed
249/328
Bootstrap loader
Figure 105. Reset Boot Sequence
ST10F252M
RSTIN 0 to 1
Standard Start
Yes (P0L[5..4] = ‘01’)
No (P0L[5..4] = ‘11’)
Boot Mode?
Yes (P0L[5..4] = ‘10’)
No (P0L[5..4] = ‘other config.’)
ST Test Modes
Software Checks
User Reset Vector
(K1 is OK?)
K1 is OK
K1 is not OK
Software Checks
Alternate Reset Vector
(K2 is OK?)
K2 is not OK
K2 is OK
Read 00’1FFCh
Long Jump to
09’0000h
SW RESET
Running from test Flash
ABM / User Flash
Start at 09’0000h
Std. Bootstrap Loader
Jump to Test-Flash
User Mode / User Flash
Selective Bootstrap Loader
Start at 00’0000h
Jump to Test-Flash
250/328
ST10F252M
Identification registers
25
Identification registers
The ST10F252M has four Identification registers, mapped in ESFR space. These register
contain:
●
●
●
●
a manufacturer identifier
a chip identifier, with its revision
an internal memory and size identifier
programming voltage description.
Manufacturer identifier register
IDMANUF register (F07Eh/3Fh)
ESFR
Reset value: 0403h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MANUF
RO
PROCESSID
RO
RO
RO
RO
RO
Table 130. Manufacturer identifier register functions
Bit Name Function
Manufacturer identifier
15.5 MANUF
‘020h’: STMelectronics manufacturer (JTAG worldwide
normalizatio
Process identifier
4.0 PROCESSID
‘03h’: 0.18 μm CMOS process
Chip identifier register
IDCHIP rster (F07Ch/3Eh)
ESFR
Reset value: 0FCxh
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PCONF
CHIPID
REVID
RO
RO
RO
RO
RO
RO
Table 131. Chip identifier register functions
Bit Name
Function
Peripheral Configuration
‘00’: (E) Enhanced (ST10F252)
‘01’: (B) Basic
15.14 PCONF
‘10’: (D) Dedicated
‘11’: reserved
251/328
Identification registers
ST10F252M
Table 131. Chip identifier register functions (continued)
Bit Name Function
ST10 Module Identifier
13.4 CHIPID
‘0FCh’: ST10F252M Identifier (252)
ST10 Module Revision Identifier (Full Mask Set revision)
‘01h’: Rev. A (First main revision)
3.0 REVID
‘02h’: Rev. B (Second main revision)
:
‘0Fh’: Rev. P
Figure 106. Internal memory and size identifier register
IDMEM register (F07Ah/3Dh)
ESFR
Reset value: 2040h
15 14 13 12
11
10
9
8
7
6
5
4
3
2
1
0
MEMTYP
RO
MEMSIZE
RO
Table 132. Internal memory and size identifier register functions
Bit Name Function
Internal memory type
‘0h’: ROM-l
‘1h’: (M) ROM memory
15.12 MEMTYP
‘2h’: (S) Standard Flash memory (ST10F252M)
‘3h’: (H) High performance Flash memory
‘4h...Fh’: reserved.
Internal Memory Size
11.0 MEMSIZ
Internal Memory size is 4 * <MEMSIZE> (in Kbyte)
‘040h’: ST10F252M (256 Kbytes).
Programming voltage description register
IDPROG register (F078h/3Ch)
15 14 13 12
ESFR
Reset value: 0040h
11
10
9
8
7
6
5
4
3
2
1
0
PROGVPP
RO
PROGVDD
RO
Table 133. Programming voltage description register functions
Bit Name Function
15.8 PROGVPP
Programming VPP voltage (no need of external VPP) - 00h
Programming VDD voltage
VDD voltage when programming EPROM or Flash devices is calculated
using the following formula:
7.0 PROGVDD
VDD = 20 * <PROGVDD> / 256 [V]
‘40h’: ST10F252M (5.0 V).
252/328
ST10F252M
Identification registers
The values written in the different identification register bits are valid only after the Flash
initialization phase is completed. When code execution is started from internal memory (pin
EA held high during reset), the Flash has certainly completed its initialization, so the bits of
identification registers are immediately ready to be read out. When code execution is started
from external memory (pin EA held low during reset), the Flash initialization is not yet
completed, so the bits of identification registers are not ready. Poll bits 15 and 14 of the
IDMEM register; when both bits read low, the Flash initialization is complete, so all
identification register bits are correct.
Before Flash initialization completion, the default setting of the different Identification
Registers are as follows:
IDMANUF
IDCHIP
0403h
0FCnh 0FBnh (with n representing the silicon revision number)
IDMEM
F2040h
0040h
IDPROG
253/328
Register set
ST10F252M
26
Register set
26.1
General purpose registers
General purpose registers (GPRs) form the register bank that the CPU works with. This
register bank may be located anywhere within the internal RAM via the context pointer (CP).
Due to the addressing mechanism, GPR banks can only reside within the internal RAM. All
GPRs are bit-addressable.
Table 134. General purpose registers (GPRs)
Physical
address address
8-bit
Reset
value
Name
Description
R0
R1
(CP) + 0
(CP) + 2
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
CPU General Purpose (word) Register R0
CPU General Purpose (word) Register R1
CPU General Purpose (word) Register 2
CPU General Purpose (word) Register R3
CPU General Purpose (word) Register R4
CPU General Purpose (word) Register R5
CPU General rpose (word) Register R6
CPU Geral Purpose (word) Register R7
CPGeneral Purpose (word) Register R8
CPU General Purpose (word) Register R9
CPU General Purpose (word) Register R10
CPU General Purpose (word) Register R11
CPU General Purpose (word) Register R12
CPU General Purpose (word) Register R13
CPU General Purpose (word) Register R14
CPU General Purpose (word) Register R15
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
UUUUh
R2
(CP) + 4
R3
(CP) + 6
R4
(CP) + 8
R5
(CP) + 10
(CP) + 12
(CP) + 14
(CP) + 16
(CP) + 18
(CP) + 20
(CP) + 22
(C+ 24
(CP) + 26
(CP) + 28
(CP) + 30
R6
R7
R8
R9
R10
R11
R12
R1
R14
R15
The first eight GPRs (R7...R0) may also be accessed byte wise. Other than with SFRs,
writing to a GPR byte does not affect the other byte of the respective GPR. The respective
halves of the byte-accessible registers receive special names as shown in Table 135.
Table 135. General purpose registers (GPRs) bit wise addressing
Physical
address address
8-bit
Reset
value
Name
Description
RL0
RH0
RL1
RH1
RL2
(CP) + 0
(CP) + 1
(CP) + 2
(CP) + 3
(CP) + 4
F0h
F1h
F2h
F3h
F4h
CPU General Purpose (byte) Register RL0
CPU General Purpose (byte) Register RH0
CPU General Purpose (byte) Register RL1
CPU General Purpose (byte) Register RH1
CPU General Purpose (byte) Register RL2
UUh
UUh
UUh
UUh
UUh
254/328
ST10F252M
Register set
Table 135. General purpose registers (GPRs) bit wise addressing (continued)
Physical
address address
8-bit
Reset
value
Name
Description
RH2
RL3
RH3
RL4
RH4
RL5
RH5
RL6
RH6
RL7
RH7
(CP) + 5
(CP) + 6
(CP) + 7
(CP) + 8
(CP) + 9
(CP) + 10
(CP) + 11
(CP) + 12
(CP) + 13
(CP) + 14
(CP) + 15
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
CPU General Purpose (byte) Register RH2
CPU General Purpose (byte) Register RL3
CPU General Purpose (byte) Register RH3
CPU General Purpose (byte) Register RL4
CPU General Purpose (byte) Register RH4
CPU General Purpose (byte) Register RL5
CPU General Purpose (byte) Register RH5
CPU General Purpose (byte) Register RL6
CPU General Purpose (byte) Register RH6
CPU General Purpose (byte) Register 7
CPU General Purpose (byte) egister RH7
UUh
UUh
UUh
UUh
UUh
UUh
UUh
UUh
UUh
UUh
UUh
26.2
Special function register overview
26.2.1
Registers ordered by name
Table 136 lists all SFRs which are implemented in the ST10F252M in alphabetical order. Bit-
addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.
Table 136. Special function registers listed by name
Psical
address
8-bit
address
Reset
value
Name
Description
ADCIC
b
b
FF98h
CCh
D0h
50h
50h
0Ch
0Dh
0Eh
0Fh
CDh
86h
8Ah
8Bh
8Ch
ADC end of Conversion Interrupt Control Reg.
ADC Control Register
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0xx0h
0000h
0000h
0000h
ADCON
ADDAT
ADDAT2
FFA0h
FEA0h
F0A0h E
ADC Result Register
ADC 2 Result Register
ADDRSEL1 FE18h
ADDRSEL2 FE1Ah
ADDRSEL3 FE1Ch
ADDRSEL4 FE1Eh
Address Select Register 1
Address Select Register 2
Address Select Register 3
Address Select Register 4
ADEIC
b
FF9Ah
ADC Overrun Error Interrupt Control Register
Bus Configuration Register 0
Bus Configuration Register 1
Bus Configuration Register 2
Bus Configuration Register 3
BUSCON0b FF0Ch
BUSCON1b FF14h
BUSCON2b FF16h
BUSCON3b FF18h
255/328
Register set
ST10F252M
Table 136. Special function registers listed by name (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
BUSCON4b FF1Ah
8Dh
25h
40h
BCh
41h
BDh
42h
BEh
43h
BFh
44h
C0h
45h
C1h
46h
C2h
47h
C3h
48h
C4h
49h
C5h
4Ah
C6h
4Bh
C7h
4Ch
C8h
4Dh
C9h
4Eh
CAh
4Fh
CBh
Bus Configuration Register 4
0000h
0000h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
CAPREL
CC0
FE4Ah
FE80h
FF78h
FE82h
FF7Ah
FE84h
FF7Ch
FE86h
FF7Eh
FE88h
FF80h
FE8Ah
FF82h
FE8Ch
FF84h
FE8Eh
FF86h
FE90h
FFh
FE92h
FF8Ah
FE94h
FF8Ch
FE96h
FF8Eh
FE98h
FF90h
FE9Ah
FF92h
FE9Ch
FF94h
FE9Eh
FF96h
GPT2 Capture/Reload Register
CAPCOM Register 0
CC0IC
CC1
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
CAPCOM Register 0 Interrupt Control Register
CAPCOM Register 1
CC1IC
CC2
CAPCOM Register 1 Interrupt Control Register
CAPCOM Register 2
CC2IC
CC3
CAPCOM Register 2 Interrupt Control Register
CAPCOM Register 3
CC3IC
CC4
CAPCOM Register 3 Interrupt Control gister
CAPCOM Register 4
CC4IC
CC5
CAPCOM Register 4 Interrupt Control Register
CAPCOM Register 5
CC5IC
CC6
CAPCOM Reer 5 Interrupt Control Register
CAPCORegister 6
CC6IC
CC7
CAOM Register 6 Interrupt Control Register
CAPCOM Register 7
CC7IC
CC8
CAPCOM Register 7 Interrupt Control Register
CAPCOM Register 8
CC8IC
CC9
CAPCOM Register 8 Interrupt Control Register
CAPCOM Register 9
CC9IC
CC10
CC10IC
CC11
CC11IC
CC12
CC12IC
CC13
CC13IC
CC14
CC14IC
CC15
CC15IC
CAPCOM Register 9 Interrupt Control Register
CAPCOM Register 10
CAPCOM Register 10 Interrupt Control Register
CAPCOM Register 11
CAPCOM Register 11 Interrupt Control Register
CAPCOM Register 12
CAPCOM Register 12 Interrupt Control Register
CAPCOM Register 13
CAPCOM Register 13 Interrupt Control Register
CAPCOM Register 14
CAPCOM Register 14 Interrupt Control Register
CAPCOM Register 15
CAPCOM Register 15 Interrupt Control Register
256/328
ST10F252M
Register set
Table 136. Special function registers listed by name (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
CC16
FE60h
30h
B0h
31h
B1h
32h
B2h
33h
B3h
34h
B4h
35h
B5h
36h
B6h
37h
B7h
38h
B8h
39h
B9h
3Ah
BAh
3Bh
BBh
3Ch
BCh
3Dh
C2h
3Eh
C6h
3Fh
CAh
A9h
AAh
CAPCOM Register 16
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
0000h
CC16IC
CC17
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
F160h
FE62h
F162h
FE64h
F164h
FE66h
F166h
FE68h
F168h
FE6Ah
E
E
E
E
E
CAPCOM Register 16 Interrupt Control Register
CAPCOM Register 17
CC17IC
CC18
CAPCOM Register 17 Interrupt Control Register
CAPCOM Register 18
CC18IC
CC19
CAPCOM Register 18 Interrupt Control Register
CAPCOM Register 19
CC19IC
CC20
CAPCOM Register 19 Interrupt Control Register
CAPCOM Register 20
CC20IC
CC21
CAPCOM Register 20 Interrupt Controegister
CAPCOM Register 21
CC21IC
CC22
F16Ah E
FE6Ch
CAPCOM Register 21 Interrupt Control Register
CAPCOM Register 22
CC22IC
CC23
F16Ch E
FE6Eh
CAPCOM Reer 22 Interrupt Control Register
CAPCORegister 23
CC23IC
CC24
F16Eh E
FE70h
CAOM Register 23 Interrupt Control Register
CAPCOM Register 24
CC24IC
CC25
F170h
FE72h
F1h
FE74h
F174h
FE76h
F176h
FE78h
F178h
FE7Ah
F184h
FE7Ch
E
E
E
E
E
E
CAPCOM Register 24 Interrupt Control Register
CAPCOM Register 25
CC25IC
CC26
CAPCOM Register 25 Interrupt Control Register
CAPCOM Register 26
CC26IC
CC27
CAPCOM Register 26 Interrupt Control Register
CAPCOM Register 27
CC27IC
CC28
CAPCOM Register 27 Interrupt Control Register
CAPCOM Register 28
CC28IC
CC29
CAPCOM Register 28 Interrupt Control Register
CAPCOM Register 29
CC29IC
CC30
CAPCOM Register 29 Interrupt Control Register
CAPCOM Register 30
CC30IC
CC31
F18Ch E
FE7Eh
CAPCOM Register 30 Interrupt Control Register
CAPCOM Register 31
CC31IC
CCM0
CCM1
b
b
b
F194h
FF52h
FF54h
E
CAPCOM Register 31 Interrupt Control Register
CAPCOM Mode Control Register 0
CAPCOM Mode Control Register 1
257/328
Register set
ST10F252M
Table 136. Special function registers listed by name (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
CCM2
b
b
b
b
b
b
FF56h
FF58h
FF22h
FF24h
FF26h
FF28h
FE10h
FF6Ah
FE08h
ABh
ACh
91h
92h
93h
94h
08h
B5h
04h
80h
81h
82h
83h
E1h
E3h
E5h
E7h
E9h
EBh
00h
01h
02h
03h
E0h
EDh
3Eh
3Fh
3Dh
3Ch
84h
85h
2Fh
2Eh
EEh
CAPCOM Mode Control Register 2
CAPCOM Mode Control Register 3
CAPCOM Mode Control Register 4
CAPCOM Mode Control Register 5
CAPCOM Mode Control Register 6
CAPCOM Mode Control Register 7
CPU Context Pointer Register
0000h
0000h
0000h
0000h
0000h
0000h
FC00h
- - 00h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0001h
0002h
0003h
0000h
0000h
CCM3
CCM4
CCM5
CCM6
CCM7
CP
CRIC
CSP
b
GPT2 CAPREL Interrupt Control Register
CPU Code Segment Pointer Register (read only)
P0L Direction Control Register
DP0L
DP0H
DP1L
DP1H
DP2
b
b
b
b
b
b
b
b
b
b
F100h
F102h
F104h
F106h
FFC2h
FFC6h
FFCAh
FFCEh
FFD2h
FFD6h
FEh
FE02h
FE04h
FE06h
E
E
E
E
P0h Direction Control Registe
P1L Direction Control Register
P1h Direction Control Register
Port 2 DirectioControl Register
DP3
Port 3 Dection Control Register
DP4
PoDirection Control Register
DP6
Port 6 Direction Control Register
DP7
Port 7 Direction Control Register
DP8
Port 8 Direction Control Register
DPP0
DPP1
DPP2
DPP3
EXICON
EXISEL
IDCHIP
IDMANUF
IDMEM
IDPROG
IDX0
CPU Data Page Pointer 0 Register (10-bit)
CPU Data Page Pointer 1 Register (10-bit)
CPU Data Page Pointer 2 Register (10-bit)
CPU Data Page Pointer 3 Register (10-bit)
External Interrupt Control Register
External Interrupt Source Selection Register
b
b
F1C0h E
F1DAh E
F07Ch E
F07Eh E
F07Ah E
Device Identifier Register (n is the device revision)
Manufacturer Identifier Register
On-chip Memory Identifier Register
Programming Voltage Identifier Register
MAC Unit Address Pointer 0
FBnh
0403h
2040h
0040h
0000h
0000h
0000h
0000h
0000h
F078h
FF08h
FF0Ah
FE5Eh
FE5Ch
FFDCh
E
b
b
IDX1
MAC Unit Address Pointer 1
MAH
MAC Unit Accumulator - High Word
MAC Unit Accumulator - Low Word
MAC Unit Control Word
MAL
MCW
b
258/328
ST10F252M
Register set
Table 136. Special function registers listed by name (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
MDC
b
FF0Eh
87h
06h
07h
EDh
EFh
E1h
E3h
E5h
E7h
E9h
EBh
8Fh
80h
81h
82h
83h
E0h
E2h
E4h
D1h
E6h
E8h
EAh
D2h
60h
61h
62h
63h
64h
65h
66h
67h
E2h
1Ch
CPU Multiply Divide Control Register
CPU Multiply Divide Register – High Word
CPU Multiply Divide Register – Low Word
MAC Unit Repeat Word
0000h
0000h
0000h
0000h
0200h
0000h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
FFFFh
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
- - 00h
XXXXh
- - 00h
- - 00h
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
MDH
MDL
FE0Ch
FE0Eh
FFDAh
FFDEh
F1C2h E
F1C6h E
F1CAh E
F1CEh E
F1D2h E
F1D6h E
FF1Eh
MRW
MSW
ODP2
ODP3
ODP4
ODP6
ODP7
ODP8
ONES
P0L
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
MAC Unit Status Word
Port 2 Open Drain Control Register
Port 3 Open Drain Control Register
Port 4 Open Drain Control Register
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
Port 8 Open Drain Control Reister
Constant Value 1’s Register (read only)
PORT0 Low Register (Lower half of PORT0)
PORT0 High gister (Upper half of PORT0)
PORT1 ow Register (Lower half of PORT1)
PO1 High Register (Upper half of PORT1)
Port 2 Register
FF00h
P0H
FF02h
P1L
FF04h
P1H
FF06h
P2
FFC0h
P3
FFC4h
Port 3 Register
P4
FFC8h
FFh
Port 4 Register (8-bit)
P5
Port 5 Register (read only)
P6
FFCCh
FFD0h
FFD4h
FFA4h
Port 6 Register (8-bit)
P7
Port 7 Register (8-bit)
P8
Port 8 Register (8-bit)
P5DIDIS
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
PICON
PP0
Port 5 Digital Disable Register
PEC Channel 0 Control Register
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
Port Input Threshold Control Register
PWM Module Period Register 0
FEC0h
FEC2h
FEC4h
FEC6h
FEC8h
FECAh
FECCh
FECEh
F1C4h E
b
F038h
E
259/328
Register set
ST10F252M
Table 136. Special function registers listed by name (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
PP1
F03Ah E
F03Ch E
F03Eh E
FF10h
1Dh
1Eh
1Fh
88h
18h
19h
1Ah
1Bh
18h
19h
1Ah
1Bh
98h
99h
BFh
02h
03h
00h
01h
84h
PWM Module Period Register 1
PWM Module Period Register 2
PWM Module Period Register 3
CPU Program Status Word
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
PP2
PP3
PSW
PT0
PT1
PT2
PT3
PW0
PW1
PW2
PW3
b
F030h
F032h
F034h
F036h
FE30h
FE32h
FE34h
FE36h
E
E
E
E
PWM Module Up/Down Counter 0
PWM Module Up/Down Counter 1
PWM Module Up/Down Counter 2
PWM Module Up/Down Counter 3
PWM Module Pulse Width Register 0
PWM Module Pulse Width Register 1
PWM Module Pulse Width Reister 2
PWM Module Pulse Width Register 3
PWM Module Control Register 0
PWM Module ntrol Register 1
PWM Mule Interrupt Control Register
MAUnit Offset Register R0
PWMCON0b FF30h
PWMCON1b FF32h
PWMIC
QR0
b
F17Eh E
F004h
F006h
F000h
F002h
F1h
FEB4h
E
E
E
E
E
QR1
MAC Unit Offset Register R1
QX0
MAC Unit Offset Register X0
QX1
MAC Unit Offset Register X1
RP0H
S0BG
b
System Start-up Configuration Register (read only)
- - XXh
0000h
Serial Channel 0 Baud Rate Generator Reload
Register
5Ah
S0CON
S0EIC
b
b
FFB0h
FF70h
FEB2h
D8h
B8h
Serial Channel 0 Control Register
0000h
- - 00h
Serial Channel 0 Error Interrupt Control Register
S0RBUF
Serial Channel 0 Receive Buffer Register (read
only)
59h
B7h
CEh
58h
B6h
- - XXh
- - 00h
- - 00h
0000h
- - 00h
S0RIC
b
b
FF6Eh
Serial Channel 0 Receive Interrupt Control
Register
S0TBIC
S0TBUF
S0TIC
F19Ch E
FEB0h
Serial Channel 0 Transmit Buffer Interrupt Control
Reg.
Serial Channel 0 Transmit Buffer Register (write
only)
b
FF6Ch
Serial Channel 0 Transmit Interrupt Control
Register
SP
FE12h
09h
5Ah
CPU System Stack Pointer Register
SSC Baud Rate Register
FC00h
0000h
SSCBR
F0B4h E
260/328
ST10F252M
Register set
Table 136. Special function registers listed by name (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
SSCCON b FFB2h
D9h
BBh
59h
BAh
58h
B9h
0Ah
0Bh
89h
28h
A8h
CEh
2Ah
29h
CFh
2Bh
20h
A0h
B0h
21h
A1h
B1h
22h
A2h
B2h
23h
A3h
B3h
24h
A4h
B4h
28h
90h
BDh
SSC Control Register
0000h
- - 00h
XXXXh
- - 00h
0000h
- - 00h
FA00h
FC00h
SSCEIC
SSCRB
SSCRIC
SSCTB
SSCTIC
STKOV
STKUN
b
b
b
FF76h
SSC Error Interrupt Control Register
SSC Receive Buffer (read only)
SSC Receive Interrupt Control Register
SSC Transmit Buffer (write only)
SSC Transmit Interrupt Control Register
CPU Stack Overflow Pointer Register
CPU Stack Underflow Pointer Register
CPU System Configuration Register
CAPCOM Timer 0 Register
F0B2h E
FF74h
F0B0h E
FF72h
FE14h
FE16h
1)
SYSCON b FF12h
T0 FE50h
T01CON b FF50h
0xx0h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
CAPCOM Timer 0 and Timer Control Register
CAPCOM Timer 0 Interrupt Control Register
CAPCOM Timer 0 Reload Register
CAPCOM Tim1 Register
T0IC
T0REL
T1
b
FF9Ch
FE54h
FE52h
FF9Eh
FE56h
FE40h
FF40h
FF60h
FEh
FF42h
FF62h
FE44h
FF44h
FF64h
FE46h
FF46h
FF66h
FE48h
FF48h
FF68h
F050h
T1IC
T1REL
T2
b
CAPCOTimer 1 Interrupt Control Register
CAOM Timer 1 Reload Register
GPT1 Timer 2 Register
T2CON
T2IC
T3
b
b
GPT1 Timer 2 Control Register
GPT1 Timer 2 Interrupt Control Register
GPT1 Timer 3 Register
T3CON
T3IC
T4
b
b
GPT1 Timer 3 Control Register
GPT1 Timer 3 Interrupt Control Register
GPT1 Timer 4 Register
T4CON
T4IC
T5
b
b
GPT1 Timer 4 Control Register
GPT1 Timer 4 Interrupt Control Register
GPT2 Timer 5 Register
T5CON
T5IC
T6
b
b
GPT2 Timer 5 Control Register
GPT2 Timer 5 Interrupt Control Register
GPT2 Timer 6 Register
T6CON
T6IC
T7
b
b
GPT2 Timer 6 Control Register
GPT2 Timer 6 Interrupt Control Register
CAPCOM Timer 7 Register
E
T78CON b FF20h
T7IC F17Ah E
CAPCOM Timer 7 and 8 Control Register
CAPCOM Timer 7 Interrupt Control Register
b
261/328
Register set
Table 136. Special function registers listed by name (continued)
ST10F252M
Physical
address
8-bit
address
Reset
value
Name
Description
T7REL
F054h
F052h
E
E
2Ah
29h
BEh
2Bh
D6h
57h
D7h
0Eh
C3h
C7h
CBh
CFh
12h
8Eh
CAPCOM Timer 7 Reload Register
CAPCOM Timer 8 Register
CAPCOM Timer 8 Interrupt Control Register
CAPCOM Timer 8 Reload Register
Trap Flag Register
0000h
0000h
T8
T8IC
T8REL
TFR
WDT
b
b
F17Ch E
- - 00h
F056h
FFACh
FEAEh
E
0000h
0000h
Watchdog Timer Register (read only)
Watchdog Timer Control Register
XPER Address Select Register 3
See Section 9.2
0000h
WDTCON b FFAEh
00xxh 2)
F01Ch
E
XADRS3
800Bh
XP0IC
XP1IC
XP2IC
XP3IC
b
b
b
b
F186h
F18Eh E
F196h
F19Eh E
E
- - 00h 3)
- - 00h 3)
- - 00h 3)
- - 00h 3)
- - 05h
See Section 9.2
E
See Section 9.2
See Section 9.2
XPERCON
ZEROS
F024h
FF1Ch
E
XPER Configuration Register
Constant Valu’s Register (read only)
b
0000h
Note:
1
2
3
The system configuration is selected dineset.
Reset value depends on different triggered reset event.
The XPnIC interrupt control registers control interrupt requests from integrated X-Bus
peripherals. Some software controlled interrupt requests may be generated by setting the
XPnIR bits (of XPnIC register) of the unused X-peripheral nodes.
26.2.2
Registers ordered by address
Table 17 lists all SFRs which are implemented in the ST10F252M ordered by their physical
address. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs
within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”.
Table 137. Special function registers listed by address
Physical
address
8-bit
address
Reset
value
Name
Description
QX0
F000h
F002h
F004h
E
E
E
E
00h
01h
02h
03h
0Eh
12h
18h
MAC Unit Offset Register X0
MAC Unit Offset Register X1
MAC Unit Offset Register R0
MAC Unit Offset Register R1
XPER Address Select Register 3
XPER Configuration Register
PWM Module Up/Down Counter 0
0000h
0000h
0000h
0000h
800Bh
- - 05h
0000h
QX1
QR0
QR1
F006h
F01Ch
E
XADRS3
XPERCON
PT0
F024h
F030h
E
E
262/328
ST10F252M
Register set
Table 137. Special function registers listed by address (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
PT1
F032h
F034h
F036h
F038h
E
E
E
E
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
28h
29h
2Ah
2Bh
3Ch
3Dh
3Eh
3Fh
50h
58h
59h
5Ah
80h
81h
82h
83h
84h
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
PWM Module Up/Down Counter 1
PWM Module Up/Down Counter 2
PWM Module Up/Down Counter 3
PWM Module Period Register 0
PWM Module Period Register 1
PWM Module Period Register 2
PWM Module Period Register 3
CAPCOM Timer 7 Register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
001740h
32040h
PT2
PT3
PP0
PP1
F03Ah E
F03Ch E
F03Eh E
PP2
PP3
T7
F050h
F052h
F054h
F056h
F078h
E
E
E
E
E
T8
CAPCOM Timer 8 Register
T7REL
T8REL
IDPROG
IDMEM
IDCHIP
IDMANUF
ADDAT2
SSCTB
SSCRB
SSCBR
DP0L
CAPCOM Timer 7 Reload Register
CAPCOM Timer 8 Reload Rester
Programming Voltage Identifier Register
On-chip Memory Identifier Register
F07Ah E
F07Ch E
F07Eh E
F0A0h E
F0B0h E
F0B2h E
F0B4h E
Device IdentifiRegister (n is the device revision)
Manufarer Identifier Register
FBnh
0403h
0000h
0000h
XXXXh
0000h
- - 00h
- - 00h
- - 00h
- - 00h
- - XXh
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
ADResult Register
SSC Transmit Buffer (write only)
SSC Receive Buffer (read only)
SSC Baud Rate Register
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
F1h
F102h
F104h
F106h
F108h
F160h
F162h
F164h
F166h
F168h
E
E
E
E
E
E
E
E
E
E
P0L Direction Control Register
DP0H
P0h Direction Control Register
DP1L
P1L Direction Control Register
DP1H
P1h Direction Control Register
RP0H
System Start-up Configuration Register (read only)
CAPCOM Register 16 Interrupt Control Register
CAPCOM Register 17 Interrupt Control Register
CAPCOM Register 18 Interrupt Control Register
CAPCOM Register 19 Interrupt Control Register
CAPCOM Register 20 Interrupt Control Register
CAPCOM Register 21 Interrupt Control Register
CAPCOM Register 22 Interrupt Control Register
CAPCOM Register 23 Interrupt Control Register
CAPCOM Register 24 Interrupt Control Register
CAPCOM Register 25 Interrupt Control Register
CC16IC
CC17IC
CC18IC
CC19IC
CC20IC
CC21IC
CC22IC
CC23IC
CC24IC
CC25IC
F16Ah E
F16Ch E
F16Eh E
F170h
F172h
E
E
263/328
Register set
ST10F252M
Table 137. Special function registers listed by address (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
CC26IC
b
b
b
b
b
b
b
b
b
b
b
b
b
F174h
F176h
F178h
E
E
E
BAh
BBh
BCh
BDh
BEh
BFh
C2h
C3h
C6h
C7h
CAh
CBh
CAPCOM Register 26 Interrupt Control Register
CAPCOM Register 27 Interrupt Control Register
CAPCOM Register 28 Interrupt Control Register
CAPCOM Timer 7 Interrupt Control Register
CAPCOM Timer 8 Interrupt Control Register
PWM Module Interrupt Control Register
CAPCOM Register 29 Interrupt Control Register
See Section 9.2
- - 00h
- - 00h
CC27IC
CC28IC
T7IC
- - 00h
F17Ah E
F17Ch E
F17Eh E
- - 00h
T8IC
- - 00h
PWMIC
CC29IC
XP0IC
CC30IC
XP1IC
CC31IC
XP2IC
S0TBIC
- - 00h
F184h
F186h
E
E
- - 00h
- - 00h 3)
F18Ch E
F18Eh E
CAPCOM Register 30 Interrupt Control Register
See Section 9.2
- - 00h
- - 00h 3)
- - 00h
F194h
F196h
E
E
CAPCOM Register 31 InterruControl Register
See Section 9.2
- - 00h 3)
F19Ch E
Serial Channel 0 Transmit Buffer Interrupt Control
Reg.
CEh
- - 00h
XP3IC
EXICON
ODP2
PICON
ODP3
ODP4
ODP6
ODP7
ODP8
EXISEL
DPP0
DPP1
DPP2
DPP3
CSP
b
b
b
b
b
b
b
b
b
b
F19Eh E
F1C0h E
F1C2h E
F1C4h E
F1C6h E
F1Ah E
1CEh E
F1D2h E
F1D6h E
F1DAh E
FE00h
CFh
E0h
E1h
E2h
E3h
E5h
E7h
E9h
EBh
EDh
00h
01h
02h
03h
04h
06h
07h
08h
09h
0Ah
See Section 9.2
- - 00h 3)
0000h
0000h
- - 00h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
0001h
0002h
0003h
0000h
0000h
0000h
FC00h
FC00h
FA00h
Exal Interrupt Control Register
Port 2 Open Drain Control Register
Port Input Threshold Control Register
Port 3 Open Drain Control Register
Port 4 Open Drain Control Register
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
Port 8 Open Drain Control Register
External Interrupt Source Selection Register
CPU Data Page Pointer 0 Register (10-bit)
CPU Data Page Pointer 1 Register (10-bit)
CPU Data Page Pointer 2 Register (10-bit)
CPU Data Page Pointer 3 Register (10-bit)
CPU Code Segment Pointer Register (read only)
CPU Multiply Divide Register – High Word
CPU Multiply Divide Register – Low Word
CPU Context Pointer Register
FE02h
FE04h
FE06h
FE08h
MDH
FE0Ch
MDL
FE0Eh
CP
FE10h
SP
FE12h
CPU System Stack Pointer Register
CPU Stack Overflow Pointer Register
STKOV
FE14h
264/328
ST10F252M
Register set
Table 137. Special function registers listed by address (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
STKUN
FE16h
0Bh
0Ch
0Dh
0Eh
0Fh
18h
19h
1Ah
1Bh
20h
21h
22h
23h
24h
25h
28h
29h
2Ah
2Bh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
CPU Stack Underflow Pointer Register
Address Select Register 1
Address Select Register 2
Address Select Register 3
Address Select Register 4
PWM Module Pulse Width Register 0
PWM Module Pulse Width Register 1
PWM Module Pulse Width Register 2
PWM Module Pulse Width Register 3
GPT1 Timer 2 Register
FC00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
ADDRSEL1 FE18h
ADDRSEL2 FE1Ah
ADDRSEL3 FE1Ch
ADDRSEL4 FE1Eh
PW0
PW1
PW2
PW3
T2
FE30h
FE32h
FE34h
FE36h
FE40h
FE42h
FE44h
FE46h
FE48h
FE4Ah
FE50h
FE52h
FE54h
FE56h
FEh
FE5Eh
FE60h
FE62h
FE64h
FE66h
FE68h
FE6Ah
FE6Ch
FE6Eh
FE70h
FE72h
FE74h
FE76h
FE78h
T3
GPT1 Timer 3 Register
T4
GPT1 Timer 4 Register
T5
GPT2 Timer 5 Register
T6
GPT2 Timer 6 egister
CAPREL
T0
GPT2 Cpture/Reload Register
CAOM Timer 0 Register
CAPCOM Timer 1 Register
CAPCOM Timer 0 Reload Register
CAPCOM Timer 1 Reload Register
MAC Unit Accumulator - Low Word
MAC Unit Accumulator - High Word
CAPCOM Register 16
T1
T0REL
T1REL
MAL
MAH
CC16
CC17
CC18
CC19
CC20
CC21
CC22
CC23
CC24
CC25
CC26
CC27
CC28
CAPCOM Register 17
CAPCOM Register 18
CAPCOM Register 19
CAPCOM Register 20
CAPCOM Register 21
CAPCOM Register 22
CAPCOM Register 23
CAPCOM Register 24
CAPCOM Register 25
CAPCOM Register 26
CAPCOM Register 27
CAPCOM Register 28
265/328
Register set
ST10F252M
Table 137. Special function registers listed by address (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
CC29
FE7Ah
FE7Ch
FE7Eh
FE80h
FE82h
FE84h
FE86h
FE88h
FE8Ah
FE8Ch
FE8Eh
FE90h
FE92h
FE94h
FE96h
FE98h
FE9Ah
FE9Ch
FE9Eh
FEh
FEAEh
FEB0h
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
57h
CAPCOM Register 29
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
CC30
CC31
CC0
CAPCOM Register 30
CAPCOM Register 31
CAPCOM Register 0
CAPCOM Register 1
CAPCOM Register 2
CAPCOM Register 3
CAPCOM Register 4
CAPCOM Register 5
CAPCOM Register 6
CAPCOM Register 7
CAPCOM Register 8
CAPCOM Register 9
CAPCOM Reer 10
CAPCORegister 11
CAOM Register 12
CAPCOM Register 13
CAPCOM Register 14
CAPCOM Register 15
ADC Result Register
Watchdog Timer Register (read only)
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CC8
CC9
CC10
CC11
CC12
CC13
CC14
CC15
ADDAT
WDT
S0TBUF
Serial Channel 0 Transmit Buffer Register (write
only)
58h
59h
5Ah
0000h
- - XXh
0000h
S0RBUF
S0BG
FEB2h
FEB4h
Serial Channel 0 Receive Buffer Register (read
only)
Serial Channel 0 Baud Rate Generator Reload
Register
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
FEC0h
FEC2h
FEC4h
FEC6h
FEC8h
FECAh
FECCh
FECEh
60h
61h
62h
63h
64h
65h
66h
67h
PEC Channel 0 Control Register
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
266/328
ST10F252M
Register set
Table 137. Special function registers listed by address (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
P0L
b
b
b
b
b
b
FF00h
FF02h
FF04h
FF06h
FF08h
FF0Ah
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
98h
99h
A0h
A1h
A2h
A3h
A4h
A8h
A9h
AAh
ABh
ACh
B0h
PORT0 Low Register (Lower half of PORT0)
PORT0 High Register (Upper half of PORT0)
PORT1 Low Register (Lower half of PORT1)
PORT1 High Register (Upper half of PORT1)
MAC Unit Address Pointer 0
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
0xx0h
0000h
0000h
P0H
P1L
P1H
IDX0
IDX1
MAC Unit Address Pointer 1
BUSCON0b FF0Ch
Bus Configuration Register 0
MDC
PSW
b
b
FF0Eh
FF10h
CPU Multiply Divide Control Register
CPU Program Status Word
1)
SYSCON b FF12h
BUSCON1b FF14h
BUSCON2b FF16h
BUSCON3b FF18h
BUSCON4b FF1Ah
CPU System Configuration Register
Bus Configuration Register 1
0xx0h
0000h
0000h
0000h
0000h
0000h
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
Bus Configuration Register 2
Bus Configuration Register 3
Bus Configuran Register 4
ZEROS
ONES
b
b
FF1Ch
FF1Eh
ConstaValue 0’s Register (read only)
Coant Value 1’s Register (read only)
CAPCOM Timer 7 and 8 Control Register
CAPCOM Mode Control Register 4
CAPCOM Mode Control Register 5
CAPCOM Mode Control Register 6
CAPCOM Mode Control Register 7
PWM Module Control Register 0
PWM Module Control Register 1
GPT1 Timer 2 Control Register
T78CON b FF20h
CCM4
CCM5
CCM6
CCM7
b
b
b
b
FF22h
FF24h
FFh
FF28h
PWMCON0b FF30h
PWMCON1b FF32h
T2CON
T3CON
T4CON
T5CON
T6CON
b
b
b
b
b
FF40h
FF42h
FF44h
FF46h
FF48h
GPT1 Timer 3 Control Register
GPT1 Timer 4 Control Register
GPT2 Timer 5 Control Register
GPT2 Timer 6 Control Register
T01CON b FF50h
CAPCOM Timer 0 and Timer 1 Control Register
CAPCOM Mode Control Register 0
CAPCOM Mode Control Register 1
CAPCOM Mode Control Register 2
CAPCOM Mode Control Register 3
GPT1 Timer 2 Interrupt Control Register
CCM0
CCM1
CCM2
CCM3
T2IC
b
b
b
b
b
FF52h
FF54h
FF56h
FF58h
FF60h
267/328
Register set
ST10F252M
Table 137. Special function registers listed by address (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
T3IC
b
b
b
b
b
b
FF62h
FF64h
FF66h
FF68h
FF6Ah
FF6Ch
B1h
B2h
B3h
B4h
B5h
GPT1 Timer 3 Interrupt Control Register
GPT1 Timer 4 Interrupt Control Register
GPT2 Timer 5 Interrupt Control Register
GPT2 Timer 6 Interrupt Control Register
GPT2 CAPREL Interrupt Control Register
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
T4IC
T5IC
T6IC
CRIC
S0TIC
Serial Channel 0 Transmit Interrupt Control
Register
B6h
B7h
- - 00h
- - 00h
S0RIC
b
FF6Eh
Serial Channel 0 Receive Interrupt Control
Register
S0EIC
SSCTIC
SSCRIC
SSCEIC
CC0IC
CC1IC
CC2IC
CC3IC
CC4IC
CC5IC
CC6IC
CC7IC
CC8IC
C9IC
CC10IC
CC11IC
CC12IC
CC13IC
CC14IC
CC15IC
ADCIC
ADEIC
T0IC
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
FF70h
FF72h
FF74h
FF76h
FF78h
FF7Ah
FF7Ch
FF7Eh
FF80h
FF82h
FF84h
F86h
FF88h
FF8Ah
FF8Ch
FF8Eh
FF90h
FF92h
FF94h
FF96h
FF98h
FF9Ah
FF9Ch
FF9Eh
FFA0h
FFA2h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
Serial Channel 0 Error Interrupt Control Register
SSC Transmit Interrupt Control Register
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
XXXXh
SSC Receive Interrupt ContrRegister
SSC Error Interrupt Conol Register
CAPCOM Register 0 Interrupt Control Register
CAPCOM Reger 1 Interrupt Control Register
CACORegister 2 Interrupt Control Register
CAPCOM Register 3 Interrupt Control Register
CAPCOM Register 4 Interrupt Control Register
CAPCOM Register 5 Interrupt Control Register
CAPCOM Register 6 Interrupt Control Register
CAPCOM Register 7 Interrupt Control Register
CAPCOM Register 8 Interrupt Control Register
CAPCOM Register 9 Interrupt Control Register
CAPCOM Register 10 Interrupt Control Register
CAPCOM Register 11 Interrupt Control Register
CAPCOM Register 12 Interrupt Control Register
CAPCOM Register 13 Interrupt Control Register
CAPCOM Register 14 Interrupt Control Register
CAPCOM Register 15 Interrupt Control Register
ADC end of Conversion Interrupt Control Reg.
ADC Overrun Error Interrupt Control Register
CAPCOM Timer 0 Interrupt Control Register
CAPCOM Timer 1 Interrupt Control Register
ADC Control Register
T1IC
ADCON
P5
Port 5 Register (read only)
268/328
ST10F252M
Register set
Table 137. Special function registers listed by address (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
P5DIDIS
TFR
b
b
FFA4h
FFACh
D2h
D6h
D7h
D8h
D9h
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
EDh
EEh
EFh
Port 5 Digital Disable Register
Trap Flag Register
0000h
0000h
00xxh 2)
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
0200h
WDTCON b FFAEh
S0CON FFB0h
SSCCON b FFB2h
Watchdog Timer Control Register
Serial Channel 0 Control Register
SSC Control Register
b
P2
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
FFC0h
FFC2h
FFC4h
FFC6h
FFC8h
FFCAh
FFCCh
FFCEh
FFD0h
FFD2h
FFD4h
FFD6h
FFDAh
FFDCh
FFEh
Port 2 Register
DP2
P3
Port 2 Direction Control Register
Port 3 Register
DP3
P4
Port 3 Direction Control Register
Port 4 Register (8-bit)
DP4
P6
Port 4 Direction Control Regiser
Port 6 Register (8-bit)
DP6
P7
Port 6 Direction Control Register
Port 7 Registe8-bit)
DP7
P8
Port 7 Dection Control Register
PoRegister (8-bit)
DP8
MRW
MCW
MSW
Port 8 Direction Control Register
MAC Unit Repeat Word
MAC Unit Control Word
MAC Unit Status Word
26.3
X-registers overview
26.3.1
X-registers ordered by name
Table 138 lists all X-Bus registers which are implemented in the ST10F252M ordered by
their name. Not all X-registers are bit-addressable.
Table 138. Registers listed by name
Reset
value
Name
Physical address
Description
CAN1BRPER
CAN1BTR
CAN1CR
EF0Ch
EF06h
EF00h
EF04h
EF18h
CAN1: BRP Extension Register
CAN1: Bit Timing Register
CAN1: CAN Control Register
CAN1: Error Counter
0000h
2301h
0001h
0000h
0000h
CAN1EC
CAN1IF1A1
CAN1: IF1 Arbitration 1
269/328
Register set
ST10F252M
Table 138. Registers listed by name (continued)
Reset
value
Name
Physical address
Description
CAN1IF1A2
EF1Ah
EF12h
EF10h
EF1Eh
EF20h
EF22h
EF24h
EF14h
EF16h
EF1Ch
EF48h
EF4Ah
EF42h
EF40h
EF4Eh
EF50h
EF52h
EF54h
EF44h
EF46h
EF4Ch
EFA0h
EFA2h
EF08h
EFB0h
EFB2h
EF90h
EF92h
EF02h
EF0Ah
EF80h
EF82h
EE0Ch
EE06h
CAN1: IF1 Arbitration 2
0000h
0000h
0001h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00x0h
0000h
0000h
0000h
2301h
CAN1IF1CM
CAN1IF1CR
CAN1IF1DA1
CAN1IF1DA2
CAN1IF1DB1
CAN1IF1DB2
CAN1IF1M1
CAN1IF1M2
CAN1IF1MC
CAN1IF2A1
CAN1IF2A2
CAN1IF2CM
CAN1IF2CR
CAN1IF2DA1
CAN1IF2DA2
CAN1IF2DB1
CAN1IF2DB2
CAN1IF2M1
CAN1IF2M2
CAN1IMC
CAN1IP1
CAN1: IF1 Command Mask
CAN1: IF1 Command Request
CAN1: IF1 Data A 1
CAN1: IF1 Data A 2
CAN1: IF1 Data B 1
CAN1: IF1 Data B 2
CAN1: IF1 Mask 1
CAN1: IF1 Mask 2
CAN1: IF1 Message Control
CAN1: IF2 Arbitration 1
CAN1: IF2 Arbitration 2
CAN1: IF2 Comand Mask
CAN1: IFCommand Request
CA1: IF2 Data A 1
CAN1: IF2 Data A 2
CAN1: IF2 Data B 1
CAN1: IF2 Data B 2
CAN1: IF2 Mask 1
CAN1: IF2 Mask 2
CAN1: IF2 Message Control
CAN1: Interrupt Pending 1
CAN1: Interrupt Pending 2
CAN1: Interrupt Register
CAN1: Message Valid 1
CAN1: Message Valid 2
CAN1: New Data 1
CAN1IP2
CAN1IR
CAN1MV1
CAN1MV2
CAN1ND1
CAN1ND2
CAN1: New Data 2
CAN1SR
CAN1: Status Register
CAN1: Test Register
CAN1TR
CAN1TR1
CAN1: Transmission Request 1
CAN1: Transmission Request 2
CAN2: BRP Extension Register
CAN2: Bit Timing Register
CAN1TR2
CAN2BRPER
CAN2BTR
270/328
ST10F252M
Register set
Table 138. Registers listed by name (continued)
Reset
value
Name
Physical address
Description
CAN2CR
EE00h
EE04h
EE18h
EE1Ah
EE12h
EE10h
EE1Eh
EE20h
EE22h
EE24h
EE14h
EE16h
EE1Ch
EE48h
EE4Ah
EE42h
EE40h
EE4Eh
EE50h
EE52h
EE54h
EE44h
EE46h
EE4Ch
EEA0h
EEA2h
EE08h
EEB0h
EEB2h
EE90h
EE92h
EE02h
EE0Ah
EE80h
CAN2: CAN Control Register
CAN2: Error Counter
0001h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00x0h
0000h
CAN2EC
CAN2IF1A1
CAN2IF1A2
CAN2IF1CM
CAN2IF1CR
CAN2IF1DA1
CAN2IF1DA2
CAN2IF1DB1
CAN2IF1DB2
CAN2IF1M1
CAN2IF1M2
CAN2IF1MC
CAN2IF2A1
CAN2IF2A2
CAN2IF2CM
CAN2IF2CR
CAN2IF2DA1
CAN2IF2DA2
CAN2IF2DB1
CAN2IDB2
CAN2IF2M1
CAN2IF2M2
CAN2IF2MC
CAN2IP1
CAN2: IF1 Arbitration 1
CAN2: IF1 Arbitration 2
CAN2: IF1 Command Mask
CAN2: IF1 Command Request
CAN2: IF1 Data A 1
CAN2: IF1 Data A 2
CAN2: IF1 Data B 1
CAN2: IF1 Data B 2
CAN2: IF1 Mask 1
CAN2: IF1 Mask 2
CAN2: IF1 Mesage Control
CAN2: IFArbitration 1
CA2: IF2 Arbitration 2
CAN2: IF2 Command Mask
CAN2: IF2 Command Request
CAN2: IF2 Data A 1
CAN2: IF2 Data A 2
CAN2: IF2 Data B 1
CAN2: IF2 Data B 2
CAN2: IF2 Mask 1
CAN2: IF2 Mask 2
CAN2: IF2 Message Control
CAN2: Interrupt Pending 1
CAN2: Interrupt Pending 2
CAN2: Interrupt Register
CAN2: Message Valid 1
CAN2: Message Valid 2
CAN2: New Data 1
CAN2IP2
CAN2IR
CAN2MV1
CAN2MV2
CAN2ND1
CAN2ND2
CAN2: New Data 2
CAN2SR
CAN2: Status Register
CAN2: Test Register
CAN2TR
CAN2TR1
CAN2: Transmission Request 1
271/328
Register set
ST10F252M
Table 138. Registers listed by name (continued)
Reset
value
Name
Physical address
Description
CAN2TR2
EE82h
EA06h
EA0Eh
EA00h
EA0Ch
EA08h
EA0Ah
ED14h
ED12h
ED00H
ED0Ch
ED0Ah
ED10h
ED0Eh
ED08h
ED06h
EA02h
EA04h
EB02h
EB76h
EB78h
EB7Ah
EB7Ch
EB14h
EB10h
EB12h
EB24h
EB20h
EB22h
EB34h
EB30h
EB32h
CAN2: Transmission Request 2
I2C Clock Control Register 1
0000h
0000h
0000h
0000h
0000h
0000h
0000h
XXXXh
XXXXh
000Xh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
0000h
0000h
- - 00h
XXXXh
XXXXh
XXXXh
XXXXh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
CCR1
CCR2
I2C Clock Control Register 2
CR
I2C Control Register
DR
I2C Data Register
OAR1
I2C Own Address Register 1
OAR2
I2C Own Address Register 1
RTCAH
RTCAL
RTCCON
RTCDH
RTCDL
RTCH
RTC Alarm Register High Byte
RTC Alarm Register Low Byte
RTC Control Register
RTC Divider Counter HiByte
RTC Divider Counter Low Byte
RTC Programable Counter High Byte
RTC Prommable Counter Low Byte
RTPrescaler Register High Byte
RTC Prescaler Register Low Byte
I2C Status Register 1
RTCL
RTCPH
RTCPL
SR1
SR2
I2C Status Register 2
XCLKOUTDIV
XEMU0
XEMU
XEMU2
XEMU3
XIR0CLR
XIR0SEL
XIR0SET
XIR1CLR
XIR1SEL
XIR1SET
XIR2CLR
XIR2SEL
XIR2SET
CLKOUT Divider Control Register
XBUS Emulation Register 0 (write only)
XBUS Emulation Register 1 (write only)
XBUS Emulation Register 2 (write only)
XBUS Emulation Register 3 (write only)
X-Interrupt 0 Clear Register (write only)
X-Interrupt 0 Selection Register
X-Interrupt 0 Set Register (write only)
X-Interrupt 1 Clear Register (write only)
X-Interrupt 1 Selection Register
X-Interrupt 1 Set Register (write only)
X-Interrupt 2 Clear Register (write only)
X-Interrupt 2 Selection Register
X-Interrupt 2 Set Register (write only)
X-Interrupt 3 Clear Selection Register
(write only)
XIR3CLR
EB44h
0000h
272/328
ST10F252M
Register set
Table 138. Registers listed by name (continued)
Reset
value
Name
XIR3SEL
Physical address
Description
EB40h
EB42h
X-Interrupt 3 Selection Register
0000h
0000h
X-Interrupt 3 Set Selection Register (write
only)
XIR3SET
XMISC
EB46h
EB36h
EB7Eh
EB26h
XBUS Miscellaneous Features Register
Port 1 Digital Disable Register
0000h
0000h
XXXXh
- - 00h
XP0DIDIS
XPEREMU
XPICON
XPERCON copy for Emulation (write only)
Port Input Threshold Control Register
XPWM Module Clear Control Reg. 0 (write
only)
XPMWCON0CLR
XPMWCON0SET
XPMWCON1CLR
XPMWCON1SET
EC08h
EC06h
EC0Ch
EC0Ah
0000h
0000h
0000h
0000h
XPWM Module Set Control Register 0
(write only)
XPWM Module Clear Corol Reg. 0 (write
only)
XPWM Module Set Control Register 0
(write only)
XPOLAR
XPP0
EC04h
EC20h
EC22h
EC24h
EC26h
EC10h
EC12h
EC14h
EC16h
EC30h
EC32h
EC34h
EC36h
EC00h
EC02h
EC80h
XPWM Mdule Channel Polarity Register
PM Module Period Register 0
XPWM Module Period Register 1
XPWM Module Period Register 2
XPWM Module Period Register 3
XPWM Module Up/Down Counter 0
XPWM Module Up/Down Counter 1
XPWM Module Up/Down Counter 2
XPWM Module Up/Down Counter 3
XPWM Module Pulse Width Register 0
XPWM Module Pulse Width Register 1
XPWM Module Pulse Width Register 2
XPWM Module Pulse Width Register 3
XPWM Module Control Register 0
XPWM Module Control Register 1
XPWM Module Port Control Register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
XPP1
XPP2
XPP3
XPT0
XPT1
XPT2
XPT3
XPW0
XPW1
XPW2
XPW3
XPWMCON0
XPWMCON1
XPWMPORT
XASC Baud Rate Generator Reload
Register
XS1BG
E906h
0000h
XS1CON
E900h
E904h
E902h
XASC Control Register
0000h
0000h
0000h
XS1CONCLR
XS1CONSET
XASC Clear Control Register (write only)
XASC Set Control Register (write only)
273/328
Register set
ST10F252M
Table 138. Registers listed by name (continued)
Reset
value
Name
Physical address
Description
XS1PORT
E980h
E90Ah
E908h
E80Ah
E800h
E804h
E802h
E880h
E808h
E806h
XASC Port Control Register
XASC Receive Buffer Register
XASC Transmit Buffer Register
XSSC Baud Rate Register
XSSC Control Register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
XXXXh
0000h
XS1RBUF
XS1TBUF
XSSCBR
XSSCCON
XSSCCONCLR
XSSCCONSET
XSSCPORT
XSSCRB
XSSC Clear Control Register (write only)
XSSC Set Control Register (write only)
XSSC Port Control Register
XSSC Receive Buffer
XSSCTB
XSSC Transmit Buffer
26.3.2
X-registers ordered by address
Table 139 lists all X-Bus registers which are implemented in the ST10F252M ordered by
their physical address. Not all X-registers are bit-addressable.
Table 139. Registers listed by address
Reset
Name
Physical address
Description
value
XSSCCON
E800h
E802h
E804h
E806h
E808h
E80Ah
E880h
E900h
E902h
E904h
XSSC Control Register
0000h
XSSCCONSET
XSSCCONCLR
XSSCT
XSSC Set Control Register (write only)
XSSC Clear Control Register (write only)
XSSC Transmit Buffer
0000h
0000h
0000h
XXXXh
0000h
0000h
0000h
0000h
0000h
XSSCRB
XSSC Receive Buffer
XSSCBR
XSSC Baud Rate Register
XSSCPORT
XS1CON
XSSC Port Control Register
XASC Control Register
XS1CONSET
XS1CONCLR
XASC Set Control Register (write only)
XASC Clear Control Register (write only)
XASC Baud Rate Generator Reload
Register
XS1BG
E906h
0000h
XS1TBUF
XS1RBUF
XS1PORT
CR
E908h
E90Ah
E980h
EA00h
EA02h
XASC Transmit Buffer Register
XASC Receive Buffer Register
XASC Port Control Register
I2C Control Register
0000h
0000h
0000h
0000h
0000h
SR1
I2C Status Register 1
274/328
ST10F252M
Register set
Table 139. Registers listed by address (continued)
Reset
value
Name
Physical address
Description
SR2
EA04h
EA06h
EA08h
EA0Ah
EA0Ch
EA0Eh
EB02h
EB10h
EB12h
EB14h
EB20h
EB22h
EB24h
EB26h
EB30h
EB32h
EB34h
EB36h
EB40h
I2C Status Register 2
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
0000h
CCR1
OAR1
OAR2
DR
I2C Clock Control Register 1
I2C Own Address Register 1
I2C Own Address Register 1
I2C Data Register
CCR2
I2C Clock Control Register 2
XCLKOUTDIV
XIR0SEL
XIR0SET
XIR0CLR
XIR1SEL
XIR1SET
XIR1CLR
XPICON
CLKOUT Divider Control Register
X-Interrupt 0 Selection Register
X-Interrupt 0 Set Register (write only)
X-Interrupt 0 Clear Register (write ly)
X-Interrupt 1 Selection Rgister
X-Interrupt 1 Set Register (write only)
X-Interrupt 1 Clear Register (write only)
Port Inpuhreshold Control Register
X-Ierrupt 2 Selection Register
-Interrupt 2 Set Register (write only)
X-Interrupt 2 Clear Register (write only)
Port 1 Digital Disable Register
X-Interrupt 3 Selection Register
XIR2SEL
XIR2SET
XIR2CLR
XP0DIDIS
XIR3SEL
X-Interrupt 3 Set Selection Register (write
only)
XIR3SET
XIR3CLR
EB42h
EB44h
0000h
0000h
X-Interrupt 3 Clear Selection Register
(write only)
XMISC
EB46h
EB76h
EB78h
EB7Ah
EB7Ch
EB7Eh
EC00h
EC02h
EC04h
XBUS Miscellaneous Features Register
XBUS Emulation Register 0 (write only)
XBUS Emulation Register 1 (write only)
XBUS Emulation Register 2 (write only)
XBUS Emulation Register 3 (write only)
XPERCON copy for Emulation (write only)
XPWM Module Control Register 0
0000h
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
0000h
XEMU0
XEMU1
XEMU2
XEMU3
XPEREMU
XPWMCON0
XPWMCON1
XPOLAR
XPWM Module Control Register 1
0000h
XPWM Module Channel Polarity Register
0000h
XPWM Module Set Control Register 0
(write only)
XPMWCON0SET
EC06h
0000h
275/328
Register set
ST10F252M
Table 139. Registers listed by address (continued)
Reset
value
Name
Physical address
Description
XPWM Module Clear Control Reg. 0 (write
only)
XPMWCON0CLR
XPMWCON1SET
XPMWCON1CLR
EC08h
EC0Ah
EC0Ch
0000h
0000h
0000h
XPWM Module Set Control Register 0
(write only)
XPWM Module Clear Control Reg. 0 (write
only)
XPT0
EC10h
EC12h
EC14h
EC16h
EC20h
EC22h
EC24h
EC26h
EC30h
EC32h
EC34h
EC36h
EC80h
ED00H
ED06h
ED08h
ED0Ah
ED0Ch
ED0Eh
ED10h
ED12h
ED14h
EE00h
EE02h
EE04h
EE06h
EE08h
EE0Ah
EE0Ch
XPWM Module Up/Down Counter 0
XPWM Module Up/Down Counter 1
XPWM Module Up/Down Counter 2
XPWM Module Up/Down Counter 3
XPWM Module Period Register 0
XPWM Module Period Register 1
XPWM Module Period Register 2
XPWM Module Period Register 3
XPWM Mule Pulse Width Register 0
XPM Module Pulse Width Register 1
PWM Module Pulse Width Register 2
XPWM Module Pulse Width Register 3
XPWM Module Port Control Register
RTC Control Register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
000Xh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
0001h
0000h
0000h
2301h
0000h
00x0h
0000h
XPT1
XPT2
XPT3
XPP0
XPP1
XPP2
XPP3
XPW0
XPW1
XPW2
XPW3
XPWMPORT
RTCCON
RTCPL
RTCPH
RTCDL
RTCDH
RTCL
RTC Prescaler Register Low Byte
RTC Prescaler Register High Byte
RTC Divider Counter Low Byte
RTC Divider Counter High Byte
RTC Programmable Counter Low Byte
RTC Programmable Counter High Byte
RTC Alarm Register Low Byte
RTC Alarm Register High Byte
CAN2: CAN Control Register
RTCH
RTCAL
RTCAH
CAN2CR
CAN2SR
CAN2EC
CAN2BTR
CAN2IR
CAN2TR
CAN2BRPER
CAN2: Status Register
CAN2: Error Counter
CAN2: Bit Timing Register
CAN2: Interrupt Register
CAN2: Test Register
CAN2: BRP Extension Register
276/328
ST10F252M
Register set
Table 139. Registers listed by address (continued)
Reset
value
Name
Physical address
Description
CAN2IF1CR
CAN2IF1CM
CAN2IF1M1
CAN2IF1M2
CAN2IF1A1
CAN2IF1A2
CAN2IF1MC
CAN2IF1DA1
CAN2IF1DA2
CAN2IF1DB1
CAN2IF1DB2
CAN2IF2CR
CAN2IF2CM
CAN2IF2M1
CAN2IF2M2
CAN2IF2A1
CAN2IF2A2
CAN2IF2MC
CAN2IF2DA1
CAN2IF2DA2
CAN2IDB1
CAN2IF2DB2
CAN2TR1
EE10h
EE12h
EE14h
EE16h
EE18h
EE1Ah
EE1Ch
EE1Eh
EE20h
EE22h
EE24h
EE40h
EE42h
EE44h
EE46h
EE48h
EE4Ah
EE4Ch
EE4Eh
EE50h
EE52h
EE54h
EE80h
EE82h
EE90h
EE92h
EEA0h
EEA2h
EEB0h
EEB2h
EF00h
EF02h
EF04h
EF06h
CAN2: IF1 Command Request
CAN2: IF1 Command Mask
CAN2: IF1 Mask 1
0001h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0001h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
2301h
CAN2: IF1 Mask 2
CAN2: IF1 Arbitration 1
CAN2: IF1 Arbitration 2
CAN2: IF1 Message Control
CAN2: IF1 Data A 1
CAN2: IF1 Data A 2
CAN2: IF1 Data B 1
CAN2: IF1 Data B 2
CAN2: IF2 Command Request
CAN2: IF2 Command Mask
CAN2: IFMask 1
CA2: IF2 Mask 2
AN2: IF2 Arbitration 1
CAN2: IF2 Arbitration 2
CAN2: IF2 Message Control
CAN2: IF2 Data A 1
CAN2: IF2 Data A 2
CAN2: IF2 Data B 1
CAN2: IF2 Data B 2
CAN2: Transmission Request 1
CAN2: Transmission Request 2
CAN2: New Data 1
CAN2TR2
CAN2ND1
CAN2ND2
CAN2: New Data 2
CAN2IP1
CAN2: Interrupt Pending 1
CAN2: Interrupt Pending 2
CAN2: Message Valid 1
CAN2: Message Valid 2
CAN1: CAN Control Register
CAN1: Status Register
CAN1: Error Counter
CAN2IP2
CAN2MV1
CAN2MV2
CAN1CR
CAN1SR
CAN1EC
CAN1BTR
CAN1: Bit Timing Register
277/328
Register set
ST10F252M
Table 139. Registers listed by address (continued)
Reset
value
Name
Physical address
Description
CAN1IR
EF08h
EF0Ah
EF0Ch
EF10h
EF12h
EF14h
EF16h
EF18h
EF1Ah
EF1Ch
EF1Eh
EF20h
EF22h
EF24h
EF40h
EF42h
EF44h
EF46h
EF48h
EF4Ah
EF4Ch
EF4Eh
EF50h
EF52h
EF54h
EF80h
EF82h
EF90h
EF92h
EFA0h
EFA2h
EFB0h
EFB2h
CAN1: Interrupt Register
CAN1: Test Register
0000h
00x0h
0000h
0001h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0001h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
CAN1TR
CAN1BRPER
CAN1IF1CR
CAN1IF1CM
CAN1IF1M1
CAN1IF1M2
CAN1IF1A1
CAN1IF1A2
CAN1IF1MC
CAN1IF1DA1
CAN1IF1DA2
CAN1IF1DB1
CAN1IF1DB2
CAN1IF2CR
CAN1IF2CM
CAN1IF2M1
CAN1IF2M2
CAN1IF2A1
CAN1IF2A2
CAN1IMC
CAN1IF2DA1
CAN1IF2DA2
CAN1IF2DB1
CAN1IF2DB2
CAN1TR1
CAN1: BRP Extension Register
CAN1: IF1 Command Request
CAN1: IF1 Command Mask
CAN1: IF1 Mask 1
CAN1: IF1 Mask 2
CAN1: IF1 Arbitration 1
CAN1: IF1 Arbitration 2
CAN1: IF1 Message Control
CAN1: IF1 Data A 1
CAN1: IF1 Data A 2
CAN1: IF1 Data B 1
CAN1: IFData B 2
CA1: IF2 Command Request
AN1: IF2 Command Mask
CAN1: IF2 Mask 1
CAN1: IF2 Mask 2
CAN1: IF2 Arbitration 1
CAN1: IF2 Arbitration 2
CAN1: IF2 Message Control
CAN1: IF2 Data A 1
CAN1: IF2 Data A 2
CAN1: IF2 Data B 1
CAN1: IF2 Data B 2
CAN1: Transmission Request 1
CAN1: Transmission Request 2
CAN1: New Data 1
CAN1TR2
CAN1ND1
CAN1ND2
CAN1: New Data 2
CAN1IP1
CAN1: Interrupt Pending 1
CAN1: Interrupt Pending 2
CAN1: Message Valid 1
CAN1: Message Valid 2
CAN1IP2
CAN1MV1
CAN1MV2
278/328
ST10F252M
Register set
26.4
Flash control registers overview
26.4.1
Registers ordered by name
Table 140 lists all Flash control registers which are implemented in the ST10F252M ordered
by their name. As these registers are physically mapped on the I-Bus, they are not bit-
addressable.
Table 140. Flash registers listed by name
Reset
Name
Physical address
Description
value
FARH
0x0008 0012
0x0008 0010
0x0008 0002
0x0008 0000
0x0008 0006
0x0008 0004
0x0008 000A
0x0008 0008
0x0008 000E
0x0008 000C
0x0008 0014
0x0008 DFB8
0x0008 DFB4
Flash Address Register High
Flash Address Register Low
Flash Control Register 0 - High
Flash Control Register 0 - Low
Flash Control Register 1 - High
Flash Control Register 1 - Low
Flash Data Register 0 - High
Flash DatRegister 0 - Low
Flash Data Register 1 - High
ash Data Register 1 - Low
Flash Error Register
0000h
0000h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
FFFFh
FFFFh
0000h
ACFFh
FFFFh
FARL
FCR0H
FCR0L
FCR1H
FCR1L
FDR0H
FDR0L
FDR1H
FDR1L
FER
FNVAPR
Flash Non Volatile Access Protection Reg. 0
Flash Non Volatile Protection I Reg.
FNVWPIR-Mirror
Flash Non Volatile Access Protection Reg. 1 -
High
FNVAPR1H
FNVAPR1L
0x0008 DFBE
0x0008 DFBC
FFFFh
FFFFh
Flash Non Volatile Access Protection Reg. 1 -
Low
FNVWPIR
XFVTAU0
0x0008 DFB0
0x0000 EB50
Flash Non Volatile Protection I Reg.
FFFFh
0000h
Xbus Flash Temporary Unprotection Register
26.4.2
Registers ordered by address
Table 141 lists all Flash control registers which are implemented in the ST10F252M ordered
by their physical address. As these registers are physically mapped on the I-Bus, they are
not bit-addressable.
Table 141. Flash registers listed by address
Reset
Name
Physical address
Description
value
FCR0L
FCR0H
0x000B 0000
0x000B 0002
Flash Control Register 0 - Low
Flash Control Register 0 - High
0000h
0000h
279/328
Register set
ST10F252M
Table 141. Flash registers listed by address (continued)
Reset
value
Name
Physical address
Description
FCR1L
FCR1H
FDR0L
FDR0H
FDR1L
FDR1H
FARL
0x000B 0004
0x000B 0006
0x000B 0008
0x000B 000A
0x000B 000C
0x000B 000E
0x000B 0010
0x000B 0012
0x000B 0014
0x000B DFB0
0x000B DFB8
Flash Control Register 1 - Low
Flash Control Register 1 - High
Flash Data Register 0 - Low
Flash Data Register 0 - High
Flash Data Register 1 - Low
Flash Data Register 1 - High
Flash Address Register Low
Flash Address Register High
Flash Error Register
0000h
0000h
FFFFh
FFFFh
FFFFh
FFFFh
0000h
0000h
0000h
FFFFh
FARH
FER
FNVWPIRL
FNVAPR0
Flash Non Volatile Protection I ReLow
Flash Non Volatile AccesProtection Reg. 0
ACFFh
FFFFh
Flash Non Volatile Access Protection Reg. 1 -
Low
FNVAPR1L
0x000B DFBC
Flash Non Volatile Access Protection Reg. 1 -
High
FNVAPR1H
XTAUR0
0x000B DFBE
0x0000 EB50
FFFFh
0000h
XbFlash Temporary Unprotection Register
280/328
ST10F252M
Electrical Characteristics
27
Electrical Characteristics
27.1
Absolute maximum ratings
Table 142. Absolute maximum ratings
Symbol
Parameter
Voltage on VDD pins with respect to ground (VSS
Voltage on VSTBY pin with respect to ground (VSS
Voltage on VAREF pins with respect to ground (VSS
Voltage on VAGND pins with respect to ground (VSS
Voltage on any pin with respect to ground (VSS
Input current on any pin during overload condition
Values
Unit
VDD
VSTBY
VAREF
VAGND
VIO
)
-0.5 to +6.5
-0.5 to +6.5
-0.5 to VDD + 0.5
VSS
V
V
)
)
V
)
V
)
-0.5 to VDD + 0.5
10
V
IOV
mA
mA
°C
V
ITOV
Absolute sum of all input currents during overload condition
Storage temperature
75 |
TST
-65 to +150
2000
ESD
ESD Susceptibility (Human Body Model)
Note:
Stresses above those listed under “Absolute maximum ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those dicated in the operational sections of this
specification is not implied. Exposure bsolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (V > V or V < V ) the
IN
DD
IN
SS
voltage on pins with respect to ground (V ) must not exceed the values defined by the
SS
Absolute Maximum Ratings.
During power-on and power-off transients (including Standby entering/exiting phases), the
relationships between voltages applied to the device and the main V must always be
DD
respected. In particular, power-on and power-off of V
must be coherent with V
AREF
DD
transiein order to avoid undesired current injection through the on-chip protection diodes.
281/328
Electrical Characteristics
ST10F252M
27.2
Recommended operating conditions
Table 143. Recommended operating conditions
Value
Symbol
Parameter
Unit
Min
Max
VDD
VSTBY
VAREF
TA
Operating supply voltage
4.5
0
5.5
V
Operation stand-by supply voltage(1)
Operating analog reference voltage(2)
Ambient temperature under bias
Junction temperature under bias
VDD + 0.1
+125
V
-40
°C
TJ
+150
1. The value of the VSTBY voltage is specified in the range of 4.5 to 5.5 volts. When VSTBY voltage is lower
than main VDD, the input section of VSTBY/EA pin can generate a spurious static consumption on VDD
power supply (in the range of tenth of µA).
2. For details on operating conditions concerning the usage of A/D Converter refer to Stion 27.7.
27.3
Power considerations
The average chip-junction temperature, T , in degrees Celsius, may be calculated using the
J
following equation:
T = T + (P x Θ ) (1)
J
A
D
JA
Where:
–
–
–
–
T is the Ambient Temperature in °C,
A
Θ
is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
JA
P is the sum of P
and P (P = P
+ P ),
INT I/O
D
INT
I/O
D
P
is he product of I and V , expressed in Watt. This is the Chip Internal
DD 18
INT
Por,
P represents the Power Dissipation on Input and Output Pins; User Determined.
I/O
–
Most of the time for the applications P < P
and may be neglected. On the other hand,
INT
I/O
P
may be significant if the device is configured to drive continuously external modules
I/O
and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
P = K / (T + 273°C) (2)
D
J
Therefore (solving equations 1 and 2):
2
K = P x (T + 273°C) + Θ x P
(3)
D
A
JA
D
Where:
K is a constant for the particular part, which may be determined from equation (3) by
measuring P (at equilibrium) for a known T Using this value of K, the values of P and T
J
D
A.
D
may be obtained by solving equations (1) and (2) iteratively for any value of T .
A
282/328
ST10F252M
Electrical Characteristics
Table 144. Thermal characteristics
Symbol
Description
Value (typical)
Unit
Thermal Resistance Junction-Ambient
LQFP 100 - 14 x 14 mm / 0.5 mm pitch
Θ
JA
55
°C/W
27.4
Parameter interpretation
The parameters listed in the following tables represent the characteristics of the
ST10F252M and its demands on the system.
Where the ST10F252M logic provides signals with their respective timing characteristics,
the symbol “CC” for Controller Characteristics, is included in the “Symbol” column.
Where the external system must provide signals with their respective timing characteristics
to the ST10F252M, the symbol “SR” for System Requirement, is included in the “Symbol”
column.
27.5
DC characteristics
V
= 5 V 10%, V = 0 V, T = -40 to +125°C
DD
SS
A
Table 145. DC characteristics
Parameter
imit values
Symbol
Unit
Test condition
Min
Max
Input low voltage (TTL mode)
(except RSTIN, EA, NMI, RPD, XTAL1,
READY)
VIL
SR
SR
-0.3
-0.3
0.8
V
V
–
–
Input low voltage (CMOS mode
(except RSTIN, EA, NMI, RXTAL1,
READY)
VILS
0.3 VDD
Input low voltage RSTIN, EA, NMI, RPD VIL1
SR
SR
SR
-0.3
-0.3
-0.3
0.3 VDD
0.3 VDD
0.8
V
V
V
–
Input low voltage XTAL1 (CMOS only)
Input lovoltage READY (TTL only)
VIL2
VIL3
Direct Drive mode
–
Iut high voltage (TTL mode)
(except RSTIN, EA, NMI, RPD, XTAL1)
VIH
SR
SR
2.0
VDD + 0.3
VDD + 0.3
V
V
–
–
Input high voltage (CMOS mode)
(except RSTIN, EA, NMI, RPD, XTAL1)
VIHS
0.7 VDD
Input high voltage RSTIN, EA, NMI, RPD VIH1
SR
SR
SR
0.7 VDD
0.7 VDD
2.0
VDD + 0.3
VDD + 0.3
VDD + 0.3
V
V
V
–
Input high voltage XTAL1 (CMOS only)
Input high voltage READY (TTL only)
VIH2
VIH3
Direct Drive mode
–
Input Hysteresis (TTL mode)
(except RSTIN, EA, NMI, XTAL1, RPD)
(1)
VHYS CC
VHYSS CC
400
750
700
mV
mV
Input Hysteresis (CMOS mode)
(except RSTIN, EA, NMI, XTAL1, RPD)
(1)
1400
283/328
Electrical Characteristics
ST10F252M
Table 145. DC characteristics (continued)
Limit values
Parameter
Symbol
Unit
Test condition
Min
Max
(1)
(1)
(1)
(1)
Input Hysteresis RSTIN, EA, NMI
Input Hysteresis XTAL1
VHYS1 CC
VHYS2 CC
VHYS3 CC
VHYS4 CC
750
0
1400
50
mV
mV
mV
mV
Input Hysteresis READY (TTL only)
Input Hysteresis RPD
400
500
700
1500
Output low voltage
(P6[7:0], ALE, RD, WR/WRL,
BHE/WRH, CLKOUT, RSTIN,
RSTOUT)
0.4
0.05
IOL = 8mA
IOL = 1mA
VOL
CC
–
V
V
Output low voltage
(P0[15:0], P1[15:0], P2[15:0],
P3[15,13:0], P4[7:0], P7[7:0],
P8[7:0])
0.4
0.05
IOL1 = 4mA
IOL1 = 0.5mA
VOL1 CC
–
–
VDD
0.5 VD
0.3 VDD
IOL2 = 85µA
IOL2 = 80µA
IOL2 = 60µA
Output low voltage RPD
VOL2 CC
V
V
Output high voltage
(P6[7:0], ALE, RD, WR/WRL,
BHE/WRH, CLKOUT, RSTOUT)
VDD - 0.8
VDD - 0.08
IOH = – 8mA
IOH = – 1mA
VOH
CC
–
–
Output high voltage(2)
(P0[15:0], P1[15:0], P2[15:0],
P3[15,13:0], P4[7:0], P7[7:0],
P8[7:0])
VDD - 0.8
VDD - 0.08
IOH1 = – 4mA
IOH1 = – 0.5mA
VOH1 CC
V
0
IOH2 = – 2mA
IOH2 = – 750µA
IOH2 = – 150µA
Output high voltage RPD
VOH2 CC
0.3 VDD
0.5 VDD
–
V
| IOZ1
Input leakage current P5[15:0])(3)
CC
–
–
0.2
0.5
µA
µA
–
–
|
Input leakage current
(all except P5[15:0], P2[0], RPD, P3[12],
P3[15])
| IOZ2
|
CC
| IOZ3
+1.0
-0.5
Input leakage current (P2[0])(4)
CC
–
–
–
–
–
µA
µA
–
–
|
| IOZ4
|
Input leakage current (RPD)
CC
3.0
1.0
5
| IOZ5
|
Input leakage current (P3[12], P3[15])
Overload current (all except P2[0])
Overload current (P2[0])(4)
CC
µA
–
| IOV1
|
(1)(5)
SR
mA
mA
| IOV2
|
+5
-1
(1)(5)
SR
RSTIN pull-up resistor
RRST CC
50
–
250
-40
kΩ
100 kΩnominal
Read/Write inactive current(6)(7)
IRWH
µA
VOUT = 2.4V
284/328
ST10F252M
Electrical Characteristics
Table 145. DC characteristics (continued)
Limit values
Parameter
Symbol
Unit
Test condition
Min
Max
Read/Write active current(6)(8)
ALE inactive current(6)(7)
IRWL
IALEL
IALEH
IP6H
-500
20
–
–
–
µA
µA
µA
µA
µA
µA
µA
pF
VOUT = 0.4V
VOUT = 0.4V
VOUT = 2.4V
VOUT = 2.4V
VOUT = 0.4V
VIN = 2.0V
ALE active current(6)(8)
300
-40
–
Port 6 inactive current (P6[4:0])(6)(7)
Port 6 active current (P6[4:0])(6)(8)
–
IP6L
-500
–
(6)
IP0H
-10
–
PORT0 configuration current(6)
(7)
IP0L
-100
–
VIN = 0.8V
(1)(6)
Pin Capacitance (Digital inputs / outputs) CIO
CC
10
Run Mode Power supply current(9)
ICC1
15 + 1.5
fCPU
–
–
–
mA
mA
mA
–
–
–
(Execution from Internal RAM)
Run Mode Power supply current(1)(10)
ICC2
15 + 1.5
fCPU
(Execution from Internal Flash)
15 + 0.6
fCPU
Idle mode supply current(11)
IID
Power-down supply current(12)
(RTC off, Oscillators off,
Main Voltage Regulator off)
IPD1
–
150
µA
µA
TA = 25°C
TA = 25°C
Power-down supply current(12)
(RTC on, Main Oscillator on,
Main Voltage Regulator off)
400
IPD2
1100
VSTBY = 5.5V
TA = TJ = 25°C
Stand-by supply current(12)
(RTC off, Oscillators off, VDoff, VSTBY
on)
–
–
–
120
500
2.5
µA
µA
ISB1
VSTBY = 5.5V
TA = TJ = 125°C
Stand-by supply current(1)(12)
(VDD transint condition)
ISB3
mA
–
1. Not % tested, guaranteed by design characterization.
2This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage is imposed by the external circuitry.
3. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
4. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 107 for a scheme of the input
circuitry.
5. Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any pin exceeds the
specified range (that is, VOV > VDD + 0.3V or VOV < -0.3V). The absolute sum of input overload currents on all port pins may
not exceed 50mA. The supply voltage must remain within the specified limits.
6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
for CS output and the open drain function is not enabled.
7. The maximum current may be drawn while the respective signal line remains inactive.
8. The minimum current must be drawn in order to drive the respective signal line active.
285/328
Electrical Characteristics
ST10F252M
9. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in Figure 108 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is
doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
10. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in Figure 108 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is
doing the following:
- Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
11. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). Thdependency is
illustrated in Figure 108 below. These parameters are tested and at maximum CPU clock with all puts disconnected and
all inputs at VIL or VIH, RSTIN pin at VIH1min
.
12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0V to 0.1V or at VDD
- 0.1V to VDD, VAREF = 0V, all outputs (including pins configured as outputs) disconected. Also, the Main Voltage
Regulator is assumed to be off; if it is not, an additional 1mA must be added.
Figure 107. Port2 test mode structure
P2.0
CC0IO
Output
buffer
Clock
Input
Alternate data input
latch
Fast external interrupt input
Test mode
Flash sense amplifier
and column decoder
286/328
ST10F252M
Electrical Characteristics
Figure 108. Supply current versus the operating frequency (RUN and IDLE modes)
150
ICC1 = ICC2
100
IID
50
0
0
10
20
30
40
50
60
70
fCPU [MHz]
287/328
Electrical Characteristics
ST10F252M
27.6
Flash characteristics
V
= 5V 10%, V = 0V
SS
DD
Table 146. Flash characteristics
Typical
Maximum
TA = 125°C
Parameter
TA = 25°C
Unit
Notes
0 cycles(1) 0 cycles(1) 100k cycles
Word Program (32-bit) (2)
35
60
80
290
570
µs
µs
–
–
Double Word Program (64-bit)(2)
150
Bank 0 Program (256 Kbyte)
(Double Word Program)
1.6
2.0
3.9
s
s
s
s
–
0.6
0.5
0.9
0.8
1.0
0.9
not preprogrammed
prepgrammed
Sector Erase (8 Kbyte)
Sector Erase (32 Kbyte)
Sector Erase (64 Kbyte)
Bank 0 Erase (256 Kbyte)(3)
1.1
0.8
2.0
1.8
2.7
2.5
not preprogrammed
preprogrammed
1.7
1.3
3.7
3.3
5.1
4.7
not preprogrammed
preprogrammed
5.6
4.0
13.6
1
19.2
17.5
not preprogrammed
preprogrammed
(4)
Recovery from Power-Down (tPD
Program Suspend Latency(4)
Erase Suspend Latency(4)
)
–
–
–
40
10
30
40
10
30
µs
µs
µs
–
–
Minimum delay between
two requests
Erase Suspend Request Rate(4)
Set Protection(4)
20
40
20
90
20
ms
µs
300
–
1. The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer).
2. Word and Double Word Programming times are provided as average values derived from a full sector programming time:
absolute value of a Word or Double Word Programming time could be longer than the average value.
3. Banrase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As
ST10F252M implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations.
4. Not 100% tested, guaranteed by Design Characterization.
288/328
ST10F252M
Electrical Characteristics
Table 147. Flash data retention characteristics
Data retention time
(average ambient temperature 60°C)
Number of program / erase cycles
(-40°C < TA < 125°C)
256 Kbyte (code store)
64 Kbyte (EEPROM emulation)(1)
0 - 100
1000
> 20 years
> 20 years
> 20 years
10 years
1 year
-
-
-
10000
100000
1. Two 64 Kbyte Flash Sectors may be typically used to emulate up to 4, 8 or 16 Kbytes of EEPROM. Therefore, in case of an
emulation of a 16 Kbyte EEPROM, 100,000 Flash Program / Erase cycles are equivalent to 800,000 EEPROM
Program/Erase cycles. For an efficient use of the EEPROM Emulation please refer to dedicated Application Note document
(AN2061 - “EEPROM Emulation with ST10F2xx”). Contact your local field service, local sales person or STMicroeectronics
representative to obtain a copy of such a guideline document.
27.7
A/D converter characteristics
V
V
= 5V 10%, V = 0V, T = -40 to +125°C, 4.5V ≤V
V
,
DD
DD
SS
SS
A
AREF
≤V
≤V + 0.2V
AGND
SS
Table 148. A/D converter characteristics
Limit values
Parameter
Symbol
Unit
Test condition
in
Max
Analog Reference voltage(1)
Analog Ground voltage
Analog Input voltage(2)
VAREF SR
VAGND SR
4.5
VSS
VDD
V
V
V
VSS + 0.2
VAREF
VAIN
SR
VAGND
Running mode(3)
Power-down mode
–
–
5
1
mA
µA
Reference supply current
IAREF CC
(4)
Sample time
tS
CC
CC
CC
CC
CC
1
3
–
–
µs
µs
(5)
Conversion time
tC
Differeal Non Linearity(6)
Itegral Non Linearity(6)
Offset Error(6)
DNL
INL
OFS
-1
+1
LSB No overload
LSB No overload
LSB No overload
-1.5
-1.5
+1.5
+1.5
-2.0
-5.0
-7.0
+2.0
+5.0
+7.0
Port5
Total unadjusted error(6)
TUE
CC
LSB Port1 - No overload(3)
Port1 - Overload(3)
Coupling Factor between inputs(3)(7)
K
CC
CC
–
–
10–6
–
On both Port5 and Port1
CP1
3
pF
Input Pin Capacitance(3)(8)
Sampling Capacitance(3)(8)
4
6
Port5
Port1
CP2
CS
CC
CC
–
–
pF
pF
3.5
289/328
Electrical Characteristics
ST10F252M
Table 148. A/D converter characteristics (continued)
Limit values
Parameter
Symbol
Unit
Test condition
Min
Max
–
–
600
Port5
Port1
RSW
RAD
CC
CC
W
W
Analog Switch Resistance(3)(8)
1600
–
1300
1. VAREF can be tied to ground when A/D Converter is not in use: There is increased consumption (approximately 200µA) on
main VDD due to internal analog circuitry not being completely turned off. Therefore, it is suggested to maintain the VAREF
at VDD level even when not in use, and to eventually switch off the A/D Converter circuitry setting bit ADOFF in ADCON
register.
2. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will
be 0x000H or 0x3FFH, respectively
3. Not 100% tested, guaranteed by design characterization
4. During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the
sample time tS, changes of the analog input voltage have no effect on the conversion result.
Values for the sample clock tS depend on programming and can be taken from Table 149: A/D convr programming.
5. This parameter includes the sample time tS, the time for determining the digital result and the time load the result register
with the conversion result. Values for the conversion clock tCC depend on programming d can be taken from the next
Table 149.
6. DNL, INL, OFS and TUE are tested at VAREF = 5.0V, VAGND = 0V, VDD = 5.0V. It is guaranteed by design characterization
for all other voltages within the defined voltage range.
‘LSB’ has a value of VAREF/1024.
For Port5 channels, the specified TUE ( 2LSB) is guaranteed also with overload condition (see IOV specification)
occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all
Port5 analog input pins does not exceed 10mA.
For Port1 channels, the specified TUE is guaranteed when eroad condition is applied to Port1 pins: when an overload
condition occurs on maximum 2 not selected analog input pif Port1 and the input positive overload current on all analog
input pins does not exceed 10mA (either dynamic or static injection), the specified TUE is degraded ( 7LSB). To obtain the
same accuracy, the negative injection current on Port1 pins must not exceed -1mA in case of both dynamic and static
injection.
7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels
with the overload current within the different specified ranges (for both positive and negative injection current).
8. Refer to scheme shown in Figure 110.
27.7.1
Conversion timing control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value several successive steps, which correspond to the 10-bit resolution of the ADC.
During these steps the internal capacitances are repeatedly charged and discharged via the
V
pin.
AREF
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions during conversion take (sampling, and converting)
can be programmed within a certain range in the ST10F252M relative to the CPU clock. The
absolute time that is consumed by the different conversion steps therefore is independent
from the general speed of the controller. This allows adjustment of the ST10F252M A/D
converter to the system’s properties:
290/328
ST10F252M
Electrical Characteristics
Fast conversion can be achieved by programming the respective times to their absolute
possible minimum. This is preferable for scanning high frequency signals. The internal
resistance of analog source and analog supply must be sufficiently low, however.
High internal resistance can be achieved by programming the respective times to a higher
value, or the possible maximum. This is preferable when using analog sources and supply
with a high internal resistance in order to keep the current as low as possible. The
conversion rate in this case may be considerably lower, however.
The conversion times are programmed via the upper four bits of register ADCON. Bit fields
ADCTC and ADSTC are used to define the basic conversion time and in particular the
partition between sample phase and comparison phases. The table below lists the possible
combinations. The timings refer to the unit TCL, where f
= 1/2TCL. A complete
CPU
conversion time includes the conversion itself, the sample time and the time required to
transfer the digital value to the result register.
Table 149. A/D converter programming
ADCTC ADSTC
Sample
Comparison
Extra
Total conversion
00
00
00
00
11
11
11
11
10
10
10
10
00
01
10
11
00
01
10
11
00
01
10
11
TCL * 120
TCL * 140
TCL * 200
TCL * 400
TCL * 240
TCL * 280
TCL * 400
TCL * 800
TCL * 480
TCL 560
TCL * 800
TCL * 1600
TCL * 240
TCL * 280
TCL * 280
TCL * 280
TCL * 480
TCL 60
TCL * 560
TCL * 560
TCL * 960
TCL * 1120
TCL * 1120
TCL * 1120
TCL * 28
TCL * 16
TCL * 52
TCL * 44
TCL * 52
TCL * 28
TCL * 100
TCL * 52
TCL * 100
TCL * 52
TCL * 196
TCL * 164
TCL * 388
TCL * 436
TCL * 532
TCL * 724
TCL * 772
TCL * 868
TCL * 1060
TCL * 1444
TCL * 1540
TCL * 1732
TCL * 2116
TCL * 2884
Note:
The total conversion time is compatible with the formula valid for ST10F269, while the
meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum
conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4.85µs (see
ST10F269).
27.7.2
A/D conversion accuracy
The A/D Converter compares the analog voltage sampled on the selected analog input
channel to its analog reference voltage (V
) and converts it into 10-bit digital data. The
AREF
absolute accuracy of the A/D conversion is the deviation between the input analog value and
the output digital value. It includes the following errors:
●
●
●
●
Offset error (OFS)
Gain Error (GE)
Quantization error
Non-Linearity error (Differential and Integral)
291/328
Electrical Characteristics
These four error quantities are explained below using Figure 109.
ST10F252M
Offset error
Offset error is the deviation between actual and ideal A/D conversion characteristics when
the digital output value changes from the minimum (zero voltage) 00 to 01 (Figure 109, see
OFS).
Gain error
Gain error is the deviation between the actual and ideal A/D conversion characteristics when
the digital output value changes from the 3FE to the maximum 3FF, once offset error is
subtracted. Gain error combined with offset error represents the so-called full-scale error
(Figure 109, OFS + GE).
Quantization error
Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB.
Non-linearity error
Non-Linearity error is the deviation between actual and the bet-fitting A/D conversion
characteristics (see Figure 109):
●
Differential Non-Linearity error is the actual step dimension versus the ideal one (1
LSB ).
IDEAL
●
Integral Non-Linearity error is the distance between the center of the actual step and
the center of the bisector line, in actual characteristics. Note that for Integral Non-
Linearity error, the effect of offset, gain and quantization errors is not included.
Note:
Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the
real characteristic, and 1/2 LSB after the last step again of the real characteristic.
27.7.3
Total unadjusted error
The Total Unajusted Error specifies the maximum deviation from the ideal characteristic:
the number provided in the Data Sheet represents the maximum error with respect to the
entire characteristic. It is a combination of the Offset, Gain and Integral Linearity errors. The
different errors may compensate each other depending on the relative sign of the Offset and
Gain errors. Refer to Figure 109, see TUE.
292/328
ST10F252M
Electrical Characteristics
Figure 109. A/D conversion characteristics
Offset Error OFS
Gain Error GE
3FF
3FE
(6)
3FD
Ideal Characteristic
3FC
3FB
3FA
Bisector Characteristic
(2)
Digital
Out
007
(7)
(HEX)
(1)
006
005
(1) Example of an actual transfer curve
(2) The ideal transfer cue
(3) Differential Non-Liney Error (DNL)
(4) Integral Non-Linty Error (INL)
(5) Centestep of the actual transfer curve
(6) Quantiztion Error (1/2 LSB)
(5)
004
003
(4)
002
001
000
(3)
(7) Toal Unadjusted Error (TUE)
1 LSB (ideal)
1
2
3
4
5
6
7
10
1020
1022
1024
V
[LSB
(LSB
ID
)
AIN
IDEAL
=
/ 1024]
EF
Offset Error OFS
27.7.4
Analog reference pins
The accuracy of the A/D converter depends on how accurate is its analog reference: a noise
in the reference results in at least that much error in a conversion. A low pass filter on the
A/D converter rerence source (supplied through pins V
and V
), is recommended
AREF
AGND
in order to cln the signal, minimizing the noise. A simple capacitive bypassing may be
sufficiein most of the cases; in presence of high RF noise energy, inductors or ferrite
beads may be necessary.
In this architecture, V
and V
pins represents also the power supply of the analog
AREF
AGND
circuitry of the A/D converter: there is an effective DC current requirement from the
reference voltage by the internal resistor string in the R-C DAC array and by the rest of the
analog circuitry.
An external resistance on V
could introduce error under certain conditions: for this
AREF
reasons, series resistance are not advisable, and more in general any series devices in the
filter network should be designed to minimize the DC resistance.
Analog input pins
To improve the accuracy of the A/D converter, it is definitively necessary that analog input
pins have low AC impedance. Placing a capacitor with good high frequency characteristics
at the input pin of the device, can be effective: the capacitor should be as large as possible,
ideally infinite. This capacitor contributes to attenuating the noise present on the input pin;
moreover, it sources charge during the sampling phase, when the analog signal source is a
high-impedance source.
293/328
Electrical Characteristics
ST10F252M
A real filter, can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC Filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth).
Figure 110. A/D converter input pins scheme
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Channel
Sampling
Selection
Source
RS
Filter
RF
Current Limiter
RL
RSW
RAD
VA
CF
CP1
CP2
CS
R
R
C
R
R
R
C
C
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
SW
AD
P
Pin Capacitance (two ribons, C and C
Sampling Capacitanc
)
P1
P2
S
Input leakage and external circuit
The series resistor utilized to limit the current to a pin (see R in Figure 110), in combination
L
with a large source impedance can lead to a degradation of A/D converter accuracy when
input leakage is esent.
Data aut maximum input leakage current at each pin is provided in the Data Sheet
(Electrical Characteristics section). Input leakage is greatest at high operating temperatures,
and in general it decreases by one half for each 10°C decrease in temperature.
Considering that, for a 10-bit A/D converter one count is about 5mV (assuming V
= 5V),
AREF
an input leakage of 100nA acting though an R = 50kΩ of external resistance leads to an
L
error of exactly one count (5mV); if the resistance were 100kΩ the error would become two
counts.
Eventual additional leakage due to external clamping diodes must also be taken into
account in computing the total leakage affecting the A/D converter measurements. Another
contribution to the total leakage is represented by the charge sharing effects with the
sampling capacitance: being C substantially a switched capacitance, with a frequency
S
equal to the conversion rate of a single channel (maximum when fixed channel continuous
conversion mode is selected), it can be seen as a resistive path to ground. For instance,
assuming a conversion rate of 250 kHz, with C equal to 4pF, a resistance of 1MΩ is
S
obtained (R = 1 / f C , where f represents the conversion rate at the considered
EQ
C
S
C
channel). To minimize the error induced by the voltage partitioning between this resistance
294/328
ST10F252M
Electrical Characteristics
+ R , the external circuit
(sampled voltage on C ) and the sum of R + R + R + R
S
S
F
L
SW
1
AD
must be designed to respect the following relation:
R
+ R + R + R
+ R
S
F
L
SW
AD
------------------------------------------------------------------------------
V
⋅
< -- LSB
A
R
2
EQ
The formula above provides constraints for external network design, in particular on
resistive path.
A second aspect involving the capacitance network must be considered. Assuming the three
capacitances C , C and C initially charged at the source voltage V (refer to the
F
P1
P2
A
equivalent circuit shown in Figure 110), when the sampling phase is started (A/D switch
close), a charge sharing phenomena is installed.
Figure 111. Charge sharing timing diagram during sampling phase
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS << TS
τ2 = RL (CS + CP1 + CP2
)
VA1
TS
t
In partilar two different transient periods can be distinguished (see Figure 111):
A first and quick charge transfer from the internal capacitance C and C to the
●
P1
P2
sampling capacitance C occurs (C is supposed initially completely discharged):
S
S
considering a worst case (since the time constant in reality would be faster) in which
C
is shown in parallel to C (call C = C + C ), the two capacitance C and C
P2
P1 P P1 P2 P S
are in series, and the time constant is:
C
⋅ C
S
P
-----------------------
τ
= (R + R
) ⋅
1
SW
AD
C
+ C
P
S
This relation can again be simplified considering only C as an additional worst
S
condition. In reality, the transient is faster, but the A/D Converter circuitry has been
designed to be robust also in the very worst case: the sampling time T is always much
S
longer than the internal time constant:
τ
< (R
+ R
) ⋅ C <
< TS
1
SW
AD
S
The charge of C and C is redistributed also on C , determining a new value of the
P1
P2
S
voltage V on the capacitance according to the following equation:
A1
V
⋅ (C + C
+ C ) = V ⋅ (C
P2
+ C
)
P2
A1
S
P1
A
P1
295/328
Electrical Characteristics
ST10F252M
●
A second charge transfer involves also C (that is typically bigger than the on-chip
F
capacitance) through the resistance R : again considering the worst case in which C
L
P2
and C were in parallel to C (since the time constant in reality would be faster), the
S
P1
time constant is:
τ
< R ⋅ (C + C
+ C
)
P2
2
L
S
P1
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time T , a constraint on
S
R sizing is obtained:
L
10 ⋅ τ = 10 ⋅ R ⋅ (C + C
+ C ) ≤ T
P2 S
2
L
S
P1
Of course, R must also be sized according to the current limitation constraints, in
L
combination with R (source impedance) and R (filter resistance). Being C
S
F
F
definitively bigger than C , C and C , then the final voltage V (at the end of the
P1
P2
S
A2
charge transfer transient) will be much higher than V . The following equation must be
A1
respected (charge balance assuming now C already charged at ):
S
A1
V
⋅ (C + C + C + C ) =V ⋅ C + V ⋅ (C + C + C )
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence
of the R C filter, is not able to provide the extra harge to compensate the voltage drop on
F
F
C with respect to the ideal source V ; the time constant R C of the filter is very high with
S
A
F F
respect to the sampling time (T ). The ter s typically designed to act as anti-aliasing (see
S
Figure 112).
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of
0
the anti-aliasing filter, f ), according to Nyquist theorem the conversion rate f must be at
F
C
least 2f ; it means that the constant time of the filter is greater than or at least equal to twice
0
the conversion period (T ). Again the conversion period T is longer than the sampling time
C
C
T , which is just portion of it, even when fixed channel continuous conversion mode is
S
selected (fastst conversion rate at a specific channel): in conclusion it is evident that the
time costant of the filter R C is definitively much higher than the sampling time T , so the
F
F
S
charge level on C cannot be modified by the analog signal source during the time in which
S
the sampling switch is closed.
Figure 112. Anti-aliasing filter and conversion rate
Analog Source Bandwidth (VA)
TC ≤2 RFCF (Conversion Rate vs. Filter Pole)
Noise
fF = f0 (Anti-aliasing Filtering Condition)
2 f0 ≤fC (Nyquist)
f0
Anti-Aliasing Filter (fF = RC Filter pole) Sampled Signal Spectrum (fC = conversion Rate)
f
fF
f0
fC
f
f
296/328
ST10F252M
Electrical Characteristics
The considerations above lead to impose new constraints to the external circuit, to reduce
the accuracy error due to the voltage drop on C ; from the two charge balance equations
S
above, it is simple to derive the following relation between the ideal and real sampled
voltage on C :
S
V
C
+ C
+ C
A
P1
----------- = ------------------------------------------------------------
+ C + C + C
P2
F
V
C
A2
P1
P2
F
S
From this formula, in the worst case (when V is maximum, that is for instance 5V),
A
assuming to accept a maximum error of half a count (~2.44mV), a constraint is immediately
evident on C value:
F
C
>2048 ⋅ C
S
F
In the next section an example of how to design the external network is provided, assuming
some reasonable values for the internal parameters and making a hypothesis on the
characteristics of the analog signal to be sampled.
Example of external network sizing
The following hypotheses are formulated in order to proceed idesigning the external
network on A/D Converter input pins:
●
●
●
●
●
●
●
●
●
●
●
Analog Signal Source Bandwidth (f ): 10 kHz
0
conversion Rate (f ): 25 kHz
C
Sampling Time (T ):
1µs
S
Pin Input Capacitance (C ): 5pF
P1
Pin Input Routing Capacitance (C ):
1pF
4pF
P2
Sampling Capacitance (C ):
S
Maximum Input Current Injection (I ): 3mA
INJ
Maximum Analog Source Voltage (V : 12V
AM)
Analog Soue Impedance (R ):
100Ω
500Ω
200Ω
S
Cnnel Switch Resistance (R ):
SW
Sampling Switch Resistance (R ):
AD
297/328
Electrical Characteristics
ST10F252M
1. Supposing to design the filter with the pole exactly at the maximum frequency of the
signal, the time constant of the filter is:
1
2πf
-----------
R C =
C F
= 15.9μs
0
2. Using the relation between C and C and taking some margin (4000 instead of 2048),
F
S
it is possible to define C :
F
C = 4000 ⋅ C = 16nF
F
S
3. As a consequence of step 1 and 2, RC can be chosen:
1
--------------------
R =
= 995Ω ≅ 1kΩ
F
2πf C
0 F
4. Considering the current injection limitation and supposing that the source can go up to
12V, the total series resistance can be defined as:
V
AM
R
+ R + R = ------------- = 4 k Ω
S
F
L
I
INJ
from which is now simple to define the value of R :
L
V
AM
R = ------------- – R – R = 2.9kΩ
L
F
S
I
INJ
5. Now the three elements of the external circuit R , C and R are defined. Some
F
F
L
conditions discussed in the previos pagraphs have been used to size the
component, the other must now bverified. The relation which allows minimization of
the accuracy error introduced by the switched capacitance equivalent resistance is in
this case:
1
R
= --------------= 10MΩ
EQ
f C
C S
So the eor due to the voltage partitioning between the real resistive path and C is
S
lesthen half a count (considering the worst case when V = 5V):
A
R
+ R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
--
= 2.35mV < LSB
V ⋅
A
R
EQ
The other condition to be verified is if the time constants of the transients are really and
significantly shorter than the sampling period duration T :
S
τ
= (R
+ R
) ⋅ C = 2.8ns
<< TS = 1μs
AD S
1
SW
10 ⋅ τ = 10 ⋅ R ⋅ (C + C
+ C )= 290ns < TS = 1μs
2
L
S
P1
P2
For the complete set of parameters characterizing the ST10F252M A/D Converter
equivalent circuit, refer to Section 27.7: A/D converter characteristics on page 289.
298/328
ST10F252M
Electrical Characteristics
27.8
AC characteristics
27.8.1
Test waveforms
Figure 113. Input / output waveforms
2.4V
2.0V
2.0V
0.8V
Test Points
0.8V
0.4V
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at VIH min. for a logic ‘1’ and VIL max for a logic ‘0’.
Figure 114. Float waveforms
VOH
VOH - 0.1V
VLOAD + 0.1V
VLOAD
Timing
Refence
Points
VLOAD - 0.1V
VOL + 0.1V
VOL
For timing purposes a port pin is no longer floating when VLOAD changes of 100mV.
It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).
27.8.2
Definition of internal timing
The intrnal operation of the ST10F252M is controlled by the internal CPU clock f
. Both
CPU
edges of the CPU clock can trigger internal (for example, pipeline) or external (for example,
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate f
.
CPU
This influence must be regarded when calculating the timings for the ST10F252M.
The example for PLL operation shown in Figure 115 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
299/328
Electrical Characteristics
Figure 115. Generation mechanisms for the CPU clock
ST10F252M
Phase locked loop operation
fXTAL
fCPU
TCLTCL
TCLTCL
Direct Clock Drive
fXTAL
fCPU
Prescaler Operation
fXTAL
fCPU
TCL L
27.8.3
Clock generation modes
The next Table 150 associates the combinations these three bits with the respective clock
generation mode.
Table 150. On-chip clock generator selections
P0.15-13
(P0H.7-5)
CPU frequency
fCPU = fXTAL x F
External clock
Notes
input range(1)(3)
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fXTAL x 4
fXTAL x 3
4 to 8 MHz
5.3 to 8 MHz
4 to 5 MHz
6.4 to 8 MHz
1 to 40 MHz
4 MHz
Default configuration
f
XTAL x 8
fXTAL x 5
XTAL x 1
f
Direct Drive (oscillator bypassed)(2)
fXTAL x 10
fXTAL / 2
-
4 to 8 MHz
-
CPU clock via prescaler(3)
Reserved
1. The external clock input range refers to a CPU clock range of 1...40 MHz. Moreover, the PLL usage is
limited to 4-8 MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock
through the internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced
through an external clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no
crystal or resonator can be used).
2. The maximum depends on the duty cycle of the external clock signal: when 40 MHz is used, 50% duty
cycle is granted (low phase = high phase = 12.5ns); when 20 MHz is selected a 25% duty cycle can be
accepted (minimum phase, high or low, again equal to 12.5ns).
3. The limits on input frequency are 4-8 MHz since the usage of the internal oscillator amplifier is required.
Also when the PLL is not used and the CPU clock corresponds to fXTAL/2, an external crystal or resonator
must be used: It is not possible to force any clock though an external clock source.
300/328
ST10F252M
Electrical Characteristics
27.8.4
Prescaler operation
When pins P0.15-13 (P0H.7-5) equal “001” during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
is half the frequency of f
and the high and low time of f
(that
CPU
XTAL
CPU
is, the duration of an individual TCL) is defined by the period of the input clock f
.
XTAL
The timings listed in the AC Characteristics that refer to TCL therefore can be calculated
using the period of f for any TCL.
XTAL
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,
then the PLL is switched off.
27.8.5
Direct drive
When pins P0.15-13 (P0H.7-5) equal “011” during reset the on-chip phase locked loop is
disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by
the input clock signal on XTAL1 pin.
The frequency of CPU clock (f
) directly follows the frequeny of f
so the high and
XTAL
CPU
low time of f
input clock f
(that is, the duration of an individual TCL) is defined by the duty cycle of the
.
CPU
XTAL
Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value
can be calculated by the following formula:
TCL
= 1
xlDC
mi
XTALl
min
DC= duty cycle
For two consecutive TCLs, the deviation caused by the duty cycle of f
is compensated,
XTAL
so the duration of 2TCL is always 1/f
.
XTAL
The minimum value TCL
has to be used only once for timings that require an odd number
min
of TCLs (1,3,...). imings that require an even number of TCLs (2,4,...) may use the formula:
2TCL= 1 ⁄ f
XTAL
Thaddress float timings in Multiplexed bus mode (t and t ) use the maximum duration of
11
45
TCL (TCL
= 1/f
x DC
) instead of TCL
.
max
XTAL
max
min
Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is
cleared, the PLL runs on its free-running frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
27.8.6
Oscillator watchdog (OWD)
An on-chip watchdog oscillator is implemented in the ST10F252M. This feature is used for
safety operation with external crystal oscillator (available only when using direct drive mode
with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the
frequency of the external crystal oscillator). This watchdog oscillator operates as following.
The reset default configuration enables the watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the
watchdog counter. On each transition of external clock, the watchdog counter is cleared. If
301/328
Electrical Characteristics
ST10F252M
an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply
current.
27.8.7
Phase locked loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see Table 150). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (f
=
CPU
f
x F). With every F’th transition of f
the PLL circuit synchronizthe CPU clock to
XTAL
XTAL
the input clock. This synchronization is done smoothly, so the CPU clck frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of f
is constantly adjusted so it is
CPU
locked to f
. The slight variation causes a jitter of
which also effects the duration of
XTAL
CPU
individual TCLs.
The timings listed in the AC Characteristichat refer to TCLs therefore must be calculated
using the minimum TCL that is possibnder the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
to
CPU
keep it locked on f
one TCL period.
. The relative deviation of TCL is the maximum when it is referred to
XTAL
This is especially important for bus cycles using wait states and for example, such as for the
operation of timor serial interfaces. For all slower operations and longer periods (for
example, pulstrain generation or measurement, or lower baudrates) the deviation caused
by the LL jitter is negligible. Refer to next Section 27.8.9: PLL jitter for more details.
27.8.8
Voltage controlled oscillator
The ST10F252M implements a PLL which combines different levels of frequency dividers
with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. The following
table gives a detailed summary of the internal settings and VCO frequency.
Table 151. Internal PLL divider mechanism
PLL
Multiply by
P0.15-13
(P0H.7-5)
Input
prescaler
Output
prescaler
CPU frequency
fCPU = fXTAL x F
XTAL frequency
Divide by
1
1
1
0
0
1
1
4 to 8 MHz
5.3 to 8 MHz(1)
4 to 5 MHz
fXTAL / 4
fXTAL / 4
fXTAL / 4
fXTAL / 4
–
64
48
64
40
4
4
2
2
–
–
–
–
–
fXTAL x 4
fXTAL x 3
fXTAL x 8
fXTAL x 5
1
1
1
0
0
1
0
1
6.4 to 8 MHz(1)
1 to 40 MHz
PLL bypassed
fXTAL x 1
302/328
ST10F252M
Electrical Characteristics
Table 151. Internal PLL divider mechanism (continued)
PLL
P0.15-13
(P0H.7-5)
Input
Output
prescaler
CPU frequency
XTAL frequency
prescaler
f
CPU = fXTAL x F
Multiply by
Divide by
0
1
0
0
0
4 MHz
fXTAL / 2
–
40
2
–
fXTAL x 10
fXTAL / 2
0
0
1
0
4 to 8 MHz(1)
PLL bypassed
fPLL / 2
–
1. The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is 64 to 128 MHz. The CPU clock
frequency range when PLL is used is 16 to 40 MHz.
Example 1
●
●
●
●
●
f
= 4 MHz
XTAL
P0(15:13) = ‘110’ (multiplication by 3)
PLL input frequency = 1 MHz
VCO frequency = 48 MHz: NOT VALID, must be 64 to 128 MHz
f
= NOT VALID
CPU
Example 2
●
●
●
●
●
●
f
= 8 MHz
XTAL
P0(15:13) = ‘100’ (multiplication by 5)
PLL input frequency = 2 MHz
VCO frequency = 80 MHz
PLL output frequency = 40 MHz (VCO frequency divided by 2)
f
= 40 MHz (no effect of Output Prescaler)
CPU
27.8.9
PLL jitter
The following rminology is hereafter defined:
●
Sef referred single period jitter
Also called “Period Jitter”, it can be defined as the difference of the T
and T
,
max
min
where T
is maximum time period of the PLL output clock and T
is the minimum
max
min
time period of the PLL output clock.
●
Self referred long term jitter
Also called “N period jitter”, it can be defined as the difference of T
and T , where
min
max
T
is the maximum time difference between N+1 clock rising edges and T
is the
max
min
minimum time difference between N+1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N=1, this becomes the single period
jitter.
Jitter at the PLL output can be due to the following reasons:
●
Jitter in the input clock
Noise in the PLL loop
●
303/328
Electrical Characteristics
ST10F252M
Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the
frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency
jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.
Noise in the PLL loop
This contribution again can be caused by the following sources:
●
Device noise of the circuit in the PLL
Noise in supply and substrate.
●
Device noise of the circuit in the PLL
The long term jitter is inversely proportional to the bandwidth of the PLL: the wider the loop
bandwidth is, the lower the jitter is due to noise in the loop. Moreover, the long term jitter is
practically independent of the multiplication factor.
The most noise sensitive circuit in the PLL circuit is definitively the VCO Voltage Controlled
Oscillator). There are two main sources of noise: thermal (random nse, frequency-
independent noise, thus, practically white noise) and flicker (lfrequency noise, 1/f). For
the frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a
2
3
1/f region in the output noise spectrum, while the flicker noise in a 1/f . Assuming a
2
noiseless PLL input and supposing that the VCO is dominated by its 1/f noise, the R.M.S.
value of the accumulated jitter is proportional to tsquare root of N, where N is the number
of clock periods within the considered time nterval.
On the contrary, assuming again a noess PLL input and supposing that the VCO is
3
dominated by its 1/f noise, the R.M.S. value of the accumulated jitter is proportional to N,
where N is the number of clock periods within the considered time interval.
2
The jitter in the PLL loop can be modelized as dominated by the i1/f noise for N smaller
than a certain value depending on the PLL output frequency and on the bandwidth
characteristics oloop. Above this first value, the jitter becomes dominated by the i1/f noise
3
component. Lastly, for N greater than a second value of N, a saturation effect is evident, so
the jitter does not grow anymore when considering a longer time interval (jitter stable
increasing the number of clock periods N). The PLL loop acts as a high pass filter for any
nose in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation
value corresponds to what has been called self referred long term jitter of the PLL. In
Figure 116 the maximum jitter trend versus the number of clock periods N (for some typical
CPU frequencies) is shown: The curves represent the very worst case, computed taking into
account all corners of temperature, power supply and process variations: The real jitter is
always measured well below the given worst case values.
Noise in supply and substrate
Digital supply noise adds deterministic components to the PLL output jitter, independent of
the multiplication factor. Its effects are strongly reduced thanks to the particular care used in
the physical implementation and integration of the PLL module inside the device.
Nonetheless, the contribution of the digital noise to the global jitter is widely taken into
account in the curves provided in Figure 116.
304/328
ST10F252M
Electrical Characteristics
Figure 116. ST10F252M PLL jitter
5
16MHz 24MHz 32MHz 40MHz
64MHz
4
3
2
1
TJIT
0
0
200
400
600
800
1000
00
1400
N (CPU clock periods)
27.8.10 PLL lock / unlock
During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the
CPU is generated, and the reference clock scillator) is automatically disconnected from
the PLL input: in this way, the PLL goeto free-running mode, providing the system with a
backup clock signal (free running frequency f ). This feature allows recovery from a crystal
free
failure occurrence without risking to go into an undefined configuration: The system is
provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path betweereference clock and PLL input can be restored only by a hardware reset,
or by a bidireional software or watchdog reset event that forces the RSTIN pin low.
Note:
The external RC circuit on RSTIN pin must be properly sized in order to extend the duration
of the low pulse to lock the PLL before the level at RSTIN pin is recognized high: A
bidirectional reset internally drives the RSTIN pin low for just 1024 TCL (definitely not
sufficient to lock the PLL starting from free-running mode).
Table 152. PLL characteristics (V = 5V 10ꢀ, V = 0V, T = -40 to +125°C)
DD
SS
A
Value
Symbol
Parameter
Conditions
Unit
Min
Max
tPSUP PLL Start-up time(1)
tLOCK PLL Lock-in time
Stable VDD and reference clock
–
–
300
µs
µs
Stable VDD and reference clock,
starting from free-running mode
250
Single Period Jitter(1)
TJIT
6 sigma time period variation
(peak to peak)
-500
+500
ps
(cycle to cycle = 2 TCL)
Multiplication factors: 3, 4
250
500
2000
4000
ffree
PLL free running frequency
kHz
Multiplication factors: 5, 8, 10, 16
1. Not 100% tested, guaranteed by design characterization
305/328
Electrical Characteristics
ST10F252M
27.8.11 Main oscillator specifications
V
= 5V 10%, V = 0V, T = -40 to +125°C
SS A
DD
Table 153. Main oscillator characteristics
Value
Typ
Symbol
Parameter
Conditions
Unit
Min
Max
Oscillator
Transconductance
gm
1.4
2.6
4.2
mA/V
VOSC Oscillation Amplitude(1)
Peak to Peak
–
–
–
–
1.5
0.8
6
–
–
V
V
VAV
Oscillation Voltage level(1) Sine wave middle
Stable VDD - Crystal
10
2
ms
ms
tSTUP Oscillator Start-up Time(1)
Stable VDD - Resonator
1
1. Not 100% tested, guaranteed by design characterization
Figure 117. Crystal oscillator and resonator connection digram
ST10F252M
ST10F252M
Crystal
Resonator
CA
CA
Table 154. Main oscillator negative resistance (module)
CA = 15pF
Typ
CA = 25pF
Typ
CA = 35pF
Typ
Min
Max
–
Min
Max
–
Min
Max
–
4 MHz
8 MHz
545 Ω
240 Ω
1035 Ω
450 Ω
550 Ω
170 Ω
1050 Ω
350 Ω
430 Ω
120 Ω
850 Ω
250 Ω
–
–
–
The given values of C do not include the stray capacitance of the package and of the
A
printed circuit board: the negative resistance values are calculated assuming additional 5pF
to the values in the table. The crystal shunt capacitance (C ) and the package capacitance
0
between XTAL1 and XTAL2 pins is globally assumed equal to 10pF.
The external resistance between XTAL1 and XTAL2 is not necessary, since already present
on the silicon.
306/328
ST10F252M
Electrical Characteristics
27.8.12 External clock drive XTAL1
When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock
directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since
the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that
targets a maximum CPU frequency of 40 MHz.
In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip
oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then, when
the on-chip oscillator is enabled it is forbidden to use any external clock source different
from crystal or ceramic resonator.
Table 155. External clock drive
Direct drive with
Direct drive
fCPU = fXTAL
PLL usage
fCPU = fXTAL x F
prescaler
Parameter
Symbol
Unit
fCPU = fXTAL / 2
Min
25
Max
Min
Max
Mn
Max
XTAL1 period(1)(2) tOSC SR
–
83.3
250
–
83.3
250
–
ns
ns
ns
ns
ns
High time(3)
Low time(3)
Rise time(3)
Fall time(3)
t1
t2
t3
t4
SR
SR
SR
SR
6
6
–
–
–
–
2
2
3
3
–
–
6
6
–
–
–
–
2
2
2
2
1. The minimum value for the XTAL1 signal pis considered the theoretical minimum. The real minimum
value depends on the duty cycle of the input clock signal.
2. 4 to 8 MHz is the input frequency range when using an external clock source. 40 MHz can be applied with
an external clock source only when Direct Drive mode is selected: in this case, the oscillator amplifier is
bypassed so it does not limit the input frequency.
3. The input clock signal must reach the defined levels VIL2 and VIH2
.
Figure 118. Exnal clock drive XTAL1
t3
t4
t1
VIH2
VIL2
t2
tOSC
Note:
When Direct Drive is selected, an external clock source can be used to drive XTAL1. The
maximum frequency of the external clock source depends on the duty cycle: When 40 MHz
is used, 50% duty cycle is granted (low phase = high phase = 12.5ns); when for instance
20 MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again
equal to 12.5ns).
27.8.13 Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes how these variables are to be computed.
307/328
Electrical Characteristics
ST10F252M
Table 156. Memory cycle variables
Description
ALE Extension
Symbol
Values
tA
tC
tF
TCL x [ALECTL]
Memory Cycle Time wait states
Memory Tri-state Time
2TCL x (15 - [MCTC])
2TCL x (1 - [MTTC])
27.8.14 External memory bus timing
The following sections include the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40 MHz.
Note:
All External Memory Bus Timings and SSC Timings listed in the following tables are granted
by Design Characterization and not fully tested in production.
27.8.15 Multiplexed bus
V
= 5V 10%, V = 0V, T = -40 to +125°C, CL = 50pF,
SS A
DD
ALE cycle time = 6 TCL + 2t + t + t (75ns at 40 MHz CPU ock without wait states)
A
C
F
Table 157. Multiplexed bus timings
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
4 + tA
Max
Min
Max
t5 CC ALE high time
–
–
–
TCL – 8.5 + tA
TCL – 11 + tA
TCL – 8.5 + tA
–
–
–
ns
ns
ns
t6 CC Address setup to ALE
t7 CC Address hold after ALE
1.5 + tA
4 + tA
ALE falling edge to RWR
t8 CC
4 + tA
–
TCL – 8.5 + tA
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
(with RW-delay)
ALE falling dge to RD, WR
t9 CC
– 8.5 + tA
–
– 8.5 + tA
–
(no RW-delay)
Adress float after RD, WR (with
RW-delay)1
t10 CC
–
6
18.5
–
–
6
Address float after RD, WR
CC
–
–
TCL + 6
(no RW-delay)1
RD, WR low time
t12 CC
15.5 + tC
2TCL – 9.5 + tC
–
(with RW-delay)
RD, WR low time
t13 CC
28 + tC
–
3TCL – 9.5 + tC
–
(no RW-delay)
RD to valid data in
t14 SR
–
–
–
6 + tC
18.5 + tC
–
–
–
2TCL – 19 + tC
3TCL – 19 + tC
(with RW-delay)
RD to valid data in
t15 SR
(no RW-delay)
17.5 +
+ tA + tC
3TCL – 20 +
+ tA + tC
t16 SR ALE low to valid data in
308/328
ST10F252M
Electrical Characteristics
Table 157. Multiplexed bus timings (continued)
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Address/Unlatched CS to valid
data in
20 + 2tA +
+ tC
4TCL – 30 +
+ 2tA + tC
t17 SR
t18 SR
–
–
ns
ns
Data hold after RD
rising edge
0
–
0
–
t19 SR Data float after RD1
t22 CC Data valid to WR
–
16.5 + tF
–
2TCL – 8.5 + tF
ns
ns
ns
ns
10 + tC
4 + tF
15 + tF
–
–
–
2TCL – 15 + tC
2TCL – 8.5 + tF
2TCL – 10 + tF
–
–
–
t23 CC Data hold after WR
t25 CC ALE rising edge after RD, WR
Address/Unlatched CS hold
after RD, WR
t27 CC
10 + tF
– 4 – tA
–
–
2TCL – 15 + tF
– 4 –
–
ns
ns
ns
ns
ns
t38 CC ALE falling edge to Latched CS
t39 SR Latched CS low to Valid Data In
t40 CC Latched CS hold after RD, WR
10 – tA
10 – tA
16.5 + tC +
+ 2tA
3TCL - 21 +
+ tC + 2tA
–
27 + tF
7 + tA
–
3TCL - 10.5 + tF
TCL - 5.5 + tA
–
–
ALE fall. edge to RdCS, WrCS
(with RW delay)
t42 CC
ALE fall. edge to RdCS, WrCS
(no RW delay)
t43 CC
-5.5 + tA
–
1.5
-5.5 + tA
–
ns
ns
ns
ns
ns
ns
ns
Address float after RdCS, WrCS
(with RW delay)1
t44 CC
–
–
1.5
Address float after RdS, WrCS
(no RW delay)1
t45 CC
–
14
–
TCL + 1.5
RdCS to Vad Data In
t46 SR
–
–
4 + tC
16.5 + tC
–
–
2TCL - 21 + tC
(with RW delay)
RCS to Valid Data In
t47 SR
–
3TCL - 21 + tC
(no RW delay)
RdCS, WrCS Low Time
CC
15.5 + tC
28 + tC
2TCL - 9.5 + tC
3TCL - 9.5 + tC
–
–
(with RW delay)
RdCS, WrCS Low Time
t49 CC
–
(no RW delay)
t50 CC Data valid to WrCS
t51 SR Data hold after RdCS
t52 SR Data float after RdCS1
10 + tC
–
–
2TCL - 15 + tC
–
ns
ns
ns
0
–
0
–
–
16.5 + tF
2TCL - 8.5 + tF
Address hold after
t54 CC
6 + tF
6 + tF
–
–
2TCL - 19 + tF
2TCL - 19 + tF
–
–
ns
ns
RdCS, WrCS
t56 CC Data hold after WrCS
309/328
Electrical Characteristics
ST10F252M
Figure 119. External memory cycle: multiplexed bus, with/without read/write delay, normal ALE
CLKOUT
t5
t25
t16
ALE
CSx
t6
t38
t40
t17
t27
t39
t6
t27
t17
A23-A16
(A15-A8)
BHE
Address
t16
t6
Read cycle
t7
t1
Data in
Address/data
bus (P0)
Address
Address
t10
t19
t8
t14
RD
t12
t13
t9
t1
t15
Write cycle
t23
Address/data
bus (P0)
Address
Data out
t8
t22
WR
WRL
WRH
t9
t12
t13
310/328
ST10F252M
Electrical Characteristics
Figure 120. External memory cycle: multiplexed bus, with/without read/write delay, extended ALE
CLKOUT
t16
t5
t25
ALE
t6
t38
t40
t17
t39
t27
CSx
t6
t17
A23-A16
(A15-A8)
BHE
Address
t27
Read cycle
t6
t7
Address/Data
Bus (P0)
Data in
Address
t18
t8
t10
t11
t19
t9
t14
RD
t15
t12
t13
Write cycle
Address/Data
Bus ()
Address
Data out
t23
t8
t10
t11
t9
t22
WR
WRL
WRH
t12
t13
311/328
Electrical Characteristics
ST10F252M
Figure 121. External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS
CLKOUT
t5
t16
t25
ALE
t6
t27
t17
A23-A16
(A15-A8)
BHE
Address
t16
t6
t7
t51
Read Cycle
Address/Data
Bus (P0)
Address
Address
Data In
t52
t42
t44
t
RdCSx
t48
t49
t43
t45
t47
t55
Write Cycle
Address/Data
Bus (P0)
Address
Data Out
t42
t50
WrCSx
t43
t48
t49
312/328
ST10F252M
Electrical Characteristics
Figure 122. External memory cycle: multiplexed bus, with/without r/w delay, extended ALE, r/w CS
CLKOUT
t16
t5
t25
ALE
t6
t17
A23-A16
(A15-A8)
BHE
Address
t54
Read cycle
t6
t7
Address/Data
Bus (P0)
Data in
Address
t18
t42
t44
t19
t43
t4
t46
t48
RdCSx
t47
t49
Write cycle
Address/data
bus (P0)
Address
Data out
t56
t42
t44
t43
t45
t50
WrCSx
t48
t49
313/328
Electrical Characteristics
ST10F252M
27.8.16 Demultiplexed bus
V
= 5V 10%, V = 0V, T = -40 to +125°C, CL = 50pF,
SS A
DD
ALE cycle time = 4 TCL + 2t + t + t (50ns at 40 MHz CPU clock without wait states).
A
C
F
.
Table 158. Demultiplexed bus timings
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
t5
t6
CC ALE high time
4 + tA
–
–
TCL - 8.5 + tA
TCL - 11 + tA
–
–
ns
ns
CC Address setup to ALE
1.5 + tA
Address/Unlatched CS setup
t80 CC to RD, WR
(with RW-delay)
2TCL - 12.5 +
+ 2tA
12.5 + 2tA
0.5 + 2tA
–
–
–
–
ns
ns
Address/Unlatched CS setup
t81 CC to RD, WR
TCL - 12 + 2tA
(no RW-delay)
RD, WR low time
(with RW-delay)
t12 CC
t13 CC
t14 SR
t15 SR
15.5 + tC
–
–
2TC- 9.5 + tC
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD, WR low time
(no RW-delay)
28 + tC
3TCL - 9.5 + tC
–
RD to valid data in
(with RW-delay)
–
–
–
–
0
–
–
6 + tC
18.5 + tC
–
–
–
–
0
–
–
2TCL - 19 + tC
3TCL - 19 + tC
RD to valid data in
(no RW-delay)
17.5 + tA +
+ tC
3TCL - 20 +
+ tA + tC
t16 SR ALE low to valid data in
Address/UnlatcheCS to
t17 SR
20 + 2tA +
+ tC
4TCL - 30 +
+ 2tA + tC
valid data i
Data hold after RD
t18 SR
–
–
rising edge
Data float after RD rising
t20 S
2TCL - 8.5 +
+ tF + 2tA
16.5 + tF
4 + tF
edge (with RW-delay)(1)
Data float after RD rising
t21 SR
TCL - 8.5 +
+ tF + 2tA
edge (no RW-delay)(1)
t22 CC Data valid to WR
10 + tC
4 + tF
–
–
–
2TCL - 15 + tC
TCL - 8.5 + tF
-10 + tF
–
–
–
ns
ns
ns
t24 CC Data hold after WR
t26 CC ALE rising edge after RD, WR
-10 + tF
Address/Unlatched CS hold
t28 CC
0 + tF
-5 + tF
-4 - tA
–
–
0 + tF
-5 + tF
-4 - tA
–
–
ns
ns
ns
after RD, WR(2)
Address/Unlatched CS hold
t28h CC
after WRH
ALE falling edge to Latched
CS
t38 CC
6 - tA
6 - tA
314/328
ST10F252M
Electrical Characteristics
Table 158. Demultiplexed bus timings (continued)
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Latched CS low to Valid Data
In
16.5 +
+ tC + 2tA
3TCL - 21 +
+ tC + 2tA
t39 SR
t41 CC
–
–
ns
ns
Latched CS hold after RD,
WR
2 + tF
–
–
TCL - 10.5 + tF
2TCL - 11 + 2tA
–
–
Address setup to RdCS,
t82 CC WrCS
(with RW-delay)
14 + 2tA
ns
ns
Address setup to RdCS,
t83 CC WrCS
2 + 2tA
–
TCL - 10.5 + 2tA
–
(no RW-delay)
RdCS to Valid Data In
(with RW-delay)
t46 SR
t47 SR
t48 CC
t49 CC
–
–
4 + tC
–
2TCL - 21 + tC
ns
ns
ns
ns
RdCS to Valid Data In
(no RW-delay)
16.5 + tC
–
3TCL - 21 + tC
RdCS, WrCS Low Time
(with RW-delay)
15.5 + tC
28 + tC
–
–
2TCL - 9.5 + tC
3TCL - 9.5 + tC
–
–
RdCS, WrCS Low Time
(no RW-delay)
t50 CC Data valid to WrCS
t51 SR Data hold after RdCS
10 + tC
0
–
–
2TCL - 15 + tC
0
–
–
ns
ns
Data float after RdCS
t53 SR
–
–
16.5 + tF
4 + tF
–
–
2TCL - 8.5 + tF
TCL - 8.5 + tF
ns
ns
(with RW-delay)(3)
Data float after RdS
t68 SR
(no RW-del)(3)
Address hold after
t55 CC
-8.5 + tF
2 + tF
–
–
-8.5 + tF
–
–
ns
ns
RdCS, WrCS
t57 CC Data hold after WrCS
TCL - 10.5 + tF
1. RW-delay and tA refer to the next following bus cycle.
2. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
315/328
Electrical Characteristics
ST10F252M
Figure 123. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE
CLKOUT
t26
t5
t9
ALE
CSx
t6
t41
t38
t
17
t41u
t39
t6
t28 (or t28h
)
t17
A23-A16
A15-A0 (P1)
BHE
Address
t18
Read cycle
Data bus (P0)
(D15-D8) D7-D0
ata in
t20
t21
t80
t
t15
t81
RD
t12
t13
Write cycle
Data bus (P0)
(D15-D8D7-D0
Data out
t80
t22
t24
t81
WR
WRL
WRH
t12
t13
316/328
ST10F252M
Electrical Characteristics
Figure 124. External memory cycle: demultiplexed bus, with/without r/w delay, extended ALE
CLKOUT
t5
t26
t16
ALE
t6
t38
t41
t17
t28
t39
CSx
t6
t17
t28
A23-A16
A15-A0 (P1)
BHE
Address
t18
Read cycle
Data bus (P0)
(D15-D8) D7-D0
Data in
t20
t80
t14
t15
t81
t21
RD
t12
t13
Write cycle
Data bus (P0)
Data out
(D15-D8) 7-D0
t80
t22
t24
t81
WR
WRL
WRH
t12
t13
317/328
Electrical Characteristics
ST10F252M
Figure 125. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE, r/w CS
CLKOUT
t26
t5
t16
ALE
t6
t55
t17
A23-A16
A15-A0 (P1)
BHE
Address
t5
Data in
Read cycle
Data bus (P0)
(D15-D8) D7-D0
t53
t68
t46
t47
t82
t83
RdCSx
t48
t49
Write cycle
Data bus (P0)
(D15-D8) D7-D0
Data out
t82
t50
t57
t83
WrCSx
t48
t49
318/328
ST10F252M
Electrical Characteristics
Figure 126. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS
CLKOUT
t5
t26
t16
ALE
t6
t55
t17
A23-A16
A15-A0 (P1)
BHE
Address
t5
Data in
Read cycle
Data bus (P0)
(D15-D8) D7-D0
t53
t46
t82
t47
t68
t83
RdCSx
t48
t49
Write cycle
Data bus (P0)
(D15-D8) D7-D0
Data out
t82
t83
t57
t50
WrCSx
t48
t49
319/328
Electrical Characteristics
ST10F252M
27.8.17 CLKOUT and READY
V
= 5V 10%, V = 0V, T = -40 to + 125°C, CL = 50pF
SS A
DD
Table 159. CLKOUT and READY timings
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
25
Max
25
Min
Max
t29 CC CLKOUT cycle time
t30 CC CLKOUT high time
2TCL
TCL - 3.5
TCL - 2.5
–
2TCL
ns
ns
ns
ns
ns
ns
9
10
–
–
t31 CC CLKOUT low time
–
4
–
4
t32 CC CLKOUT rise time
–
t33 CC CLKOUT fall time
–
4
–
4
t34 CC CLKOUT rising edge to ALE falling edge
-2 + tA
8 + tA
-2 + t
8 + tA
Synchronous READY setup time to
CLKOUT
t35 SR
17
2
–
–
17
2
–
–
ns
ns
Synchronous READY hold time after
CLKOUT
t36 SR
t37 SR Asynchronous READY low time
t58 SR Asynchronous READY setup time(1)
t59 SR Asynchronous READY hold time(1)
35
7
2
–
–
–
2TCL + 10
–
–
–
ns
ns
ns
17
2
Asynchronous READY hold time after RD,
t60 SR
0
2tA + tC + tF
0
2tA + tC + tF ns
WR high (Demultiplexed Bus)(2)
1. These timings are given for characterization purposes only, in order to assure recognition at a specific clock edge.
2. Demultiplexed bus is the worst cse. For multiplexed bus 2TCL are to be added to the maximum values. This adds even
more time for deactivating READ2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
320/328
ST10F252M
Electrical Characteristics
Figure 127. CLKOUT and READY
READY
wait state
Running cycle (1)
MUX / Tri-state (6)
t
t
t
32
33
31
CLKOUT
ALE
t
t
30
t
29
34
7)
RD, WR
2)
t
t
t
t
t
t
36
35
36
35
Synchronous
READY
3)
3)
58
t
t
t
(4)
60
58
59
59
Asynchronous
READY
(3)
(3)
37
(6)
(5)
t
1. Cycle as programmed, including MCTC wait stat(Example shows 0 MCTC WS).
2. The leading edge of the respective commaepends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
LOW at this sampling point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
CLKOUT (for example, because CLKOUT is not enabled), it must fulfill t37 in order to be safely
synchronized. Tis guaranteed, if READY is removed in response to the command (see Note 4).
6. Multiplexed s modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
may inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus
ithout MTTC wait state this delay is zero.
7. The next external bus cycle may start here.
27.8.18 High-speed synchronous serial interface (SSC) timing
27.8.18.1 Master mode
V
= 5V 10%, V = 0V, T = -40 to +125°C, C = 50pF
DD
SS
A
L
Table 160. SSC master mode timings
Maximum baudrate
6.6 Mbaud(1)
Variable baudrate
@ fCPU = 40 MHz
(<SSCBR> = 0002h)
(<SSCBR> = 0001h - FFFFh)
Symbol
Parameter
Unit
Min
Max
Min
Max
t300 CC SSC clock cycle time(2)
t301 CC SSC clock high time
150
63
150
–
8TCL
262144 TCL
–
ns
ns
t300 / 2 - 12
321/328
Electrical Characteristics
ST10F252M
Table 160. SSC master mode timings (continued)
Maximum baudrate
6.6 Mbaud(1)
@ fCPU = 40 MHz
(<SSCBR> = 0002h)
Variable baudrate
(<SSCBR> = 0001h - FFFFh)
Symbol
Parameter
Unit
Min
Max
Min
Max
t302 CC SSC clock low time
63
–
–
t300 / 2 - 12
–
ns
ns
ns
ns
ns
t303 CC SSC clock rise time
10
10
15
–
–
–
10
10
15
–
t304 CC SSC clock fall time
–
t305 CC Write data valid after shift edge
t306 CC Write data hold after shift edge(3)
–
–
-2
-2
Read data setup time before latch
t307p SR edge, phase error detection on
(SSCPEN = 1)
37.5
50
25
0
–
–
–
–
2TCL + 12.5
–
–
–
–
ns
ns
ns
ns
Read data hold time after latch
t308p SR edge, phase error detection on
(SSCPEN = 1)
4TCL
2TCL
0
Read data setup time before latch
t307 SR edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
t308 SR edge, phase error detection off
(SSCPEN = 0)
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only with CPU clock equal to (or lower than) 32 MHz.
2. Formula for SSC Clock Cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125ns (corresponding to 8Mbaud).
3. Partially tested, guaranteed design characterization.
Figure 128. SSC master timing
t300
t301
t302
(2)
(1)
SCLK
t304
t305
t303
t305
t305
t306
1st out bit
t307 t308
1st in bit
2nd out bit
Last out bit
t307 t308
Last in bit
MTSR
MRST
2nd In bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
322/328
ST10F252M
Electrical Characteristics
27.8.18.2 Slave mode
V
= 5V 10%, V = 0V, T = -40 to +125°C, C = 50pF
DD
SS
A
L
Table 161. SSC slave mode timings
Maximum baudrate
6.6 Mbaud(1)
Variable baudrate
@ fCPU = 40 MHz
(<SSCBR> = 0002h)
(<SSCBR> = 0001h - FFFFh)
Symbol
Parameter
Unit
Min
Max
Min
Max
t310 SR SSC clock cycle time(2)
t311 SR SSC clock high time
t312 SR SSC clock low time
150
63
63
–
150
–
8TCL
262144 TCL
ns
ns
ns
ns
ns
ns
ns
t310 / 2 - 12
–
–
t310 / 2 - 12
–
t313 SR SSC clock rise time
10
10
55
–
–
–
–
0
10
t314 SR SSC clock fall time
–
10
2TCL + 30
–
t315 CC Write data valid after shift edge
t316 CC Write data hold after shift edge
–
0
Read data setup time before latch
t317p SR edge, phase error detection on
(SSCPEN = 1)
62
87
6
–
–
–
–
4TCL + 12
6TCL + 12
6
–
–
–
–
ns
ns
ns
ns
Read data hold time after latch
t318p SR edge, phase error detection on
(SSCPEN = 1)
Read data setup time before latch
t317 SR edge, phase error detection off
(SSCPEN = 0)
Read data hold time ter latch
t318 SR edge, phase erroetection off
(SSCPEN 0)
31
2TCL + 6
1. When 40 MHz PU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after
checking hat resulting timings are suitable for the master).
2. Forma for SSC Clock Cycle time: t310 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).
323/328
Electrical Characteristics
Figure 129. SSC slave timing
t310
ST10F252M
t311
t312
(2)
(1)
SCLK
MRST
MTSR
t314
t315
t313
t316
t315
t315
1st out bit
t317 t318
2nd out bit
2nd in bit
Last out bit
t317 t318
1st in bit
Last in bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure s the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idlock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
324/328
ST10F252M
Package information
28
Package information
®
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK
®
packages. ECOPACK packages are lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 130.LQFP100 mechanical data and package dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
1.600
TYP. MAX.
0.0630
A
A1
A2
b
0.050
0.150 0.0020
0.0059
1.350 1.400 1.450 0.0531 0.0551 0.0571
0.170 0.220 0.270 0.0067 0.0087 0.0106
c
0.090
0.200 0.0035
0.0079
D
15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3
E
12.000
0.4724
15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5559
E3
e
12.000
0.500
0.4724
0.0197
L
0.450 0.600 0.750 0.0177 0.0236 0.0295
1.000 0.0394
L1
K
LQFP100 (14x14x1.40mm)
Low profile Quad Flat Package
0˚ (min.), 3.5˚ (typ.), 7˚(max.)
0.080
ccc
0.003
0086901 D
325/328
Ordering Information
ST10F252M
29
Ordering Information
Table 162. Device summary
Temperature
range (°C)
CPU frequency
range (MHz)
Order code
Package
Packing
ST10F252M-4T3
ST10F252M-4TR3
Tray
LQFP100
-40 to +125
1 to 40
Tape and reel
326/328
ST10F252M
Revision history
30
Revision history
Table 163. Document revision history
Date
Revision
Changes
7-Feb-2008
1
Initial release
327/328
ST10F252M
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and servis described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services decribed herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a lse grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained ther
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR RRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PRERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST poducts with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warry granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2008 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
328/328
相关型号：
ST10F252M-4TR3
16-BIT, FLASH, 40MHz, RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100
STMICROELECTR
ST10F269-DPR
16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP144, 28 X 28 MM, PLASTIC, QFP-144
STMICROELECTR
ST10F269Z1Q3
16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM
STMICROELECTR
ST10F269Z1Q6
16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM
STMICROELECTR
ST10F269Z1T3
16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明