ST10F273MR-4T3 [STMICROELECTRONICS]
MICROCONTROLLER;
| 型号： | ST10F273MR-4T3 |
| 厂家： | 
ST |
| 描述： | MICROCONTROLLER 微控制器 外围集成电路 |
| 文件： | 总186页 (文件大小：2034K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST10F273M
16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
Datasheet − production data
Features
■ High performance 16-bit CPU with DSP
functions
– 50ns instruction cycle time at 40 MHz max
CPU clock
– Multiply/accumulate unit (MAC) 16 x 16-bit
multiplication, 40-bit accumulator
PQFP144 (28 x 28 x 3.4mm)
LQFP144 (20 x 20 x 1.4mm)
(Low Profile Quad Flat Package)
(Plastic Quad Flat Package)
■ 24-channel A/D converter
– Enhanced boolean bit manipulations
– Single-cycle context switching support
– 16-channel 10-bit, accuracy +/-2 LSB
– 8-channel 10-bit, accuracy +/-5 LSB
– 4.85µs Minimum conversion time
■ Memory organization
– 512 Kbyte on-chip Flash memory single
voltage with erase/program controller (full
performance, 32-bit fetch)
■ Serial channels
– 2 synch. / asynch. serial channels
– 2 high-speed synchronous channels
– 100 K erasing/programming cycles
2
– I C standard interface
– Up to 16 Mbyte linear address space for
2
■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN
code and data (5 Mbytes with CAN or I C)
buses (64 or 2x32 messages, C-CAN version)
– 2 Kbyte on-chip internal RAM (IRAM)
■ Fail-safe protection
– 34 Kbyte on-chip extension RAM (XRAM)
– Programmable watchdog timer
– Oscillator watchdog
– Programmable external bus configuration
and characteristics for different address
ranges
■ On-chip bootstrap loader
– 5 programmable chip-select signals
■ Clock generation
– Hold-acknowledge bus arbitration support
– On-chip PLL and 4 to 12 MHz oscillator
– Direct or prescaled clock input
■ Interrupt
– 8-channel peripheral event controller for
single cycle interrupt driven data transfer
– 16-priority-level interrupt system with 56
sources, sampling rate down to 25ns
■ Real time clock and 32 kHz on-chip oscillator
■ Up to 111 general purpose I/O lines
– Individually programmable as input, output
or special function
– Programmable threshold (hysteresis)
■ Timers
– 2 multifunctional general purpose timer
units with 5 timers
■ Idle, power down and standby modes
■ Single voltage supply: 5 V 10ꢀ (embedded
■ Two 16-channel capture / compare units
■ 4-channel PWM unit + 4-channel XPWM
regulator for 1.8 V core supply)
■ Temperature range: -40°C to 125°C
September 2013
Doc ID 13453 Rev 4
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This is information on a product in full production.
www.st.com
1
Contents
ST10F273M
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Special characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.1
1.2.2
X-Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Improved supply ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
3
4
5
Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
5.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.1
5.2.2
5.2.3
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3
5.4
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Flash control registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
Flash control register 0 low (FCR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Flash control register 0 high (FCR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash control register 1 low (FCR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Flash control register 1 high (FCR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Flash data register 0 low (FDR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Flash data register 0 high (FDR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Flash data register 1 low (FDR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Flash data register 1 high (FDR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Flash address register low (FARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4.10 Flash address register high (FARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4.11 Flash error register (FER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4.12 XFlash interface control dummy register (XFICR) . . . . . . . . . . . . . . . . . 40
5.5
Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.5.1
Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
5.5.9
Flash non-volatile write protection I register low (FNVWPIRL) . . . . . . . 41
Flash non-volatile write protection I register high (FNVWPIRH) . . . . . . 42
Flash non-volatile write protection I register low Mirror (FNVWPIRL-m) 42
Flash non-volatile write protection I register high Mirror (FVWPIRH-m) 42
Flash non-volatile access protection register 0 (FNVAPR0) . . . . . . . . . 43
Flash non-volatile access protection register 1 low (FNVAPR1L) . . . . . 43
Flash non-volatile access protection register 1 high (FNVAPR1H) . . . . 44
Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.10 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.5.11 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.6
5.7
Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6
Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1
6.2
6.3
Selection among user-code, standard or selective bootstrap . . . . . . . . . . 49
Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . . 50
6.3.1
6.3.2
6.3.3
Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.1
7.2
7.3
Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8
9
External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.1
9.2
X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10
11
Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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11.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12
13
Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.2 I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14
15
A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
15.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 74
15.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
15.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
15.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 75
16
17
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
17.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
17.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
17.2.1 Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.2.2 Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17.2.3 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
18
19
20
Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
20.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21.2.1 Protected power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
21.2.2 Interruptible power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
21.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
21.3.1 Entering standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
21.3.2 Exiting standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
21.3.3 Real time clock and standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
21.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
22
23
Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
23.2 X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
24
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
24.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
24.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
24.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
24.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
24.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
24.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
24.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
24.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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24.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
24.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
24.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
24.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
24.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
24.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
24.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
24.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
24.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
24.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
24.8.7 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
24.8.8 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
24.8.9 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
24.8.10 PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
24.8.11 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
24.8.12 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
24.8.13 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
24.8.14 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
24.8.15 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
24.8.16 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
24.8.17 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
24.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
24.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
24.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 177
25
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
25.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
25.2 PQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
25.3 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
26
27
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Summary of IFlash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash module address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Flash module sectorization (read operations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Flash module sectorization (write operations, or ROMS1 = ‘1’) . . . . . . . . . . . . . . . . . . . . . 29
Flash control registers summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FCR0L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FCR0H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FCR1L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FCR1H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Bank (BxS) and sectors (BxFy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FDR0L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FDR0H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FDR1L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FDR1H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FARL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FARH register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FER register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FNVWPIRL register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FNVWPRIH register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FNVAPR0 register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FNVAPR1L register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FNVAPR1H register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ST10F273M boot mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MAC instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 63
GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 64
GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 66
PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 68
ASC asynchronous baudrates by reload value and deviation errors . . . . . . . . . . . . . . . . . 74
ASC synchronous baudrates by reload value and deviation errors . . . . . . . . . . . . . . . . . . 75
SSC synchronous baudrate and reload values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
WDTREL reload value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 107
Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
List of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
List of XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
List of Flash control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
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List of tables
ST10F273M
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
IDMANUF register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
IDCHIP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
IDMEM register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
IDPROG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Flash characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Flash data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
PLL characteristics (V = 5V 10ꢀ, V = 0V, T = -40°C to +125°C) . . . . . . . . . . . . 157
DD
SS
A
Main oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
32 kHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Minimum values of negative resistance (module) for 32 kHz oscillator . . . . . . . . . . . . . . 159
External clock drive XTAL1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Multiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
SSC slave mode timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
PQFP144 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
ST10F273M logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ST10F273M memory mapping (XADRS3 = 800Bh - reset value) . . . . . . . . . . . . . . . . . . . 25
ST10F273M memory mapping (XADRS3 = E009h - user programmed value) . . . . . . . . . 26
Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Write operation control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 11. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 12. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 13. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 14. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 79
Figure 15. Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 79
Figure 16. Connection to two different CAN buses (for example for gateway application) . . . . . . . . . 80
Figure 17. Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . . 80
Figure 18. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 19. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 20. Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 21. Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 22. Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 23. Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 24. Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 25. Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 26. SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 27. SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 28. SW / WDT bidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 29. SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 30. SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET . . . . . . . . . . . . . . . . 101
Figure 31. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 32. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 33. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 34. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 104
Figure 35. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 105
Figure 36. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 37. External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 38. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 39. Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 137
Figure 40. A/D conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 41. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 42. Charge-sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 43. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 44. Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 45. Float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 46. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 47. ST10F273M PLL jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 48. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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Figure 49. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 50. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 51. External memory cycle: multiplexed bus, with/ without read/ write delay, normal ALE. . . 163
Figure 52. External memory cycle: multiplexed bus, with/ without read/ write delay, extended ALE. 164
Figure 53. External memory cycle: multiplexed bus, with/ without read/ write delay, normal ALE,
read/ write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 54. External memory cycle: multiplexed bus, with/ without read/ write delay, extended ALE,
read/ write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 55. External memory cycle: demultiplexed bus, with/ without read/ write delay, normal ALE. 169
Figure 56. External memory cycle: demultiplexed bus, with/ without read/ write delay, extended ALE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 57. External memory cycle: demultiplexed bus, with/ without read/ write delay, normal ALE,
read/ write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 58. External memory cycle: demultiplexed bus, without read/ write delay, extended ALE,
read/ write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 59. CLKOUT and READY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 60. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 61. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 62. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 63. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 64. PQFP144 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 65. LQFP144 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10/186
Doc ID 13453 Rev 4
ST10F273M
Introduction
1
Introduction
1.1
Description
®
The ST10F273M device is a new derivative of the STMicroelectronics ST10 family of 16-bit
single-chip CMOS microcontrollers.
The ST10F273M combines high CPU performance (up to 20 million instructions per second)
with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip
high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation
via PLL.
The ST10F273M is processed in 0.18mm CMOS technology. The MCU core and the logic is
supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V
supply and I/Os work at 5V.
The ST10F273M is an optimized version of the ST10F273E, upward compatible with the
following set of differences:
●
Maximum CPU frequency is 40 MHz
●
A single bank of IFlash has been implemented but the programming interface has been
kept compatible with the ST10F273E
●
●
●
Identification registers: the IDMEM register reflects the Flash type difference and allows
to differentiate the two devices by software
Improved EMC behavior thanks to the introduction of an internal RC filter on the 5V for
the ballast transistors
The clock to the X-Peripherals is gated: X-Peripheral not used will not get the clock in
order to reduce the power consumption.
1.2
Special characteristics
1.2.1
X-Peripheral clock gating
This new feature have been implemented on the ST10F273M: once the EINIT instruction
has been executed, only the X-Peripherals enabled in the XPERCON register will be
clocked.
The new feature allows to reduce the power consumption and also should improve the
emissions as it avoids to propagate useless clock signals across the device.
1.2.2
Improved supply ring
An RC filter has been introduced in the 5V power supply ring of the ballast transistor. In
addition, the supply rings for the internal voltage regulators and the IOs have been split.
These two modifications should improve the behavior of the device regarding conducted
emissions.
Doc ID 13453 Rev 4
11/186
Introduction
ST10F273M
Figure 1.
ST10F273M logic symbol
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Doc ID 13453 Rev 4
ST10F273M
Pin data
2
Pin data
Figure 2.
Pin configuration (top view)
P6.0 / CS0
P6.1 / CS1
P6.2 / CS2
P6.3 / CS3
P6.4 / CS4
1
2
3
4
5
6
7
8
9
108 P0H.0 / AD8
107 P0L.7 / AD7
106 P0L.6 / AD6
105 P0L.5 / AD5
104 P0L.4 / AD4
103 P0L.3 / AD3
102 P0L.2 / AD2
101 P0L.1 / AD1
100 P0L.0 / AD0
P6.5 / HOLD / SCLK1
P6.6 / HLDA / MTSR1
P6.7 / BREQ / MRST1
P8.0 / XPOUT0 / CC16IO
P8.1 / XPOUT1 / CC17IO 10
P8.2 / XPOUT2 / CC18IO 11
P8.3 / XPOUT3 / CC19IO 12
P8.4 / CC20IO 13
P8.5 / CC21IO 14
P8.6 / RxD1 / CC22IO 15
P8.7 / TxD1 / CC23IO 16
VDD 17
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
EA / VSTBY
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7 / A23 / CAN2_TxD / SDA
VSS 18
P4.6 / A22 / CAN1_TxD / CAN2_TxD
P4.5 / A21 / CAN1_RxD / CAN2_RxD
P4.4 / A20 / CAN2_RxD / SCL
P4.3 / A19
ST10F273M
P7.0 / POUT0 19
P7.1 / POUT1 20
P7.2 / POUT2 21
P7.3 / POUT3 22
P7.4 / CC28IO 23
P7.5 / CC29IO 24
P7.6 / CC30IO 25
P7.7 / CC31IO 26
P5.0 / AN0 27
P4.2 / A18
P4.1 / A17
P4.0 / A16
RPD
VSS
VDD
P5.1 / AN1 28
P3.15 / CLKOUT
P3.13 / SCLK0
P3.12 / BHE / WRH
P3.11 / RxD0
P5.2 / AN2 29
P5.3 / AN3 30
P5.4 / AN4 31
P5.5 / AN5 32
P3.10 / TxD0
P5.6 / AN6 33
P3.9 / MTSR0
P3.8 / MRST0
P3.7 / T2IN
P5.7 / AN7 34
P5.8 / AN8 35
P5.9 / AN9 36
P3.6 / T3IN
Doc ID 13453 Rev 4
13/186
Pin data
Table 1.
ST10F273M
Pin description
Symbol
Pin
Type
Function
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 6 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The
following Port 6 pins have alternate functions:
1 - 8
I/O
1
...
5
O
P6.0
CS0
Chip select 0 output
... ...
...
...
O
I
P6.4
CS4
Chip select 4 output
P6.0 - P6.7
P6.5
P6.6
P6.7
HOLD
SCLK1
HLDA
MTSR1
BREQ
MRST1
External master hold request input
SSC1: master clock output / slave clock input
Hold acknowledge output
6
7
8
I/O
O
I/O
O
SSC1: master-transmitter / slave-receiver O/I
Bus request output
I/O
SSC1: master-receiver / slave-transmitter I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
9-16
I/O high impedance state. Port 8 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS).
The following Port 8 pins have alternate functions:
I/O P8.0
O
CC16IO
XPWM0
...
CAPCOM2: CC16 capture input / compare output
PWM1: channel 0 output
9
...
... ...
I/O P8.3
O
...
CC19IO
XPWM0
CC20IO
CC21IO
CC22IO
RxD1
CAPCOM2: CC19 capture input / compare output
PWM1: channel 3 output
P8.0 - P8.7
12
13
14
I/O P8.4
I/O P8.5
I/O P8.6
I/O
CAPCOM2: CC20 capture input / compare output
CAPCOM2: CC21 capture input / compare output
CAPCOM2: CC22 capture input / compare output
ASC1: Data input (Asynchronous) or I/O (Synchronous)
CAPCOM2: CC23 capture input / compare output
ASC1: Clock / Data output (Asynchronous/Synchronous)
15
16
I/O P8.7
O
CC23IO
TxD1
14/186
Doc ID 13453 Rev 4
ST10F273M
Pin data
Table 1.
Symbol
Pin description (continued)
Pin
Type
Function
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
19-26
I/O high impedance state. Port 7 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS).
The following Port 7 pins have alternate functions:
19
...
O
P7.0
POUT0
...
PWM0: channel 0 output
P7.0 - P7.7
... ...
...
22
23
...
O
P7.3
POUT3
CC28IO
...
PWM0: channel 3 output
I/O P7.4
... ...
I/O P7.7
CAPCOM2: CC28 capture input / compare output
...
26
CC31IO
CAPCOM2: CC31 capture input / compare output
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can
be the analog input channels (up to 16) for the A/D converter, where P5.x equals
ANx (Analog input channel x), or they are timer inputs. The input threshold of
Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate
functions:
27-36
39-44
I
I
39
40
41
42
43
44
I
I
I
I
I
I
P5.10 T6EUD
P5.11 T5EUD
P5.12 T6IN
GPT2: timer T6 external up/down control input
GPT2: timer T5 external up/down control input
GPT2: timer T6 count input
P5.0 - P5.9
P5.10 - P5.15
P5.13 T5IN
GPT2: timer T5 count input
P5.14 T4EUD
P5.15 T2EUD
GPT1: timer T4 external up/down control input
GPT1: timer T2 external up/down control input
16-bit bidirectional I/O port, bit-wise programmable for input or output via
direction bit. Programming an I/O pin as input forces the corresponding output
I/O driver to high impedance state. Port 2 outputs can be configured as push-pull or
open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS).
The following Port 2 pins have alternate functions:
47-54
57-64
47
...
I/O P2.0
... ...
CC0IO
...
CAPCOM: CC0 capture input/compare output
...
P2.0 - P2.7
P2.8 - P2.15
54
I/O P2.7
CC7IO
CC8IO
EX0IN
...
CAPCOM: CC7 capture input/compare output
CAPCOM: CC8 capture input/compare output
Fast external interrupt 0 input
...
I/O
P2.8
I
57
...
... ...
I/O
CC15IO
CAPCOM: CC15 capture input/compare output
Fast external interrupt 7 input
CAPCOM2: timer T7 count input
64
I
I
P2.15 EX7IN
T7IN
Doc ID 13453 Rev 4
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Pin data
Table 1.
ST10F273M
Pin description (continued)
Symbol
Pin
Type
Function
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
65-70,
73-80,
81
I/O output via direction bit. Programming an I/O pin as input forces the
I/O corresponding output driver to high impedance state. Port 3 outputs can be
I/O configured as push-pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or CMOS). The following Port 3 pins have alternate functions:
65
66
67
68
69
70
73
74
75
76
77
78
I
O
I
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
T0IN
CAPCOM1: timer T0 count input
T6OUT
CAPIN
T3OUT
T3EUD
T4IN
GPT2: timer T6 toggle latch output
GPT2: register CAPREL capture input
O
I
GPT1: timer T3 toggle latch output
GPT1: timer T3 external up/down control input
GPT1; timer T4 input for count/gate/reload/capture
GPT1: timer T3 count/gate input
I
P3.0 - P3.5
P3.6 - P3.13,
P3.15
I
T3IN
I
T2IN
GPT1: timer T2 input for count/gate/reload / capture
SSC0: master-receiver/slave-transmitter I/O
SSC0: master-transmitter/slave-receiver O/I
ASC0: clock / data output (asynchronous/synchronous)
ASC0: data input (asynchronous) or I/O (synchronous)
External memory high byte enable signal
External memory high byte write strobe
SSC0: master clock output / slave clock input
I/O P3.8
I/O P3.9
MRST0
MTSR0
O
P3.10 TxD0
I/O P3.11 RxD0
BHE
79
O
P3.12
WRH
80
81
I/O P3.13 SCLK0
System clock output (programmable divider on CPU
clock)
O
P3.15 CLKOUT
16/186
Doc ID 13453 Rev 4
ST10F273M
Pin data
Table 1.
Symbol
Pin description (continued)
Pin
Type
Function
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. The input threshold is
85-92
I/O selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured
as push-pull or open drain drivers.
In case of an external bus configuration, Port 4 can be used to output the
segment address lines:
85
86
87
88
O
O
O
O
O
I
P4.0
P4.1
P4.2
P4.3
A16
A17
A18
A19
A20
Segment address line
Segment address line
Segment address line
Segment address line
Segment address line
89
90
91
P4.4
P4.5
P4.6
P4.7
CAN2_RxD CAN2: receive data input
P4.0 –P4.7
I/O
O
I
SCL
A21
I2C Interface: serial clock
Segment address line
CAN1_RxD CAN1: receive data input
CAN2_RxD CAN2: receive data input
I
O
O
O
O
O
I/O
A22
Segment address line
CAN1_TxD CAN1: transmit data output
CAN2_TxD CAN2: transmit data output
A23
Most significant segment address line
92
95
96
CAN2_TxD CAN2: transmit data output
SDA
I2C Interface: serial data
External memory read strobe. RD is activated for every external instruction or
data read access.
RD
O
External memory write strobe. In WR-mode this pin is activated for every
external data write access. In WRL mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in the SYSCON register for mode selection.
WR/WRL
O
Ready input. The active level is programmable. When the ready function is
enabled, the selected inactive level at this pin, during an external memory
access, will force the insertion of waitstate cycles until the pin returns to the
selected active level.
READY/
READY
97
98
I
Address latch enable output. In case of use of external addressing or of
multiplexed mode, this signal is the latch command of the address lines.
ALE
O
Doc ID 13453 Rev 4
17/186
Pin data
Table 1.
ST10F273M
Pin description (continued)
Symbol
Pin
Type
Function
External access enable pin.
A low level applied to this pin during and after Reset forces the ST10F273M to
start the program from the external memory space. A high level forces
ST10F273M to start in the internal memory space. This pin is also used (when
Standby mode is entered, that is ST10F273M under reset and main VDD turned
off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference
voltage for the low-power embedded voltage regulator which generates the
internal 1.8V supply for the RTC module (when not disabled) and to retain data
inside the Standby portion of the XRAM (16 Kbyte).
EA / VSTBY
99
I
It can range from 4.5 to 5.5V (6V for a reduced amount of time during the device
life, 4.0V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In
running mode, this pin can be tied low during reset without affecting 32 kHz
oscillator, RTC and XRAM activities, since the presence of a stable VDD
guarantees the proper biasing of all those modules.
Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. The input threshold of
Port 0 is selectable (TTL or CMOS).
In case of an external bus configuration, PORT0 serves as the address (A) and
as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus
in demultiplexed bus modes.
Demultiplexed bus modes
P0L.0 -P0L.7, 100-107,
P0H.0 108,
P0H.1 - P0H.7 111-117
Data path width
P0L.0 – P0L.7:
P0H.0 – P0H.7:
8-bit
16-bit
I/O
D0 – D7
I/O
D0 - D7
D8 - D15
Multiplexed bus modes
Data path width
P0L.0 – P0L.7:
P0H.0 – P0H.7:
8-bit
16-bit
AD0 – AD7
A8 – A15
AD0 - AD7
AD8 - AD15
Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the
corresponding output driver to high impedance state. PORT1 is used as the 16-
bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is
configured such the demultiplexed mode is selected, the pis of PORT1 are not
available for general purpose I/O function. The input threshold of Port 1 is
selectable (TTL or CMOS).
118-125
128-135
I/O
The pins of P1L also serve as the additional (up to 8) analog input channels for
the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x
+ 16). This additional function have higher priority on demultiplexed bus function.
The following PORT1 pins have alternate functions:
P1L.0 - P1L.7
P1H.0 - P1H.7
132
133
134
135
I
I
I
I
P1H.4 CC24IO
P1H.5 CC25IO
P1H.6 CC26IO
P1H.7 CC27IO
CAPCOM2: CC24 capture input
CAPCOM2: CC25 capture input
CAPCOM2: CC26 capture input
CAPCOM2: CC27 capture input
18/186
Doc ID 13453 Rev 4
ST10F273M
Pin data
Table 1.
Symbol
Pin description (continued)
Pin
Type
Function
XTAL1
XTAL2
138
137
I
XTAL1 Main oscillator amplifier circuit and/or external clock input.
XTAL2 Main oscillator amplifier circuit output.
O
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in
the AC Characteristics must be observed.
XTAL3
XTAL4
143
144
I
XTAL3 32 kHz oscillator amplifier circuit input
XTAL4 32 kHz oscillator amplifier circuit output
O
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32
in RTCCON register shall be set. 32 kHz oscillator can only be driven by an
external crystal, and not by a different clock source.
Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the ST10F273M. An
internal pull-up resistor permits power-on reset using only a capacitor connected
to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in
SYSCON register), the RSTIN line is pulled low for the duration of the internal
reset sequence.
RSTIN
140
141
I
Internal Reset Indication Output. This pin is driven to a low level during
hardware, software or watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
RSTOUT
O
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power down) instruction is executed, the NMI pin must be low in
order to force the ST10F273M to go into power down mode. If NMI is high and
PWDCFG = ‘0’, when PWRDN is executed, the part will continue to run in
normal mode.
NMI
142
I
If not used, pin NMI should be pulled high externally.
VAREF
VAGND
37
38
-
-
A/D converter reference voltage and analog supply
A/D converter reference and analog ground
Timing pin for the return from interruptible power down mode and synchronous /
asynchronous reset selection.
RPD
84
-
17, 46,
72,82,93,
109, 126,
136
Digital supply voltage = + 5V during normal operation, idle and power down
modes.
It can be turned off when Standby RAM mode is selected.
VDD
-
18,45,
55,71,
83,94,
110, 127,
139
VSS
-
-
Digital ground
1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF)
must be connected between this pin and nearest VSS pin.
V18
56
Doc ID 13453 Rev 4
19/186
Functional description
ST10F273M
3
Functional description
The architecture of the ST10F273M combines advantages of both RISC and CISC
processors and an advanced peripheral subsystem. The block diagram gives an overview of
the different on-chip components and the high bandwidth internal bus structure of the
ST10F273M.
Figure 3.
Block diagram
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Doc ID 13453 Rev 4
ST10F273M
Memory organization
4
Memory organization
The memory space of the ST10F273M is configured in a unified memory architecture. Code
memory, data memory, registers and I/O ports are organized within the same linear address
space of 16 Mbytes. The entire memory space can be accessed Bytewise or Wordwise.
Particular portions of the on-chip memory have additionally been made directly bit
addressable.
IFlash: 512 Kbytes of on-chip Flash memory implemented as a unique Bank (Bank0).
Bank0 is divided in 12 blocks (B0F0...B0F11).
Note:
Read-while-write operations are not allowed: Write commands must be executed from a non
IFlash memory area (on-chip RAM or external memory).
When Bootstrap mode is selected, the Test-Flash Block B0TF (4 Kbytes) appears at
address 00’0000h: Refer to the device User Manual for more details on the memory
mapping in Bootstrap mode. The summary of address range for IFlash is the following:
Table 2.
Summary of IFlash address range
Blocks
User mode
Size (bytes)
B0TF
B0F0
B0F1
B0F2
B0F3
B0F4
B0F5
B0F6
B0F7
B0F8
B0F9
Not visible
4 K
8 K
00’0000h - 00’1FFFh
00’2000h - 00’3FFFh
00’4000h - 00’5FFFh
00’6000h - 00’7FFFh
01’8000h - 01’FFFFh
02’0000h - 02’FFFFh
03’0000h - 03’FFFFh
04’0000h - 04’FFFFh
05’0000h - 05’FFFFh
06’0000h - 06’FFFFh
07’0000h - 07’FFFFh
08’0000h - 08’FFFFh
8 K
8 K
8 K
32 K
64 K
64 K
64 K
64 K
64 K
64 K
64 K
B1F0 / B0F10 (1)
B1F1 / B0F11 (1)
Note:
A single Flash bank is implemented on the ST10F273M compared to the ST10F273E. The
last two sectors (B0F10 and B0F11) can be seen as the Bank1 of the ST10F273E in order
to maintain the compatibility with the existing Flash programming drivers. For this, the
control and status bit of the blocks B0F10 and B0F11 have been duplicated to be usable as
blocks B1F0 and B1F1 of the ST10F273E.
XFLASH / Flash Control Registers: Address range 0E’0000h-0E’FFFFh is reserved for
the Flash Control Register and other internal service memory space used by the Flash
Program/Erase Controller. XFLASHEN bit in XPERCON register must be set to access the
Flash Control Register. Note that when Flash Control Registers are not accessible, no
program/erase operations are possible. The Flash Control Registers are accessed in 16-bit
demultiplexed bus-mode without read/write delay. Byte and word accesses are allowed.
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Memory organization
ST10F273M
IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0
to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
XRAM: 34 Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage for
data, user stack and code.
The XRAM is divided into two areas, the first 2 Kbytes named XRAM1 and the second
32 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an
external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay
(50ns access at 40 MHz CPU clock). Byte and Word accesses are allowed.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set.
If XRAM1EN or XPEN is cleared, then any access in the address range 00’E000h -
00’E7FFh will be directed to external memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx register.
The XRAM2 address range is F’0000h - F’7FFFFh if XPEN (bit 2 of SYSCON register), and
XRAM2EN (bit 3 of XPERCON register) are set.
If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be
directed to external memory interface, using the BUSCONx register corresponding to
address matching ADDRSELx register.
The 16 kbytes lower portion of the XRAM2 (address range F’0000h - F’3FFFFh) represents
also the Standby RAM, which can be maintained biased through EA / V
pin when the
STBY
main supply V is turned off.
DD
As the XRAM appears like external memory, it cannot be used as system stack or as
register banks. The XRAM is not provided for single bit storage and therefore is not bit
addressable.
SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function
register (SFR) areas. SFRs are Wordwide registers which are used to control and to monitor
the function of the different on-chip units.
CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. The
CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 100ns at 40 MHz CPU clock. No tri-state wait states are used.
CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The
CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed
addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an
access time of 100ns at 40 MHz CPU clock. No tri-state wait states are used.
Note:
If one or the two CAN modules are used, Port 4 cannot be programmed to output all eight
segment address lines. Thus, only four segment address lines can be used, reducing the
external memory space to 5 Mbytes (1 Mbyte per CS line).
RTC: Address range 00’ED00h - 00’EDFFh is reserved for the RTC Module access. The
RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON
register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
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ST10F273M
Memory organization
PWM1: Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 Module access.
The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the
XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16-
bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns
at 40 MHz CPU clock. No tristate waitstate is used. Only word access is allowed.
ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The
ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON
register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The
SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON
register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz
CPU clock. No tristate waitstate is used.
I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is
enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register.
Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word
accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock.
No tristate waitstate is used.
X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set
of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON
register and bit 10 of the XPERCON register. Accesses to this additional features use
demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two
waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used.
The following set of features are provided:
●
●
●
●
●
●
●
●
CLKOUT programmable divider
XBUS interrupt management registers
ADC multiplexing on P1L register
Port1L digital disable register for extra ADC channels
CAN2 multiplexing on P4.5/P4.6
CAN1-2 main clock prescaler
Main Voltage Regulator disable for power-down mode
TTL / CMOS threshold selection for Port0, Port1 and Port5
In order to meet the needs of designs where more memory is required than is provided on
chip, up to 16 Mbytes of external memory can be connected to the microcontroller.
Visibility of XBUS peripherals
In order to keep the ST10F273M compatible with the ST10F168 / ST10F269, the XBUS
peripherals can be selected to be visible on the external address / data bus. Different bits for
X-Peripheral enabling in XPERCON register must be set. If these bits are cleared before the
global enabling with XPEN bit in SYSCON register, the corresponding address space, port
pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and
not available. Refer to Chapter 23: Register set on page 115.
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Memory organization
ST10F273M
XPERCON and X-Peripheral clock gating
As already mentioned, the XPERCON register must be programmed to enable the single
XBus modules separately. The XPERCON is a read/write ESFR register.
The new feature of Clock Gating has been implemented by means of this register: Once the
EINIT instruction has been executed, all the peripherals (except RAMs and XMISC) not
enabled in the XPERCON register are not be clocked. The clock gating can reduce power
consumption and improve EMI when the user does not use all X-Peripherals.
Note:
When the clock has been gated in the disabled peripherals, no Reset will be raised once the
EINIT instruction has been executed.
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Doc ID 13453 Rev 4
ST10F273M
Figure 4.
Memory organization
ST10F273M memory mapping (XADRS3 = 800Bh - reset value)
Code
Data
Page
Data
Page
Code
Segment
Segment
FF FFFF
255
1023
11 FFFF
67
66
65
64
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
17
00 FFFF
00 FE00
00 FDFF
SFR
512
2K
11 0000
10 FFFF
16
X-Peripherals (2Kbyte)
10 0000
0F FFFF
Reserved
I-RAM
15
00 F000
XRAM2
32K
64K
00 EFFF
(StandBy)
0F 0000
0E FFFF
XCAN1
XCAN2
256
256
256
256
256
256
256
256
Flash
Control
00 F600
00 F5FF
00 EF00
00 EEFF
14
Registers
1K
Reserved
ESFR
0E 0000
0D FFFF
00 F200
00 F1FF
00 F000
00 EFFF
00 EE00
00 EDFF
Reserved
13
512
0D 0000
0C FFFF
XRTC
XPWM
XCAN1
XCAN2
XRTC
XPWM
256
256
256
256
00 ED00
00 ECFF
Reserved
12
0C 0000
0B FFFF
00 EC00
00 EBFF
XMiscellaneous 256
XI2C
XASC
XSSC
256
256
256
Reserved
11
XMiscellaneous
XI2C
0B 0000
0A FFFF
00 EB00
00 EAFF
00 E800
00 E7FF
Reserved
10
0A 0000
09 FFFF
00 EA00
00 E9FF
XRAM1
2K
Re
served
XASC
XSSC
9
00 E900
00 E8FF
09 0000
08 FFFF
00 E000
00 DFFF
B0F11
8
(B1F1)
00 E800
00 E7FF
08 0000
07 FFFF
B0F10
7
(B1F0)
07 0000
06 FFFF
B0F9
B0F8
B0F7
B0F6
B0F5
6
06 0000
05 FFFF
5
05 0000
04 FFFF
4
Ext. Memory
8K
04 0000
03 FFFF
3
03 0000
02 FFFF
2
8
7
6
5
4
3
2
02 0000
01 FFFF
B0F4
Address Area defined by
XADRS3 by default after reset
1
Ext. Mem
01 0000
00 FFFF
Ext. Mem
B0F3
0
0
0
1
0
00 0000
B0F2
B0F1
B0F0
00 C000
00 0000
Flash + XRAM - 1Mbyte
Data Page 3 (Segment 0) - 16Kbyte
16 MB
Doc ID 13453 Rev 4
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Memory organization
ST10F273M
Figure 5.
ST10F273M memory mapping (XADRS3 = E009h - user programmed value)
Code
Data
Page
Data
Page
Code
Segment
Segment
FF FFFF
255
1023
11 FFFF
67
66
65
64
67
66
65
64
63
17
00 FFFF
00 FE00
00 FDFF
SFR
512
2K
11 0000
10 FFFF
16
X-Peripherals (2Kbyte)
10 0000
0F FFFF
Reserved
I-RAM
62
61
32K
15
00 F000
XRAM2
00 EFFF
60
59
32K
(StandBy)
0F 0000
0E FFFF
XCAN1
XCAN2
256
256
256
Flash
Control
00 F600
00 F5FF
58
57
64K
00 EF00
00 EEFF
14
Registers
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Reserved
ESFR
1K
0E 0000
0D FFFF
00 F200
00 F1FF
00 F000
00 EFFF
00 EE00
00 EDFF
13
512
0D 0000
0C FFFF
XRTC
XPWM
XCAN1
XCAN2
XRTC
256
256
256
256
00 ED00
00 ECFF
12
256
256
256
256
256
XPWM
0C 0000
0B FFFF
Ext
00 EC00
00 EBFF
XMiscellaneous 256
XI2C
XASC
XSSC
256
256
256
11
Memory
XMiscellaneous
XI2C
0B 0000
0A FFFF
00 EB00
00 EAFF
00 E800
00 E7FF
10
0A 0000
09 FFFF
00 EA00
00 E9FF
XRAM1
2K
XASC
XSSC
9
00 E900
00 E8FF
09 0000
08 FFFF
00 E000
00 DFFF
B0F11
8
(B1F1)
00 E800
00 E7FF
08 0000
07 FFFF
B0F10
7
(B1F0)
07 0000
06 FFFF
B0F9
B0F8
B0F7
B0F6
B0F5
6
06 0000
05 FFFF
5
05 0000
04 FFFF
4
Ext. Memory 8K
04 0000
03 FFFF
3
03 0000
02 FFFF
2
8
7
6
5
4
3
02 0000
01 FFFF
Address Area defined by
XADRS3 after reprogramming
B0F4
1
Ext Mem
Note: E009h defines a 128K wide
window starting from 0E’0000h
01 0000
00 FFFF
Ext Mem
B0F3
B0F2
2
0
0
0
1
00 0000
00 C000
B0F1
B0F0
00 0000
0
Flash + XRAM - 1Mbyte
Data Page 3 (Segment 0) - 16Kbyte
16 MB
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Doc ID 13453 Rev 4
ST10F273M
Internal Flash memory
5
Internal Flash memory
5.1
Overview
The on-chip Flash is composed of one matrix module of one bank of 512 Kbytes, named
Bank0, that can be read and modified. This module is called IFlash because it is on the
ST10 Internal bus.
Figure 6.
Flash structure
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The programming operations of the Flash are managed by an embedded Flash
Program/Erase Controller (FPEC). The high voltages needed for Program/Erase operations
are generated internally.
The Data bus is 32-bit wide for fetch accesses to IFlash. Read/write accesses to IFlash
Control Registers area are 16-bit wide.
5.2
Functional description
5.2.1
Structure
Table 3 below shows the address space reserved for the Flash module.
Table 3.
Flash module address space
Description
Addresses
Size
IFlash sectors
0x00 0000 to 0x08 FFFF
0x0E 0000 to 0x0E FFFF
512 Kbytes
64 Kbytes
Registers and Flash internal reserved area
5.2.2
Module structure
The IFlash module is composed of a bank (Bank 0) of 512 Kbytes of program memory
divided in 12 sectors (B0F0...B0F11). Bank 0 also contains a reserved sector named Test-
Flash.
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Internal Flash memory
ST10F273M
The Addresses from 0x0E 0000 to 0x0E FFFF are reserved for the Control Register
Interface and other internal service memory space used by the Flash Program/Erase
controller.
The following tables show the memory mapping of the Flash when it is accessed in read
mode (Table 4: Flash module sectorization (read operations)), and when accessed in write
or erase mode (Table 5: Flash module sectorization (write operations, or ROMS1 = ‘1’)).
Note:
With this second mapping, the first four sectors are remapped into code segment 1 (same
as obtained setting bit ROMS1 in SYSCON register).
Table 4.
Bank
Flash module sectorization (read operations)
Description
Addresses
Size (bytes)
Bank 0 Flash 0 (B0F0)
Bank 0 Flash 1 (B0F1)
0x00 0000 - 0x00 1FFF
0x00 2000 - 0x00 3FFF
0x00 4000 - 0x00 5FFF
0x00 6000 - 0x00 7FFF
0x01 8000 - 0x01 FFFF
0x02 0000 - 0x02 FFFF
0x03 0000 - 0x03 FFFF
0x04 0000 - 0x04 FFFF
0x05 0000 - 0x05 FFFF
0x06 0000 - 0x06 FFFF
0x07 0000 - 0x07 FFFF
0x08 0000 - 0x08 FFFF
8 K
8 K
Bank 0 Flash 2 (B0F2)
8 K
Bank 0 Flash 3 (B0F3)
8 K
Bank 0 Flash 4 (B0F4)
32 K
64 K
64 K
64 K
64 K
64 K
64 K
64 K
Bank 0 Flash 5 (B0F5)
B0
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
Bank 0 Flash 8 (B0F8)
Bank 0 Flash 9 (B0F9)
Bank 0 Flash 10 (B0F10 / B1F0) (1)
Bank 0 Flash 11 (B0F11 / B1F1) (1)
1. A single bank is implemented but the last two sectors can be seen as a Bank 1 in order to maintain
compatibility with the Flash Programming routines developed for the ST10F273E (based on ST10F276E).
This means that the Control and Status flags for the blocks B0F10 and B0F11 are duplicated to also be
accessible as blocks B1F0 and B1F1.
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ST10F273M
Internal Flash memory
Table 5.
Bank
Flash module sectorization (write operations, or ROMS1 = ‘1’)
Description
Addresses
Size (bytes)
Bank 0 Test-Flash (B0TF)
Bank 0 Flash 0 (B0F0)
0x00 0000 - 0x00 0FFF
0x01 0000 - 0x01 1FFF
0x01 2000 - 0x01 3FFF
0x01 4000 - 0x01 5FFF
0x01 6000 - 0x01 7FFF
0x01 8000 - 0x01 FFFF
0x02 0000 - 0x02 FFFF
0x03 0000 - 0x03 FFFF
0x04 0000 - 0x04 FFFF
0x05 0000 - 0x05 FFFF
0x06 0000 - 0x06 FFFF
0x07 0000 - 0x07 FFFF
0x08 0000 - 0x08 FFFF
4 K
8 K
Bank 0 Flash 1 (B0F1)
8 K
Bank 0 Flash 2 (B0F2)
8 K
Bank 0 Flash 3 (B0F3)
32 K
64 K
64 K
64 K
64 K
64 K
64 K
64 K
8 K
Bank 0 Flash 4 (B0F4)
B0
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
Bank 0 Flash 8 (B0F8)
Bank 0 Flash 9 (B0F9)
Bank 0 Flash 10 (B0F10 / B1F0) (1)
Bank 0 Flash 11 (B0F11 / B1F1) (1)
1. A single bank is implemented but the last two sectors can be seen as a Bank 1 in order to maintain
compatibility with the Flash Programming routines developed for the ST10F273E (based on ST10F276E).
This means that the Control and Status flags for the blocks B0F10 and B0F11 are duplicated to also be
accessible as blocks B1F0 and B1F1.
Table 5 above refers to the configuration when bit ROMS1 of SYSCON register is set.
When Bootstrap mode is entered:
●
●
●
Test-Flash is seen and available for code fetches (address 0x00 0000)
User IFlash is only available for read and write accesses
Write accesses must be made with addresses starting in segment 1 from 0x01 0000,
whatever ROMS1 bit in SYSCON value
●
Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in
segment 0.
Example 1:
In default configuration, to program address 0, the user must put the value 0x01 0000 in the
FARL and FARH registers but to verify the content of the address 0, a read to 0x00 0000
must be performed.
The next Table 6 shows the Control Register interface composition: This set of registers can
be addressed by the CPU .
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Internal Flash memory
ST10F273M
Table 6.
Name
Flash control registers summary
Description
Addresses
Size Bus size
Flash control registers 1 - 0 High &
Low
FCR1 - 0
FDR1 - 0
0x0E 0000 - 0x0E 0007
8 byte
Flash data registers 1 - 0 High &
Low
0x0E 0008 - 0x0E 000F
8 byte
FAR
FER
Flash address registers
Flash error register
0x0E 0010 - 0x0E 0013
0x0E 0014 - 0x0E 0015
4 byte
2 byte
Flash non-volatile protection I
registers mirrored
FVWPIR-mirror
FVWPIR
0x0E DFB0 - 0x0E DFB3
4 byte
4 byte
2 byte
16-bit
(XBus)
Flash volatile protection I registers 0x0E DFB4 - 0x0E DFB7
Flash volatile access protection
0x0E DFB8 - 0x0E DFB9
register 0
FVAPR0
Flash non-volatile access
protection register 1
FVAPR1
XFICR
0x0E DFBC - 0x0E DFBF 4 byte
0x0E E000 - 0x0E E001 2 byte
XFlash Interface Control register
(dummy register)
Note:
FVWPIR-mirror is a mirror of the FVWPIR to maintain software compatibility with the
ST10F273E in the handling of the last two blocks B0F10/B1F0 and B0F11/B1F1.
XFICR is a dummy register that can be read and written (for compatibility with the
ST10F273E) but its content has no effect on the XBus timings.
5.2.3
Low power mode
The Flash module is automatically switched off executing PWRDN instruction. The
consumption is drastically reduced, but exiting this state can require a long time (t ).
PD
Recovery time from Power-down mode for the Flash modules is anyway shorter than the
main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash,
it is important to size properly the external circuit on RPD pin.
Note:
PWRDN instruction must not be executed while a Flash program/erase operation is in
progress.
5.3
Write operation
The Flash module has a single register interface mapped in the XBus memory space
0x0E 0000 - 0x0E 0015. All the operations are enabled through four 16-bit control registers:
Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers are
used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L-
FDR0H/L) and Write Operation Error flags (FER). All registers are accessible with 8- and
16-bit instructions (since they are mapped on the XBus).
Note:
To have access to the Flash Control Registers used for program/erasing operations, bit 5
(XFLASHEN) in XPERCON register must be set.
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ST10F273M
Caution:
Internal Flash memory
During a Flash write operation any attempt to read the IFlash will output the invalid data
009Bh (corresponding, for code fetch, to the software trap 009Bh). This means that the
IFlash is not fetchable when a programming operation is active: the write operation
commands must be executed from another memory (one of the on-chip RAMs or some
external memory).
Warning: During a Write operation, when bit LOCK of FCR0 is set, it is
forbidden to write into the Flash Control Registers.
Power supply drop
If during a write operation the internal low voltage supply drops below a certain internal
voltage threshold, any write operation running is suddenly interrupted and the module is
reset to Read mode. At following Power-on, the interrupted Flash write operation must be
repeated.
5.4
Flash control registers description
5.4.1
Flash control register 0 low (FCR0L)
The Flash Control Register 0 Low (FCR0L), together with the Flash Control Register 0 High
(FCR0H), is used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is
seen by the user in Bootstrap mode only.
FCR0L (0x0E 0000)
FCR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res
-
DBSY BSY
1
BSY
NVR
Reserved
-
LOCK
RO
Reserved
-
0
RO
RO
RO
Table 7.
FCR0L register description
Bit
Name
Function
15:7
-
Reserved. These bits must be left to their reset value (0).
Dummy Bank1 Busy
It is a replication of the BSY0 bit: it is set whenever a write operation is on-going.
This bit is emulating the BSY1 bit of the ST10F273E device. When write
operations are on going on B0F10 and/or B0F11 blocks of the ST10F273M, this
bit will be set in order to indicate that their equivalent B1F0 or B1F1 in the
ST10F273E are busy.
6
DBSY1
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Internal Flash memory
Table 7.
ST10F273M
FCR0L register description (continued)
Name Function
Bit
Bank0 Busy
This bits indicate that a write operation is running in the Bank0. It is automatically
set when bit WMS is set. When this bit is set every read access to the Bank0 will
output invalid data (software trap 009Bh), while every write access will be ignored.
At the end of the write operation or during a Program or Erase Suspend this bit is
automatically reset and Flash Bank returns to read mode. After a Program or
Erase Resume this bit is automatically set again.
5
BSY0
Flash registers access locked
When this bit is set, it means that the access to the Flash Control Registers
FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC:
any read access to the registers will output invalid data (software trap 009Bh) and
any write access will be ineffective. LOCK bit is automatically set when the Flash
bit WMS is set.
4
LOCK
This is the only bit the user can always access to detect the status of the Flash:
once it is found low, the rest of FCR0L and all the other Flash registers are
accessible by the user as well.
Note that FER content can be read when LOCK is low, but its content is updated
only when also BSYx bits are reset.
3:2
1
-
Reserved. These bits must be left to their reset value (0).
Busy of Non-Volatile Registers
This bit indicate that a write operation is running in the corresponding on “Non-
volatile registers”. They are automatically set when bit WMS is set. When this bit
is set every read access to the IFlash will output the value 009Bh (software trap),
while every write access to the IFlash will be ignored. At the end of the write
operation or during a Program Suspend this bit is automatically reset and the
IFlash returns to read mode. After a Program this bit is automatically set again.
BSYNVR
0
-
Reserved. This bit must be left to its reset value (0).
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ST10F273M
Internal Flash memory
5.4.2
Flash control register 0 high (FCR0H)
The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low
(FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is
seen by the user in Bootstrap mode only.
FCR0H (0x0E 0002)
FCR
Reset value: 0000h
15
WMS SUSP WPG DWPG SER
RS RW RW RW RW
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DS
MOD
Reserved
-
SPR
RW
Reserved
-
RW
Table 8.
FCR0H register description
Bit
Name
Function
Write mode start
This bit must be set to start every write operation in the Flash module. At the end
of the write operation or during a Suspend, this bit is automatically reset. To
resume a suspended operation, this bit must be set again.
It is forbidden to set this bit if bit ERR of FER is high (the operation is not
accepted).
15
WMS
It is also forbidden to start a new write (program or erase) operation (by setting
WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no
effect.
Suspend
This bit must be set to suspend the current Program (Word or Double Word) or
Sector Erase operation in order to read data in another part of the Flash. The
Suspend operation resets the Bank0 to normal read mode (automatically resetting
bits BSYx). When in Program Suspend, the Flash module accepts only the
following operations: Read and Program Resume. When in Erase Suspend the
module accepts only the following operations: Read, Erase Resume. To resume a
suspended operation, the WMS bit must be set again, together with the selection
bit corresponding to the operation to resume (WPG, DWPG, SER).(1)
14
SUSP
Word program
This bit must be set to select the Word (32 bits) Program operation in the Flash
module. The Word Program operation allows to program 0s in place of 1s. The
Flash Address to be programmed must be written in the FARH/L registers, while
the Flash Data to be programmed must be written in the FDR0H/L registers before
starting the execution by setting bit WMS. WPG bit is automatically reset at the
end of the Word Program operation.
13
WPG
Double word program
This bit must be set to select the Double Word (64 bits) Program operation in the
Flash module. The Double Word Program operation allows to program 0s in place
of 1s. The Flash Address in which to program (aligned with even words) must be
written in the FARH/L registers, while the two Flash Data words to be programmed
must be written in the FDR0H/L registers (even word) and FDR1H/L registers (odd
word) before starting the execution by setting bit WMS. DWPG bit is automatically
reset at the end of the Double Word Program operation.
12 DWPG
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Internal Flash memory
Table 8.
ST10F273M
FCR0H register description (continued)
Name Function
Bit
Sector erase
This bit must be set to select the Sector Erase operation. The Sector Erase
operation allows to erase all the Flash locations to value 0xFFFF. From 1 to all of
Bank0’s sectors (excluding Test-Flash) can be selected to be erased through bits
BxFy of FCR1H/L registers before starting the execution by setting bit WMS. It is
not necessary to preprogram the sectors to 0, because this is done automatically.
SER bit is automatically reset at the end of the Sector Erase operation.
11
SER
10:9
-
Reserved. This bit must be left to their reset value (0).
Set protection
This bit must be set to select the Set Protection operation. The Set Protection
operation allows to program 0s in place of 1s in the Flash Non-Volatile Protection
Registers. The Flash Address in which to program must be written in the FARH/L
registers, while the Flash Data to be programmed must be written in the FDR0H/L
before starting the execution by setting bit WMS. A sequence error is flagged by bit
SEQER of FER if the address written in FARH/L is not in the range 0x0E DFB0-
0x0E DFBF.
8
SPR
SPR bit is automatically reset at the end of the Set Protection operation.
Dummy Select Module
This is a dummy SMOD bit that is maintaining software compatibility with the
ST10F273E where it must be set before every Write Operation to the IFlash.
It has no effect in the ST10F273M.
7
DSMOD
-
6:0
Reserved. These bits must be kept to their reset value (0).
1. It is forbidden to start a new Write operation with bit SUSP already set.
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Doc ID 13453 Rev 4
ST10F273M
Internal Flash memory
5.4.3
Flash control register 1 low (FCR1L)
The Flash Control Register 1 Low (FCR1L), together with Flash Control Register 1 High
(FCR1H), is used to select the sectors to erase or during any write operation, to monitor the
status of each sector and bank.
FCR1L (0x0E 0004)
FCR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B0F
11
B0F
10
B0F
9
B0F
8
B0F
7
B0F
6
B0F
5
B0F
4
B0F
3
B0F
2
B0F
1
B0F
0
Reserved
-
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
Table 9.
Bit
FCR1L register description
Name
Function
15:12
-
Reserved. These bits must be kept to their default value (0).
Bank0 IFlash sector 11:10 status
These bits are a copy of bits B0F10 and B0F11 in FCR1H.
It is possible use these bits as well as the bits B0F10/B1F0 and B0F11/B1F1 in
FCR1H.
B0F11
B0F10
11:10
To preserve compatibility with the ST10F273E, these bits must be left at their
default value ‘0’ and the FCR1H register must be used.
Bank 0 IFlash sector 9:0 status
These bits must be set during a Sector Erase operation to select the sectors to
erase in Bank 0. Besides, during any erase operation, these bits are
automatically set and give the status of the first 10 sectors of Bank 0 (B0F9-
B0F0). The meaning of B0Fy bit for Sector y of Bank 0 is given by Table 11:
Bank (BxS) and sectors (BxFy) status bits meaning. These bits are
automatically reset at the end of a Write operation if no errors are detected.
B0F9
...
B0F0
9:0
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Internal Flash memory
ST10F273M
5.4.4
Flash control register 1 high (FCR1H)
The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low
(FCR1L), is used to select the sectors to erase or during any write operation, to monitor the
status of each sector and bank.
FCR1H (0x0E 0006)
FCR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B0F11
/B1F1
B0F10
/B1F0
Reserved
-
DB1S
RS
B0S
RS
Reserved
-
RS
RS
Table 10. FCR1H register description
Bit
Name
Function
15:10
-
Reserved. These bits must be kept to their default value (0).
Dummy Bank1 status
This is a replication of B0S bit.
In order to maintain compatibility with the ST10F273E where operations on
the last 2 sectors were flagged in this position.
9
DB1S
Bank0 status
During any erase operation, this bit is automatically modified and gives the
status of the Bank 0. The meaning of B0S bit is given in the next Table 11:
Bank (BxS) and sectors (BxFy) status bits meaning. This bit is automatically
reset at the end of a erase operation if no errors are detected.
8
B0S
-
7:2
Reserved. These bits must be kept to their default value (0).
Bank0 IFlash sector 11:10 status / Bank1 IFlash sector 1:0 status
These bits must be set during a Sector Erase operation to select the last 2
sectors of Bank0. Besides, during any erase operation, these bits are
automatically set and give the status of the last two sectors of Bank0
(B0F11-B0F10). The meaning of B0Fy bit for Sector y of Bank 0 is given by
the next Table 11: Bank (BxS) and sectors (BxFy) status bits meaning.
These bits are automatically reset at the end of a Write operation if no errors
are detected.
B0F10/B1F0
B0F11/B1F1
1:0
Note: These bits can also be seen as selecting the two sectors of Bank1 for
compatibility with the ST10F273E.
Table 11.
Bank (BxS) and sectors (BxFy) status bits meaning
Operation
BxS = 1 meaning
BxFy = 1 meaning
Erase Suspend
1
-
Erase error
Erase error in sector y
0
0
1
0
Erase suspended in bank x
Don’t care
Erase suspended in sector y of bank x
Don’t care
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Doc ID 13453 Rev 4
ST10F273M
Internal Flash memory
5.4.5
Flash data register 0 low (FDR0L)
During program operations, the Flash Address Registers (FARH/L) are used to store the
Flash address in which to program and the Flash Data Registers (FDR1H/L-FDR0H/L) are
used to store the Flash data to program.
FDR0L (0x0E 0008)
FCR
Reset value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN
15
DIN
14
DIN
13
DIN
12
DIN
11
DIN
10
DIN
9
DIN
8
DIN
7
DIN
6
DIN
5
DIN
4
DIN
3
DIN
2
DIN
1
DIN
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 12. FDR0L register description
Bit Name
Function
Data input 15:0
These bits must be written with the Data to program in Flash during the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
15:0 DIN[15:0]
5.4.6
Flash data register 0 high (FDR0H)
FDR0H (0x0E 000A)
FCR
Reset value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN
31
DIN
30
DIN
29
DIN
28
DIN
27
DIN
26
DIN
25
DIN
24
DIN
23
DIN
22
DIN
21
DIN
20
DIN
19
DIN
18
DIN
17
DIN
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 13. FDR0H register description
Bit Name
Function
Data input 31:16
These bits must be written with the Data to program in Flash during the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
15:0 DIN[31:16]
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Internal Flash memory
ST10F273M
5.4.7
5.4.8
5.4.9
Flash data register 1 low (FDR1L)
FDR1L (0x0E 000C)
FCR
Reset value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 14. FDR1L register description
Bit Name
Function
Data input 15:0
15:0 DIN[15:0]
These bits must be written with the Data to program in Flash during the following
operations: Double Word Program (64-bit) and Set Protection.
Flash data register 1 high (FDR1H)
FDR1H (0x0E 000E)
FCR
Reset value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 15. FDR1H register description
Bit Name
Function
Data input 31:16
15:0 DIN[31:16]
These bits must be written with the Data to program in Flash during the following
operations: Double Word Program (64-bit) and Set Protection.
Flash address register low (FARL)
FARL (0x0E 0010)
FCR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reserved
-
Table 16. FARL register description
Bit Name
Function
Address 15:2
These bits must be written with the Address of the Flash location to program
during the following operations: Word Program (32-bit) and Double Word
Program (64-bit).
15:2 ADD[15:2]
In Double Word Program bit ADD2 must be written to ‘0’.
1:0
-
Reserved. These bits must be kept to their default value (0).
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Doc ID 13453 Rev 4
ST10F273M
Internal Flash memory
5.4.10
Flash address register high (FARH)
FARH (0x0E 0012)
FCR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADD
20
ADD
19
ADD
18
ADD
17
ADD
16
Reserved
-
RW
RW
RW
RW
RW
Table 17. FARH register description
Bit
Name
Function
Address 20:16
ADD20
...
ADD16
4:0
These bits must be written with the Address of the Flash location to program
during the following operations: Word Program and Double Word Program.
15:5
-
Reserved. These bits must be kept to their default value (0).
5.4.11
Flash error register (FER)
The Flash error register, as well as all the other Flash registers, can be read only once the
LOCK bit of register FCR0L is low. Nevertheless, the FER content is updated after
completion of the Flash operation, that is, when BSYx bits are reset. Therefore, the FER
content can only be read once the LOCK and BSYx bits are cleared.
FER (0xE 0014h)
FCR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
-
WPF RESERSEQER
Reserved
-
10ER PGER ERER ERR
RC RC RC RC
RC
RC
RC
Table 18. FER register bits
Bit
Name
Function
15:9
-
Reserved. These bits must be kept to their default value (0).
Write protection flag
This bit is automatically set when trying to program or erase in a sector write
protected. In case of multiple Sector Erase, the not protected sectors are
erased, while the protected sectors are not erased and bit WPF is set. This
bit must be cleared by software.
8
7
WPF
Resume error
This bit is automatically set when a suspended Program or Erase operation is
not resumed correctly due to a protocol error. In this case the suspended
operation is aborted. This bit must be cleared by software.
RESER
Sequence error
This bit is automatically set when the control registers (FCR1H/L-FCR0H/L,
FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid Write
Operation. In this case no Write Operation is executed. This bit must be
cleared by software.
6
SEQER
-
5:4
Reserved. These bits must be kept to their default value (0).
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Internal Flash memory
ST10F273M
Table 18. FER register bits (continued)
Bit
Name
Function
1 over 0 error
This bit is automatically set when trying to program at 1 bits previously set at
0 (this does not happen when programming the Protection bits). This error is
not due to a failure of the Flash cell, but only flags that the desired data has
not been written. This bit must be cleared by software.
3
10ER
Program error
This bit is automatically set when a Program error occurs during a Flash write
operation. This error is due to a real failure of a Flash cell, that can no more
be programmed. The word where this error occurred must be discarded. This
bit must be cleared by software.
2
PGER
Erase error
This bit is automatically set when an Erase error occurs during a Flash write
operation. This error is due to a real failure of a Flash cell, that can no more
be erased. This kind of error is fatal and the sector where it occurred must be
discarded. This bit must be cleared by software.
1
0
ERER
ERR
Write error
This bit is automatically set when an error occurs during a Flash write
operation or when a bad write operation setup is done. Once the error has
been discovered and understood, ERR bit must be cleared by software.
5.4.12
XFlash interface control dummy register (XFICR)
XFICR (0x0E E0000)
FCR
Reset value: 0007h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
-
WS3 WS2 WS1 WS0
RW RW RW RW
Table 19. XFlash interface control register
Bit Name
Function
Dummy Wait States 3:0
In the ST10F273E, these bits were used to configure the number of wait-
states to access the XFlash. As there is no XFlash on the Root part number
1, these bits have no effect.
3:0 WS3...WS0
This register is implemented for software compatibility with the ST10F273E.
15:4
-
Reserved. These bits must be kept to their default value (0).
5.5
Protection strategy
The protection bits are stored in Non-Volatile Flash cells that are read once at reset and
stored in five Volatile registers. Before they are read from the Non-Volatile cells, all the
available protections are forced active during reset.
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Doc ID 13453 Rev 4
ST10F273M
Internal Flash memory
Note:
The protection bits in the Non-Volatile registers are programmable one time and this
programing is permanent. Temporary unprotection will be handled with their Volatile
equivalent.
The protections can be programmed using the Set Protection operation (see Section 5.4:
Flash control registers description) that must be executed from the on-chip RAMs or from
external memories.
Two kind of protections are available:
●
write protections to avoid unwanted writings
access protections to avoid piracy
●
The next sections show the different level of protections and highlight the architecture
limitations.
5.5.1
Protection registers
The five Non-Volatile Protection Registers are one-time programmable for the user.
Two registers, FVWPIRL and FVWPIRH, are used to store the Write Protection fuses for
each sector IFlash module. The other three registers (FNVAPR0 and FNVAPR1L/H) are
used to store the Access Protection fuses.
Note:
On-going protection operations are flagged with BSYNVR, bit 1 of FCR0L register.
5.5.2
Flash non-volatile write protection I register low (FNVWPIRL)
FNVWPIRL (0x0E DFB4)
NVR
Delivery value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W0P W0P W0P W0P W0P W0P W0P W0P W0P W0P W0P W0P
Reserved
-
11
10
9
8
7
6
5
4
3
2
1
0
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 20. FNVWPIRL register bits
Bit
Name
Function
Reserved. These bits must be left to their default value ‘1’ when programming
PVWPIRL.
15:12
-
Read-Only for Write protection Bank0 sectors 11 and 10
These bits must be left to their default value ‘1’ when programming FVWPIRL
(they can not be used to set write protection on sectors B0F11 and B0F10).
After a protection command, these bits will reflect the value of bit 0 and 1 of
FVWPIRH register (W0P11 and W0P10).
W0P11
W0P10
11:10
9:0
Write protection bank 0 / sectors 9-0
W0P9
...
W0P0
These bits, if programmed at 0, disable any write access to the sectors of
Bank 0 (IFlash).
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Internal Flash memory
ST10F273M
5.5.3
Flash non-volatile write protection I register high (FNVWPIRH)
FNVWPIRH (0x0E DFB6)
NVR
Delivery value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W0P11-W0P10-
W1P1 W1P0
Reserved
-
RW
RW
Table 21. FNVWPRIH register bits
Bit
Name
Function
Reserved. These bits must be left to their default value ‘1’.
15:2
-
Write protection Bank0 - sectors 11:10 / Write protection Bank1 - sectors 1:0
W0P11/W1P1
W0P10/W1P0
1:0
These bits, if programmed at 0, disable any write access to the selected
sectors.
5.5.4
Flash non-volatile write protection I register low Mirror (FNVWPIRL-m)
FNVWPIRL-m (0x0E DFB0)
NVR
Delivery value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W0P W0P W0P W0P W0P W0P W0P W0P W0P W0P W0P W0P
Reserved
-
11
10
9
8
7
6
5
4
3
2
1
0
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
This register is mirroring the register at FVWPIRL (address 0x0E DFB4). It is intended to
maintain software compatibility with the ST10F273E.
In applications ported from a ST10F273E, FVWPIRL-m register (address 0x0E DFB0) must
be used to maintain the existing Flash drivers.
In applications ported from a ST10F272x, FVWPIRL register (address 0x0E DFB4) must be
used to maintain existing drivers.
5.5.5
Flash non-volatile write protection I register high Mirror (FVWPIRH-m)
FVWPIRH-m (0x0E DFB2
NVR
Delivery value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W0P11-W0P10-
W1P1 W1P0
Reserved
-
RW
RW
This register is mirroring the register at FVWPIRH (address 0x0E DFB6). It is intended to
maintain software compatibility with the ST10F273E.
In applications ported from a ST10F273E, FVWPIRH-m register (address 0x0E DFB2) must
be used to maintain the existing Flash drivers.
In applications ported from a ST10F272x, FVWPIRH register (address 0x0E DFB6) must be
used to maintain existing drivers.
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Doc ID 13453 Rev 4
ST10F273M
Internal Flash memory
5.5.6
Flash non-volatile access protection register 0 (FNVAPR0)
FNVAPR0 (0x0E DFB8)
NVR
Delivery value: ACFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
-
DBGP ACCP
RW RW
Table 22. FNVAPR0 register bits
Bit
Name
Description
15:2
-
Reserved. These bits must be left to their default value.
Debug protection
This bit, if erased at 1, allows to bypass all the protections using the Debug
features through the Test Interface. If programmed at 0, on the contrary, all
the debug features, the Test Interface and all the Flash Test modes are
disabled.
Even STMicroelectronics will not be able to access the device to run any
eventual failure analysis.
1
0
DBGP
ACCP
Access protection
This bit, if programmed at 0, disables any access (read/write) to data mapped
inside IFlash Module address space, unless the current instruction is fetched
from IFlash.
5.5.7
Flash non-volatile access protection register 1 low (FNVAPR1L)
FNVAPR1L (0x0E DFBC)
NVR
Delivery value: FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 23. FNVAPR1L register bits
Bit
Name
Function
Protections disable15-0
If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit
ACCP is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and
ACCP have already been programmed at 0. Bit PDSx can be programmed at 0
only if bit PENx-1 has already been programmed at 0.
PDS15
...
PDS0
15:0
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Internal Flash memory
ST10F273M
5.5.8
Flash non-volatile access protection register 1 high
(FNVAPR1H
)
NVR
Delivery value: FFFFh
FNVAPR1H (0x0E DFBE)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 24. FNVAPR1H register bits
Bit
Name
Function
Protections enable 15-0
PEN15
...
PEN0
If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit
ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has
already been programmed at 0.
15:0
5.5.9
Access protection
The IFlash module has one level of access protection (access to data both in Reading and
Writing): If bit ACCP of FNVAPR0 is programmed at 0, the IFlash module becomes access
protected, meaning data in the IFlash module can be read only if the current execution is
from the IFlash module itself.
Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H (user
operation before returning parts to STMicroelectronics for analysis). Protection can be
permanently enabled again by programming bit PEN0 of FNVAPR1L. The action to disable
and enable again Access Protections in a permanent way can be executed a maximum of
16 times.
Trying to write into the access protected Flash from internal RAM or external memories will
be unsuccessful. Trying to read into the access protected Flash from internal RAM or
external memories will output a dummy data (software trap 009Bh).
When the Flash module is protected in access, data access through PEC of a peripheral is
also forbidden. To read/write data in PEC mode from/to a protected Bank, it is necessary to
first temporarily unprotect the Flash module.
The following table summarizes all possible Access Protection levels: In particular, it shows
what is possible and not possible to do when fetching from a memory (see fetch location
column) supposing all possible access protections are enabled.
Table 25. Summary of access protection level
Read XRAM or
Read IFlash /
Jump to IFlash
external memory /
Jump to XRAM or
external memory
Read Flash
registers
Write Flash
registers
Fetch location
Fetching from IFlash
Fetching from IRAM
Fetching from XRAM
Yes / Yes
No / Yes
No / Yes
Yes / Yes
Yes / Yes
Yes / Yes
Yes
Yes
Yes
Yes
No
No
Fetching from external
memory
No / Yes
Yes / Yes
Yes
No
44/186
Doc ID 13453 Rev 4
ST10F273M
Internal Flash memory
5.5.10
Write protection
The Flash modules have one level of Write Protections: Each sector can be Software Write
Protected by programming at 0 the related bit WyPx in FNVWPIRL/H register.
5.5.11
Temporary unprotection
Bits WyPx of FNVWPIRL/H can be temporarily unprotected by executing the Set Protection
operation and writing 1 into these bits.
Bit ACCP can be temporarily unprotected by executing the Set Protection operation and
writing are executed from IFlash.
To restore the write access protection bits it is necessary to reset the microcontroller or to
execute a Set Protection operation and write 0 into the desired bits.
In reality, when a temporary unprotection operation is executed, the corresponding volatile
register is written to 1, while the non-volatile registers bits previously written to 0 (for a
protection set operation), will continue to maintain the 0. For this reason, the user software
must be in charge to track the current protection status (for instance using a specific RAM
area), it is not possible to deduce it by reading the non-volatile register content (a temporary
unprotection cannot be detected).
5.6
Write operation examples
In the following, examples for each kind of Flash write operation are presented.
The examples are showing the sequence of instructions needed to start an operation. Write
operations should be followed by a status check (FER register).
Note:
After a write operation has started, the Flash control registers are not accessible for a short
time. The LOCK bit, bit 4 of FCR0L register, must be polled in order to know when the Flash
control registers can be accessed again (LOCK = ‘1’: no access to Flash control registers).
Write operation on IBus registers is 16 bits wide.
Word program
Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x025554
FCR0H|= 0x2000;
FARL = 0x5554;
FARH = 0x0002;
FDR0L = 0xAAAA;
FDR0H = 0xAAAA;
FCR0H|= 0x8000;
/*Set WPG in FCR0H*/
/*Load Add in FARL*/
/*Load Add in FARH*/
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Operation start*/
Double word program
Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x035558 and
data 0xAA55AA55 at address 0x03555C.
FCR0H
FARL
|= 0x1000;
= 0x5558;
= 0x0003;
= 0x55AA;
/*Set DWPG in FCR0H*/
/*Load Add in FARL*/
/*Load Add in FARH*/
/*Load Data in FDR0L*/
FARH
FDR0L
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Internal Flash memory
ST10F273M
FDR0H
FDR1L
FDR1H
FCR0H
= 0x55AA;
= 0xAA55;
= 0xAA55;
|= 0x8000;
/*Load Data in FDR0H*/
/*Load Data in FDR1L*/
/*Load Data in FDR1H*/
/*Operation start*/
Double Word Program is always performed on the Double Word aligned on an even Word:
bit ADD2 of FARL is ignored.
Sector erase
Example: Sector Erase of sectors B0F1 and B0F0 of Bank 0.
FCR0H
FCR1L
FCR0H
|= 0x0800;
|= 0x0003;
|= 0x8000;
/*Set SER in FCR0H*/
/*Set B0F1, B0F0*/
/*Operation start*/
Suspend and resume
Word Program, Double Word Program, and Sector Erase operations can be suspended in
the following way:
FCR0H
|= 0x4000;
/*Set SUSP in FCR0H*/
Then the operation can be resumed in the following way:
FCR0H
FCR0H
|= 0x0800;
|= 0x8000;
/*Set SER in FCR0H*/
/*Operation resume*/
Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is
already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of
Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise
the operation is aborted and bit RESER of FER is set.
Set protection
Example 1: Enable Write Protection of sectors B0F3-0 of Bank 0.
FCR0H
FARL
|= 0x0100;
= 0xDFB4;
= 0x000E;
= 0xFFF0;
= 0xFFFF;
|= 0x8000;
/*Set SPR in FCR0H*/
/*Load Add of register FNVWPIR in FARL*/
/*Load Add of register FNVWPIR in FARH*/
/*Load Data in FDR0L*/
FARH
FDR0L
FDR0H
FCR0H
/*Load Data in FDR0H*/
/*Operation start*/
Example 2: Enable Access and Debug Protection.
FCR0H
FARL
|= 0x0100;
= 0xDFB8;
= 0x000E;
= 0xFFFC;
|= 0x8000;
/*Set SPR in FCR0H*/
/*Load Add of register FNVAPR0 in FARL*/
/*Load Add of register FNVAPR0 in FARH*/
/*Load Data in FDR0L*/
FARH
FDR0L
FCR0H
/*Operation start*/
Example 3: Disable in a permanent way Access and Debug Protection.
FCR0H
FCR0H
FARL
|= 0x0100;
|= 0x0100;
= 0xDFBC;
= 0x000E;
/*Set SPR in FCR0H*/
/*Set SPR in FCR0H*/
/*Load Add of register FNVAPR1L in FARL*/
/*Load Add of register FNVAPR1L in FARH*/
FARH
46/186
Doc ID 13453 Rev 4
ST10F273M
Internal Flash memory
FDR0L
FCR0H
= 0xFFFE;
/*Load Data in FDR0L for clearing PDS0*/
/*Operation start*/
|= 0x8000;
Example 4: Enable again in a permanent way Access and Debug Protection, after having
disabled them.
FCR0H|= 0x0100;
FARL = 0xDFBC;
FARH = 0x000E;
FDR0H = 0xFFFE;
FCR0H|= 0x8000;
/*Set SPR in FCR0H*/
/*Load Add register FNVAPR1H in FARL*/
/*Load Add register FNVAPR1H in FARH*/
/*Load Data in FDR0H to clear PEN0*/
/*Operation start*/
Disable and re-enable of Access and Debug Protection in a permanent way (as shown by
examples 3 and 4) can be done for a maximum of 16 times.
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Internal Flash memory
ST10F273M
5.7
Write operation summary
In general, each write operation is started through a sequence of three steps:
1. The first instruction is used to select the desired operation by setting its corresponding
selection bit in the Flash Control Register 0.
2. The second step is the definition of the Address and Data for programming or the
sectors to erase.
3. The last instruction is used to start the write operation, by setting the start bit WMS in
the FCR0. This last instruction must not be executed from Flash.
Once selected, but not yet started, one operation can be canceled by resetting the operation
selection bit.
Available Flash Module Write Operations are summarized in the following Table 26.
Table 26. Flash write operations
Operation
Select bit
Address and data
Start bit
FARL/FARH
FDR0L/FDR0H
Word program (32-bit)
WPG
FARL/FARH
FDR0L/FDR0H
FDR1L/FDR1H
Double word program (64-bit)
DWPG
WMS
None
Sector erase
SER
SPR
FCR1L/FCR1H
FDR0L/FDR0H
None
Set protection
Program/erase suspend
SUSP
Figure 7 shows the complete flow needed for a Write operation.
Figure 7. Write operation control flow
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Doc ID 13453 Rev 4
ST10F273M
Bootstrap loader
6
Bootstrap loader
The ST10F273M implements Boot capabilities in order to:
●
Support bootstrap via UART or bootstrap via CAN for the standard bootstrap
●
Support a Selective Bootstrap Loader, to manage the bootstrap sequence in a different
way
6.1
Selection among user-code, standard or selective bootstrap
The boot modes are triggered with a special combination set on Port0L[5...4]. Those
signals, as other configuration signals, are latched on the rising edge of RSTIN pin.
●
Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) selects the normal mode (also
called User mode) and selects the user Flash to be mapped from address 00’0000h.
●
Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) selects ST10 standard bootstrap
mode (Test-Flash is active and overlaps user Flash for code fetches from address
00'0000h; user Flash is active and available for read accesses).
●
Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) activates additional verifications
to select which bootstrap software to execute:
–
if the User mode signature in the User Flash is programmed correctly, then a
software reset sequence is selected and the User code is executed;
–
if the User mode signature is not programmed correctly in the user Flash, then the
User key location is read again. Its value determines which communication
channel will be enabled for bootstrapping.
.
Table 27. ST10F273M boot mode selection
P0.5
P0.4
ST10 decoding
1
1
User mode: User Flash mapped at 00’0000h
Standard Bootstrap Loader: User Flash mapped from 00’0000h, code fetches
redirected to Test-Flash at 00’0000h
1
0
Selective Boot mode: User Flash mapped from 00’0000h, code fetches
redirected to Test-Flash at 00’0000h (different sequence execution compared to
Standard Bootstrap Loader)
0
0
1
0
Reserved
6.2
Standard bootstrap loader
After entering the standard BSL mode and the respective initialization, the ST10F273M
scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from the
CAN interface or a start condition from the UART line.
Start condition on UART RxD: ST10F273M starts standard bootstrap loader. This
bootstrap loader is identical to that of other ST10 devices (example: ST10F269, ST10F168).
Valid dominant bit on CAN1 RxD: ST10F273M start bootstrapping via CAN1.
Caution:
As both UART_RxD and CAN1_RxD lines are polled to detect a start of communication,
ensure a stable level on the unused channel by adding a pull-up resistor.
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Bootstrap loader
ST10F273M
6.3
Alternate and selective boot mode (ABM and SBM)
6.3.1
Activation of the ABM and SBM
Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of
RSTIN.
6.3.2
6.3.3
User mode signature integrity check
The behavior of the Selective Boot mode is based on the computing of a signature between
the content of two memory locations and a comparison with a reference signature. This
requires that users who use Selective Boot have reserved and programmed the Flash
memory locations.
Selective boot mode
When the user signature is not correct, instead of executing the Standard Bootstrap Loader
(triggered by P0L.4 low at reset), additional check is made.
Depending on the value at the User key location, the following behavior occurs:
●
●
●
●
A jump is performed to the Standard Bootstrap Loader
Only UART is enabled for bootstrapping
Only CAN1 is enabled for bootstrapping
The device enters an infinite loop
50/186
Doc ID 13453 Rev 4
ST10F273M
Central processing unit (CPU)
7
Central processing unit (CPU)
The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and
dedicated SFRs. Additional hardware has been added for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Most of the ST10F273M’s instructions can be executed in one instruction cycle which
requires 50ns at 40 MHz CPU clock. For example, shift and rotate instructions are
processed in one instruction cycle independent of the number of bits to be shifted.
Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles,
16 x 16-bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles.
The jump cache reduces the execution time of repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
The CPU uses a bank of 16 word registers to run the current context. This bank of General
Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area.
A Context Pointer (CP) register determines the base address of the active register bank to
be accessed by the CPU.
The number of register banks is only restricted by the available Internal RAM space. For
easy parameter passing, a register bank may overlap others.
A system stack of up to 2048 bytes is provided as a storage for temporary data. The system
stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack
pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer
value upon each stack access for the detection of a stack overflow or underflow.
Figure 8.
CPU block diagram (MAC unit not included)
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51/186
Central processing unit (CPU)
ST10F273M
7.1
Multiplier-accumulator unit (MAC)
The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order
to improve the performances of the ST10 Family in signal processing algorithms.
The standard ST10 CPU has been modified to include new addressing capabilities which
enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle.
This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a
repeat unit.
The co-processor instructions extend the ST10 CPU instruction set with multiply, multiply-
accumulate, 32-bit signed arithmetic operations.
Figure 9.
MAC unit architecture
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Doc ID 13453 Rev 4
ST10F273M
Central processing unit (CPU)
7.2
Instruction set summary
Table 28 lists the instructions of the ST10F273M. The detailed description of each
instruction can be found in the ST10 Family Programming Manual.
Table 28. Standard instruction set summary
Mnemonic
ADD(B)
Description
Bytes
Add word (byte) operands
2 / 4
2 / 4
2 / 4
2 / 4
2
ADDC(B)
SUB(B)
Add word (byte) operands with Carry
Subtract word (byte) operands
SUBC(B)
MUL(U)
DIV(U)
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-/16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
2
DIVL(U)
CPL(B)
2
2
NEG(B)
AND(B)
OR(B)
2
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
2 / 4
2 / 4
2 / 4
2
XOR(B)
BCLR
BSET
Set direct bit
2
BMOV(N)
BAND, BOR, BXOR
BCMP
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Compare direct bit to direct bit
4
4
4
Bitwise modify masked high/low byte of bit-addressable direct word
memory with immediate data
BFLDH/L
4
CMP(B)
Compare word (byte) operands
2 / 4
2 / 4
2 / 4
CMPD1/2
CMPI1/2
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct word GPR and
store result in direct word GPR
PRIOR
2
SHL / SHR
ROL / ROR
ASHR
Shift left/right direct word GPR
2
2
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
Move word (byte) data
2
MOV(B)
2 / 4
2 / 4
2 / 4
4
MOVBS
Move byte operand to word operand with sign extension
Move byte operand to word operand with zero extension
Jump absolute/indirect/relative if condition is met
Jump absolute to a code segment
MOVBZ
JMPA, JMPI, JMPR
JMPS
4
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Central processing unit (CPU)
ST10F273M
Bytes
Table 28. Standard instruction set summary (continued)
Mnemonic Description
Jump relative if direct bit is (not) set
J(N)B
JBC
4
4
4
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
JNBS
CALLA, CALLI,
CALLR
Call absolute/indirect/relative subroutine if condition is met
Call absolute subroutine in any code segment
4
4
4
CALLS
PCALL
Push direct word register onto system stack and call absolute
subroutine
TRAP
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
2
2
PUSH, POP
Push direct word register onto system stack and update register
with word operand
SCXT
4
RET
Return from intra-segment subroutine
Return from inter-segment subroutine
2
2
RETS
Return from intra-segment subroutine and pop direct word register
from system stack
RETP
2
RETI
Return from interrupt service subroutine
Software Reset
2
4
SRST
IDLE
Enter Idle mode
4
PWRDN
SRVWDT
DISWDT
EINIT
Enter Power-down mode (supposes NMI-pin being low)
Service Watchdog Timer
4
4
Disable Watchdog Timer
4
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
4
ATOMIC
EXTR
2
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
2
EXTP(R)
EXTS(R)
NOP
2 / 4
2 / 4
2
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Doc ID 13453 Rev 4
ST10F273M
Central processing unit (CPU)
7.3
MAC co-processor specific instructions
Table 29 lists the MAC instructions of the ST10F273M. The detailed description of each
instruction can be found in the ST10 Family Programming Manual. Note that all MAC
instructions are encoded on 4 bytes.
Table 29. MAC instruction set summary
Mnemonic
Description
Absolute value of the accumulator
CoABS
CoADD(2)
Addition
CoASHR(rnd)
CoCMP
Accumulator arithmetic shift right & optional round
Compare accumulator with operands
Load accumulator with operands
CoLOAD(-,2)
CoMAC(R,u,s,-,rnd)
(Un)signed/(Un)Signed Multiply-Accumulate & Optional Round
(Un)Signed/(Un)signed multiply-accumulate with parallel data move
& optional round
CoMACM(R)(u,s,-,rnd)
CoMAX / CoMIN
CoMOV
maximum / minimum of operands and accumulator
Memory to memory move
CoMUL(u,s,-,rnd)
CoNEG(rnd)
CoNOP
(Un)signed/(Un)signed multiply & optional round
Negate accumulator & optional round
No-operation
CoRND
Round accumulator
CoSHL / CoSHR
CoSTORE
Accumulator logical shift left / right
Store a MAC unit register
CoSUB(2,R)
Subtraction
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External bus controller
ST10F273M
8
External bus controller
All of the external memory accesses are performed by the on-chip external bus controller.
The EBC can be programmed to single chip mode when no external memory is required, or
to one of four different external memory access modes:
●
●
●
●
16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed
16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed
16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed
16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed
In demultiplexed bus modes addresses are output on PORT1 and data is input / output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use
PORT0 for input / output.
Timing characteristics of the external bus interface (memory cycle time, memory tri-state
time, length of ALE and read / write delay) are programmable giving the choice of a wide
range of memories and external peripherals.
Up to four independent address windows may be defined (using register pairs ADDRSELx /
BUSCONx) to access different resources and bus characteristics.
These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3
and BUSCON2 overrides BUSCON1.
All accesses to locations not covered by these four address windows are controlled by
BUSCON0. Up to five external CS signals (four windows plus default) can be generated in
order to save external glue logic. Access to very slow memories is supported by a ‘Ready’
function.
A HOLD / HLDA protocol is available for bus arbitration which shares external resources
with other bus masters.
The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN
once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In
master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to ‘1’ the
slave mode is selected where pin HLDA is switched to input. This directly connects the slave
controller to another master controller without glue logic.
For applications which require less external memory space, the address space can be
restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an
address space of 16 Mbytes is used, otherwise four, two or no address lines.
Chip select timing can be made programmable. By default (after reset), the CSx lines
change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the
SYSCON register the CSx lines change with the rising edge of ALE.
The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers.
When the READY function is enabled for a specific address window, each bus cycle within
the window must be terminated with the active level defined by bit RDYPOL in the
associated BUSCON register.
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ST10F273M
Interrupt system
9
Interrupt system
The interrupt response time for internal program execution is from 125ns to 300ns at
40 MHz CPU clock.
The ST10F273M architecture supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources (internal or external) to the
microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or
by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’
from the current CPU activity to perform a PEC service. A PEC service implies a single Byte
or Word data transfer between any two memory locations with an additional increment of
either the PEC source or destination pointer. An individual PEC transfer counter is implicitly
decremented for each PEC service except when performing in the continuous transfer
mode. When this counter reaches zero, a standard interrupt is performed to the
corresponding source related vector location. PEC services are very well suited to perform
the transmission or the reception of blocks of data. The ST10F273M has eight PEC
channels, each of them offers such fast interrupt-driven data transfer capabilities.
An interrupt control register which contains an interrupt request flag, an interrupt enable flag
and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its
related register, each source can be programmed to one of sixteen interrupt priority levels.
Once starting to be processed by the CPU, an interrupt service can only be interrupted by a
higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt sources has a dedicated vector location.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge,
falling edge or both edges).
Fast external interrupts may also have interrupt sources selected from other peripherals; for
2
example the CANx controller receive signals (CANx_RxD) and I C serial clock signal can be
used to interrupt the system.
Table 30 shows all the available ST10F273M interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Table 30. Interrupt sources
Source of interrupt or
PEC service request
Request
flag
Enable
flag
Interrupt
vector
Vector
location
Trap
number
CAPCOM Register 0
CAPCOM Register 1
CAPCOM Register 2
CAPCOM Register 3
CAPCOM Register 4
CAPCOM Register 5
CC0IR
CC1IR
CC2IR
CC3IR
CC4IR
CC5IR
CC0IE
CC1IE
CC2IE
CC3IE
CC4IE
CC5IE
CC0INT
CC1INT
CC2INT
CC3INT
CC4INT
CC5INT
00’0040h
00’0044h
00’0048h
00’004Ch
00’0050h
00’0054h
10h
11h
12h
13h
14h
15h
Doc ID 13453 Rev 4
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Interrupt system
ST10F273M
Table 30. Interrupt sources (continued)
Source of interrupt or
PEC service request
Request
flag
Enable
flag
Interrupt
vector
Vector
location
Trap
number
CAPCOM Register 6
CAPCOM Register 7
CAPCOM Register 8
CAPCOM Register 9
CAPCOM Register 10
CAPCOM Register 11
CAPCOM Register 12
CAPCOM Register 13
CAPCOM Register 14
CAPCOM Register 15
CAPCOM Register 16
CAPCOM Register 17
CAPCOM Register 18
CAPCOM Register 19
CAPCOM Register 20
CAPCOM Register 21
CAPCOM Register 22
CAPCOM Register 23
CAPCOM Register 24
CAPCOM Register 25
CAPCOM Register 26
CAPCOM Register 27
CAPCOM Register 28
CAPCOM Register 29
CAPCOM Register 30
CAPCOM Register 31
CAPCOM Timer 0
CC6IR
CC7IR
CC8IR
CC9IR
CC10IR
CC11IR
CC12IR
CC13IR
CC14IR
CC15IR
CC16IR
CC17IR
CC18IR
CC19IR
CC20IR
CC21IR
CC22IR
CC23IR
CC24IR
CC25IR
CC26IR
CC27IR
CC28IR
CC29IR
CC30IR
CC31IR
T0IR
CC6IE
CC7IE
CC8IE
CC9IE
CC10IE
CC11IE
CC12IE
CC13IE
CC14IE
CC15IE
CC16IE
CC17IE
CC18IE
CC19IE
CC20IE
CC21IE
CC22IE
CC23IE
CC24IE
CC25IE
CC26IE
CC27IE
CC28IE
CC29IE
CC30IE
CC31IE
T0IE
CC6INT
CC7INT
CC8INT
CC9INT
CC10INT
CC11INT
CC12INT
CC13INT
CC14INT
CC15INT
CC16INT
CC17INT
CC18INT
CC19INT
CC20INT
CC21INT
CC22INT
CC23INT
CC24INT
CC25INT
CC26INT
CC27INT
CC28INT
CC29INT
CC30INT
CC31INT
T0INT
00’0058h
00’005Ch
00’0060h
00’0064h
00’0068h
00’006Ch
00’0070h
00’0074h
00’0078h
00’007Ch
00’00C0h
00’00C4h
00’00C8h
00’00CCh
00’00D0h
00’00D4h
00’00D8h
00’00DCh
00’00E0h
00’00E4h
00’00E8h
00’00ECh
00’00F0h
00’0110h
00’0114h
00’0118h
00’0080h
00’0084h
00’00F4h
00’00F8h
00’0088h
00’008Ch
00’0090h
00’0094h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
44h
45h
46h
20h
21h
3Dh
3Eh
22h
23h
24h
25h
CAPCOM Timer 1
T1IR
T1IE
T1INT
CAPCOM Timer 7
T7IR
T7IE
T7INT
CAPCOM Timer 8
T8IR
T8IE
T8INT
GPT1Timer 2
T2IR
T2IE
T2INT
GPT1 Timer 3
T3IR
T3IE
T3INT
GPT1 Timer 4
T4IR
T4IE
T4INT
GPT2Timer 5
T5IR
T5IE
T5INT
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Doc ID 13453 Rev 4
ST10F273M
Interrupt system
Table 30. Interrupt sources (continued)
Source of interrupt or
PEC service request
Request
flag
Enable
flag
Interrupt
vector
Vector
location
Trap
number
GPT2 Timer 6
T6IR
CRIR
T6IE
CRIE
T6INT
CRINT
00’0098h
00’009Ch
00’00A0h
00’00A4h
00’00A8h
00’011Ch
00’00ACh
00’00B0h
00’00B4h
00’00B8h
00’00BCh
00’00FCh
00’0100h
00’0104h
00’0108h
00’010Ch
26h
27h
28h
29h
2Ah
47h
2Bh
2Ch
2Dh
2Eh
2Fh
3Fh
40h
41h
42h
43h
GPT2 CAPREL Register
A/D Conversion Complete
A/D Overrun Error
ASC0 Transmit
ADCIR
ADEIR
S0TIR
S0TBIR
S0RIR
S0EIR
SCTIR
SCRIR
SCEIR
PWMIR
XP0IR
XP1IR
XP2IR
XP3IR
ADCIE
ADEIE
S0TIE
S0TBIE
S0RIE
S0EIE
SCTIE
SCRIE
SCEIE
PWMIE
XP0IE
XP1IE
XP2IE
XP3IE
ADCINT
ADEINT
S0TINT
S0TBINT
S0RINT
S0EINT
SCTINT
SCRINT
SCEINT
PWMINT
XP0INT
XP1INT
XP2INT
XP3INT
ASC0 Transmit Buffer
ASC0 Receive
ASC0 Error
SSC Transmit
SSC Receive
SSC Error
PWM Channel 0...3
See Section 9.1
See Section 9.1
See Section 9.1
See Section 9.1
Hardware traps are exceptions or error conditions that arise during run-time. They cause
immediate non-maskable system reaction similar to a standard interrupt service (branching
to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). A hardware trap will interrupt any other program execution except when
another higher prioritized trap service is in progress. Hardware trap services cannot not be
interrupted by a standard interrupt or by PEC interrupts.
9.1
X-Peripheral interrupt
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some
constraints on the implementation of the new functionality. In particular, the additional X-
2
Peripherals SSC1, ASC1, I C, PWM1 and RTC need some resources to implement interrupt
and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt
management is proposed. In the next Figure 10, the principle is explained through a simple
diagram, which shows the basic structure replicated for each of the four X-interrupt available
vectors (XP0INT, XP1INT, XP2INT and XP3INT).
It is based on a set of 16-bit registers XIRxSEL (x = 0,1,2,3), divided in two portions each:
●
Byte High
Byte Low
XIRxSEL[15:8]
XIRxSEL[7:0]
Interrupt Enable bits
Interrupt Flag bits
●
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Interrupt system
ST10F273M
When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL
register) define a mask which controls which sources will be associated with the unique
available vector. If more than one source is enabled to issue the request, the service routine
will have to take care to identify the real event to be serviced. This can easily be done by
checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also
provide information about events which are not currently serviced by the interrupt controller
(since masked through the enable bits), allowing an effective software management also in
absence of the possibility to serve the related interrupt request: a periodic polling of the flag
bits may be implemented inside the user application.
Figure 10. X-Interrupt basic structure
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Table 31 summarizes the mapping of the different interrupt sources which shares the four X-
interrupt vectors.
Table 31. X-Interrupt detailed mapping
Interrupt source
CAN1 Interrupt
XP0INT
XP1INT
XP2INT
XP3INT
x
x
x
CAN2 Interrupt
I2C Receive
x
x
x
x
x
x
x
I2C Transmit
I2C Error
x
x
SSC1 Receive
SSC1 Transmit
SSC1 Error
x
x
x
x
x
x
ASC1 Receive
ASC1 Transmit
ASC1 Transmit Buffer
ASC1 Error
x
x
x
x
x
x
x
x
x
x
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Doc ID 13453 Rev 4
ST10F273M
Interrupt system
Table 31. X-Interrupt detailed mapping (continued)
Interrupt source XP0INT XP1INT
XP2INT
XP3INT
x
x
PLL Unlock / OWD
PWM1 Channel 3...0
x
9.2
Exception and error traps list
Table 32 shows all of the possible exceptions or error conditions that can arise during run-
time.
Table 32. Trap priorities
Trap
flag
Trap
vector
Vector
location
Trap
number
Trap
Exception condition
priority(1)
Reset Functions:
Hardware Reset
Software Reset
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
00h
00h
00h
III
III
III
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008h
00’0010h
00’0018h
02h
04h
06h
II
II
II
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
MAC Interruption
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLINA
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
I
I
I
I
I
I
ILLBUS
Reserved
[002Ch - 003Ch] [0Bh - 0Fh]
Any
Current
CPU
Priority
Software Traps
TRAP Instruction
Any
0000h – 01FCh
[00h - 7Fh]
in steps of 4h
1. - All the class B traps have the same trap number (and vector) and the same lower priority compared to the
class A traps and to the resets.
- Each class A trap has a dedicated trap number (and vector). They are prioritized in the second priority
level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.
Doc ID 13453 Rev 4
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Capture / compare (CAPCOM) units
ST10F273M
10
Capture / compare (CAPCOM) units
The ST10F273M has two 16-channel CAPCOM units which support generation and control
of timing sequences on up to 32 channels with a maximum resolution of 200ns at 40 MHz
CPU clock.
The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation (PMW), digital to analog (D/A) conversion,
software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases
for the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows precise
adjustments to application specific requirements. In addition, external count inputs for
CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers
relative to external events.
Each of the two capture/compare register arrays contain 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7
or T8, respectively), and programmed for capture or compare functions. Each of the 32
registers has one associated port pin which serves as an input pin for triggering the capture
function, or as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current contents
of the allocated timer will be latched (captured) into the capture/compare register in
response to an external event at the port pin which is associated with this register. In
addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a negative external signal transition at
the pin can be selected as the triggering event. The contents of all registers which have
been selected for one of the five compare modes are continuously compared with the
contents of the allocated timers.
When a match occurs between the timer value and the value in a capture / compare
register, specific actions will be taken based on the selected compare mode.
The input frequencies f , for the timer input selector Tx, are determined as a function of the
Tx
CPU clocks. The timer input frequencies, resolution and periods which result from the
selected prescaler option in TxI when using a 40 MHz CPU clock are listed in Table 34.
The numbers for the timer periods are based on a reload value of 0000h. Note that some
numbers may be rounded off to three significant figures.
Table 33. Compare modes
Compare modes
Function
Mode 0
Mode 1
Mode 2
Interrupt-only compare mode; several compare interrupts per timer period are possible
Pin toggles on each compare match; several compare events per timer period are possible
Interrupt-only compare mode; only one compare interrupt per timer period is generated
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Doc ID 13453 Rev 4
ST10F273M
Capture / compare (CAPCOM) units
Table 33. Compare modes (continued)
Compare modes
Function
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per
timer period is generated
Mode 3
Two registers operate on one pin; pin toggles on each compare match; several compare
events per timer period are possible.
Double Register mode
Table 34. CAPCOM timer input frequencies, resolutions and periods at 40 MHz
Timer input selection TxI
fCPU = 40 MHz
000b
001b
010b
011b
100b
101b
110b
111b
Prescaler for
fCPU
8
16
32
64
128
256
512
1024
Input frequency
Resolution
Period
5 MHz
200ns
2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz
400ns
0.8µs
1.6µs
3.2µs
6.4µs
12.8µs
25.6µs
1.678s
13.1ms
26.2ms
52.4ms
104.8ms
209.7ms
419.4ms
838.9ms
Doc ID 13453 Rev 4
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General purpose timer unit
ST10F273M
11
General purpose timer unit
The GPT unit is a flexible multifunctional timer/counter structure which is used for time
related tasks such as event timing and counting, pulse width and duty cycle measurements,
pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized
into two separate modules GPT1 and GPT2. Each timer in each module may operate
independently in several different modes, or may be concatenated with another timer of the
same module.
11.1
GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for
one of four basic modes of operation: timer, gated timer, counter mode and incremental
interface mode.
In timer mode, the input clock for a timer is derived from the CPU clock, divided by a
programmable prescaler.
In counter mode, the timer is clocked in reference to external events.
Pulse width or duty cycle measurement is supported in gated timer mode where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input.
Table 35 lists the timer input frequencies, resolution and periods for each prescaler option at
40 MHz CPU clock.
In Incremental Interface mode, the GPT1 timers (T2, T3, T4) can be directly connected to
the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals so that the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow /
underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
high resolution of long duration measurements.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or
capture registers for timer T3.
Table 35. GPT1 timer input frequencies, resolutions and periods at 40 MHz
Timer input selection T2I / T3I / T4I
fCPU = 40 MHz
000b
001b
010b
011b
100b
101b
110b
111b
Prescaler factor
Input frequency
Resolution
8
16
32
64
128
256
512
1024
5 MHz
200ns
13.1ms
2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz
400ns
0.8µs
1.6µs
3.2µs
6.4µs
12.8µs
25.6µs
1.678s
Period maximum
26.2ms
52.4ms
104.8ms 209.7ms
419.4ms
838.9ms
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Doc ID 13453 Rev 4
ST10F273M
General purpose timer unit
Figure 11. Block diagram of GPT1
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Doc ID 13453 Rev 4
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General purpose timer unit
ST10F273M
11.2
GPT2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock which is derived from the CPU clock via a programmable prescaler or with
external signals. The count direction (up/down) for each timer is programmable by software
or may additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin
(T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL
register may capture the contents of timer T5 based on an external signal transition on the
corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture
procedure. This allows absolute time differences to be measured or pulse multiplication to
be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1
timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental
Interface mode.
Table 36 lists the timer input frequencies, resolution and periods for each prescaler option at
40 MHz CPU clock.
Table 36. GPT2 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T5I / T6I
fCPU = 40 MHz
000b
001b
010b
011b
100b
101b
110b
111b
Prescaler factor
Input frequency
Resolution
4
8
16
32
64
128
256
512
10 MHz
100ns
5 MHz
200ns
13.1ms
2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz
400ns
0.8µs
1.6µs
3.2µs
6.4µs
12.8µs
Period maximum 6.55ms
26.2ms
52.4ms
104.8ms 209.7ms
419.4ms
838.9ms
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Doc ID 13453 Rev 4
ST10F273M
General purpose timer unit
Figure 12. Block diagram of GPT2
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Doc ID 13453 Rev 4
67/186
PWM modules
ST10F273M
12
PWM modules
Two pulse width modulation modules are available on ST10F273M: standard PWM0 and
XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned
or center-aligned PWM. In addition, the PWM modules can generate PWM burst signals and
single shot outputs. Table 37 shows the PWM frequencies for different resolutions. The level
of the output signals is selectable and the PWM modules can generate interrupt requests.
Figure 13. Block diagram of PWM module
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Table 37. PWM unit frequencies and resolutions at 40 MHz CPU clock
Mode 0
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU Clock/1
CPU Clock/64
25ns
156.25 kHz
2.44 kHz
39.1 kHz
610 Hz
9.77 kHz
152.6 Hz
2.44 Hz
610 Hz
9.54 Hz
1.6µs
38.15 Hz
Mode 1
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU Clock/1
CPU Clock/64
25ns
78.12 kHz
1.22 kHz
19.53 kHz
305.17Hz
4.88 kHz
76.29 Hz
1.22 kHz
19.07 Hz
305.2 Hz
4.77 Hz
1.6µs
68/186
Doc ID 13453 Rev 4
ST10F273M
Parallel ports
13
Parallel ports
13.1
Introduction
The ST10F273M MCU provides up to 111 I/O lines with programmable features. These
capabilities permit this MCU to be adapted to a wide range of applications.
The ST10F273M I/O lines are organized in nine groups:
●
Port 0 is a two time 8-bit port named P0L (low as less significant byte) and P0H (high
as most significant byte)
●
●
●
●
●
●
Port 1 is a two time 8-bit port named P1L and P1H
Port 2 is a 16-bit port
Port 3 is a 15-bit port (P3.14 line is not implemented)
Port 4 is an 8-bit port
Port 5 is a 16-bit port input only
Port 6, Port 7 and Port 8 are 8-bit ports
These ports may be used as general purpose bidirectional input or output, software
controlled with dedicated registers.
For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured
(bitwise) for push-pull or open drain operation using ODPx registers.
The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of
a pin is clocked into the input latch once per state time, regardless whether the port is
configured for input or output. The threshold is selected with PICON and XPICON registers
control bits.
A write operation to a port pin configured as an input causes the value to be written into the
port output latch, while a read operation returns the latched state of the pin itself. A read-
modify-write operation reads the value of the pin, modifies it, and writes it back to the output
latch.
Writing to a pin configured as an output (DPx.y = ‘1’) causes the output latch and the pin to
have the written value, since the output buffer is enabled. Reading this pin returns the value
of the output latch. A read-modify-write operation reads the value of the output latch,
modifies it, and writes it back to the output latch, thus also modifying the level at the pin.
I/O lines support an alternate function which is detailed in the following description of each
port.
13.2
I/O’s special features
13.2.1
Open drain mode
Some of the I/O ports of ST10F273M support the open drain capability. This programmable
feature may be used with an external pull-up resistor, in order to get an AND wired logical
function.
This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections)
and is controlled through the respective Open Drain Control Registers ODPx.
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Parallel ports
ST10F273M
13.2.2
Input threshold control
The standard inputs of the ST10F273M determine the status of input signals according to
TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be
selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds
are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs
from toggling while the respective input signal level is near the thresholds.
The Port Input Control registers PICON and XPICON are used to select these thresholds for
each byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and
P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each.
All options for individual direction and output mode control are available for each pin,
independent of the selected input threshold.
13.3
Alternate port functions
Each port line has one associated programmable alternate input or output function.
●
PORT0 and PORT1 may be used as address and data lines when accessing external
memory. Additionally, PORT1 provides:
–
–
Input capture lines
8 additional analog input channels to the A/D converter
●
Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of
the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module
and of the ASC1.
Port 2 is also used for fast external interrupt inputs and for timer 7 input.
●
●
Port 3 includes the alternate functions of timers, serial interfaces, the optional bus
control signal BHE and the system clock output (CLKOUT).
Port 4 outputs the additional segment address bit A23...A16 in systems where more
than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I C
2
lines are provided.
●
●
Port 5 is used as analog input channels of the A/D converter or as timer control signals.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals and the SSC1 lines.
If the alternate output function of a pin is to be used, the direction of this pin must be
programmed for output (DPx.y = ‘1’), except for some signals that are used directly after
reset and are configured automatically. Otherwise the pin remains in the high-impedance
state and is not effected by the alternate output function. The respective port latch should
hold a ‘1’, because its output is ANDed with the alternate output data (except for PWM
output signals).
If the alternate input function of a pin is used, the direction of the pin must be programmed
for input (DPx.y = ‘0’) if an external device is driving the pin. The input direction is the default
after reset. If no external device is connected to the pin, however, the direction for this pin
can also be set to output. In this case, the pin reflects the state of the port output latch.
Thus, the alternate input function reads the value stored in the port output latch. This can be
used for testing purposes to allow a software trigger of an alternate input function by writing
to the port output latch.
On most of the port lines, the user software is responsible for setting the proper direction
when using an alternate input or output function of a pin.
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ST10F273M
Parallel ports
This is done by setting or clearing the direction control bit DPx.y of the pin before enabling
the alternate function.
There are port lines, however, where the direction of the port line is switched automatically.
For instance, in the multiplexed external bus modes of PORT0, the direction must be
switched several times for an instruction fetch in order to output the addresses and to input
the data.
Obviously, this cannot be done through instructions. In these cases, the direction of the port
line is switched automatically by hardware if the alternate function of such a pin is enabled.
To determine the appropriate level of the port output latches, check how the alternate data
output is combined with the respective port latch output.
There is one basic structure for all port lines with only an alternate input function. Port lines
with only an alternate output function, however, have different structures due to the way the
direction of the pin is switched and depending on whether the pin is accessible by the user
software or not in the alternate function mode.
All port lines that are not used for these alternate functions may be used as general purpose
I/O lines.
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A/D converter
ST10F273M
14
A/D converter
A 10-bit A/D converter with 24 multiplexed input channels and a sample and hold circuit is
integrated on-chip. An automatic self-calibration adjusts the A/D converter module to
process parameter variations at each reset event. The sample time (for loading the
capacitors) and the conversion time is programmable and can be adjusted to the external
circuitry.
The ST10F273M has 16 + 8 multiplexed input channels on Port 5 and Port 1 respectively.
The selection between Port 5 and Port 1 is made via a bit in an XBus register. Refer to the
User Manual for a detailed description.
A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog
channels (with higher restrictions when overload conditions occur); in particular, Port 5
channels are more accurate than the Port 1 channels. Refer to Section 24: Electrical
characteristics for details.
The A/D converter input bandwidth is limited by the achievable accuracy: Supposing a
maximum error of 0.5LSB (2mV) impacting the global TUE (TUE depends also on other
causes), in worst case of temperature and process, the maximum frequency for a sine wave
analog signal is around 7.5 kHz. Of course, to reduce the effect of the input signal variation
on the accuracy down to 0.05LSB, the maximum input frequency of the sine wave must be
reduced to 800 Hz.
If a static signal is applied during the sampling phase, a series resistance shall not be
greater than 20kΩ (this taking into account eventual input leakage). It is suggested to not
connect any capacitance on analog input pins, in order to reduce the effect of charge
partitioning (and consequent voltage drop error) between the external and the internal
capacitance: In case an RC filter is necessary, the external capacitance must be greater
than 10nF to minimize the accuracy impact.
Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt
request is generated when the result of a previous conversion has not been read from the
result register at the time the next conversion is complete, or the next conversion is
suspended until the previous result has been read. For applications which require less than
16+8 analog input channels, the rning channel inputs can be used as digital input port pins.
The A/D converter of the ST10F273M supports different conversion modes:
●
●
●
Single channel single conversion: The analog level of the selected channel is
sampled once and converted. The result of the conversion is stored in the ADDAT
register.
Single channel continuous conversion: The analog level of the selected channel is
repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
register.
Auto scan single conversion: The analog level of the selected channels are sampled
once and converted. After each conversion the result is stored in the ADDAT register.
The data can be transferred to the RAM by interrupt software management or using the
powerful Peripheral Event Controller (PEC) data transfer.
●
Auto scan continuous conversion: The analog level of the selected channels are
repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
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ST10F273M
A/D converter
register. The data can be transferred to the RAM by interrupt software management or
using the PEC data transfer.
●
●
Wait for ADDAT read mode: When using continuous modes, in order to avoid to
overwrite the result of the current conversion by the next one, the ADWR bit of ADCON
control register must be activated. Then, until the ADDAT register is read, the new
result is stored in a temporary buffer and the conversion is on hold.
Channel injection mode: When using continuous modes, a selected channel can be
converted in between without changing the current operating mode. The 10-bit data of
the conversion are stored in ADRES field of ADDAT2. The current continuous mode
remains active after the single conversion is completed.
A full calibration sequence is performed after a reset. This full calibration lasts up to 40630
CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It
compensates the capacitance mismatch, so the calibration procedure does not need any
update during normal operation.
No conversion can be performed during this time: The bit ADBSY shall be polled to verify
when the calibration is over, and the module is able to start a conversion.
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Serial channels
ST10F273M
15
Serial channels
Serial communication with other microcontrollers, microprocessors, terminals or external
peripheral components is provided by up to four serial interfaces: two asynchronous /
synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial
channel (SSC0 and SSC1). Dedicated baudrate generators set up all standard baudrates
without the requirement of oscillator tuning. For transmission, reception and erroneous
reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A
more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and
SSC1 (XBUS mapped).
15.1
15.2
Asynchronous / synchronous serial interfaces
The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial
communication between the ST10F273M and other microcontrollers, microprocessors or
external peripherals.
ASCx in asynchronous mode
In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop
bits can be selected. Parity framing and overrun error detection is provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. Full-
duplex communication up to 1.25 Mbaud (at 40 MHz of f
) is supported in this mode.
CPU
Table 38. ASC asynchronous baudrates by reload value and deviation errors
S0BRS = ‘0’, fCPU = 40 MHz S0BRS = ‘1’, fCPU = 40 MHz
Reload value
Reload value
(hex)
Baudrate (baud) Deviation error
Baudrate (baud) Deviation error
(hex)
1 250 000
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
600
0.0ꢀ / 0.0ꢀ
+1.5ꢀ / -7.0ꢀ
+1.5ꢀ / -3.0ꢀ
+1.7ꢀ / -1.4ꢀ
+0.2ꢀ / -1.4ꢀ
+0.2ꢀ / -0.6ꢀ
+0.2ꢀ / -0.2ꢀ
+0.2ꢀ / 0.0ꢀ
0.1ꢀ / 0.0ꢀ
0000 / 0000
000A / 000B
0015 / 0016
001F / 0020
0040 / 0041
0081 / 0082
0103 / 0104
0207 / 0208
0410 / 0411
0822 / 0823
1045 / 1046
1FE8 / 1FE9
833 333
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
600
0.0ꢀ / 0.0ꢀ
+6.3ꢀ / -7.0ꢀ
+6.3ꢀ / -0.8ꢀ
+3.3ꢀ / -1.4ꢀ
+0.9ꢀ / -1.4ꢀ
+0.9ꢀ / -0.2ꢀ
+0.4ꢀ / -0.2ꢀ
+0.1ꢀ / -0.2ꢀ
+0.1ꢀ / -0.1ꢀ
+0.1ꢀ / 0.0ꢀ
0.0ꢀ / 0.0ꢀ
0000 / 0000
0006 / 0007
000D / 000E
0014 / 0015
002A / 002B
0055 / 0056
00AC / 00AD
015A / 015B
02B5 / 02B6
056B / 056C
0AD8 / 0AD9
1FE8 / 1FE9
0.0ꢀ / 0.0ꢀ
300
0.0ꢀ / 0.0ꢀ
300
153
0.0ꢀ / 0.0ꢀ
102
0.0ꢀ / 0.0ꢀ
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Doc ID 13453 Rev 4
ST10F273M
Serial channels
Note:
The deviation errors given in the Table 38 are rounded off. To avoid deviation errors use a
baudrate crystal (providing a multiple of the ASC0 sampling frequency).
15.3
ASCx in synchronous mode
In synchronous mode, data is transmitted or received synchronously to a shift clock which is
generated by the ST10F273M. Half-duplex communication up to 5 Mbaud (at 40 MHz of
f
) is possible in this mode.
CPU
Table 39. ASC synchronous baudrates by reload value and deviation errors
S0BRS = ‘0’, fCPU = 40 MHz S0BRS = ‘1’, fCPU = 40 MHz
Reload value
Reload value
(hex)
Baudrate (baud) Deviation error
Baudrate (baud) Deviation error
(hex)
5 000 000
112 000
56 000
38 400
19 200
9 600
0.0ꢀ / 0.0ꢀ
+1.5ꢀ / -0.8ꢀ
+0.3ꢀ / -0.8ꢀ
+0.2ꢀ / -0.6ꢀ
+0.2ꢀ / -0.2ꢀ
+0.2ꢀ / 0.0ꢀ
+0.1ꢀ / 0.0ꢀ
0.0ꢀ / 0.0ꢀ
0.0ꢀ / 0.0ꢀ
0.0ꢀ / 0.0ꢀ
0.0ꢀ / 0.0ꢀ
0000 / 0000
002B / 002C
0058 / 0059
0081 / 0082
0103 / 0104
0207 / 0208
0410 / 0411
0822 / 0823
1045 / 1046
15B2 / 15B3
1FE8 / 1FE9
3 333 333
112 000
56 000
38 400
19 200
9 600
0.0ꢀ / 0.0ꢀ
+2.6ꢀ / -0.8ꢀ
+0.9ꢀ / -0.8ꢀ
+0.9ꢀ / -0.2ꢀ
+0.4ꢀ / -0.2ꢀ
+0.1ꢀ / -0.2ꢀ
+0.1ꢀ / -0.1ꢀ
+0.1ꢀ / 0.0ꢀ
0.0ꢀ / 0.0ꢀ
0000 / 0000
001C / 001D
003A / 003B
0055 / 0056
00AC / 00AD
015A / 015B
02B5 / 02B6
056B / 056C
0AD8 / 0AD9
15B2 / 15B3
1FFD / 1FFE
4 800
4 800
2 400
2 400
1 200
1 200
900
600
0.0ꢀ / 0.0ꢀ
612
407
0.0ꢀ / 0.0ꢀ
Note:
The deviation errors given in the are rounded off. To avoid deviation errors use a baudrate
crystal (providing a multiple of the ASC0 sampling frequency).
15.4
High speed synchronous serial interfaces
The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible high-
speed serial communication between the ST10F273M and other microcontrollers,
microprocessors or external peripherals.
The SSCx supports full-duplex and half-duplex synchronous communication. The serial
clock signal can be generated by the SSCx itself (master mode) or be received from an
external master (slave mode). Data width, shift direction, clock polarity and phase are
programmable.
This allows communication with SPI-compatible devices. Transmission and reception of data
is double-buffered. A 16-bit baudrate generator provides the SSCx with a separate serial
clock signal. The serial channel SSCx has its own dedicated 16-bit baudrate generator with
16-bit reload capability, allowing baudrate generation independent from the timers.
Doc ID 13453 Rev 4
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Serial channels
ST10F273M
Table 40 lists some possible baudrates against the required reload values and the resulting
bit times for the 40 MHz CPU clock. The maximum is limited to 8 Mbaud.
Table 40. SSC synchronous baudrate and reload values
Baudrate for fCPU = 40 MHz
Bit time
Reload value
Reserved
-
0000h
0001h
0002h
0003h
0007h
0013h
00C7h
07CFh
4E1Fh
FF4Eh
Can be used only with fCPU = 32 MHz (or lower)
-
6.6 Mbaud
5 Mbaud
150ns
200ns
400ns
1µs
2.5 Mbaud
1 Mbaud
100 Kbaud
10 Kbaud
1 Kbaud
10µs
100µs
1ms
306 baud
3.26ms
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ST10F273M
I2C interface
16
I2C interface
2
The integrated I C Bus Module handles the transmission and reception of frames over the
2
2
two-line SDA/SCL in accordance with the I C Bus specification. The I C Module can
operate in slave mode, in master mode or in multi-master mode. It can receive and transmit
data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s
2
(both Standard and Fast I C bus modes are supported).
The module can generate three different types of interrupt:
●
●
●
requests related to bus events, such as start or stop events, or arbitration lost
requests related to data transmission
requests related to data reception
These requests are issued to the interrupt controller by three different lines, and identified as
Error, Transmit, and Receive interrupt lines.
2
When the I C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and
P4.7 (where SCL and SDA are respectively mapped as alternate functions) are
automatically configured as bidirectional open-drain: the value of the external pull-up
resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin
configuration.
2
When the I C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O
controlled by P4, DP4 and ODP4.
2
The speed of the I C interface can be selected between Standard mode (0 to 100 kHz) and
2
Fast I C mode (100 to 400 kHz).
Doc ID 13453 Rev 4
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CAN modules
ST10F273M
17
CAN modules
The two integrated CAN modules (CAN1 and CAN2) are identical and handle the
completely autonomous transmission and reception of CAN frames according to the CAN
specification V2.0 part B (active). It is based on the C-CAN specification.
Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers
as well as extended frames with 29-bit identifiers.
Because of duplication of the CAN controllers, the following adjustments are to be
considered:
●
Same internal register addresses of both CAN controllers, but with base addresses
differing in address bit A8; separate chip select for each CAN module. Refer to
Section 4: Memory organization on page 21.
●
●
●
●
●
The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and
the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.
The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and
the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.
Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS
interrupt lines together with other X-Peripherals sharing the four vectors.
The CAN modules must be selected with corresponding CANxEN bit of XPERCON
register before the bit XPEN of SYSCON register is set.
The reset default configuration is: CAN1 enabled, CAN2 disabled.
Note:
If one or both CAN modules is used, Port 4 cannot be programmed to output all eight
segment address lines. Thus, only four segment address lines can be used, reducing the
external memory space to 5 Mbytes (1 Mbyte per CS line).
17.1
Configuration support
It is possible that both CAN controllers are working on the same CAN bus, supporting
together up to 64 message objects. In this configuration, both receive signals and both
transmit signals are linked together when using the same CAN transceiver. This
configuration is especially supported by providing open drain outputs for the CAN1_Txd and
CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4:
in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with
P4.7 (transmit lines configured to be configured as Open-Drain).
The user may also map internally both CAN modules on the same pins P4.5 and P4.6. In
2
this way, P4.4 and P4.7 can be used either as general purpose I/O lines, or used for I C
interface. This is possible by setting bit CANPAR of the XMISC register. To access this
register it is necessary to set bit XMISCEN of the XPERCON register and bit XPEN of the
SYSCON register.
17.2
CAN bus configurations
Depending on the application, CAN bus configuration may be one single bus with a single or
multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F273M can
support both configurations.
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Doc ID 13453 Rev 4
ST10F273M
CAN modules
17.2.1
Single CAN bus
The single CAN bus multiple interfaces configuration may be implemented using two CAN
transceivers as shown in Figure 14.
Figure 14. Connection to single CAN bus via separate CAN transceivers
;0,6&ꢎ&$13$5ꢂ ꢂꢊ
&$1ꢀ
5; 7;
&$1ꢁ
5; 7;
3ꢈꢎꢄ
3ꢈꢎꢅ 3ꢈꢎꢈ
3ꢈꢎꢋ
&$1
&$1
WUDQVFHLYHU
WUDQVFHLYHU
&$1B+
&$1B/
&$1ꢂEXV
("1($'5ꢀꢀꢁꢂꢂ
The ST10F273M also supports single CAN bus multiple (dual) interfaces using the open
drain option of the CANx_TxD output as shown in Figure 15. Thanks to the OR-Wired
Connection, only one transceiver is required. In this case the design of the application must
take in account the wire length and the noise environment.
Figure 15. Connection to single CAN bus via common CAN transceivers
;0,6&ꢎ&$13$5ꢂ ꢂꢊ
&$1ꢀ
5; 7;
&$1ꢁ
5; 7;
ꢐꢄ9
ꢁꢎꢋN:
3ꢈꢎꢄ
3ꢈꢎꢅ 3ꢈꢎꢈ
2'
3ꢈꢎꢋ
2'
&$1
WUDQVFHLYHU
&$1B+
&$1B/
&$1ꢂEXV
2'ꢂ ꢂ2SHQꢂ'UDLQꢂ2XWSXW
("1($'5ꢀꢀꢁꢂꢇ
Doc ID 13453 Rev 4
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CAN modules
ST10F273M
17.2.2
Multiple CAN bus
The ST10F273M provides two CAN interfaces to support such kind of bus configuration as
shown in Figure 16.
Figure 16. Connection to two different CAN buses (for example for gateway
application)
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17.2.3
Parallel mode
In addition to previous configurations, a parallel mode is supported. This is shown in
Figure 17.
Figure 17. Connection to one CAN bus with internal parallel mode enabled
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1. P4.4 and P4.7 when not used as CAN functions can be used as general purpose I/O while they cannot be
used as external bus address lines.
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Doc ID 13453 Rev 4
ST10F273M
Real time clock
18
Real time clock
The Real Time Clock is an independent timer, in which the clock is derived directly from the
clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator)
so that it can continue running even in Idle or Power-down modes (if so enabled). Registers
access is implemented onto the XBUS. This module is designed with the following
characteristics:
●
generation of the current time and date for the system
●
cyclic time based interrupt, on Port2 external interrupts every “RTC basic clock tick”
and after n ’RTC basic clock ticks’ (n is programmable) if enabled
●
●
58-bit timer for long term measurement
capability to exit the ST10 chip from Power-down mode (if PWDCFG of SYSCON set)
after a programmed delay
The real time clock is based on two main blocks of counters. The first block is a prescaler
which generates a basic reference clock (for example, a 1 second period). This basic
reference clock is provided by the 20-bit DIVIDER. This 20-bit counter is driven by an input
clock derived from the on-chip CPU clock, predivided by a 1/64 fixed counter. This 20-bit
counter is loaded at each basic reference clock period with the value of the 20-bit
PRESCALER register. The value of the 20-bit RTCP register determines the period of the
basic reference clock.
A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The
second block of the RTC is a 32-bit counter that may be initialized with the current system
time. This counter is driven with the basic reference clock signal. In order to provide an
alarm function the contents of the counter is compared with a 32-bit alarm register. The
alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI),
may be generated when the value of the counter matches the alarm register.
The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external
interrupt via the EXISEL register of port 2 and wake up the ST10 chip when running power-
down mode. Using the RTCOFF bit of the RTCCON register, the user may switch off the
clock oscillator when entering the power-down mode.
The last function implemented in the RTC is to switch off the main on-chip oscillator and the
32 kHz on chip oscillator if the ST10 enters the Power-down mode, so that the chip can be
fully switched off (if RTC is disabled).
At power-on, and after Reset phase, if the presence of a 32 kHz oscillation on XTAL3 /
XTAL4 pins is detected, then the RTC counter is driven by this low frequency reference
clock: when Power-down mode is entered, the RTC can either be stopped or left running,
and in both the cases the main oscillator is turned off, reducing the power consumption of
the device to the minimum required to keep on running the RTC counter and relative
reference oscillator. This is also valid if Standby mode is entered (switching off the main
supply V ), since both the RTC and the low power oscillator (32 kHz) are biased by the
DD
V
. Vice versa, when at power on and after Reset, the 32 kHz is not present, the main
STBY
oscillator drives the RTC counter, and since it is powered by the main power supply, it
cannot be maintained running in Standby mode, while in Power-down mode the main
oscillator is maintained running to provide the reference to the RTC module (if not disabled).
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Watchdog timer
ST10F273M
19
Watchdog timer
The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from
malfunctioning for long periods of time.
The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in
the time interval until the EINIT (end of initialization) instruction has been executed.
Therefore, the chip start-up procedure is always monitored. The software must be designed
to service the watchdog timer before it overflows. If, due to hardware or software related
failures, the software fails to do so, the watchdog timer overflows and generates an internal
hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components
to be reset.
Each of the different reset sources is indicated in the WDTCON register:
●
●
●
Watchdog Timer Reset in case of an overflow
Software Reset in case of execution of the SRST instruction
Short,Long and Power-On Reset in case of hardware reset (and depending of reset
pulse duration and RPD pin configuration)
The indicated bits are cleared with the EINIT instruction. The source of the reset can be
identified during the initialization phase.
The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high
byte of the watchdog timer register can be set to a prespecified reload value (stored in
WDTREL).
Each time it is serviced by the application software, the high byte of the watchdog timer is
reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced
Table 41 shows the watchdog time range for 40 MHz CPU clock.
Table 41. WDTREL reload value
Prescaler for fCPU = 40 MHz
Reload value in WDTREL
2 (WDTIN = ‘0’)
128 (WDTIN = ‘1’)
FFh
00h
12.8µs
819.2µs
209.7ms
3.277ms
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System reset
20
System reset
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in Table 42.
Table 42. Reset event definition
RPD
Reset source
Flag
Conditions
status
Power-on reset
PONR
Low
Low
Power-on
(1)
Asynchronous hardware reset
tRSTIN >
LHWR
Synchronous long hardware
reset
High
High
t
RSTIN > (1032 + 12)TCL + max(4 TCL, 500ns)
RSTIN > max(4 TCL, 500ns)
Synchronous short hardware
reset
t
SHWR
tRSTIN ≤ (1032 + 12)TCL + max(4 TCL, 500ns)
(2)
(3)
Watchdog timer reset
Software reset
WDTR
SWR
WDT overflow
SRST instruction execution
1. RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
2. See next Section 20.1 for more details on minimum reset pulse duration
3. The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD
low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
Sections 20.4, 20.5 and 20.6).
The figures in the upcoming sections 20.2, 20.3, 20.5 and 20.6 use the following
terminology:
●
transparent = level of the pin affects the internal reset logic
not transparent = level of the pin does not affect internal logic
●
20.1
Input filter
On the RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all spikes
shorter than 50ns. On the other hand, a valid pulse longer than 500ns is required for the
ST10 to recognize a reset command. In between 50ns and 500ns a pulse can either be
filtered or recognized as valid, depending on the operating conditions and process
variations.
For this reason all minimum durations mentioned in this chapter for the different kinds of
reset events must be carefully evaluated, taking into account the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input
reset pulse duration, the operating frequency is a key factor.
Examples:
●
●
For a CPU clock of 40 MHz, 4 TCL is 50ns, so it would be filtered. In this case the
minimum becomes the one imposed by the filter (that is 500ns).
For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula
is coherent with the limit imposed by the filter.
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System reset
ST10F273M
20.2
Asynchronous reset
An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low
level. Then the ST10F273M is immediately (after the input filter delay) forced in reset default
state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all
internal/external bus cycles, it switches buses (data, address and control signals) and I/O
pin drivers to high-impedance, it pulls high Port0 pins.
Note:
If an asynchronous reset occurs during a read or write phase in internal memories, the
content of the memory itself could be corrupted: To avoid this, synchronous reset usage is
strongly recommended.
Power-on reset
The asynchronous reset must be used during the power-on of the device. Depending on
crystal or resonator frequency, the on-chip oscillator needs about 1ms to 10ms to stabilize
(refer to Section 24: Electrical characteristics), with an already stable V . The logic of the
DD
ST10F273M does not need a stabilized clock signal to detect an asynchronous reset, so it is
suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the
RPD pin must be held at low level until the device clock signal is stabilized and the system
configuration value on Port0 is settled.
At power-on it is important to respect some additional constraints introduced by the start-up
phase of the different embedded modules.
In particular the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8V
for the core logic: this time is computed from when the external reference (V ) becomes
DD
stable (inside specification range, that is at least 4.5V). This is a constraint for the
application hardware (external voltage regulator): the RSTIN pin assertion shall be extended
to guarantee the voltage regulator stabilization.
A second constraint is imposed by the embedded Flash. When booting from internal
memory, starting from RSTIN releasing, it needs a maximum of 1ms for its initialization:
before that, the internal reset (RST signal) is not released, so the CPU does not start code
execution in internal memory.
Note:
This is not true if external memory is used (pin EA held low during reset phase). In this case,
once RSTIN pin is released, and after few CPU clock (Filter delay plus 3...8 TCL), the
internal reset signal RST is released as well, so the code execution can start immediately
after. Obviously, an eventual access to the data in internal Flash is forbidden before its
initialization phase is completed: an eventual access during starting phase will return FFFFh
(just at the beginning), while later 009Bh (an illegal opcode trap can be generated).
At power-on, the RSTIN pin shall be tied low for a minimum time that includes also the start-
up time of the main oscillator (t
= 1ms for resonator, 10ms for crystal) and PLL
STUP
synchronization time (t
= 200µs): this means that if the internal Flash is used, the
PSUP
RSTIN pin could be released before the main oscillator and PLL are stable to recover some
time in the start-up phase (Flash initialization only needs stable V , but does not need
18
stable system clock since an internal dedicated oscillator is used).
Warning: It is recommended to provide the external hardware with a
current limitation circuitry. This is necessary to avoid
permanent damage of the device during the power-on
transient, when the capacitance on V pin is charged. For
18
the on-chip voltage regulator functionality 10nF is sufficient:
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Doc ID 13453 Rev 4
ST10F273M
System reset
In any case, a maximum of 100nF on V pin should not
18
generate problems of over-current (higher value is allowed if
current is limited by the external hardware). External current
limitation is nevertheless also recommended to avoid risks of
damage in case of a temporary short between V and
18
ground: The internal 1.8V drivers are sized to drive currents
of several tens of amps, so the current must be limited by the
external hardware.
The limit of current is imposed by power dissipation
considerations (refer to Section 24: Electrical
characteristics).
In Figures 18 and 19 Asynchronous Power-on timing diagrams are shown, respectively with
boot from internal or external memory, highlighting the reset phase extension introduced by
the embedded IFlash module when selected.
Caution:
Never power the device without keeping the RSTIN pin grounded: The device could enter
into unpredictable states, risking also permanent damage.
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System reset
ST10F273M
Figure 18. Asynchronous power-on RESET (EA = 1)
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Doc ID 13453 Rev 4
ST10F273M
System reset
Figure 19. Asynchronous power-on RESET (EA = 0)
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1. 3 to 8 TCL depending on clock source selection
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the
application. It may be triggered by the hardware of the application. Internal hardware logic
and application circuitry are described in Reset circuitry chapter and Figures 31, 32 and 33.
It occurs when RSTIN is low and RPD is detected (or becomes) low as well.
Doc ID 13453 Rev 4
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System reset
ST10F273M
Figure 20. Asynchronous hardware RESET (EA = 1)
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1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed).
Longer than 500ns to take into account of Input Filter on RSTIN pin.
88/186
Doc ID 13453 Rev 4
ST10F273M
System reset
Figure 21. Asynchronous hardware RESET (EA = 0)
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1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed).
Longer than 500ns to take into account of Input Filter on RSTIN pin.
2. 3 to 8 TCL depending on clock source selection.
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: As already mentioned, if internal
Flash is used, the restarting occurs after the embedded Flash initialization routine is
completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are
driven to their inactive level. The ST10F273M starts program execution from memory
location 00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. The timings of asynchronous Hardware Reset sequence are
summarized in Figure 20 and Figure 21.
20.3
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (two periods of CPU clock): refer also to Section 20.1 for
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
cancelled and the current internal access cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
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System reset
ST10F273M
register was previously set by software. Note that this bit is always cleared on power-on or
after a reset sequence.
Short and long synchronous reset
Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts.
It is 1024 TCL cycles long: at the end of it, and after other 8TCL the level of RSTIN is
sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short
Reset is flagged (refer to Chapter 19 for details on reset flags); if it is recognized still low, the
Long reset is flagged as well. The major difference between Long and Short reset is that
during the Long reset, also P0(15:13) become transparent, so it is possible to change the
clock options.
Warning: In case of a short pulse on RSTIN pin, and when Bidirectional
reset is enabled, the RSTIN pin is held low by the internal
circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is
released, but due to the presence of the input analog filter the
internal input reset signal (RSTF in the drawings) is released
later (from 50 to 500ns). This delay is in parallel with the
additional 8 TCL, at the end of which the internal input reset
line (RSTF) is sampled, to decide if the reset event is Short or
Long. In particular:
●
●
If 8 TCL > 500ns (f
< 8 MHz), the reset event is always recognized as Short
CPU
If 8 TCL < 500ns (f
> 8 MHz), the reset event could be recognized either as Short or
CPU
Long, depending on the real filter delay (between 50 and 500ns) and the CPU
frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long
reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the
P0(15:13) pins becomes transparent, so the system clock can be reconfigured. The
port returns not transparent 3-4TCL after the internal RSTF signal becomes high.
The same behavior just described, occurs also when unidirectional reset is selected and
RSTIN pin is held low till the end of the internal sequence (exactly 1024TCL + max 16 TCL)
and released exactly at that time.
Note:
When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be
recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns);
so it might happen that a short reset pulse is not filtered by the analog input filter, but on the
other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would
generate a Flash reset but not a system reset. In this condition, the Flash answers always
with FFFFh, which leads to an illegal opcode and consequently a trap event is generated.
Exit from synchronous reset state
The reset sequence is extended until RSTIN level becomes high. Besides, it is internally
prolonged by the Flash initialization when EA = 1 (internal memory selected). Then, the
code execution restarts. The system configuration is latched from Port0, and ALE, RD and
WR/WRL pins are driven to their inactive level. The ST10F273M starts program execution
from memory location 00'0000h in code segment 0. This starting location will typically point
to the general initialization routine. Timing of synchronous reset sequence are summarized
in Figure 22 and Figure 23 where a Short Reset event is shown, with particular emphasis on
the fact that it can degenerate into Long Reset: The two figures show the behavior when
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Doc ID 13453 Rev 4
ST10F273M
System reset
booting from internal or external memory respectively. Figure 24 and Figure 25 report the
timing of a typical synchronous Long Reset, again when booting from internal or external
memory.
Synchronous reset and RPD pin
Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a
Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance
(if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage
level on RPD pin reaches the input low threshold (around 2.5V), the reset event becomes
immediately asynchronous. In case of hardware reset (short or long) the situation goes
immediately to the one illustrated in Figure 20. There is no effect if RPD comes again above
the input threshold: the asynchronous reset is completed coherently. To grant the normal
completion of a synchronous reset, the value of the capacitance shall be big enough to
maintain the voltage on RPD pin sufficient high along the duration of the internal reset
sequence.
For a Software or Watchdog reset events, an active synchronous reset is completed
regardless of the RPD status.
It is important to highlight that the signal that makes RPD status transparent under reset is
the internal RSTF (after the noise filter).
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System reset
ST10F273M
Figure 22. Synchronous short / long hardware RESET (EA = 1)
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1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit
BDRSTEN is cleared after reset.
4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1).
92/186
Doc ID 13453 Rev 4
ST10F273M
System reset
Figure 23. Synchronous short / long hardware RESET (EA = 0)
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1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered.
3. 3 to 8 TCL depending on clock source selection.
4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit
BDRSTEN is cleared after reset.
5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1).
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System reset
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Figure 24. Synchronous long hardware RESET (EA = 1)
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1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered. Even if RPD returns above the
threshold, the reset is definitely taken as asynchronous.
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1).
94/186
Doc ID 13453 Rev 4
ST10F273M
System reset
Figure 25. Synchronous long hardware RESET (EA = 0)
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1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered.
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1).
3. 3 to 8 TCL depending on clock source selection.
20.4
Software reset
A software reset sequence can be triggered at any time by the protected SRST (software
reset) instruction. This instruction can be deliberately executed within a program, for
example, to leave bootstrap loader mode, or on a hardware trap that reveals system failure.
On execution of the SRST instruction, the internal reset sequence is started. The
microcontroller behavior is the same as for a synchronous short reset, except that only bits
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (that is written at ‘1’).
A Software reset is always taken as synchronous: there is no influence on Software Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
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Refer to the next Figure 26 and Figure 27 for unidirectional SW reset timing, and to
Figure 28, Figure 29 and Figure 30 for bidirectional.
20.5
Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly
during program execution, it will overflow and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after
the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
Refer to the next Figure 26 and Figure 27 for unidirectional SW reset timing, and to
Figure 28, Figure 29 and Figure 30 for bidirectional.
Figure 26. SW / WDT unidirectional RESET (EA = 1)
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Doc ID 13453 Rev 4
ST10F273M
System reset
Figure 27. SW / WDT unidirectional RESET (EA = 0)
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20.6
Bidirectional reset
As shown in the previous sections, the RSTOUT pin is driven active (low level) at the
beginning of any reset sequence (synchronous/asynchronous hardware, software and
watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization
routine, until the protected EINIT instruction (End of Initialization) is completed.
The Bidirectional Reset function is useful when external devices require a reset signal but
cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It
is, for instance, the case of external memory running initialization routine before the
execution of EINIT instruction.
Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It
only can be enabled during the initialization routine, before EINIT instruction is completed.
When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal,
for the duration of the internal reset sequence (synchronous/asynchronous hardware,
synchronous software and synchronous watchdog timer resets). At the end of the internal
reset sequence the pull down is released and:
●
After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low eight
TCL periods after the internal reset sequence completion (refer to Figure 22 and
Figure 23), the Short Reset becomes a Long Reset. On the contrary, if RSTF is
sampled high the device simply exits reset state.
●
After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF
remains still low for at least four TCL periods (minimum time to recognize a Short
Hardware reset) after the reset exiting (refer to Figure 28 and Figure 29), the Software
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System reset
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or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains
low for less than 4 TCL, the device simply exits reset state.
The Bidirectional reset is not effective in case RPD is held low, when a Software or
Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset
event is active and RPD becomes low, the RSTIN pin is immediately released, while the
internal reset sequence is completed regardless of RPD status change (1024 TCL).
Note:
The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of
SYSCON is cleared). To be activated again it must be enabled during the initialization
routine.
WDTCON flags
Similarly to what already highlighted in the previous section when discussing about Short
reset and the degeneration into Long reset, similar situations may occur when Bidirectional
reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: when
RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed,
so it remains still active (low) for a while. It means that depending on the internal clock
speed, a short reset may be recognized as a long reset: the WDTCON flags are set
accordingly.
Besides, when either Software or Watchdog bidirectional reset events occur, again when the
RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal
(after the filter) remains low for a while, and depending on the clock frequency it is
recognized high or low: 8TCL after the completion of the internal sequence, the level of
RSTF signal is sampled, and if recognized still low a Hardware reset sequence starts, and
WDTCON will flag this last event, masking the previous one (Software or Watchdog reset).
Typically, a Short Hardware reset is recognized, unless the RSTIN pin (and consequently
internal signal RSTF) is sufficiently held low by the external hardware to inject a Long
Hardware reset. After this occurrence, the initialization routine is not able to recognize a
Software or Watchdog bidirectional reset event, since a different source is flagged inside
WDTCON register. This phenomenon does not occur when internal Flash is selected during
reset (EA = 1), since the initialization of the Flash itself extend the internal reset duration
well beyond the filter delay.
The next Figure 28, Figure 29 and Figure 30 summarize the timing for Software and
Watchdog Timer Bidirectional reset events: In particular Figure 30 shows the degeneration
into Hardware reset.
98/186
Doc ID 13453 Rev 4
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System reset
Figure 28. SW / WDT bidirectional RESET (EA = 1)
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System reset
ST10F273M
Figure 29. SW / WDT bidirectional RESET (EA = 0)
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Doc ID 13453 Rev 4
ST10F273M
System reset
Figure 30. SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET
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20.7
Reset circuitry
Internal reset circuitry is described in Figure 33. The RSTIN pin provides an internal pull-up
resistor of 50kΩ to 250kΩ (The minimum reset time must be calculated using the lowest
value).
It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output
internal reset state signal (synchronous reset, watchdog timer reset or software reset).
This bidirectional reset function is useful in applications where external devices require a
reset signal but cannot be connected to RSTOUT pin.
This is the case of an external memory running codes before EINIT (end of initialization)
instruction is executed. RSTOUT pin is pulled high only when EINIT is executed.
The RPD pin provides an internal weak pull-down resistor which discharges external
capacitor at a typical rate of 200µA. If bit PWDCFG of SYSCON register is set, an internal
pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any
capacitor connected on RPD pin.
The simplest way to reset the ST10F273M is to insert a capacitor C1 between RSTIN pin
and V , and a capacitor between RPD pin and V (C0) with a pull-up resistor R0 between
SS
SS
RPD pin and V . The input RSTIN provides an internal pull-up device equalling a resistor of
DD
50kΩ to 250kΩ (the minimum reset time must be determined by the lowest value). Select C1
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System reset
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that produce a sufficient discharge time to permit the internal or external oscillator and / or
internal PLL and the on-chip voltage regulator to stabilize.
To ensure correct power-up reset with controlled supply current consumption, specially if
clock signal requires a long period of time to stabilize, an asynchronous hardware reset is
required during power-up. For this reason, it is recommended to connect the external R0-C0
circuit shown in Figure 31 to the RPD pin. On power-up, the logical low level on RPD pin
forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-up
R0 will then charge the capacitor C0. Note that an internal pull-down device on RPD pin is
turned on when RSTIN pin is low, and causes the external capacitor (C0) to begin
discharging at a typical rate of 100-200µA. With this mechanism, after power-up reset, short
low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted
longer than the time needed for C0 to be discharged by the internal pull-down device, then
the device is forced in an asynchronous reset. This mechanism insures recovery from very
catastrophic failure.
Figure 31. Minimum external reset circuitry
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the ST10F273M itself during software or watchdog triggered resets, because of the
capacitor C1 that will keep the voltage on RSTIN pin above V after the end of the internal
IL
reset sequence, and thus will trigger an asynchronous reset sequence.
Figure 32 shows an example of a reset circuit. In this example, R1-C1 external circuit is only
used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up
reset and to exit from Power-down mode. Diode D1 creates a wired-OR gate connection to
the reset pin and may be replaced by open-collector Schmitt trigger buffer. Diode D2
provides a faster cycle time for repetitive power-on resets.
R2 is an optional pull-up for faster recovery and correct biasing of TTL Open Collector
drivers.
102/186
Doc ID 13453 Rev 4
ST10F273M
System reset
Figure 32. System reset circuit
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System reset
ST10F273M
20.8
Reset application examples
The next two timing diagrams (Figure 34 and Figure 35) provide additional examples of
bidirectional internal reset events (Software and Watchdog) including in particular the
external capacitances charge and discharge transients (refer also to Figure 32 for the
external circuit scheme).
Figure 34. Example of software or watchdog bidirectional reset (EA = 1)
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104/186
Doc ID 13453 Rev 4
ST10F273M
System reset
Figure 35. Example of software or watchdog bidirectional reset (EA = 0)
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System reset
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20.9
Reset summary
The following table summarizes the different reset events.
Table 43. Reset event
Event
RSTIN
WDTCON flags
Min
Max
1 ms (VREG)
1.2 ms
0
0
N
Asynch.
Asynch.
(Reson. + PLL)
10.2 ms
(Crystal + PLL)
-
-
1
1
1
1
1
1
1
1
0
0
Power-on Reset
0
1
x
0
0
0
0
1
x
x
0
1
0
1
N
x
1ms (VREG)
FORBIDDEN
Y
N
N
Y
Y
-
Asynch.
Asynch.
Asynch.
Asynch.
500ns
500ns
500ns
500ns
-
-
-
-
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Hardware Reset
(Asynchronous)
1032 + 12 TCL +
max(4 TCL, 500ns)
1
1
0
1
N
N
Synch.
Synch.
max (4 TCL, 500ns)
max (4 TCL, 500ns)
max (4 TCL, 500ns)
0
0
0
0
1
1
1
1
0
0
1032 + 12 TCL +
max(4 TCL, 500ns)
Short Hardware
Reset
1032 + 12 TCL +
max(4 TCL, 500ns)
1
1
0
1
Y
Y
Synch.
Synch.
0
0
0
0
1
1
1
1
0
0
(Synchronous)(1)
Activated by internal logic for 1024 TCL
1032 + 12 TCL +
max (4 TCL, 500ns)
max(4 TCL, 500ns)
Activated by internal logic for 1024 TCL
1032 + 12 TCL +
max(4 TCL, 500ns)
1
1
0
1
N
N
Synch.
Synch.
-
0
0
1
1
1
1
1
1
0
0
1032 + 12 TCL +
max(4 TCL, 500ns)
-
Long Hardware
Reset
(Synchronous)
1032 + 12 TCL +
max(4 TCL, 500ns)
-
1
1
0
1
Y
Y
Synch.
Synch.
0
0
1
1
1
1
1
1
0
0
Activated by internal logic only for 1024 TCL
1032 + 12 TCL +
max(4 TCL, 500ns)
-
Activated by internal logic only for 1024 TCL
106/186
Doc ID 13453 Rev 4
ST10F273M
System reset
WDTCON flags
Table 43. Reset event (continued)
RSTIN
Event
Min
Max
x
x
0
1
x
x
0
1
0
0
1
1
0
0
1
1
N
N
Y
Y
N
N
Y
Y
Synch.
Synch.
Synch.
Synch.
Synch.
Synch.
Synch.
Synch.
Not activated
Not activated
Not activated
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
Software Reset(2)
Watchdog Reset(2)
Activated by internal logic for 1024 TCL
Not activated
Not activated
Not activated
Activated by internal logic for 1024 TCL
1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for
details).
2. When Bidirectional is active (and with RPD = 0), it can be followed by a Short Hardware Reset and
consequently differently flagged (see Section 20.6 for details).
The start-up configurations and some system features are selected on reset sequences as
described in Table 44 and Figure 36.
Table 44 describes the system configuration latched on PORT0 in the six different reset
modes. Figure 36 summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers.
Table 44. PORT0 latched configuration for the different reset events
PORT0
X: Pin is sampled
-: Pin is not sampled
Sample event
Software Reset
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
Watchdog Reset
-
-
-
-
-
-
Synchronous Short Hardware Reset
Synchronous Long Hardware Reset
Asynchronous Hardware Reset
Asynchronous Power-On Reset
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Doc ID 13453 Rev 4
107/186
System reset
ST10F273M
Figure 36. PORT0 bits latched into the different registers after reset
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108/186
Doc ID 13453 Rev 4
ST10F273M
Power reduction modes
21
Power reduction modes
Three different power reduction modes with different levels of power reduction have been
implemented in the ST10F273M. In Idle mode only the CPU is stopped, while peripherals
still operate. In Power-down mode both the CPU and peripherals are stopped. In Standby
mode the main power supply (V ) can be turned off while a portion of the internal RAM
DD
remains powered via V
dedicated power pin.
STBY
Idle and Power-down modes are software activated by a protected instruction and are
terminated in different ways as described in the following sections.
Standby mode is entered by simply removing V , holding the MCU under reset state.
DD
Note:
All external bus actions are completed before Idle or Power-down mode is entered.
However, Idle or Power-down mode is not entered if READY is enabled, but has not been
activated (driven low for negative polarity, or driven high for positive polarity) during the last
bus access.
21.1
Idle mode
Idle mode is entered by running the IDLE protected instruction. The CPU operation is
stopped and the peripherals still run.
Idle mode is terminated by any interrupt request. Whether or not the interrupt is serviced,
the instruction following the IDLE instruction will be executed after the return from interrupt
(RETI) instruction, and the CPU then resumes the normal program.
21.2
Power-down mode
Power-down mode starts by running the PWRDN protected instruction. The internal clock is
stopped and all MCU parts including the watchdog timer are on hold. The only exception
could be the Real Time Clock if programmed accordingly in conjuction with selecting one of
the two oscillator circuits (either the main or the 32 kHz on-chip oscillator).
If the Real Time Clock module is used when the device is in Power-down mode, a reference
clock is needed. In this case, two possible configurations may be selected by the user
application according to the desired level of power reduction:
●
A 32 kHz crystal is connected to the on-chip low-power oscillator (pins XTAL3 / XTAL4)
and running. In this case the main oscillator is stopped when Power-down mode is
entered, while the Real Time Clock continues counting using a 32 kHz clock signal as
reference. The presence of a running low-power oscillator is detected after the Power-
on: This clock is immediately assumed (if present, or as soon as it is detected) as
reference for the Real Time Clock counter and it will be maintained indefinitely (unless
specifically disabled via software).
●
Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case the main
oscillator is not stopped when Power-down is entered, and the Real Time Clock
continues counting using the main oscillator clock signal as reference.
There are two different operating Power-down modes: protected mode and interruptible
mode.
Doc ID 13453 Rev 4
109/186
Power reduction modes
ST10F273M
Before entering Power-down mode (by executing the instruction PWRDN), bit VREGOFF in
the XMISC register must be set.
Note:
Leaving the main voltage regulator active during Power-down may lead to unexpected
behavior (example: CPU wake-up) and power consumption higher than what is specified.
21.2.1
Protected power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The Protected
Power-down mode is only activated if the NMI pin is pulled low when executing PWRDN
instruction (this means that the PWRD instruction belongs to the NMI software routine). This
mode is only deactivated with an external hardware reset on RSTIN pin.
21.2.2
Interruptible power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is set.
The Interruptible Power-down mode is only activated if all the enabled Fast External
Interrupt pins are in their inactive level.
This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt
request applied to one of the Fast External Interrupt pins, or with an interrupt generated by
2
the Real Time Clock, or with an interrupt generated by the activity on CAN’s and I C module
interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low
according the recommendations described in Section 20: System reset on page 83.
An external RC circuit must be connected to RPD pin, as shown in the Figure 37.
Figure 37. External RC circuitry on RPD pin
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To exit Power-down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40ns.
21.3
Standby mode
In Standby mode, it is possible to turn off the main V provided that V
is available
STBY
DD
through the dedicated pin of the ST10F273M.
To enter Standby mode it is mandatory to held the device under reset: once the device is
under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital
interface is frozen in order to avoid any kind of data corruption.
A dedicated embedded low-power voltage regulator is implemented to generate the internal
low voltage supply (about 1.65V in Standby mode) to bias all those circuits that shall remain
110/186
Doc ID 13453 Rev 4
ST10F273M
Power reduction modes
active: the portion of XRAM (16 Kbytes for ST10F273M), the RTC counters and 32 kHz on-
chip oscillator amplifier.
In normal running mode (that is, when main V is on) the V
pin can be tied to V
SS
DD
STBY
during reset to exercise the EA functionality associated with the same pin: The voltage
supply for the circuitries which are usually biased with V (see in particular the 32 kHz
STBY
oscillator used in conjunction with Real Time Clock module), is granted by the active main
V
.
DD
It must be noted that Standby mode can generate problems associated with the usage of
different power supplies in CMOS systems; particular attention must be paid when the
ST10F273M I/O lines are interfaced with other external CMOS integrated circuits: If V of
DD
ST10F273M becomes (for example, in Standby mode) lower than the output level forced by
the I/O lines of these external integrated circuits, the ST10F273M could be directly powered
through the inherent diode existing on ST10F273M output driver circuitry. The same is valid
for ST10F273M interfaced to active/inactive communication buses during Standby mode:
Current injection can be generated through the inherent diode.
Furthermore, the sequence of turning on/off of the different voltage could be critical for the
system (not only for the ST10F273M device). The device Standby mode current (I
) may
STBY
vary while V to V
(and vice versa) transition occurs: Some current flows between
DD
STBY
V
and V
pins. System noise on both V and V
can contribute to increase this
STBY
DD
STBY
DD
phenomenon.
21.3.1
Entering standby mode
As already stated, to enter Standby mode the XRAM2EN bit in the XPERCON register must
be cleared: This allows the RAM interface to be frozen immediately, avoiding any data
corruption. As a consequence of a RESET event, the RAM power supply is switched to the
internal low-voltage supply V
(derived from V
through the low-power voltage
18SB
STBY
regulator). The RAM interface remains frozen until the bit XRAM2EN is set again by
software initialization routine (at next exit from main V power-on reset sequence).
DD
Since V is falling down (as a consequence of V turning off), it can happen that the
18
DD
XRAM2EN bit is no longer able to guarantee its content (logic “0”), being the XPERCON
Register powered by internal V . This does not generate any problem, because the
18
Standby mode switching dedicated circuit continues to confirm the RAM interface freezing,
irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when
internal V comes back over internal standby reference V
.
18
18SB
If internal V becomes lower than internal standby reference (V
) of about 0.3 to 0.45V
18SB
18
with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a
temporary drop on internal V voltage versus internal V during normal code execution,
18
18SB
no spurious Standby mode switching can occur (the RAM is not frozen and can still be
accessed).
The ST10F273M Core module, generating the RAM control signals, is powered by internal
V
supply; during turning off transient these control signals follow the V , while RAM is
18
18
switched to V
internal reference. It could happen that a high level of RAM write strobe
18SB
from ST10F273M Core (active low signal) is low enough to be recognized as a logic “0” by
the RAM interface (due to V lower than V ): The bus status could contain a valid
18
18SB
address for the RAM and an unwanted data corruption could occur. For this reason, an extra
interface, powered by the switched supply, is used to prevent the RAM from this kind of
potential corruption mechanism.
Doc ID 13453 Rev 4
111/186
Power reduction modes
ST10F273M
Warning: During power-off phase, it is important that the external
hardware maintains a stable ground level on RSTIN pin,
without any glitch, in order to avoid spurious exiting from
reset status with unstable power supply.
21.3.2
Exiting standby mode
After the system has entered the Standby mode, the procedure to exit this mode consists of
a standard Power-on sequence, with the only difference that the RAM is already powered
through V
internal reference (derived from V
pin external voltage).
18SB
STBY
It is recommended to held the device under RESET (RSTIN pin forced low) until external
voltage pin is stable. Even though, at the very beginning of the power-on phase, the
V
DD
device is maintained under reset by the internal low voltage detector circuit (implemented
inside the main voltage regulator) till the internal V becomes higher than about 1.0V, there
18
is no guaranty that the device stays under reset status if RSTIN is at high level during power
ramp up. So, it is important the external hardware is able to guarantee a stable ground level
on RSTIN along the power-on phase, without any temporary glitch.
The external hardware shall be responsible to drive low the RSTIN pin until the V is
DD
stable, even though the internal LVD is active.
Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to
the main V .
18
At this time, everything becomes stable, and the execution of the initialization routines can
start: XRAM2EN bit can be set, enabling the RAM.
21.3.3
21.3.4
Real time clock and standby mode
When Standby mode is entered (turning off the main supply V ), the Real Time Clock
counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide
the reference to the counter. This is not possible if the main oscillator is used as reference
for the counter: Being the main oscillator powered by V , once this is switched off, the
oscillator is stopped.
DD
DD
Power reduction modes summary
The different Power reduction modes are summarized in the following Table 45.
112/186
Doc ID 13453 Rev 4
ST10F273M
Power reduction modes
Table 45. Power reduction modes summary
Mode
on
on
on
on
on
off
off
on
on
on
on
on
on
on
off
off
off
off
off
off
off
on
on
off
off
off
off
off
off
on
off
on
on
off
on
run
run
off
on
off
off
off
off
on
off
off
on
off
on
biased biased
biased biased
biased biased
biased biased
biased biased
Idle
Power-down
Standby
biased
biased
off
off
Doc ID 13453 Rev 4
113/186
Programmable output clock divider
ST10F273M
22
Programmable output clock divider
A specific register mapped on the XBUS allows to choose the division factor on the
CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address
range.
When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the
CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of
register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15
a prescaled value of the CPU clock can be output.
When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15
does not output any clock signal, even though XCLKOUTDIV register is programmed.
114/186
Doc ID 13453 Rev 4
ST10F273M
Register set
23
Register set
This section summarizes all registers implemented in the ST10F273M, ordered by name.
23.1
Special function registers
The following table lists all SFRs which are implemented in the ST10F273M in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”.
SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column
“Physical Address”.
Table 46. List of special function registers
Physical
address
8-bit
address
Reset
value
Name
Description
A/D converter end of conversion interrupt control
register
ADCIC
b
b
FF98h
CCh
- - 00h
ADCON
ADDAT
FFA0h
FEA0h
D0h
50h
50h
0Ch
0Dh
0Eh
0Fh
CDh
86h
8Ah
8Bh
8Ch
8Dh
25h
40h
BCh
41h
BDh
42h
BEh
43h
BFh
A/D converter control register
A/D converter result register
A/D converter 2 result register
Address select register 1
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0xx0h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
ADDAT2
ADDRSEL1
ADDRSEL2
ADDRSEL3
ADDRSEL4
ADEIC
F0A0h
FE18h
FE1Ah
FE1Ch
FE1Eh
FF9Ah
FF0Ch
FF14h
FF16h
FF18h
FF1Ah
FE4Ah
FE80h
FF78h
FE82h
FF7Ah
FE84h
FF7Ch
FE86h
FF7Eh
E
Address select register 2
Address select register 3
Address select register 4
b
b
b
b
b
b
A/D converter overrun error interrupt control register
Bus configuration register 0
Bus configuration register 1
Bus configuration register 2
Bus configuration register 3
Bus configuration register 4
GPT2 capture/reload register
CAPCOM register 0
BUSCON0
BUSCON1
BUSCON2
BUSCON3
BUSCON4
CAPREL
CC0
CC0IC
b
b
b
b
CAPCOM register 0 interrupt control register
CAPCOM register 1
CC1
CC1IC
CAPCOM register 1 interrupt control register
CAPCOM register 2
CC2
CC2IC
CAPCOM register 2 interrupt control register
CAPCOM register 3
CC3
CC3IC
CAPCOM register 3 interrupt control register
Doc ID 13453 Rev 4
115/186
Register set
ST10F273M
Table 46. List of special function registers (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
CC4
FE88h
FF80h
FE8Ah
FF82h
FE8Ch
FF84h
FE8Eh
FF86h
FE90h
FF88h
FE92h
FF8Ah
FE94h
FF8Ch
FE96h
FF8Eh
FE98h
FF90h
FE9Ah
FF92h
FE9Ch
FF94h
FE9Eh
FF96h
FE60h
44h
C0h
45h
C1h
46h
C2h
47h
C3h
48h
C4h
49h
C5h
4Ah
C6h
4Bh
C7h
4Ch
C8h
4Dh
C9h
4Eh
CAh
4Fh
CBh
30h
B0h
31h
B1h
32h
B2h
33h
B3h
34h
B4h
CAPCOM register 4
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
CC4IC
CC5
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
CAPCOM register 4 interrupt control register
CAPCOM register 5
CC5IC
CC6
CAPCOM register 5 interrupt control register
CAPCOM register 6
CC6IC
CC7
CAPCOM register 6 interrupt control register
CAPCOM register 7
CC7IC
CC8
CAPCOM register 7 interrupt control register
CAPCOM register 8
CC8IC
CC9
CAPCOM register 8 interrupt control register
CAPCOM register 9
CC9IC
CC10
CAPCOM register 9 interrupt control register
CAPCOM register 10
CC10IC
CC11
CAPCOM register 10 interrupt control register
CAPCOM register 11
CC11IC
CC12
CAPCOM register 11 interrupt control register
CAPCOM register 12
CC12IC
CC13
CAPCOM register 12 interrupt control register
CAPCOM register 13
CC13IC
CC14
CAPCOM register 13 interrupt control register
CAPCOM register 14
CC14IC
CC15
CAPCOM register 14 interrupt control register
CAPCOM register 15
CC15IC
CC16
CAPCOM register 15 interrupt control register
CAPCOM register 16
CC16IC
CC17
F160h
FE62h
F162h
FE64h
F164h
FE66h
F166h
FE68h
F168h
E
CAPCOM register 16 interrupt control register
CAPCOM register 17
CC17IC
CC18
E
E
E
E
CAPCOM register 17 interrupt control register
CAPCOM register 18
CC18IC
CC19
CAPCOM register 18 interrupt control register
CAPCOM register 19
CC19IC
CC20
CAPCOM register 19 interrupt control register
CAPCOM register 20
CC20IC
CAPCOM register 20 interrupt control register
116/186
Doc ID 13453 Rev 4
ST10F273M
Register set
Table 46. List of special function registers (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
CC4
FE88h
FF80h
FE8Ah
FF82h
FE8Ch
FF84h
FE8Eh
FF86h
FE90h
FF88h
FE92h
FF8Ah
FE94h
FF8Ch
FE96h
FF8Eh
FE98h
FF90h
FE9Ah
FF92h
FE9Ch
FF94h
FE9Eh
FF96h
FE60h
44h
C0h
45h
C1h
46h
C2h
47h
C3h
48h
C4h
49h
C5h
4Ah
C6h
4Bh
C7h
4Ch
C8h
4Dh
C9h
4Eh
CAh
4Fh
CBh
30h
B0h
31h
B1h
32h
B2h
33h
B3h
34h
B4h
CAPCOM register 4
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
CC4IC
CC5
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
CAPCOM register 4 interrupt control register
CAPCOM register 5
CC5IC
CC6
CAPCOM register 5 interrupt control register
CAPCOM register 6
CC6IC
CC7
CAPCOM register 6 interrupt control register
CAPCOM register 7
CC7IC
CC8
CAPCOM register 7 interrupt control register
CAPCOM register 8
CC8IC
CC9
CAPCOM register 8 interrupt control register
CAPCOM register 9
CC9IC
CC10
CAPCOM register 9 interrupt control register
CAPCOM register 10
CC10IC
CC11
CAPCOM register 10 interrupt control register
CAPCOM register 11
CC11IC
CC12
CAPCOM register 11 interrupt control register
CAPCOM register 12
CC12IC
CC13
CAPCOM register 12 interrupt control register
CAPCOM register 13
CC13IC
CC14
CAPCOM register 13 interrupt control register
CAPCOM register 14
CC14IC
CC15
CAPCOM register 14 interrupt control register
CAPCOM register 15
CC15IC
CC16
CAPCOM register 15 interrupt control register
CAPCOM register 16
CC16IC
CC17
F160h
FE62h
F162h
FE64h
F164h
FE66h
F166h
FE68h
F168h
E
CAPCOM register 16 interrupt control register
CAPCOM register 17
CC17IC
CC18
E
E
E
E
CAPCOM register 17 interrupt control register
CAPCOM register 18
CC18IC
CC19
CAPCOM register 18 interrupt control register
CAPCOM register 19
CC19IC
CC20
CAPCOM register 19 interrupt control register
CAPCOM register 20
CC20IC
CAPCOM register 20 interrupt control register
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Register set
ST10F273M
Table 46. List of special function registers (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
CC21
FE6Ah
35h
B5h
36h
B6h
37h
B7h
38h
B8h
39h
B9h
3Ah
BAh
3Bh
BBh
3Ch
BCh
3Dh
C2h
3Eh
C6h
3Fh
CAh
A9h
AAh
ABh
ACh
91h
92h
93h
94h
08h
B5h
04h
80h
CAPCOM register 21
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
FC00h
- - 00h
0000h
- - 00h
CC21IC
CC22
b
b
b
b
b
b
b
b
b
b
F16Ah
FE6Ch
F16Ch
FE6Eh
F16Eh
FE70h
F170h
FE72h
F172h
FE74h
F174h
FE76h
F176h
FE78h
F178h
FE7Ah
F184h
FE7Ch
F18Ch
FE7Eh
F194h
FF52h
FF54h
FF56h
FF58h
FF22h
FF24h
FF26h
FF28h
FE10h
FF6Ah
FE08h
F100h
E
CAPCOM register 21 interrupt control register
CAPCOM register 22
CC22IC
CC23
E
E
E
E
E
E
E
E
E
E
CAPCOM register 22 interrupt control register
CAPCOM register 23
CC23IC
CC24
CAPCOM register 23 interrupt control register
CAPCOM register 24
CC24IC
CC25
CAPCOM register 24 interrupt control register
CAPCOM register 25
CC25IC
CC26
CAPCOM register 25 interrupt control register
CAPCOM register 26
CC26IC
CC27
CAPCOM register 26 interrupt control register
CAPCOM register 27
CC27IC
CC28
CAPCOM register 27 interrupt control register
CAPCOM register 28
CC28IC
CC29
CAPCOM register 28 interrupt control register
CAPCOM register 29
CC29IC
CC30
CAPCOM register 29 interrupt control register
CAPCOM register 30
CC30IC
CC31
CAPCOM register 30 interrupt control register
CAPCOM register 31
CC31IC
CCM0
CCM1
CCM2
CCM3
CCM4
CCM5
CCM6
CCM7
CP
b
b
b
b
b
b
b
b
b
CAPCOM register 31 interrupt control register
CAPCOM Mode Control register 0
CAPCOM Mode Control register 1
CAPCOM Mode Control register 2
CAPCOM Mode Control register 3
CAPCOM Mode Control register 4
CAPCOM Mode Control register 5
CAPCOM Mode Control register 6
CAPCOM Mode Control register 7
CPU Context Pointer register
CRIC
b
b
GPT2 CAPREL interrupt control register
CPU Code Segment Pointer register (read only)
P0L direction control register
CSP
DP0L
E
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Doc ID 13453 Rev 4
ST10F273M
Register set
Table 46. List of special function registers (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
DP0H
DP1L
DP1H
DP2
b
b
b
b
b
b
b
b
b
F102h
F104h
F106h
FFC2h
FFC6h
FFCAh
FFCEh
FFD2h
FFD6h
FE00h
FE02h
FE04h
FE06h
FE0Ah
F1C0h
F1DAh
F07Ch
F07Eh
F07Ah
F078h
FF08h
FF0Ah
FE5Eh
FE5Ch
FFDCh
FF0Eh
FE0Ch
FE0Eh
FFDAh
FFDEh
F1C2h
F1C6h
F1CAh
F1CEh
E
81h
82h
83h
E1h
E3h
E5h
E7h
E9h
EBh
00h
01h
02h
03h
05h
E0h
EDh
3Eh
3Fh
3Dh
3Ch
84h
85h
2Fh
2Eh
EEh
87h
06h
07h
EDh
EFh
E1h
E3h
E5h
E7h
P0h direction control register
- - 00h
- - 00h
- - 00h
0000h
0000h
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0001h
0002h
0003h
- - XXh
0000h
0000h
111nh
0403h
2080h
0040h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0200h
0000h
0000h
- - 00h
- - 00h
E
E
P1L direction control register
P1h direction control register
Port 2 direction control register
Port 3 direction control register
Port 4 direction control register
Port 6 direction control register
Port 7 direction control register
Port 8 direction control register
CPU data page pointer 0 register (10-bit)
CPU data page pointer 1 register (10-bit)
CPU data page pointer 2 register (10-bit)
CPU data page pointer 3 register (10-bit)
Emulation control register
DP3
DP4
DP6
DP7
DP8
DPP0
DPP1
DPP2
DPP3
EMUCON
EXICON
EXISEL
IDCHIP
IDMANUF
IDMEM
IDPROG
IDX0
b
b
E
E
E
E
E
E
External interrupt control register
External interrupt source selection register
Device identifier register (n is the device revision)
Manufacturer identifier register
On-chip memory identifier register
Programming voltage identifier register
MAC unit address pointer 0
b
b
IDX1
MAC unit address pointer 1
MAH
MAC unit accumulator - high word
MAC unit accumulator - low word
MAC unit control word
MAL
MCW
b
b
MDC
CPU multiply divide control register
CPU multiply divide register – high word
CPU multiply divide register – low word
MAC unit repeat word
MDH
MDL
MRW
b
b
b
b
b
b
MSW
MAC unit status word
ODP2
ODP3
ODP4
ODP6
E
E
E
E
Port 2 open drain control register
Port 3 open drain control register
Port 4 open drain control register
Port 6 open drain control register
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Register set
ST10F273M
Table 46. List of special function registers (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
ODP7
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
F1D2h
F1D6h
FF1Eh
FF00h
FF02h
FF04h
FF06h
FFC0h
FFC4h
FFC8h
FFA2h
FFCCh
FFD0h
FFD4h
FFA4h
FEC0h
FEC2h
FEC4h
FEC6h
FEC8h
FECAh
FECCh
FECEh
F1C4h
F038h
F03Ah
F03Ch
F03Eh
FF10h
F030h
F032h
F034h
F036h
FE30h
E
E9h
EBh
8Fh
80h
81h
82h
83h
E0h
E2h
E4h
D1h
E6h
E8h
EAh
D2h
60h
61h
62h
63h
64h
65h
66h
67h
E2h
1Ch
1Dh
1Eh
1Fh
88h
18h
19h
1Ah
1Bh
18h
Port 7 open drain control register
Port 8 open drain control register
Constant value 1’s register (read only)
PORT0 low register (lower half of PORT0)
PORT0 high register (upper half of PORT0)
PORT1 low register (lower half of PORT1)
PORT1 high register (upper half of PORT1)
Port 2 register
- - 00h
- - 00h
FFFFh
- - 00h
- - 00h
- - 00h
- - 00h
0000h
0000h
- - 00h
XXXXh
- - 00h
- - 00h
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
ODP8
ONES
P0L
E
P0H
P1L
P1H
P2
P3
Port 3 register
P4
Port 4 register (8-bit)
P5
Port 5 register (read only)
P6
Port 6 register (8-bit)
P7
Port 7 register (8-bit)
P8
Port 8 register (8-bit)
P5DIDIS
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
PICON
PP0
Port 5 digital disable register
PEC channel 0 control register
PEC channel 1 control register
PEC channel 2 control register
PEC channel 3 control register
PEC channel 4 control register
PEC channel 5 control register
PEC channel 6 control register
PEC channel 7 control register
Port input threshold control register
PWM module period register 0
PWM module period register 1
PWM module period register 2
PWM module period register 3
CPU program status word
b
b
E
E
E
E
E
PP1
PP2
PP3
PSW
PT0
E
E
E
E
PWM module up/down counter 0
PWM module up/down counter 1
PWM module up/down counter 2
PWM module up/down counter 3
PWM module pulse width register 0
PT1
PT2
PT3
PW0
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Doc ID 13453 Rev 4
ST10F273M
Register set
Table 46. List of special function registers (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
PW1
PW2
PW3
FE32h
FE34h
FE36h
FF30h
FF32h
19h
1Ah
1Bh
98h
99h
BFh
02h
03h
00h
01h
84h
5Ah
D8h
B8h
59h
B7h
CEh
58h
B6h
09h
5Ah
D9h
BBh
59h
BAh
58h
B9h
0Ah
0Bh
89h
28h
A8h
CEh
2Ah
PWM module pulse width register 1
PWM module pulse width register 2
PWM module pulse width register 3
PWM module control register 0
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
- - XXh
0000h
0000h
- - 00h
- - XXh
- - 00h
- - 00h
0000h
- - 00h
FC00h
0000h
0000h
- - 00h
XXXXh
- - 00h
0000h
- - 00h
FA00h
FC00h
0xx0h(1)
0000h
0000h
- - 00h
0000h
PWMCON0
PWMCON1
PWMIC
QR0
b
b
b
PWM module control register 1
F17Eh
F004h
F006h
F000h
F002h
F108h
FEB4h
FFB0h
FF70h
FEB2h
FF6Eh
F19Ch
FEB0h
FF6Ch
FE12h
F0B4h
FFB2h
FF76h
F0B2h
FF74h
F0B0h
FF72h
FE14h
FE16h
FF12h
FE50h
FF50h
FF9Ch
FE54h
E
PWM module interrupt control register
MAC unit offset register r0
E
E
E
E
E
QR1
MAC unit offset register R1
QX0
MAC unit offset register X0
QX1
MAC unit offset register X1
RP0H
b
System start-up configuration register (read only)
Serial channel 0 baudrate generator reload register
Serial channel 0 control register
S0BG
S0CON
S0EIC
b
b
Serial channel 0 error interrupt control register
Serial channel 0 receive buffer register (read only)
Serial channel 0 receive interrupt control register
Serial channel 0 transmit buffer interrupt control reg.
Serial channel 0 transmit buffer register (write only)
Serial channel 0 transmit interrupt control register
CPU system stack pointer register
SSC baudrate register
S0RBUF
S0RIC
S0TBIC
S0TBUF
S0TIC
b
b
E
E
b
SP
SSCBR
SSCCON
SSCEIC
SSCRB
SSCRIC
SSCTB
SSCTIC
STKOV
STKUN
SYSCON
T0
b
b
SSC control register
SSC error interrupt control register
SSC receive buffer (read only)
E
E
b
b
SSC receive interrupt control register
SSC transmit buffer (write only)
SSC transmit interrupt control register
CPU stack overflow pointer register
CPU stack underflow pointer register
CPU system configuration register
CAPCOM timer 0 register
b
T01CON
T0IC
b
b
CAPCOM timer 0 and timer 1 control register
CAPCOM timer 0 interrupt control register
CAPCOM timer 0 reload register
T0REL
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Register set
ST10F273M
Table 46. List of special function registers (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
T1
FE52h
FF9Eh
FE56h
FE40h
FF40h
FF60h
FE42h
FF42h
FF62h
FE44h
FF44h
FF64h
FE46h
FF46h
FF66h
FE48h
FF48h
FF68h
29h
CFh
2Bh
20h
A0h
B0h
21h
A1h
B1h
22h
A2h
B2h
23h
A3h
B3h
24h
A4h
B4h
28h
90h
BDh
2Ah
29h
BEh
2Bh
D6h
57h
D7h
0Eh
C3h
C7h
CBh
CFh
CAPCOM timer 1 register
0000h
- - 00h
0000h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
0000h
00xxh(2)
800Bh
- - 00h(3)
- - 00h(3)
- - 00h(3)
- - 00h(3)
T1IC
b
CAPCOM timer 1 interrupt control register
CAPCOM timer 1 reload register
GPT1 timer 2 register
T1REL
T2
T2CON
T2IC
b
b
GPT1 timer 2 control register
GPT1 timer 2 interrupt control register
GPT1 timer 3 register
T3
T3CON
T3IC
b
b
GPT1 timer 3 control register
GPT1 timer 3 interrupt control register
GPT1 timer 4 register
T4
T4CON
T4IC
b
b
GPT1 timer 4 control register
GPT1 timer 4 interrupt control register
GPT2 timer 5 register
T5
T5CON
T5IC
b
b
GPT2 timer 5 control register
GPT2 timer 5 interrupt control register
GPT2 timer 6 register
T6
T6CON
T6IC
b
b
GPT2 timer 6 control register
GPT2 timer 6 interrupt control register
CAPCOM timer 7 register
T7
F050h
FF20h
F17Ah
F054h
F052h
F17Ch
F056h
FFACh
FEAEh
FFAEh
F01Ch
F186h
F18Eh
F196h
F19Eh
E
T78CON
T7IC
b
b
CAPCOM timer 7 and 8 control register
CAPCOM timer 7 interrupt control register
CAPCOM timer 7 reload register
CAPCOM timer 8 register
E
E
E
E
E
T7REL
T8
T8IC
b
b
b
CAPCOM timer 8 interrupt control register
CAPCOM timer 8 reload register
Trap Flag register
T8REL
TFR
WDT
Watchdog timer register (read only)
Watchdog timer control register
XPER address select register 3
See Section 9.1
WDTCON
XADRS3
XP0IC
XP1IC
XP2IC
XP3IC
E
E
E
E
E
b
b
b
b
See Section 9.1
See Section 9.1
See Section 9.1
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ST10F273M
Register set
Table 46. List of special function registers (continued)
Physical
address
8-bit
address
Reset
value
Name
Description
XPERCON
ZEROS
b
b
F024h
FF1Ch
E
12h
8Eh
XPER configuration register
Constant value 0’s register (read only)
- - 05h
0000h
1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b.
2. Reset value depends on different triggered reset event.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software
controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-Peripheral
nodes.
23.2
X-registers
The following table lists in order of their names all X-Bus registers which are implemented in
the ST10F273M. Even though they are also physically mapped on XBus memory space, the
Flash control registers are listed in a separate section.
Note:
The X-Registers are not bit-addressable.
Table 47. List of XBus registers
Physical
address
Reset
value
Name
Description
CAN1BRPER
CAN1BTR
EF0Ch
EF06h
EF00h
EF04h
EF18h
EF1Ah
EF12h
EF10h
EF1Eh
EF20h
EF22h
EF24h
EF14h
EF16h
EF1Ch
EF48h
EF4Ah
EF42h
EF40h
EF4Eh
CAN1: BRP extension register
CAN1: Bit timing register
CAN1: CAN control register
CAN1: error counter
0000h
2301h
0001h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0001h
0000h
CAN1CR
CAN1EC
CAN1IF1A1
CAN1IF1A2
CAN1IF1CM
CAN1IF1CR
CAN1IF1DA1
CAN1IF1DA2
CAN1IF1DB1
CAN1IF1DB2
CAN1IF1M1
CAN1IF1M2
CAN1IF1MC
CAN1IF2A1
CAN1IF2A2
CAN1IF2CM
CAN1IF2CR
CAN1IF2DA1
CAN1: IF1 arbitration 1
CAN1: IF1 arbitration 2
CAN1: IF1 command mask
CAN1: IF1 command request
CAN1: IF1 data A 1
CAN1: IF1 data A 2
CAN1: IF1 data B 1
CAN1: IF1 data B 2
CAN1: IF1 mask 1
CAN1: IF1 mask 2
CAN1: IF1 message control
CAN1: IF2 arbitration 1
CAN1: IF2 arbitration 2
CAN1: IF2 command mask
CAN1: IF2 command request
CAN1: IF2 data A 1
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Register set
ST10F273M
Table 47. List of XBus registers (continued)
Physical
Name
Reset
value
Description
address
CAN1IF2DA2
CAN1IF2DB1
CAN1IF2DB2
CAN1IF2M1
CAN1IF2M2
CAN1IF2MC
CAN1IP1
EF50h
EF52h
EF54h
EF44h
EF46h
EF4Ch
EFA0h
EFA2h
EF08h
EFB0h
EFB2h
EF90h
EF92h
EF02h
EF0Ah
EF80h
EF82h
EE0Ch
EE06h
EE00h
EE04h
EE18h
EE1Ah
EE12h
EE10h
EE1Eh
EE20h
EE22h
EE24h
EE14h
EE16h
EE1Ch
EE48h
EE4Ah
CAN1: IF2 data A 2
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00x0h
0000h
0000h
0000h
2301h
0001h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
CAN1: IF2 data B 1
CAN1: IF2 data B 2
CAN1: IF2 Mask 1
CAN1: IF2 mask 2
CAN1: IF2 message control
CAN1: interrupt pending 1
CAN1: interrupt pending 2
CAN1: interrupt register
CAN1: message valid 1
CAN1: message valid 2
CAN1: new data 1
CAN1IP2
CAN1IR
CAN1MV1
CAN1MV2
CAN1ND1
CAN1ND2
CAN1: new data 2
CAN1SR
CAN1: status register
CAN1: test register
CAN1TR
CAN1TR1
CAN1: transmission request 1
CAN1: transmission request 2
CAN2: BRP extension register
CAN2: bit timing register
CAN2: CAN control register
CAN2: error counter
CAN1TR2
CAN2BRPER
CAN2BTR
CAN2CR
CAN2EC
CAN2IF1A1
CAN2IF1A2
CAN2IF1CM
CAN2IF1CR
CAN2IF1DA1
CAN2IF1DA2
CAN2IF1DB1
CAN2IF1DB2
CAN2IF1M1
CAN2IF1M2
CAN2IF1MC
CAN2IF2A1
CAN2IF2A2
CAN2: IF1 arbitration 1
CAN2: IF1 arbitration 2
CAN2: IF1 command mask
CAN2: IF1 command request
CAN2: IF1 data A 1
CAN2: IF1 data A 2
CAN2: IF1 data B 1
CAN2: IF1 data B 2
CAN2: IF1 mask 1
CAN2: IF1 mask 2
CAN2: IF1 message control
CAN2: IF2 arbitration 1
CAN2: IF2 arbitration 2
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ST10F273M
Register set
Table 47. List of XBus registers (continued)
Physical
Name
Reset
value
Description
address
CAN2IF2CM
CAN2IF2CR
CAN2IF2DA1
CAN2IF2DA2
CAN2IF2DB1
CAN2IF2DB2
CAN2IF2M1
CAN2IF2M2
CAN2IF2MC
CAN2IP1
CAN2IP2
CAN2IR
EE42h
EE40h
EE4Eh
EE50h
EE52h
EE54h
EE44h
EE46h
EE4Ch
EEA0h
EEA2h
EE08h
EEB0h
EEB2h
EE90h
EE92h
EE02h
EE0Ah
EE80h
EE82h
EA06h
EA0Eh
EA00h
EA0Ch
EA08h
EA0Ah
EA02h
EA04h
ED14h
ED12h
ED00H
ED0Ch
ED0Ah
ED10h
CAN2: IF2 command mask
0000h
0001h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00x0h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
XXXXh
XXXXh
000Xh
XXXXh
XXXXh
XXXXh
CAN2: IF2 command request
CAN2: IF2 data A 1
CAN2: IF2 data A 2
CAN2: IF2 data B 1
CAN2: IF2 data B 2
CAN2: IF2 mask 1
CAN2: IF2 mask 2
CAN2: IF2 message control
CAN2: interrupt pending 1
CAN2: interrupt pending 2
CAN2: interrupt register
CAN2: message valid 1
CAN2: message valid 2
CAN2: new data 1
CAN2MV1
CAN2MV2
CAN2ND1
CAN2ND2
CAN2SR
CAN2TR
CAN2: new data 2
CAN2: status register
CAN2: test register
CAN2TR1
CAN2TR2
I2CCCR1
I2CCCR2
I2CCR
CAN2: transmission request 1
CAN2: Transmission request 2
I2C clock control register 1
I2C clock control register 2
I2C control register
I2CDR
I2C data register
I2COAR1
I2COAR2
I2CSR1
I2C own address register 1
I2C own address register 2
I2C status register 1
I2CSR2
I2C status register 2
RTCAH
RTC alarm register high byte
RTC alarm register low byte
RTC control register
RTCAL
RTCCON
RTCDH
RTC divider counter high byte
RTC divider counter low byte
RTC programmable counter high byte
RTCDL
RTCH
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Register set
ST10F273M
Table 47. List of XBus registers (continued)
Physical
Name
Reset
value
Description
address
RTCL
ED0Eh
ED08h
ED06h
EB02h
EB76h
EB78h
EB7Ah
EB7Ch
EB14h
EB10h
EB12h
EB24h
EB20h
EB22h
EB34h
EB30h
EB32h
EB44h
EB40h
EB42h
EB46h
EB36h
EB7Eh
EB26h
EC04h
EC20h
EC22h
EC24h
EC26h
EC10h
EC12h
EC14h
EC16h
EC30h
RTC programmable counter low byte
RTC prescaler register high byte
XXXXh
XXXXh
XXXXh
- - 00h
XXXXh
XXXXh
XXXXh
XXXXh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
XXXXh
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
RTCPH
RTCPL
RTC prescaler register low byte
XCLKOUTDIV
XEMU0
XEMU1
XEMU2
XEMU3
XIR0CLR
XIR0SEL
XIR0SET
XIR1CLR
XIR1SEL
XIR1SET
XIR2CLR
XIR2SEL
XIR2SET
XIR3CLR
XIR3SEL
XIR3SET
XMISC
CLKOUT divider control register
XBUS emulation register 0 (write only)
XBUS emulation register 1 (write only)
XBUS emulation register 2 (write only)
XBUS emulation register 3 (write only)
X-Interrupt 0 clear register (write only)
X-Interrupt 0 selection register
X-Interrupt 0 set register (write only)
X-Interrupt 1 clear register (write only)
X-Interrupt 1 selection register
X-Interrupt 1 set register (write only)
X-Interrupt 2 clear register (write only)
X-Interrupt 2 selection register
X-Interrupt 2 set register (write only)
X-Interrupt 3 clear selection register (write only)
X-Interrupt 3 selection register
X-Interrupt 3 set selection register (write only)
XBUS miscellaneous features register
Port 1 digital disable register
XP1DIDIS
XPEREMU
XPICON
XPOLAR
XPP0
XPERCON copy for emulation (write only)
Extended port input threshold control register
XPWM module channel polarity register
XPWM module period register 0
XPP1
XPWM module period register 1
XPP2
XPWM module period register 2
XPP3
XPWM module period register 3
XPT0
XPWM module up/down counter 0
XPWM module up/down counter 1
XPWM module up/down counter 2
XPWM module up/down counter 3
XPWM module pulse width register 0
XPT1
XPT2
XPT3
XPW0
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ST10F273M
Register set
Table 47. List of XBus registers (continued)
Physical
Name
Reset
value
Description
address
XPW1
EC32h
EC34h
EC36h
EC00h
EC08h
EC06h
EC02h
EC0Ch
EC0Ah
EC80h
E906h
E900h
E904h
E902h
E980h
E90Ah
E908h
E80Ah
E800h
E804h
E802h
E880h
E808h
E806h
XPWM module pulse width register 1
XPWM module pulse width register 2
XPWM module pulse width register 3
XPWM module control register 0
XPWM module clear control reg. 0 (write only)
XPWM module set control register 0 (write only)
XPWM module control register 1
XPWM module clear control reg. 0 (write only)
XPWM module set control register 0 (write only)
XPWM module port control register
XASC baudrate generator reload register
XASC control register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
XXXXh
0000h
XPW2
XPW3
XPWMCON0
XPWMCON0CLR
XPWMCON0SET
XPWMCON1
XPWMCON1CLR
XPWMCON1SET
XPWMPORT
XS1BG
XS1CON
XS1CONCLR
XS1CONSET
XS1PORT
XASC clear control register (write only)
XASC set control register (write only)
XASC port control register
XS1RBUF
XASC receive buffer register
XS1TBUF
XASC transmit buffer register
XSSCBR
XSSC baudrate register
XSSCCON
XSSCCONCLR
XSSCCONSET
XSSCPORT
XSSCRB
XSSC control register
XSSC clear control register (write only)
XSSC set control register (write only)
XSSC port control register
XSSC receive buffer
XSSCTB
XSSC transmit buffer
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Register set
ST10F273M
23.3
Flash registers ordered by name
The following table lists in the order of their names all Flash Control Registers which are
implemented in the ST10F273M. These registers are physically mapped on the XBus.
Note:
These registers are not bit-addressable.
Table 48. List of Flash control registers
Physical
Name
Description
Reset value
address
FARH
0x000E 0012
0x000E 0010
0x000E 0002
0x000E 0000
0x000E 0006
0x000E 0004
0x000E 000A
0x000E 0008
0x000E 000E
0x000E 000C
0x000E 0014
0x000E DFB8
Flash address register - high
Flash address register - low
Flash control register 0 - high
Flash control register 0 - low
Flash control register 1 - high
Flash control register 1 - low
Flash data register 0 - high
Flash data register 0 - low
Flash data register 1 - high
Flash data register 1 - low
Flash error register
0000h
0000h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
FFFFh
FFFFh
0000h
ACFFh
FFFFh
FFFFh
FFFFh
FFFFh
FARL
FCR0H
FCR0L
FCR1H
FCR1L
FDR0H
FDR0L
FDR1H
FDR1L
FER
FNVAPR0
FNVAPR1H
FNVAPR1L
FNVWPIRH
FNVWPIRL
Flash non-volatile access protection reg.0
0x000E DFBE Flash non-volatile access protection reg.1 - high
0x000E DFBC Flash non-volatile access protection reg.1 - low
0x000E DFB6
0x000E DFB4
Flash non-volatile protection i register high
Flash non-volatile protection i register low
23.4
Identification registers
The ST10F273M has four Identification registers, mapped in ESFR space. These registers
contain:
●
A manufacturer identifier
●
●
●
A chip identifier with its revision
An internal Flash and size identifier
Programming voltage description
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ST10F273M
Register set
IDMANUF (F07Eh / 3Fh)
ESFR
Reset value: 0403h
15
14
13
12
11
10
MANUF
RO
9
8
7
6
5
4
0
3
0
2
0
1
1
0
1
RO
RO
RO
RO
RO
Table 49. IDMANUF register description
Bit Name
Function
Manufacturer identifier
15:5 MANUF
020h: STMicroelectronics manufacturer (JTAG worldwide normalization)
IDCHIP (F07Ch / 3Eh)
ESFR
Reset value: 111Xh
15
14
13
12
11
10
IDCHIP
RO
9
8
7
6
5
4
3
2
1
0
REVID
RO
Table 50. IDCHIP register description
Bit Name
Function
Device identifier
15:4 IDCHIP
111h: ST10F273M identifier (273)
Device revision identifier
3:0
REVID
Xh: According to revision number
IDMEM (F07Ah / 3Dh)
ESFR
Reset value: 2080h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MEMTYP
RO
MEMSIZE
RO
Table 51. IDMEM register description
Bit Name
Function
Internal memory size
15:12 MEMSIZE
Internal memory size is 4 x (MEMSIZE) (in Kbyte)
080h for 512 Kbytes (ST10F273M)
Internal memory type
0h: ROM-Less
1h: (M) ROM memory
11:0 MEMTYP
2h: (S) Standard Flash memory (ST10F273M)
3h: (H) High performance Flash memory
4h...Fh: Reserved
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Register set
ST10F273M
IDPROG (F078h / 3Ch)
ESFR
Reset value: 0040h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PROGVPP
RO
PROGVDD
RO
Table 52. IDPROG register description
Bit Name
Function
15:8 PROGVPP Programming VPP voltage (no need of external VPP) - 00h
Programming VDD voltage
VDD voltage when programming EPROM or Flash devices is calculated using
the following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for
ST10F273M (5V).
7:0 PROGVDD
Note:
All identification words are read-only registers.
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ST10F273M
Electrical characteristics
24
Electrical characteristics
24.1
Absolute maximum ratings
Table 53. Absolute maximum ratings
Symbol
Parameter
Values
Unit
VDD
Voltage on VDD pins with respect to ground (VSS
)
-0.5 to +6.5
-0.5 to +6.5
-0.5 to VDD + 0.5
VSS
VSTBY Voltage on VSTBY pin with respect to ground (VSS
VAREF Voltage on VAREF pins with respect to ground (VSS
VAGND Voltage on VAGND pins with respect to ground (VSS
)
)
V
)
VIO
IOV
Voltage on any pin with respect to ground (VSS
)
-0.5 to VDD + 0.5
10
Input current on any pin during overload condition
mA
ITOV
TST
ESD
Absolute sum of all input currents during overload condition
Storage temperature
| 75 |
-65 to +150
2000
°C
V
ESD susceptibility (Human Body Model)
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (V > V or V < V ) the
IN
DD
IN
SS
voltage on pins with respect to ground (V ) must not exceed the values defined by the
SS
Absolute Maximum Ratings.
During power-on and power-off transients (including standby entering/exiting phases), the
relationships between voltages applied to the device and the main V shall be always
DD
respected. In particular power-on and power-off of V
shall be coherent with V
AREF
DD
transient, in order to avoid undesired current injection through the on-chip protection diodes.
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Electrical characteristics
ST10F273M
24.2
Recommended operating conditions
Table 54. Recommended operating conditions
Value
Symbol
Parameter
Unit
Min
Max
VDD
VSTBY
VAREF
TA
Operating supply voltage
4.5
0
5.5
V
Operating standby supply voltage(1)
Operating analog reference voltage(2)
Ambient temperature under bias
Junction temperature under bias
VDD + 0.1
+125
-40
°C
TJ
+150
1. The value of the VSTBY voltage is specified in the range of 4.5 to 5.5 Volt. Nevertheless, it is acceptable to
exceed the upper limit (up to 6.0 Volt) for a maximum of 100 hours over the global 300000 hours,
representing the lifetime of the device (about 30 years). On the other hand, it is possible to exceed the
lower limit (down to 4.0 Volt) whenever RTC and 32 kHz on-chip oscillator amplifier are turned off (only
Standby RAM powered through VSTBY pin in Standby mode). When VSTBY voltage is lower than main
V
DD, the input section of VSTBY/EA pin can generate a spurious static consumption on VDD power supply
(in the range of tenth of µA).
2. For details on operating conditions concerning the usage of A/D converter refer to Section 24.7.
24.3
Power considerations
The average chip-junction temperature, T , in degrees Celsius, may be calculated using the
J
following equation:
Equation 1:
T = T + (P x Θ )
J
A
D
JA
Where:
T is the Ambient Temperature in °C,
A
Θ
is the Package Junction-to-Ambient Thermal Resistance, in °C/W,
JA
P is the sum of P
and P (P = P
+ P ),
INT I/O
D
INT
I/O
D
P
P
is the product of I and V , expressed in Watt. This is the Chip Internal Power,
DD DD
INT
I/O
represents the Power Dissipation on Input and Output Pins; User Determined.
and may be neglected. On the other hand,
Most of the time for the applications P < P
I/O
INT
P
may be significant if the device is configured to drive continuously external modules
I/O
and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
Equation 2:
P = K / (T + 273°C)
D
J
Therefore (solving equations 1 and 2):
Equation 3:
2
K = P x (T + 273°C) + Θ x P
D
D
A
JA
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ST10F273M
Electrical characteristics
Where:
K is a constant for the particular part, which may be determined from Equation 3 by
measuring P (at equilibrium) for a known T Using this value of K, the values of P and T
J
D
A.
D
may be obtained by solving Equation 1 and Equation 2 iteratively for any value of T .
A
Table 55. Thermal characteristics
Symbol
Description
Value (typical)
Unit
Thermal Resistance Junction-Ambient
PQFP 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch
LQFP 144 - 20 x 20 mm / 0.5 mm pitch
30
40
35
ΘJA
°C/W
LQFP 144 - 20 x 20 mm / 0.5 mm pitch on four-layer FR4
board (2 layers signals / 2 layers power)
Based on thermal characteristics of the package and with reference to the power
consumption figures provided in the next tables and diagrams, the following product
classification can be proposed. Anyhow, the exact power consumption of the device inside
the application must be computed according to different working conditions, thermal profiles,
real thermal resistance of the system (including printed circuit board or other substrata), I/O
activity, and so on.
Table 56. Package characteristics
Package
Ambient temperature range
CPU frequency range
PQFP 144
LQFP 144
-40 to +125°C
1 to 40 MHz
24.4
Parameter interpretation
The parameters listed in the following tables represent the characteristics of the
ST10F273M and its demands on the system.
Where the ST10F273M logic provides signals with their respective timing characteristics,
the symbol “CC” for Controller Characteristics, is included in the “Symbol” column. Where
the external system must provide signals with their respective timing characteristics to the
ST10F273M, the symbol “SR” for System Requirement, is included in the “Symbol” column.
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Electrical characteristics
ST10F273M
24.5
DC characteristics
V
= 5 V 10ꢀ, V = 0 V, T = -40 to +125°C
SS A
DD
Table 57. DC characteristics
Limit values
Symbol
Parameter
Test condition
Unit
Min
Max
Input low voltage (TTL mode)
(except RSTIN, EA, NMI, RPD, XTAL1, READY)
VIL
SR
SR
–
–
-0.3
0.8
V
V
Input low voltage (CMOS mode)
(except RSTIN, EA, NMI, RPD, XTAL1, READY)
VILS
-0.3
0.3 VDD
VIL1
VIL2
VIL3
SR Input low voltage RSTIN, EA, NMI, RPD
SR Input low voltage XTAL1 (CMOS only)
SR Input low voltage READY (TTL only)
–
-0.3
-0.3
-0.3
0.3 VDD
0.3 VDD
0.8
V
V
V
Direct drive mode
–
Input high voltage (TTL mode)
SR
VIH
–
2.0
VDD + 0.3
V
(except RSTIN, EA, NMI, RPD, XTAL1)
Input high voltage (CMOS mode)
SR
VIHS
VIH1
VIH2
–
–
0.7 VDD
0.7 VDD
VDD + 0.3
VDD + 0.3
VDD + 0.3
V
V
V
(except RSTIN, EA, NMI, RPD, XTAL1)
SR Input high voltage RSTIN, EA, NMI, RPD
Input high voltage XTAL1
(CMOS only)
SR
Direct drive mode 0.7 VDD
Input high voltage READY
(TTL only)
VIH3
SR
–
2.0
400
750
VDD + 0.3
700
V
Input hysteresis (TTL mode)
CC
(3)
VHYS
mV
mV
(except RSTIN, EA, NMI, XTAL1, RPD)
Input hysteresis (CMOS mode)
(except RSTIN, EA, NMI, XTAL1, RPD)
(3)
VHYSS CC
1400
(3)
(3)
(3)
(3)
VHYS1 CC Input hysteresis RSTIN, EA, NMI
VHYS2 CC Input hysteresis XTAL1
VHYS3 CC Input hysteresis READY (TTL only)
VHYS4 CC Input hysteresis RPD
Output low voltage
750
0
1400
50
mV
mV
mV
mV
400
500
700
1500
IOL = 8mA
IOL = 1mA
0.4
0.05
VOL
CC (P6[7:0], ALE, RD, WR/WRL, BHE/WRH,
CLKOUT, RSTIN, RSTOUT)
–
–
V
V
V
V
Output low voltage
IOL1 = 4mA
IOL1 = 0.5mA
0.4
0.05
VOL1
VOL2
VOH
CC (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0],
P4[7:0], P7[7:0], P8[7:0])
IOL2 = 85µA
IOL2 = 80µA
IOL2 = 60µA
VDD
0.5 VDD
0.3 VDD
CC Output low voltage RPD
–
Output high voltage
CC (P6[7:0], ALE, RD, WR/WRL, BHE/WRH,
CLKOUT, RSTOUT)
VDD - 0.8
VDD
IOH = -8mA
OH = -1mA
-
–
I
0.08
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ST10F273M
Electrical characteristics
Table 57. DC characteristics (continued)
Limit values
Unit
Symbol
Parameter
Output high voltage (1)
Test condition
Min
Max
VDD - 0.8
IOH1 = -4mA
IOH1 = -0.5mA
VOH1
CC (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0],
P4[7:0], P7[7:0], P8[7:0])
VDD
0.08
-
–
V
V
I
OH2 = -2mA
0
VOH2
|IOZ1
|IOZ2
CC Output high voltage RPD
IOH2 = -750µA
IOH2 = -150µA
0.3 VDD
0.5 VDD
–
|
CC Input leakage current (P5[15:0]) (2)
–
–
–
–
0.2
0.5
µA
µA
Input leakage current
(all except P5[15:0], P2[0], RPD, P3[12], P3[15])
|
|
CC
+1.0
-0.5
|IOZ3
CC Input leakage current (P2[0]) (3)
–
–
–
µA
|IOZ4
|IOZ5
|IOV1
|
|
|
CC Input leakage current (RPD)
–
–
–
3.0
1.0
5
µA
µA
CC Input leakage current (P3[12], P3[15])
SR Overload current (all except P2[0])
–
(3)(4)
mA
+5
-1
(3)(4)
|IOV2
|
SR Overload current (P2[0])(3)
–
mA
RRST
IRWH
IRWL
IALEL
IALEH
IP6H
CC RSTIN pull-up resistor
Read/Write inactive current(4)(5)
Read/Write active current(4)(7)
ALE inactive current(4)(5)
100 kΩ nominal
VOUT = 2.4V
VOUT = 0.4V
VOUT = 0.4V
VOUT = 2.4V
VOUT = 2.4V
VOUT = 0.4V
VIN = 2.0V
50
–
250
-40
–
kΩ
µA
µA
µA
µA
µA
µA
µA
µA
-500
20
–
–
ALE active current(4)(7)
300
-40
–
Port 6 inactive current (P6[4:0])(4)(5)
Port 6 active current (P6[4:0])(4)(6)
–
IP6L
-500
–
(5)
IP0H
-10
–
PORT0 configuration current(4)
(6)
IP0L
VIN = 0.8V
-100
Pin capacitance
CC
(3)(5)
CIO
–
–
–
–
10
pF
(digital inputs / outputs)
Run mode power supply current (7)
(execution from internal RAM)
ICC1
ICC2
IID
–
–
–
20 + 2 fCPU mA
20 + 1.8 fCPU mA
Run mode power supply current(8)(9)
(execution from internal Flash)
20 + 0.6 fCP
mA
Idle mode supply current(10)
U
Power down supply current(11)
IPD1
(RTC off, oscillators off, main voltage regulator
off)
TA = 25°C
TA = 25°C
–
–
150
8
µA
Power down supply current(11)(12)
(RTC on, main oscillator on, main voltage
regulator off)
IPD2
mA
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Electrical characteristics
ST10F273M
Table 57. DC characteristics (continued)
Limit values
Symbol
Parameter
Test condition
Unit
Min
Max
Power down supply current(11)
(RTC on, 32 kHz oscillator on, main voltage
regulator off)
IPD3
TA = 25°C
–
200
µA
VSTBY = 5.5 V
TA = TJ = 25°C
–
–
–
–
–
250
500
250
500
2.5
µA
µA
µA
µA
mA
Standby supply current(13)
(RTC off, oscillators off, VDD off, VSTBY on)
ISB1
VSTBY = 5.5 V
TA = TJ = 125°C
VSTBY = 5.5 V
Standby supply current(13)
(RTC on, 32 kHz oscillator on, main VDD off,
VSTBY on)
TA = TJ = 25°C
ISB2
VSTBY = 5.5 V
TA = TJ = 125°C
Standby supply current(8)(13)
(VDD transient condition)
ISB3
–
1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage is imposed by the external circuitry.
2. Port 5 leakage values are granted for not selected A/D converter channel. One channels is always selected (by default,
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
3. Consult your vendor to know which version of the on-chip oscillator amplifier is enabled (Low-Power or Wide-Swing).
The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 38 for a scheme of the input
circuitry.
4. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
for CS output and the open drain function is not enabled.
5. The maximum current may be drawn while the respective signal line remains inactive.
6. The minimum current must be drawn in order to drive the respective signal line active.
7. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure Figure 39 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all
outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: This implies that I/O current is not considered.
The device is doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
8. Not 100ꢀ tested, guaranteed by design characterization.
9. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 39 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: This implies that I/O current is not considered. The
device is doing the following:
Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
10. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 38 below. These parameters are tested and at maximum CPU clock with all outputs disconnected
and all inputs at VIL or VIH, RSTIN pin at VIH1Min.
136/186
Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
11. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD
– 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
Regulator is assumed off: in case it is not, additional 1mA shall be assumed. The value for this parameter shall be
considered as “Target Value” to be confirmed by silicon characterization.
12. Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any pin exceeds the
specified range (that is, VOV > VDD + 0.3 V or VOV < –0.3 V). The absolute sum of input overload currents on all port pins
may not exceed 50mA. The supply voltage must remain within the specified limits.
13. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD
– 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
Regulator is assumed off: in case it is not, additional 1mA shall be assumed. The value for this parameter shall be
considered as “Target Value” to be confirmed by silicon characterization.
Figure 38. Port2 test mode structure
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Doc ID 13453 Rev 4
137/186
Electrical characteristics
ST10F273M
24.6
Flash characteristics
V
= 5V 10ꢀ, V = 0V
SS
DD
Table 58. Flash characteristics
Typical
Maximum
TA = 125°C
TA = 25°C
Parameter
Unit
Notes
100k
cycles
0 cycles(1) 0 cycles(1)
Word program (32-bit)(2)
35
60
80
290
570
µs
µs
–
–
Double word program
(64-bit)(2)
150
Bank 0 program (512K)
(double word program)
3.9
9.9
37.3
s
s
–
0.6
0.5
0.9
0.8
1.0
0.9
not preprogrammed
preprogrammed
Sector erase (8K)
Sector erase (32K)
Sector erase (64K)
1.1
0.8
2.0
1.8
2.7
2.5
not preprogrammed
preprogrammed
s
1.7
1.3
3.7
3.3
5.1
4.7
not preprogrammed
preprogrammed
s
11.2
8.0
27.2
23.9
38.4
35.1
not preprogrammed
preprogrammed
Bank 0 erase (512K)(3)
s
Recovery from power-down
(4)
-
40
40
µs
(tPD
)
Program suspend latency(4)
Erase suspend latency(4)
-
-
10
30
10
30
µs
µs
Minimum delay
between 2 requests
Erase suspend request rate(4)
Set protection(4)
20
40
20
20
ms
µs
170
170
1. The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer).
2. Word and Double Word Programming times are provided as average values derived from a full sector
programming time: The absolute value of a Word or Double Word Programming time could be longer than
the average value.
3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the
Bank). As ST10F273M implements only one bank, the Bank Erase operation is equivalent to Module and
Chip Erase operations.
4. Not 100ꢀ tested, guaranteed by Design Characterization
138/186
Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
Table 59. Flash data retention characteristics
Data retention time
(average ambient temperature 60°C)
Number of program / erase
cycles
64 Kbyte
(-40°C < TA < 125°C)
256 Kbyte (code store)
(EEPROM emulation)(1)
0 - 100
1000
> 20 years
> 20 years
> 20 years
10 years
1 year
-
-
-
10000
100000
1. Two 64 Kbyte Flash Sectors may be typically used to emulate up to 4, 8 or 16 Kbytes of EEPROM.
Therefore, in case of an emulation of a 16 Kbyte EEPROM, 100,000 Flash Program / Erase cycles are
equivalent to 800,000 EEPROM Program/Erase cycles.
For an efficient use of the Read While Write feature and/or EEPROM Emulation, please refer to the
dedicated application note EEPROM Emulation with ST10F2xx (AN2061). Contact your local field service,
local sales person or STMicroelectronics representative to obtain a copy of such a guideline document.
24.7
A/D converter characteristics
V
V
= 5V 10ꢀ, V = 0V, T = -40 to +125°C, 4.5V ≤ V
≤ V
,
DD
DD
SS
SS
A
AREF
≤ V
≤ V + 0.2V
AGND
SS
Table 60. A/D converter characteristics
Symbol Parameter
Limit values
Test condition
Unit
Min
Max
VAREF
VAGND SR Analog ground voltage
SR Analog reference voltage(1)
4.5
VSS
VAGND
–
VDD
V
V
VSS + 0.2
VAIN
SR Analog input voltage(2)
VAREF
5
V
Running mode(3)
mA
µA
µs
IAREF
CC Reference supply current
Power down mode
–
1
(4)
tS
CC Sample time
1
–
(5)
tC
CC Conversion time
CC Differential non linearity(6)
CC Integral non linearity(6)
CC Offset error(6)
3
–
µs
DNL
INL
OFS
No overload
No overload
No overload
Port5
–1
+1
LSB
LSB
LSB
–1.5
–1.5
+1.5
+1.5
–2.0
–5.0
–7.0
+2.0
+5.0
+7.0
TUE
CC Total unadjusted error(6)
Port1 - No overload(3)
Port1 - Overload(3)
LSB
Coupling factor between
On both Port5 and
Port1
K
CC
–
–
–
10–6
3
–
inputs(3)(7)
CP1
CP2
CC
pF
pF
Input pin capacitance(3)(8)
Port5
Port1
4
6
CC
Doc ID 13453 Rev 4
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Electrical characteristics
ST10F273M
Table 60. A/D converter characteristics (continued)
Symbol Parameter Test condition
Limit values
Unit
Min
Max
CS
CC Sampling capacitance(3)(8)
–
3.5
pF
Ω
Port5
Port1
–
–
600
1600
RSW
RAD
CC
Analog switch resistance(3)(8)
CC
–
1300
Ω
1. VAREF can be tied to ground when A/D converter is not in use: An extra consumption (around 200µA) on
main VDD is added due to internal analog circuitry not completely turned off. Therefore, it is suggested to
maintain the VAREF at VDD level even when not in use, and eventually switch off the A/D converter circuitry
by setting bit ADOFF in ADCON register.
2. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be 0x000H or 0x3FFH, respectively.
3. Not 100ꢀ tested, guaranteed by design characterization.
4. During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
Values for the sample clock tS depends on programming and can be taken from Table 61: A/D converter
programming.
5. This parameter includes the sample time tS, the time for determining the digital result and the time to load
the result register with the conversion result. Values for the conversion clock tCC depend on programming
and can be taken from next Table 61.
6. DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0V, VDD = 5.0 V. It is guaranteed by design
characterization for all other voltages within the defined voltage range.
‘LSB’ has a value of VAREF/1024.
For Port5 channels, the specified TUE ( 2LSB) is guaranteed also with an overload condition (see IOV
specification) occurring on maximum 2 not selected analog input pins of Port5 and if the absolute sum of
input overload currents on all Port5 analog input pins does not exceed 10 mA.
For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins:
When an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input
positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static
injection), the specified TUE is degraded ( 7LSB). To acheive the same accuracy, the negative injection
current on Port1 pins must not exceed -1mA in case of both dynamic and static injection.
7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not
selected channels with the overload current within the different specified ranges (for both positive and
negative injection current).
8. Refer to scheme in Figure 41.
24.7.1
Conversion timing control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value several successive steps, which correspond to the 10-bit resolution of the ADC.
During these steps the internal capacitances are repeatedly charged and discharged via the
V
pin.
AREF
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions (sampling, and converting) take during conversion
can be programmed within a certain range in the ST10F273M relative to the CPU clock. The
absolute time that is consumed by the different conversion steps therefore is independent
140/186
Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
from the general speed of the controller. This allows adjusting the A/D converter of the
ST10F273M to the properties of the system:
Fast conversion can be achieved by programming the respective times to their absolute
possible minimum. This is preferable for scanning high frequency signals. The internal
resistance of analog source and analog supply must be sufficiently low, however.
High internal resistance can be achieved by programming the respective times to a higher
value, or the possible maximum. This is preferable when using analog sources and supply
with a high internal resistance in order to keep the current as low as possible. The
conversion rate in this case may be considerably lower, however.
The conversion times are programmed via the upper four bits of register ADCON. Bit fields
ADCTC and ADSTC are used to define the basic conversion time and in particular the
partition between sample phase and comparison phases. The table below lists the possible
combinations. The timings refer to the unit TCL, where f
= 1/2TCL. A complete
CPU
conversion time includes the conversion itself, the sample time and the time required to
transfer the digital value to the result register.
Table 61. A/D converter programming
ADCTC ADSTC
Sample
Comparison
Extra
Total conversion
00
00
00
00
11
11
11
11
10
10
10
10
00
01
10
11
00
01
10
11
00
01
10
11
TCL * 120
TCL * 140
TCL * 200
TCL * 400
TCL * 240
TCL * 280
TCL * 400
TCL * 800
TCL * 480
TCL * 560
TCL * 800
TCL * 1600
TCL * 240
TCL * 280
TCL * 280
TCL * 280
TCL * 480
TCL * 560
TCL * 560
TCL * 560
TCL * 960
TCL * 1120
TCL * 1120
TCL * 1120
TCL * 28
TCL * 16
TCL * 52
TCL * 44
TCL * 52
TCL * 28
TCL * 100
TCL * 52
TCL * 100
TCL * 52
TCL * 196
TCL * 164
TCL * 388
TCL * 436
TCL * 532
TCL * 724
TCL * 772
TCL * 868
TCL * 1060
TCL * 1444
TCL * 1540
TCL * 1732
TCL * 2116
TCL * 2884
Note:
The total conversion time is compatible with the formula valid for ST10F269, while the
meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum
conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4.85µs (see
ST10F269).
24.7.2
A/D conversion accuracy
The A/D converter compares the analog voltage sampled on the selected analog input
channel to its analog reference voltage (V
) and converts it into 10-bit digital data. The
AREF
Doc ID 13453 Rev 4
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Electrical characteristics
ST10F273M
absolute accuracy of the A/D conversion is the deviation between the input analog value and
the output digital value. It includes the following errors:
●
●
●
●
Offset error (OFS)
Gain error (GE)
Quantization error
Non-linearity error (Differential and Integral)
These four error quantities are explained below using Figure 40.
Offset error
Offset error is the deviation between actual and ideal A/D conversion characteristics when
the digital output value changes from the minimum (zero voltage) 00 to 01 (Figure 40, see
OFS).
Gain error
Gain error is the deviation between the actual and ideal A/D conversion characteristics when
the digital output value changes from the 3FEh to the maximum 3FFh once offset error is
subtracted. Gain error combined with offset error represents the so-called full-scale error
(Figure 40, OFS + GE).
Quantization error
Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB.
Non-linearity error
Non-linearity error is the deviation between actual and the best-fitting A/D conversion
characteristics (see Figure 40):
●
Differential non-linearity error is the actual step dimension versus the ideal one
(1 LSB ).
IDEAL
●
Integral non-linearity error is the distance between the center of the actual step and the
center of the bisector line, in the actual characteristics. Note that for integral non-
linearity error, the effect of offset, gain and quantization errors is not included.
Note:
Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the
real characteristic, and 1/2 LSB after the last step again of the real characteristic.
24.7.3
Total unadjusted error
The total unadjusted error specifies the maximum deviation from the ideal characteristic:
The number provided in the datasheet represents the maximum error with respect to the
entire characteristic. It is a combination of the offset, gain and integral linearity errors. The
different errors may compensate each other depending on the relative sign of the offset and
gain errors. Refer to Figure 40, see TUE.
142/186
Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
Figure 40. A/D conversion characteristics
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24.7.4
Analog reference pins
The accuracy of the A/D converter depends on the accuracy of its analog reference: A noise
in the reference results in at least that much error in a conversion. A low pass filter on the
A/D converter reference source (supplied through pins V
and V
) is recommended
AREF
AGND
in order to clean the signal, minimizing the noise. A simple capacitive bypass may be
sufficient in most cases; in presence of high RF noise energy, inductors or ferrite beads may
be necessary.
In this architecture, V
and V
pins also represent the power supply of the analog
AREF
AGND
circuitry of the A/D converter: There is an effective DC current requirement from the
reference voltage by the internal resistor string in the R-C DAC array and by the rest of the
analog circuitry.
An external resistance on V
could introduce error under certain conditions: For this
AREF
reason, series resistance is not advisable, and more in general any series devices in the
filter network should be designed to minimize the DC resistance.
Analog input pins
To improve the accuracy of the A/D converter, it is necessary that analog input pins have low
AC impedance. Placing a capacitor with good high frequency characteristics at the input pin
of the device can be effective: The capacitor should be as large as possible, ideally infinite.
This capacitor contributes to attenuating the noise present on the input pin; moreover, it
sources charge during the sampling phase, when the analog signal source is a high-
impedance source.
Doc ID 13453 Rev 4
143/186
Electrical characteristics
ST10F273M
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC Filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth).
Figure 41. A/D converter input pins scheme
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Input leakage and external circuit
The series resistor utilized to limit the current to a pin (see R in Figure 41), in combination
L
with a large source impedance, can lead to a degradation of A/D converter accuracy when
input leakage is present.
Data about maximum input leakage current at each pin is provided in the datasheet
(Electrical characteristics section). Input leakage is greatest at high operating temperatures
and in general decreases by one half for each 10°C decrease in temperature.
Considering that, for a 10-bit A/D converter one count is about 5mV (assuming V
= 5V),
AREF
an input leakage of 100nA acting though an R = 50kΩ of external resistance leads to an
L
error of exactly one count (5mV); if the resistance were 100kΩ, the error would become two
counts.
Eventual additional leakage due to external clamping diodes must also be taken into
account in computing the total leakage affecting the A/D converter measurements. Another
contribution to the total leakage is represented by the charge-sharing effects with the
sampling capacitance: C being substantially a switched capacitance, with a frequency
S
equal to the conversion rate of a single channel (maximum when fixed channel continuous
conversion mode is selected), it can be seen as a resistive path to ground. For instance,
assuming a conversion rate of 250 kHz, with C equal to 4pF, a resistance of 1MΩ is
S
obtained (R = 1 / f C , where f represents the conversion rate at the considered
EQ
C
S
C
channel). To minimize the error induced by the voltage partitioning between this resistance
144/186
Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
(sampled voltage on C ) and the sum of R + R + R + R
+ R , the external circuit
AD
S
S
F
L
SW
must be designed to respect the following relation:
R
+ R + R + R
+ R
S
F
L
SW
AD
1
2
--
⋅ ------------------------------------------------------------------------------ < LSB
V
A
R
EQ
The formula above provides constraints for external network design, in particular on a
resistive path.
A second aspect involving the capacitance network must be considered. Assuming the three
capacitances C , C and C initially charged at the source voltage V (refer to the
F
P1
P2
A
equivalent circuit reported in Figure 41), when the sampling phase is started (A/D switch
close), a charge-sharing phenomena is installed.
Figure 42. Charge-sharing timing diagram during sampling phase
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In particular two different transient periods can be distinguished (see Figure 42):
●
A first and quick charge transfer from the internal capacitance C and C to the
P1 P2
sampling capacitance C occurs (C is supposed initially completely discharged):
S
S
considering a worst case (since the time constant in reality would be faster) in which
C
is reported in parallel to C (call C = C + C ), the two capacitances C and
P2
P1 P P1 P2 P
C are in series, and the time constant is:
S
C ⋅ C
P
S
τ
= (R
+ R ) ⋅ ---------------------
1
SW
AD
C + C
P
S
●
This relation can again be simplified considering only C as an additional worst
S
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time T is always much
S
longer than the internal time constant:
τ < (R
+ R ) ⋅ C « T
AD S S
1
SW
●
The charge of C and C is redistributed also on C , determining a new value of the
P1 P2 S
voltage V on the capacitance according to the following equation:
A1
V
⋅ (C + C
+ C ) = V ⋅ (C
P2
+ C
)
P2
A1
S
P1
A
P1
Doc ID 13453 Rev 4
145/186
Electrical characteristics
ST10F273M
●
A second charge transfer involves also C (that is typically bigger than the on-chip
F
capacitance) through the resistance R : again considering the worst case in which C
L
P2
and C were in parallel to C (since the time constant in reality would be faster), the
S
P1
time constant is:
τ
< R ⋅ (C + C
+ C
)
P2
2
L
S
P1
●
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time T , a constraint on
S
R sizing is obtained:
L
10 ⋅ τ = 10 ⋅ R ⋅ (C + C
+ C ) ≤ T
P2 S
2
L
S
P1
●
Of course, R shall be sized also according to the current limitation constraints, in
L
combination with R (source impedance) and R (filter resistance). C being
S
F
F
definitively bigger than C , C and C , the final voltage V (at the end of the charge
P1
P2
S
A2
transfer transient) will then be much higher than V . The following equation must be
A1
respected (charge balance assuming now C already charged at V ):
S
A1
V
⋅(C + C + C + C ) =V ⋅C + V ⋅(C + C + C )
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence
of the R C filter, is not able to provide the extra charge to compensate the voltage drop on
F
F
C with respect to the ideal source V ; the time constant R C of the filter is very high with
S
A
F F
respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing (see
S
Figure 43).
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of
0
the anti-aliasing filter, f ), according to Nyquist theorem the conversion rate f must be at
F
C
least 2f ; it means that the constant time of the filter is greater than or at least equal to twice
0
the conversion period (T ). Again the conversion period T is longer than the sampling time
C
C
T , which is just a portion of it, even when fixed channel continuous conversion mode is
S
selected (fastest conversion rate at a specific channel): In conclusion it is evident that the
time constant of the filter R C is definitively much higher than the sampling time T , so the
F
F
S
charge level on C cannot be modified by the analog signal source during the time in which
S
the sampling switch is closed.
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Electrical characteristics
Figure 43. Anti-aliasing filter and conversion rate
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The considerations above lead to impose new constraints to the external circuit, to reduce
the accuracy error due to the voltage drop on C ; from the two charge balance equations
S
above, it is simple to derive the following relation between the ideal and real sampled
voltage on C :
S
V
C
+ C
+ C
A
P1
----------- = ------------------------------------------------------------
+ C + C + C
P2
F
V
C
A2
P1
P2
F
S
From this formula, in the worst case (when V is maximum, that is, for instance 5V),
A
assuming to accept a maximum error of half a count (~2.44mV), a constraint is immediately
obvious on C value:
F
C
> 2048 ⋅C
S
F
In the next section an example of how to design the external network is provided, assuming
some reasonable values for the internal parameters and making a hypothesis on the
characteristics of the analog signal to be sampled.
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Electrical characteristics
ST10F273M
Example of external network sizing
The following hypotheses are formulated in order to proceed in designing the external
network on A/D converter input pins:
●
●
●
●
●
●
●
●
●
●
●
Analog Signal Source Bandwidth (f ): 10 kHz
0
Conversion Rate (f ):
25 kHz
1µs
C
Sampling Time (T ):
S
Pin Input Capacitance (C ):
5pF
P1
Pin Input Routing Capacitance (C ): 1pF
P2
Sampling Capacitance (C ):
4pF
S
Maximum Input Current Injection (I ): 3mA
INJ
Maximum Analog Source Voltage (V :12V
AM)
Analog Source Impedance (R ):
100Ω
S
Channel Switch Resistance (R ):
500Ω
200Ω
SW
Sampling Switch Resistance (R ):
AD
1. Supposing to design the filter with the pole exactly at the maximum frequency of the
signal, the time constant of the filter is:
1
2πf
R C = ------------ = 15.9μs
C F
0
2. Using the relation between C and C and taking some margin (4000 instead of 2048),
F
S
it is possible to define C :
F
C = 4000 C⋅ = 16nF
F
S
3. As a consequence of step 1 and 2, RC can be chosen:
1
R = -------------------- = 995Ω ≅ 1kΩ
F
2πf C
0 F
4. Considering the current injection limitation and supposing that the source can go up to
12V, the total series resistance can be defined as:
V
AM
R
+ R + R = ------------- = 4 k Ω
S
F
L
I
INJ
from which is now simple to define the value of R :
L
V
AM
R = ------------- – R – R = 2.9kΩ
L
F
S
I
INJ
5. Now the three elements of the external circuit R , C and R are defined. Some
F
F
L
conditions discussed in the previous paragraphs have been used to size the
component, the other must now be verified. The relation which allows minimization of
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ST10F273M
Electrical characteristics
the accuracy error introduced by the switched capacitance equivalent resistance is in
this case:
1
R
= --------------= 10MΩ
EQ
f C
C S
So the error due to the voltage partitioning between the real resistive path and C is
S
less then half a count (considering the worst case when V = 5V):
A
R
+ R + R + R
+ R
S
F
L
SW
AD
1
2
--
V ⋅--------------------------------------------------------------------------= 2.35mV < LSB
A
R
EQ
The other condition to be verified is if the time constants of the transients are really and
significantly shorter than the sampling period duration T :
S
τ = (R
+ R
) ⋅ C = 2.8ns
AD S
TS = 1μs
1
SW
10 ⋅τ = 10 ⋅R ⋅(C + C
+ C )= 290ns
TS = 1μs
2
L
S
P1
P2
For the complete set of parameters characterizing the ST10F273M A/D converter equivalent
circuit, refer to Section 24.7: A/D converter characteristics on page 139.
24.8
AC characteristics
24.8.1
Test waveforms
Figure 44. Input/output waveforms
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Electrical characteristics
ST10F273M
Figure 45. Float waveform
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24.8.2
Definition of internal timing
The internal operation of the ST10F273M is controlled by the internal CPU clock f
. Both
CPU
edges of the CPU clock can trigger internal (for example pipeline) or external (for example
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate f
.
CPU
This influence must be regarded when calculating the timings for the ST10F273M.
The example for PLL operation shown in Figure 46 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
Figure 46. Generation mechanisms for the CPU clock
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Electrical characteristics
24.8.3
Clock generation modes
The next Table 62 associates the combinations of these three bits with the respective clock
generation mode.
Table 62. On-chip clock generator selections
External clock input range(1)(2)
P0.15-13
(P0H.7-5)
CPU frequency
fCPU = fXTAL x F
Notes
Main OSC (MHz)
1
1
1
1
1
1
0
0
1
0
1
0
fXTAL x 4
4 to 8
5.3 to 10.6
4 to 5
Default configuration
f
XTAL x 3
fXTAL x 8
fXTAL x 5
6.4 to 8
Direct drive
0
1
1
fXTAL x 1
1 to 40
(oscillator bypassed)(3)
0
0
0
1
0
0
0
1
0
fXTAL x 10
4
4 to 12
-
fXTAL / 2
CPU clock via prescaler(2)
Reserved
-
1. The external clock input range refers to a CPU clock range of 1...40 MHz. Moreover, the PLL usage is
limited to 4 to 12 MHz input frequency range. All configurations need a crystal (or ceramic resonator) to
generate the CPU clock through the internal oscillator amplifier (apart from Direct Drive): vice versa, the
clock can be forced through an external clock source only in Direct Drive mode (on-chip oscillator amplifier
disabled, so no crystal or resonator can be used).
2. The limits on input frequency are 4 to 12 MHz since the usage of the internal oscillator amplifier is required.
Also when the PLL is not used and the CPU clock corresponds to fXTAL/2, an external crystal or resonator
shall be used: it is not possible to force any clock though an external clock source.
3. The maximum depends on the duty cycle of the external clock signal: When 40 MHz is used, 50ꢀ duty
cycle shall be granted (low phase = high phase = 12.5ns); when 20 MHz is selected, a 25ꢀ duty cycle can
be accepted (minimum phase, high or low, again equal to 12.5ns).
24.8.4
Prescaler operation
When pins P0.15-13 (P0H.7-5) equal ‘001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
is half the frequency of f
and the high and low time of f
(that
CPU
XTAL
CPU
is, the duration of an individual TCL) is defined by the period of the input clock f
.
XTAL
The timings listed in the AC Characteristics that refer to TCL therefore can be calculated
using the period of f for any TCL.
XTAL
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,
then the PLL is switched off.
24.8.5
Direct drive
When pins P0.15-13 (P0H.7-5) equal ‘011’ during reset the on-chip phase locked loop is
disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by
the input clock signal on XTAL1 pin.
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Electrical characteristics
ST10F273M
The frequency of CPU clock (f
) directly follows the frequency of f
so the high and
XTAL
CPU
low time of f
input clock f
(that is, the duration of an individual TCL) is defined by the duty cycle of the
.
CPU
XTAL
Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value
can be calculated by the following formula:
TCL
= 1 ⁄ f
xlDC
min
XTALl
min
DC= duty cycle
For two consecutive TCLs, the deviation caused by the duty cycle of f
is compensated,
XTAL
so the duration of 2TCL is always 1/f
.
XTAL
The minimum value TCL
has to be used only once for timings that require an odd number
min
of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
2TCL= 1 ⁄ f
XTAL
The address float timings in Multiplexed bus mode (t and t ) use the maximum duration of
11
45
TCL (TCL
= 1/f
x DC
) instead of TCL
.
max
XTAL
max
min
Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is
cleared, the PLL runs on its free-running frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
24.8.6
Oscillator watchdog (OWD)
An on-chip watchdog oscillator is implemented in the ST10F273M. This feature is used for
safety operation with external crystal oscillator (available only when using direct drive mode
with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the
frequency of the external crystal oscillator). This watchdog oscillator operates as following.
The reset default configuration enables the watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the
watchdog counter. On each transition of external clock, the watchdog counter is cleared. If
an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply
current.
24.8.7
Phase locked loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see Table 62). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (f
=
CPU
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Electrical characteristics
f
x F). With every F’th transition of f
the PLL circuit synchronizes the CPU clock to
XTAL
XTAL
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of f
is constantly adjusted so it is
CPU
locked to f
. The slight variation causes a jitter of f
which also effects the duration of
XTAL
CPU
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
to
CPU
keep it locked on f
one TCL period.
. The relative deviation of TCL is the maximum when it is referred to
XTAL
This is especially important for bus cycles using wait states and for example, such as for the
operation of timers or serial interfaces. For all slower operations and longer periods (for
example, such as pulse train generation or measurement, or lower baudrates) the deviation
caused by the PLL jitter is negligible. Refer to the next Section 24.8.9: PLL jitter for more
details.
24.8.8
Voltage controlled oscillator
The ST10F273M implements a PLL which combines different levels of frequency dividers
with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. Table 63 on
page 153 gives a detailed summary of the internal settings and VCO frequency.
Table 63. Internal PLL divider mechanism
PLL
P0.15-13
(P0H.7-5)
Input
prescaler
Output
prescaler fCPU = fXTAL x F
CPU frequency
XTAL frequency
Multiply
by
Divide by
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
4 to 8 MHz
5.3 to 10.6 MHz
4 to 5 MHz
6.4 to 8 MHz
1 to 40 MHz
4 MHz
64
48
64
40
fXTAL x 4
4
2
f
XTAL x 3
fXTAL / 4
–
fXTAL x 8
fXTAL x 5
–
fXTAL / 2
–
PLL bypassed
fXTAL x 1
40
2
–
fXTAL x 10
fXTAL / 2
4 to 12 MHz
Reserved
PLL bypassed
fPLL / 2
Note:
The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is
64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 40 MHz.
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Electrical characteristics
Example 1
ST10F273M
●
●
●
●
●
f
= 4 MHz
XTAL
P0(15:13) = ‘110’ (multiplication by 3)
PLL Input Frequency = 1 MHz
VCO frequency = 48 MHz: NOT VALID, must be 64 to 128 MHz
f
= NOT VALID
CPU
Example 2
●
●
●
●
●
●
f
= 8 MHz
XTAL
P0(15:13) = ‘100’ (multiplication by 5)
PLL Input Frequency = 2 MHz
VCO frequency = 80 MHz
PLL Output Frequency = 40 MHz (VCO frequency divided by 2)
f
= 40 MHz (no effect of Output Prescaler)
CPU
24.8.9
PLL jitter
The following terminology is hereafter defined:
●
Self referred single period jitter
Also called “Period Jitter”, it can be defined as the difference of the T
and T
,
max
min
where T
is maximum time period of the PLL output clock and T
is the minimum
max
min
time period of the PLL output clock.
●
Self referred long term jitter
Also called “N period jitter”, it can be defined as the difference of T
and T , where
min
max
T
is the maximum time difference between N + 1 clock rising edges and T
is the
max
min
minimum time difference between N + 1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N = 1, this becomes the single period
jitter.
Jitter at the PLL output can be due to the following reasons:
●
Jitter in the input clock
Noise in the PLL loop
●
Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the
frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency
jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.
Noise in the PLL loop
This contribution again can be caused by the following sources:
●
Device noise of the circuit in the PLL
Noise in supply and substrate.
●
Device noise of the circuit in the PLL
The long term jitter is inversely proportional to the bandwidth of the PLL: the wider is the
loop bandwidth, the lower is the jitter due to noise in the loop. Besides, the long term jitter is
practically independent on the multiplication factor.
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Electrical characteristics
The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled
Oscillator). There are two main sources of noise: thermal (random noise, frequency
independent so practically white noise) and flicker (low frequency noise, 1/f). For the
2
frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f
3
region in the output noise spectrum, while the flicker noise in a 1/f . Assuming a noiseless
2
PLL input and supposing that the VCO is dominated by its 1/f noise, the R.M.S. value of the
accumulated jitter is proportional to the square root of N, where N is the number of clock
periods within the considered time interval.
On the contrary, assuming again a noiseless PLL input and supposing that the VCO is
3
dominated by its 1/f noise, the R.M.S. value of the accumulated jitter is proportional to N,
where N is the number of clock periods within the considered time interval.
2
The jitter in the PLL loop can be modelized as dominated by the i1/f noise for N smaller
than a certain value depending on the PLL output frequency and on the bandwidth
characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f noise
3
component. Lastly, for N greater than a second value of N, a saturation effect is evident, so
the jitter does not grow anymore when considering a longer time interval (jitter stable
increasing the number of clock periods N). The PLL loop acts as a high pass filter for any
noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation
value corresponds to what has been called self referred long term jitter of the PLL. In
Figure 47 the maximum jitter trend versus the number of clock periods N (for some typical
CPU frequencies) is reported: the curves represent the very worst case, computed taking
into account all corners of temperature, power supply and process variations: the real jitter
is always measured well below the given worst case values.
Noise in supply and substrate
Digital supply noise adds deterministic components to the PLL output jitter, independent on
multiplication factor. Its effects is strongly reduced thanks to particular care used in the
physical implementation and integration of the PLL module inside the device. Anyhow, the
contribution of the digital noise to the global jitter is widely taken into account in the curves
provided in Figure 47.
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Electrical characteristics
ST10F273M
Figure 47. ST10F273M PLL jitter
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24.8.10 PLL lock / unlock
During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the
CPU is generated, and the reference clock (oscillator) is automatically disconnected from
the PLL input: in this way, the PLL goes into free-running mode, providing the system with a
backup clock signal (free running frequency f ). This feature allows to recover from a
free
crystal failure occurrence without risking to go into an undefined configuration: The system
is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path between reference clock and PLL input can be restored only by a hardware reset,
or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
Note:
The external RC circuit on RSTIN pin shall be properly sized in order to extend the duration
of the low pulse to grant the PLL gets locked before the level at RSTIN pin is recognized
high: bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitively not
sufficient to get the PLL locked starting from free-running mode).
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Electrical characteristics
Table 64. PLL characteristics (V = 5V ± 10%, V = 0V, T = -40°C to +125°C)
DD
SS
A
Value
Symbol
Parameter
Conditions
Unit
Min
Max
TPSUP
TLOCK
PLL start-up time(1)
PLL lock-in time
Stable VDD and reference clock
–
–
300
µs
Stable VDD and reference clock,
starting from free-running mode
250
Single period jitter(1)
(cycle to cycle = 2 TCL)
6 sigma time period variation
(peak to peak)
TJIT
-500
+500
ps
Multiplication factors: 3, 4
250
500
2000
4000
Ffree
PLL free running frequency
kHz
Multiplication factors: 5, 8, 10
1. Not 100ꢀ tested, guaranteed by design characterization.
24.8.11 Main oscillator specifications
= 5V 10ꢀ, V = 0V, T = -40 to +125°C
DD
SS
A
Table 65. Main oscillator characteristics
Value
Typ
Symbol
Parameter
Conditions
Unit
Min
Max
Oscillator
transconductance
gm
–
8
17
35 mA/V
VOSC
VAV
Oscillation amplitude(1)
Peak to peak
VDD – 0.4
–
V
–
Oscillation voltage level(1) Sine wave middle
VDD / 2 – 0.25
–
Stable VDD - crystal
Oscillator start-up time(1)
3
2
4
tSTUP
ms
3
Stable VDD - resonator
1. Not 100ꢀ tested, guaranteed by design characterization.
Figure 48. Crystal oscillator and resonator connection diagram
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Electrical characteristics
ST10F273M
47pF
Table 66. Main oscillator negative resistance (module)
CA =
12pF
15pF
18pF
22pF
27pF
33pF
39pF
4 MHz
8 MHz
12 MHz
460 Ω
380 Ω
370 Ω
550 Ω
460 Ω
420 Ω
675 Ω
540 Ω
360 Ω
800 Ω
640 Ω
-
840 Ω
580 Ω
-
1000 Ω
1180 Ω
1200 Ω
-
-
-
-
-
-
The given values of C do not include the stray capacitance of the package and of the
A
printed circuit board: the negative resistance values are calculated assuming additional 5pF
to the values in the table. The crystal shunt capacitance (C ), the package and the stray
0
capacitance between XTAL1 and XTAL2 pins is globally assumed equal to 4pF.
The external resistance between XTAL1 and XTAL2 is not necessary, since already present
on the silicon.
24.8.12 32 kHz oscillator specifications
V
= 5V 10ꢀ, V = 0V, T = -40 to +125°C
SS A
DD
Table 67. 32 kHz oscillator characteristics
Value
Typ
Symbol
Parameter
Conditions
Unit
Min
Max
Start-up
20
8
31
17
1.0
0.9
1
50
30
2.4
1.2
5
gm32
Oscillator transconductance(1)
µA/V
Normal run
VOSC32 Oscillation amplitude(2)
VAV32
Oscillation voltage level(2)
tSTUP32 Oscillator start-up time(2)
Peak to peak
Sine wave middle
Stable VDD
0.5
0.7
–
V
s
1. At power-on a high current biasing is applied for faster oscillation start-up. Once the oscillation is started,
the current biasing is reduced to lower the power consumption of the system.
2. Not 100ꢀ tested, guaranteed by design characterization.
Figure 49. 32 kHz crystal oscillator connection diagram
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ST10F273M
Electrical characteristics
Table 68. Minimum values of negative resistance (module) for 32 kHz oscillator
Frequency CA = 6pF CA = 12pF CA = 15pF CA = 18pF CA = 22pF CA = 27pF CA = 33pF
32 kHz
-
-
-
-
150 kΩ
120 kΩ
90 kΩ
The given values of C do not include the stray capacitance of the package and of the
A
printed circuit board: The negative resistance values are calculated assuming additional 5pF
to the values in the table. The crystal shunt capacitance (C ) and the package capacitance
0
between XTAL3 and XTAL4 pins is globally assumed equal to 4pF. The external resistance
between XTAL3 and XTAL4 is not necessary, since already present on the silicon.
Warning: Direct driving on XTAL3 pin is not supported. Always use a
32 kHz crystal oscillator.
24.8.13 External clock drive XTAL1
When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock
directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since
the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that
targets a maximum CPU frequency of 40 MHz.
In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip
oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then, when
the on-chip oscillator is enabled it is forbidden to use any external clock source different
from crystal or ceramic resonator.
Table 69. External clock drive XTAL1 timing
Direct drive with
Direct drive
CPU = fXTAL
PLL usage
prescaler
f
f
CPU = fXTAL x F
Parameter
Symbol
Unit
fCPU = fXTAL / 2
Min
Max
Min
Max
Min
Max
XTAL1 period(1)(2) tOSC SR
25
6
–
–
–
2
2
10
3
250
–
100
6
250
–
High time(3)
Low time(3)
Rise time(3)
Fall time(3)
t1
t2
t3
t4
SR
SR
SR
SR
6
3
–
6
–
ns
–
–
2
–
2
–
–
2
–
2
1. The minimum value for the XTAL1 signal period shall be considered as the theoretical minimum. The real
minimum value depends on the duty cycle of the input clock signal.
2. 4 to 12 MHz is the input frequency range when using an external clock source. 40 MHz can be applied with
an external clock source only when Direct Drive mode is selected: in this case, the oscillator amplifier is
bypassed so it does not limit the input frequency.
3. The input clock signal must reach the defined levels VIL2 and VIH2
.
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Electrical characteristics
ST10F273M
Figure 50. External clock drive XTAL1
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Note:
When Direct Drive is selected, an external clock source can be used to drive XTAL1. The
maximum frequency of the external clock source depends on the duty cycle: when 40 MHz
is used, 50% duty cycle shall be granted (low phase = high phase = 12.5ns); when for
instance 20 MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low,
again equal to 12.5ns).
24.8.14 Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes how these variables are to be computed.
Table 70. Memory cycle variables
Description
ALE Extension
Symbol
Values
tA
tC
tF
TCL x [ALECTL]
Memory Cycle Time wait states
Memory Tri-stateTime
2TCL x (15 - [MCTC])
2TCL x (1 - [MTTC])
24.8.15 External memory bus timing
The following sections present the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40 MHz.
Note:
All external memory bus timings and SSC timings reported in the following tables are based
on design characterization and not fully tested in production.
24.8.16 Multiplexed bus
V
= 5V 10ꢀ, V = 0V, T = -40 to +125°C, CL = 50pF,
SS A
DD
ALE cycle time = 6 TCL + 2t + t + t (75ns at 40 MHz CPU clock without wait states)
A
C
F
Table 71. Multiplexed bus timings
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
t5 CC ALE high time
4 + tA
–
–
TCL - 8.5 + tA
TCL - 11 + tA
–
–
ns
ns
t6 CC Address setup to ALE
1.5 + tA
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Electrical characteristics
Table 71. Multiplexed bus timings (continued)
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
t7 CC Address hold after ALE
4 + tA
4 + tA
–
TCL - 8.5 + tA
TCL - 8.5 + tA
–
ns
ns
ALE falling edge to RD, WR
t8 CC
–
–
(with RW-delay)
ALE falling edge to RD, WR (no
RW-delay)
t9 CC
-8.5 + tA
–
6
-8.5 + tA
–
ns
ns
ns
ns
ns
ns
ns
Address float after RD, WR
t10 CC
–
–
6
(with RW-delay)
Address float after RD, WR (no
RW-delay)1
t11 CC
–
15.5 + tC
28 + tC
–
18.5
–
–
TCL + 6
RD, WR low time
t12 CC
2TCL - 9.5 + tC
3TCL - 9.5 + tC
–
–
(with RW-delay)
RD, WR low time
t13 CC
–
–
(no RW-delay)
RD to valid data in
t14 SR
6 + tC
2TCL - 19 + tC
3TCL - 19 + tC
(with RW-delay)
RD to valid data in
t15 SR
–
–
–
18.5 + tC
–
–
–
(no RW-delay)
t16 SR ALE low to valid data in
17.5 + tA + tC
20 + 2tA + tC
3TCL - 20 + tA + tC ns
4TCL - 30 + 2tA + tC ns
Address/Unlatched CS to valid
t17 SR
data in
Data hold after RD
t18 SR
0
–
0
–
ns
rising edge
t19 SR Data float after RD1
t22 CC Data valid to WR
–
16.5 + tF
–
2TCL - 8.5 + tF
ns
ns
ns
ns
10 + tC
4 + tF
15 + tF
–
–
–
2TCL - 15 + tC
2TCL - 8.5 + tF
2TCL - 10 + tF
–
–
–
t23 CC Data hold after WR
t25 CC ALE rising edge after RD, WR
Address/unlatched CS hold
after RD, WR
t27 CC
10 + tF
–
2TCL - 15 + tF
–
ns
ns
t38 CC ALE falling edge to latched CS
t39 SR Latched CS low to valid data in
t40 CC Latched CS hold after RD, WR
-4 - tA
–
10 - tA
16.5 + tC + 2tA
–
-4 - tA
10 - tA
–
3TCL - 21 + tC + 2tA ns
27 + tF
3TCL - 10.5 + tF
–
–
ns
ns
ALE fall. edge to RdCS, WrCS
t42 CC
7 + tA
-5.5 + tA
–
–
–
TCL - 5.5 + tA
(with RW delay)
ALE fall. edge to RdCS, WrCS
(no RW delay)
t43 CC
-5.5 + tA
–
–
ns
ns
Address float after RdCS, WrCS
(with RW delay)
t44 CC
1.5
1.5
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Electrical characteristics
ST10F273M
Table 71. Multiplexed bus timings (continued)
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Address float after RdCS, WrCS
(no RW delay)
t45 CC
t46 SR
t47 SR
t48 CC
t49 CC
–
14
–
TCL + 1.5
ns
ns
ns
ns
ns
RdCS to Valid Data in
(with RW delay)
–
–
4 + tC
–
2TCL - 21 + tC
RdCS to Valid Data in
(no RW delay)
16.5 + tC
–
3TCL - 21 + tC
RdCS, WrCS Low Time
(with RW delay)
15.5 + tC
28 + tC
–
–
2TCL - 9.5 + tC
3TCL - 9.5 + tC
–
–
RdCS, WrCS Low Time
(no RW delay)
t50 CC Data valid to WrCS
t51 SR Data hold after RdCS
t52 SR Data float after RdCS1
10 + tC
–
–
2TCL - 15 + tC
–
ns
ns
ns
0
–
0
–
–
16.5 + tF
2TCL - 8.5 + tF
Address hold after
t54 CC
6 + tF
6 + tF
–
–
2TCL - 19 + tF
2TCL - 19 + tF
–
–
ns
ns
RdCS, WrCS
t56 CC Data hold after WrCS
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Electrical characteristics
Figure 51. External memory cycle: multiplexed bus, with/ without read/ write delay, normal ALE
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Doc ID 13453 Rev 4
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Electrical characteristics
ST10F273M
Figure 52. External memory cycle: multiplexed bus, with/ without read/ write delay, extended
ALE
CLKOUT
t16
t5
t6
t25
ALE
t38
t40
t17
t39
t27
CSx
t6
t17
A23-A16
(A15-A8)
BHE
Address
t27
Read Cycle
t6
t7
Address/Data
Bus (P0)
Data In
t18
Address
t8
t10
t11
t19
t9
t14
RD
t15
t13
t12
Write Cycle
Address/Data
Bus (P0)
Address
Data Out
t23
t8
t10
t11
t9
t22
WR
WRL
WRH
t12
t13
GAPGCFT00935
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Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
Figure 53. External memory cycle: multiplexed bus, with/ without read/ write delay, normal ALE,
read/ write chip select
CLKOUT
t5
t25
t16
ALE
t6
t27
t17
A23-A16
(A15-A8)
BHE
Address
t16
t6
t7
Read Cycle
Address/Data
Bus (P0)
t51
Data In
Address
Address
t44
t52
t42
t46
RdCSx
t48
t49
t43
t45
t47
Write Cycle
t56
Address/Data
Bus (P0)
Address
Data Out
t42
t50
WrCSx
t43
t48
t49
GAPGCFT00936
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Electrical characteristics
ST10F273M
Figure 54. External memory cycle: multiplexed bus, with/ without read/ write delay, extended
ALE, read/ write chip select
CLKOUT
t16
t5
t25
ALE
t6
t17
A23-A16
(A15-A8)
BHE
Address
t54
Read Cycle
t6
t7
Address/Data
Bus (P0)
Data In
t18
Address
t42
t44
t19
t43
t45
t46
t48
RdCSx
t47
t49
Write Cycle
Address/Data
Bus (P0)
Address
t43
Data Out
t42
t56
t44
t45
t50
WrCSx
t48
t49
GAPGCFT00937
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Electrical characteristics
24.8.17 Demultiplexed bus
V
= 5V 10ꢀ, V = 0V, T = -40 to +125°C, CL = 50pF,
SS A
DD
ALE cycle time = 4 TCL + 2t + t + t (50ns at 40 MHz CPU clock without wait states).
A
C
F
Table 72. Demultiplexed bus timings
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU Clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
t5
t6
CC ALE high time
4 + tA
–
–
TCL - 8.5 + tA
TCL - 11 + tA
–
–
ns
ns
CC Address setup to ALE
Address/Unlatched CS
1.5 + tA
t80 CC setup to RD, WR
(with RW-delay)
12.5 + 2tA
0.5 + 2tA
–
–
2TCL - 12.5 + 2tA
TCL - 12 + 2tA
–
–
ns
ns
Address/Unlatched CS
t81 CC setup to RD, WR
(no RW-delay)
RD, WR low time
t12 CC
15.5 + tC
28 + tC
–
–
–
2TCL - 9.5 + tC
3TCL - 9.5 + tC
–
–
ns
ns
ns
(with RW-delay)
RD, WR low time
t13 CC
–
(no RW-delay)
RD to valid data in
t14 SR
6 + tC
2TCL - 19 + tC
(with RW-delay)
RD to valid data in
t15 SR
–
–
–
18.5 + tC
–
–
–
3TCL - 19 + tC
ns
ns
(no RW-delay)
t16 SR ALE low to valid data in
17.5 + tA + tC
20 + 2tA + tC
3TCL - 20 + tA + tC
Address/Unlatched CS to
t17 SR
4TCL - 30 + 2tA + tC ns
ns
valid data in
Data hold after RD
t18 SR
0
–
–
–
0
–
–
–
rising edge
Data float after RD rising
t20 SR
16.5 + tF
4 + tF
2TCL - 8.5 + tF + 2tA ns
TCL - 8.5 + tF + 2tA ns
edge (with RW-delay)(1)
Data float after RD rising
t21 SR
edge (no RW-delay)(1)
t22 CC Data valid to WR
t24 CC Data hold after WR
10 + tC
4 + tF
–
–
2TCL - 15 + tC
TCL - 8.5 + tF
–
–
ns
ns
ALE rising edge after RD,
t26 CC
WR
-10 + tF
0 + tF
–
–
-10 + tF
0 + tF
–
–
ns
ns
ns
ns
Address/Unlatched CS
t28 CC
hold after RD, WR (2)
Address/Unlatched CS
t28h CC
-5 + tF
-4 - tA
–
-5 + tF
-4 - tA
–
hold after WRH
ALE falling edge to
t38 CC
6 - tA
6 - tA
Latched CS
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Electrical characteristics
ST10F273M
Table 72. Demultiplexed bus timings (continued)
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU Clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
3TCL - 21 + tC + 2tA ns
Latched CS low to Valid
Data in
t39 SR
t41 CC
–
16.5 + tC + 2tA
–
Latched CS hold after RD,
WR
2 + tF
–
–
TCL - 10.5 + tF
–
–
ns
ns
Address setup to RdCS,
t82 CC WrCS
(with RW-delay)
14 + 2tA
2TCL - 11 + 2tA
TCL - 10.5 + 2tA
Address setup to RdCS,
t83 CC WrCS
2 + 2tA
–
–
ns
(no RW-delay)
RdCS to Valid Data in
(with RW-delay)
t46 SR
t47 SR
t48 CC
t49 CC
–
–
4 + tC
–
2TCL - 21 + tC
ns
ns
ns
ns
RdCS to Valid Data in
(no RW-delay)
16.5 + tC
–
3TCL - 21 + tC
RdCS, WrCS Low Time
(with RW-delay)
15.5 + tC
28 + tC
–
–
2TCL - 9.5 + tC
3TCL - 9.5 + tC
–
–
RdCS, WrCS Low Time
(no RW-delay)
t50 CC Data valid to WrCS
t51 SR Data hold after RdCS
Data float after RdCS
10 + tC
0
–
–
2TCL - 15 + tC
0
–
–
ns
ns
t53 SR
t68 SR
t55 CC
–
–
16.5 + tF
4 + tF
–
–
2TCL - 8.5 + tF
TCL - 8.5 + tF
ns
ns
3
(with RW-delay)
Data float after RdCS
(no RW-delay) 3
Address hold after
RdCS, WrCS
-8.5 + tF
2 + tF
–
–
-8.5 + tF
–
–
ns
ns
t57 CC Data hold after WrCS
TCL - 10.5 + tF
1. RW-delay and tA refer to the next following bus cycle
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore
address changes before the end of RD have no impact on read cycles.
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Electrical characteristics
Figure 55. External memory cycle: demultiplexed bus, with/ without read/ write delay, normal
ALE
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Doc ID 13453 Rev 4
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Electrical characteristics
ST10F273M
Figure 56. External memory cycle: demultiplexed bus, with/ without read/ write delay, extended
ALE
CLKOUT
t5
t6
t26
t16
ALE
t38
t41
t28
t17
t39
CSx
t6
t28
t17
A23-A16
A15-A0 (P1)
BHE
Address
t18
Data In
Read Cycle
Data Bus (P0)
(D15-D8) D7-D0
t20
t14
t80
t15
t21
t81
RD
t12
t13
Write Cycle
Data Bus (P0)
(D15-D8) D7-D0
Data Out
t80
t81
t24
t22
WR
WRL
WRH
t12
t13
GAPGCFT00939
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Electrical characteristics
Figure 57. External memory cycle: demultiplexed bus, with/ without read/ write delay, normal
ALE, read/ write chip select
CLKOUT
t26
t5
t16
ALE
t6
t17
t55
A23-A16
A15-A0 (P1)
BHE
Address
t51
Data In
Read Cycle
Data Bus (P0)
(D15-D8) D7-D0
t53
t68
t82
t46
t47
t83
RdCSx
t48
t49
Write Cycle
Data Bus (P0)
(D15-D8) D7-D0
Data Out
t82
t50
t57
t83
WrCSx
t48
t49
GAPGCFT00940
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Electrical characteristics
ST10F273M
Figure 58. External memory cycle: demultiplexed bus, without read/ write delay, extended ALE,
read/ write chip select
CLKOUT
t5
t26
t16
ALE
t6
t55
t17
A23-A16
A15-A0 (P1)
BHE
Address
t51
Data In
Read Cycle
Data Bus (P0)
(D15-D8) D7-D0
t53
t46
t82
t47
t68
t83
RdCSx
t48
t49
Write Cycle
Data Bus (P0)
(D15-D8) D7-D0
Data Out
t82
t83
t57
t50
WrCSx
t48
t49
GAPGCFT00941
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ST10F273M
Electrical characteristics
24.8.18 CLKOUT and READY
V
= 5V 10ꢀ, V = 0V, T = -40 to + 125°C, CL = 50pF
SS A
DD
Table 73. CLKOUT and READY timings
fCPU = 40 MHz
Variable CPU clock
TCL = 12.5ns
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
t29 CC CLKOUT cycle time
t30 CC CLKOUT high time
t31 CC CLKOUT low time
t32 CC CLKOUT rise time
t33 CC CLKOUT fall time
25
9
25
–
2TCL
2TCL
TCL – 3.5
–
–
4
4
10
–
–
TCL – 2.5
4
–
–
–
4
CLKOUT rising edge to
t34 CC
– 2 + tA
8 + tA
– 2 + tA
8 + tA
ALE falling edge
Synchronous READY
t35 SR
17
2
–
–
–
–
–
17
–
–
–
–
–
setup time to CLKOUT
ns
Synchronous READY
t36 SR
2
hold time after CLKOUT
Asynchronous READY
t37 SR
low time
35
17
2
2TCL + 10
Asynchronous READY
t58 SR
17
2
setup time(1)
Asynchronous READY
t59 SR
hold time (1)
Async. READY hold time
t60 SR after RD, WR high
(Demultiplexed bus)(2)
0
2tA + tC + tF
0
2tA + tC + tF
1. These timings are given for characterization purposes only, in order to assure recognition at a specific
clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.
This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers
to the current bus cycle.
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Electrical characteristics
ST10F273M
Figure 59. CLKOUT and READY
READY
Running cycle 1)
MUX / Tri-state 6)
wait state
t
t
32
33
31
CLKOUT
ALE
t
t
30
34
t
29
t
7)
RD, WR
2)
t
t
t
t
t
t
36
35
36
59
35
Synchronous
READY
3)
3)
58
t
t
t
60
4)
58
59
Asynchronous
READY
3)
3)
6)
5)
t
37
GAPGCFT00942
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
LOW at this sampling point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
CLKOUT (for example, because CLKOUT is not enabled), it must fulfill t37 in order to be safely
synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4).
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus
without MTTC wait state this delay is zero.
7. The next external bus cycle may start here.
24.8.19 External bus arbitration
VDD = 5V 10ꢀ, VSS = 0V, TA = -40 to +125°C, CL = 50pF
Table 74. External bus arbitration timings
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
t61 SR HOLD input setup time to CLKOUT
18.5
–
18.5
–
ns
ns
CLKOUT to HLDA high
t62 CC
–
12.5
–
12.5
or BREQ low delay
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Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
Variable CPU clock
Table 74. External bus arbitration timings (continued)
fCPU = 40 MHz
TCL = 12.5ns
1/2 TCL = 1 to 40 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
CLKOUT to HLDA low
or BREQ high delay
t63 CC
–
12.5
–
12.5
ns
t64 CC CSx release(1)
–
-4
–
20
15
20
15
–
-4
–
20
15
20
15
ns
ns
ns
ns
t65 CC CSx drive
t66 CC Other signals release(1)
t67 CC Other signals drive
-4
-4
1. Partially tested, guaranteed by design characterization
Figure 60. External bus arbitration (releasing the bus)
CLKOUT
t
61
HOLD
t
63
1)
HLDA
BREQ
t
t
62
64
2)
3)
CSx
(P6.x)
t
66
1)
Others
GAPGCFT00943
1. The ST10F273M will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t64
.
Doc ID 13453 Rev 4
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Electrical characteristics
ST10F273M
Figure 61. External bus arbitration (regaining the bus)
2)
CLKOUT
t61
HOLD
t62
HLDA
t62
t62
t63
1)
BREQ
t65
CSx
(On P6.x)
t67
Other
Signals
GAPGCFT00944
1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated
earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be
deactivated without the ST10F273M requesting the bus.
2. The next ST10F273M driven bus cycle may start here.
176/186
Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
24.8.20 High-speed synchronous serial interface (SSC) timing
Master mode
V
= 5V 10ꢀ, V = 0V, T = -40 to +125°C, C = 50pF
DD
SS
A
L
Table 75. SSC master mode timings
Max. baudrate 6.6Mbaud(1)
@fCPU = 40 MHz
Variable baudrate
(<SSCBR> = 0001h - FFFFh)
Symbol
Parameter
Unit
(<SSCBR> = 0002h)
Min
Max
Min
Max
t300 CC SSC clock cycle time(2)
t301 CC SSC clock high time
150
63
63
–
150
–
8TCL
262144 TCL
t300 / 2 - 12
–
–
t302 CC SSC clock low time
–
t300 / 2 - 12
t303 CC SSC clock rise time
10
10
15
–
–
–
10
10
15
–
t304 CC SSC clock fall time
–
t305 CC Write data valid after shift edge
t306 CC Write data hold after shift edge(3)
–
–
-2
-2
Read data setup time before latch
t307p SR edge, phase error detection on
(SSCPEN = 1)
ns
37.5
50
25
0
–
–
–
–
2TCL + 12.5
4TCL
–
–
–
–
Read data hold time after latch
t308p SR edge, phase error detection on
(SSCPEN = 1)
Read data setup time before latch
t307 SR edge, phase error detection off
(SSCPEN = 0)
2TCL
Read data hold time after latch
t308 SR edge, phase error detection off
(SSCPEN = 0)
0
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only with CPU clock equal to (or lower than) 32 MHz.
2. Formula for SSC Clock Cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125ns (corresponding to 6.6Mbaud)
3. Partially tested, guaranteed by design characterization
Doc ID 13453 Rev 4
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Electrical characteristics
ST10F273M
Figure 62. SSC master timing
t300 t301
t302
2)
1)
SCLK
t304
t305
t303
t306
t305
t305
1st Out Bit
2nd Out Bit
Last Out Bit
MTSR
MRST
t307 t308
t307 t308
2nd.In Bit
1st.In Bit
Last.In Bit
GAPGCFT00946
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Slave mode
V
= 5V 10ꢀ, V = 0V, T = -40 to +125°C, C = 50pF
DD
SS
A
L
Table 76. SSC slave mode timings
Max. baudrate 6.6 Mbaud(1)
@ fCPU = 40 MHz
Variable baudrate
(<SSCBR> = 0001h - FFFFh)
Symbol
Parameter
Unit
(<SSCBR> = 0002h)
Min
Max
Min
Max
t310 SR SSC clock cycle time(2)
t311 SR SSC clock high time
t312 SR SSC clock low time
150
63
63
–
150
–
8TCL
262144 TCL
ns
ns
ns
ns
ns
ns
ns
t310 / 2 – 12
–
–
t310 / 2 – 12
–
t313 SR SSC clock rise time
10
10
55
–
–
–
–
0
10
t314 SR SSC clock fall time
–
10
2TCL + 30
–
t315 CC Write data valid after shift edge
t316 CC Write data hold after shift edge
–
0
Read data setup time before latch
t317p SR edge, phase error detection on
(SSCPEN = 1)
62
87
–
–
4TCL + 12
6TCL + 12
–
–
ns
ns
Read data hold time after latch
t318p SR edge, phase error detection on
(SSCPEN = 1)
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Doc ID 13453 Rev 4
ST10F273M
Electrical characteristics
Variable baudrate
Table 76. SSC slave mode timings (continued)
Max. baudrate 6.6 Mbaud(1)
@ fCPU = 40 MHz
(<SSCBR> = 0002h)
(<SSCBR> = 0001h - FFFFh)
Symbol
Parameter
Unit
Min
Max
Min
Max
Read data setup time before latch
t317 SR edge, phase error detection off
(SSCPEN = 0)
6
–
6
–
ns
ns
Read data hold time after latch
t318 SR edge, phase error detection off
(SSCPEN = 0)
31
–
2TCL + 6
–
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after
checking that resulting timings are suitable for the master).
2. Formula for SSC Clock Cycle time: t310 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t310 is 150ns (corresponding to 6.6Mbaud).
Figure 63. SSC slave timing
t310
t311
t312
2)
1)
SCLK
MRST
MTSR
t314
t315
t313
t316
t315
t315
1st Out Bit
2nd Out Bit
2nd.In Bit
Last Out Bit
t317 t318
t317 t318
1st.In Bit
Last.In Bit
GAPGCFT00947
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Doc ID 13453 Rev 4
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Package information
ST10F273M
25
Package information
25.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
25.2
PQFP144 mechanical data
Table 77. PQFP144 mechanical data
mm
Dim
Min.
Typ.
Max.
A
A1
A2
b
4.10
0.50
0.25
3.20
3.40
3.60
0.29
0.45
c
0.11
0.23
D
30.95
27.80
31.20
28.00
22.75
31.20
28.00
22.75
0.65
31.45
28.20
D1
D3
E
30.95
27.80
31.45
28.20
E1
E3
e
L
0.73
0°
0.88
1.03
L1
L2
k
0.25
1.60
7°
ddd
0.10
180/186
Doc ID 13453 Rev 4
ST10F273M
Package information
Figure 64. PQFP144 package dimensions
("1($'5ꢀꢃꢀꢃꢂ
Doc ID 13453 Rev 4
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Package information
ST10F273M
25.3
LQFP144 mechanical data
Table 78. LQFP144 mechanical data
mm
Dim
Min.
Typ.
Max.
A
1.60
0.15
A1
A2
b
0.05
1.35
1.40
0.22
1.45
0.17
0.27
c
0.09
0.20
D
21.80
19.80
22.00
20.00
17.50
22.00
20.00
17.50
0.50
22.20
20.20
D1
D3
E
21.80
19.80
22.20
20.20
E1
E3
e
L
0.45
0
0.60
0.75
L1
k
1.00
3.5
7
ccc
0.8
182/186
Doc ID 13453 Rev 4
ST10F273M
Package information
Figure 65. LQFP144 package dimensions
("1($'5ꢀꢀꢁꢂꢀ
Doc ID 13453 Rev 4
183/186
Ordering information
ST10F273M
26
Ordering information
Table 79. Order codes
Order code
Temperature
range
CPU frequency
range
Package
Packing
ST10F273MR-4Q3
Tray
PQFP144
LQFP144
ST10F273MR-4QR3
ST10F273MR-4T3
ST10F273MR-4TX3
Tape and reel
Tray
-40 to +125°C
1 to 40 MHz
Tape and reel
184/186
Doc ID 13453 Rev 4
ST10F273M
Revision history
27
Revision history
Table 80. Document revision history
Date
Revision
Changes
03-May-2007
1
Initial release
Changed document status from Preliminary Data to Datasheet
Section 4: Memory organization on page 21:
- changed size of B0TF from 8 to 4Kbytes
- removed ‘Flash Temporary Unprotection’ from X-Miscellaneous
features
Table 2: Summary of IFlash address range on page 21: Changed size
of B0TF from 8 to 4Kbytes
Figure 6: Flash structure on page 27: Changed Test-Flash size from 8
to 4Kbytes
Table 5: Flash module sectorization (write operations, or ROMS1 = ‘1’)
on page 29: Changed B0TF address and size (8 to 4Kbytes)
Section 14: A/D converter on page 72: Replaced ‘40.630 CPU clock
cycles’ with ‘40630 CPU clock cycles’ in end of section
Section 21.1: Idle mode on page 109: Made minor text changes
Section 21.2: Power-down mode on page 109: Made minor text
changes
Table 57: DC characteristics on page 134:
- changed max value and unit for IPD1 from 1mA to 150µA
- changed max value and unit for IPD3 from 1.1mA to 200µA
- changed test conditions and max values for ISB2
- changed footnote link for symbol IP0H
02-Jul-2007
2
- changed footnote link for symbol IP0L
Table 58: Flash characteristics on page 138:
- modified Bank 0 program parameter and values
- removed Bank 1 program parameter and values
- modified Bank 0 erase parameter and values
- removed Bank 1 erase parameter and values
Section 24.7.4: Analog reference pins on page 143: Minor text editing
changes
Table 62: On-chip clock generator selections on page 151:
- changed external clock input range for fXTAL x 5
- changed external clock input range for fXTAL x 1
- replaced ‘CPU clock range of 1...60 MHz’ with ‘CPU clock range of
1...40 MHz’ in footnote 1
Added Section 25.1: ECOPACK® on page 180 and updated content
Added Section 26.2: Mechanical data and package dimensions on
page 174
Updated Table 17: FARH register description
Updated Chapter 25: Package information
Updated Table 79: Order codes
20-Aug-2012
17-Sep-2013
3
4
Updated Disclaimer
Doc ID 13453 Rev 4
185/186
ST10F273M
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Doc ID 13453 Rev 4
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