ST14C02C-D20
更新时间：2024-09-18 02:06:17
描述：Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM
概述
规格参数
数据手册ST14C02C-D20 概述
Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM 记忆卡IC的2 Kbit的256 ×8串行I2C总线EEPROM EEPROM
ST14C02C-D20 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | WAFER | 包装说明： | , MODULE,8LEAD,.4 |
| Reach Compliance Code： | not_compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.32.00.51 | 风险等级： | 5.92 |
| 最大时钟频率 (fCLK)： | 0.1 MHz | 数据保留时间-最小值： | 10 |
| 耐久性： | 1000000 Write/Erase Cycles | I2C控制字节： | 1010000R |
| JESD-30 代码： | X-XUUC-N | 内存密度： | 2048 bit |
| 内存集成电路类型： | EEPROM | 内存宽度： | 8 |
| 湿度敏感等级： | 1 | 功能数量： | 1 |
| 端子数量： | 8 | 字数： | 256 words |
| 字数代码： | 256 | 工作模式： | SYNCHRONOUS |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 组织： | 256X8 | 封装主体材料： | UNSPECIFIED |
| 封装等效代码： | MODULE,8LEAD,.4 | 封装形状： | UNSPECIFIED |
| 封装形式： | UNCASED CHIP | 并行/串行： | SERIAL |
| 峰值回流温度（摄氏度）： | 225 | 电源： | 3.3/5 V |
| 认证状态： | Not Qualified | 串行总线类型： | I2C |
| 最大待机电流： | 0.0001 A | 子类别： | EEPROMs |
| 最大压摆率： | 0.002 mA | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 3 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | COMMERCIAL | 端子形式： | NO LEAD |
| 端子位置： | UPPER | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 最长写入周期时间 (tWC)： | 10 ms | Base Number Matches： | 1 |
ST14C02C-D20 数据手册
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PDF下载ST14C02C
Memory Card IC
2 Kbit (256 x 8) Serial I2C Bus EEPROM
■ Single Supply Voltage (3 V to 5.5 V)
2
■ Two Wire I C Serial Interface
■ BYTE and MULTBYTE WRITE (up to 4 Bytes)
■ PAGE WRITE (up to 8 Bytes)
■ BYTE, RANDOM and SEQUENTIAL READ
Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ 1 Million Erase/Write Cycles (minimum)
■ 10 Year Data Retention (minimum)
Micromodule (D15)
Micromodule (D20)
DESCRIPTION
This device is an electrically erasable programma-
ble memory (EEPROM) fabricated with
STMicroelectronics’s High Endurance, Advanced
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one million
Erase/Write cycles, with a data retention of 10
years. The memory operates with a power supply
as low as 3 V.
The device is available in wafer form (either sawn
or unsawn) and in micromodule form (on film).
The memory is compatible with the I C standard.
Wafer
2
This is a two wire serial interface that uses a bi-di-
rectional data bus and serial clock. The memory
carries a built-in 7-bit unique Device Type Identifi-
Figure 1. Logic Diagram
2
er code (1010000) in accordance with the I C bus
definition. Only one memory can be attached to
each I C bus.
V
CC
2
SCL
Table 1. Signal Names
SDA
ST14C02C
SDA
Serial Data/Address Input/
Output
MODE
SCL
Serial Clock
Write Mode
Supply Voltage
Ground
MODE
GND
V
CC
AI01162
GND
DS.ST14C02C/9811V2
1/12
ST14C02C
Figure 2. D15 Contact Connections
Figure 3. D20 Contact Connections
V
CC
GND
SDA
V
GND
SDA
CC
SCL
SCL
MODE
AI02492
AI02491
2
The memory behaves as a slave device in the I C
protocol, with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by
the Device Select Code which is composed of a
stream of 7 bits (1010000), plus one read/write bit
(R/W) and is terminated by an acknowledge bit.
Power On Reset: V
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the V
voltage has reached the
CC
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when V drops from the
CC
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9 bit time,
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
th
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoACK for READ.
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
Wafer form
Module form
-65 to 150
-40 to 120
TSTG
Storage Temperature
°C
VIO
Input or Output range
Supply Voltage
-0.3 to 6.5
-0.3 to 6.5
4000
V
V
V
VCC
2
Electrostatic Discharge Voltage (Human Body model)
VESD
3
500
V
Electrostatic Discharge Voltage (Machine model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
3. EIAJ IC-121 (Condition C) (200 pF, 0 Ω)
2/12
ST14C02C
Table 3. Endurance and Data Retention
Device
Endurance (Erase/Write Cycles)
1,000,000
Data Retention (Years)
ST14C02C
10
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to synchronize all data
in and out of the memory. A pull up resistor can be
connected from the SCL line to V . (Figure 4 in-
dicates how the value of the pull-up resistor can be
calculated).
When unconnected, the MODE input is internally
read as a V (Multibyte Write mode). Note that the
IH
voltages are CMOS levels, and are not TTL com-
patible.
On the D15 micromodule, the MODE pin is not
connected to a contact. This pin is left floating on
the silicon. This type of ST14C02C is always in its
MultiByte mode, and cannot be changed from this.
CC
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
DEVICE OPERATION
The memory device supports the I C protocol, as
2
summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitter,
and any device that reads the data to be a receiv-
er. The device that controls the data transfer is
known as the master, and the other as the slave.
A data transfer can only be initiated by the master,
which will also provide the serial clock for synchro-
nization. The memory device is always a slave de-
vice in all communication.
to V . (Figure 4 indicates how the value of the
CC
pull-up resistor can be calculated).
Mode (MODE)
The MODE input may be driven dynamically. It
must be held at:
■ V or V for the Byte Write mode
IL
IH
■ V for Multibyte Write mode
IH
■ V for Page Write mode
IL
2
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I C Bus
20
V
CC
16
R
R
L
L
12
SDA
C
BUS
MASTER
SCL
8
4
C
BUS
V
= 5V
CC
0
100
200
(pF)
300
400
C
AI01100
BUS
3/12
ST14C02C
2
Figure 5. I C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
Start Condition
state. A STOP condition terminates communica-
tion between the memory and the bus master. A
STOP condition at the end of a Read command
forces the memory device into its standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory continuously
monitors (except during a programming cycle) the
SDA and SCL lines for a START condition, and will
not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after
th
sending 8 bits of data. During the 9 clock pulse
1
Table 4. Device Select Code
Device Code
RW
b0
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
0
Device Select
RW
Note: 1. The most significant bit, b7, is sent first.
4/12
ST14C02C
period the receiver pulls the SDA bus low to ac-
knowledge the receipt of the 8 data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Following a START condition, the master sends a
Device Select Code with the RW bit reset to ‘0’.
The memory device acknowledges this, and waits
for a byte address. The 8-bit byte address allows
access within a 256-byte memory address-space.
After receipt of the byte address, the device again
responds with an acknowledge bit.
Byte Write
In the Byte Write mode, the master sends one data
byte, which is acknowledged by the memory, as
shown in Figure 6. The master then terminates the
transfer by generating a STOP condition. The
Write mode is independent of the state of the
MODE pin, as shown in Table 5, which could be
left floating if only this mode is to be used. Howev-
er this is not a recommended operating mode, as
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW bit.
this pin has to be connected to either V or V to
IH
IL
The seven most significant bits of the Device Se-
lect Code are the Device Type Identifier, according
minimize the stand-by current.
Multibyte Write
2
to the I C bus definition. For the memory device,
For the Multibyte Write mode, the MODE pin must
the seven bits are fixed at 1010000b (A0h), as
be held at V as shown in Table 5. The Multibyte
shown in Table 4.
IH,
Write mode can be started from any address in the
memory. The master sends one, two, three or four
bytes of data, which are each acknowledged by
the memory. The transfer is terminated by the
master generating a STOP condition. The maxi-
th
The 8 bit is the read or write bit (RW). This bit is
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor-
responding memory gives an acknowledgment on
th
the SDA bus during the 9 bit time.
mum duration of the write cycle is t =10 ms (as
W
Write Operations
The Multibyte Write mode is selected when the
shown in Table 8), except when bytes span across
two rows. (That is, when they have different values
for the 6 most significant address bits, A7-A2). The
programming time is then doubled to a maximum
of 20 ms. Writing more than four bytes in the Multi-
MODE pin is at V , and the Page Write mode is
IH
selected when MODE pin is at V . The MODE pin
IL
may be driven dynamically to CMOS input levels.
Figure 6. Write Mode Sequences
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
ACK
BYTE ADDR
ACK
PAGE WRITE
DEV SEL
ACK
DATA IN 1
DATA IN 2
R/W
ACK
DATA IN N
AI01941
5/12
ST14C02C
Table 5. Operating Modes
Mode
1
RW bit
‘1’
Bytes
Initial Sequence
MODE
Current Address Read
X
X
1
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Mode
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
‘0’
Random Address Read
‘1’
X
1
Sequential Read
Byte Write
‘1’
X
≥ 1
1
‘0’
X
Multibyte Write
‘0’
VIH
VIL
≤ 4
≤ 8
Page Write
‘0’
Note: 1. X = VIH or VIL.
byte Write mode may modify data bytes in an ad-
jacent row. (Each row is 8 bytes long). However,
the Multibyte Write can properly write up to eight
consecutive bytes only if the first address is the
first address of the row (the seven following bytes
thereby being written to the seven following bytes
of this same row).
When not connected, the MODE pin is internally
pulled to “1” and the multibyte write option is se-
lected.
The sequence, as shown in Figure 7, is as follows:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a device select byte (first byte of the
new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an ACK, indicating that the memory is
ready to receive the second part of the next in-
struction (the first byte of this instruction having
been sent during Step 1).
Page Write
For the Page Write mode, the MODE pin must be
held at V (as shown in Table 5). The Page Write
IL
mode allows up to eight bytes to be written in a sin-
gle write cycle, provided that they are all located in
the same row. That is, the five most significant
memory address bits (A7-A3) must be the same.
The master sends between one and eight bytes of
data, each of which are acknowledged by the
memory. After each byte is transferred, the inter-
nal byte address counter is incremented (this han-
dles the three least significant address bits). Care
must be taken to avoid address counter ‘roll-over’,
as this could result in data being overwritten.
The transfer is terminated by the master generat-
ing a STOP condition. For any write mode, the
generation by the master of the STOP condition
starts the internal memory program cycle. All in-
puts are disabled until the completion of this cycle
and the memory will not respond to any request.
Read Operations
Read operations are independent of the state of
the MODE pin. On delivery, the memory content is
set at all “1’s” (FFh).
Current Address Read
The memory has an internal byte address counter.
Each time a byte is read, this counter is increment-
ed. For the Current Address Read mode, following
a START condition, the master sends a device se-
lect with the RW bit set to ‘1’. The memory device
acknowledges this, and outputs the byte ad-
dressed by the internal byte address counter, as
shown in Figure 9. The counter is then increment-
ed. The master must not acknowledge the byte
output, and terminates the transfer with a STOP
condition.
Random Address Read
Minimizing System Delays by Polling On ACK
A dummy write is performed to load the address
into the address counter, as shown in Figure 6.
This is followed by another START condition from
the master and the device select is repeated with
the RW bit set to ‘1’. The memory device acknowl-
edges this, and outputs the byte addressed. The
master must not acknowledge the byte output, and
terminates the transfer with a STOP condition.
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t ) is indicated in Table 8, but the
w
typical time is shorter. To make use of this, an ACK
polling sequence can be used by the master.
6/12
ST14C02C
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by ST14C02C
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI02454
Table 6. AC Measurement Conditions
Figure 8. AC Testing Input/Output Waveform
Input Rise and Fall Times
Input Pulse Voltages
≤ 20 ns
0.2V to 0.8V
0.8V
CC
0.7V
CC
CC
CC
CC
0.3V
CC
0.2V
CC
Input and Output Timing
Reference Voltages
0.3V to 0.7V
CC
AI00825
1
Table 7. Capacitance (T = 25 °C, f = 100 kHz)
A
Symbol
CIN
Parameter
Test Condition
Min.
Max.
Unit
pF
Input Capacitance (SDA)
Input Capacitance (other pins)
8
6
CIN
pF
tNS
Noise suppression Time Con-
stant (SCL & SDA Inputs)
100
400
ns
Note: 1. Sampled only, not 100% tested.
7/12
ST14C02C
Figure 9. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
DATA OUT N
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01942
Sequential Read
Acknowledge in Read Mode
This mode can be initiated with either a Current
Address Read or a Random Address Read. How-
ever, in this case the master does acknowledge
the data byte output, and the memory continues to
output the next byte in sequence. To terminate the
stream of bytes, the master must not acknowledge
the last byte output, and must generate a STOP
condition. The output data comes from consecu-
tive byte addresses, with the internal byte address
counter automatically incremented after each byte
output. After the last memory address, the address
counter will ‘roll-over’ and the memory will contin-
ue to output data from the start of the memory
block.
In all read modes the memory waits for an ac-
knowledgment during the 9 bit time. If the master
does not pull the SDA line low during this time, the
memory device terminates the data transfer and
switches to its standby state.
th
8/12
ST14C02C
Table 8. AC Characteristics
(T = 0 to 70 °C; V = 3 V to 5.5 V)
A
CC
ST14C02C
Symbol
Alt.
Parameter
Unit
Min
Max
1
tCH1CH2
tCL1CL2
tDH1DH2
tDL1DL2
tR
tF
Clock Rise Time
Clock Fall Time
SDA Rise Time
SDA Fall Time
µs
ns
µs
ns
µs
µs
µs
µs
µs
ns
µs
µs
µs
ns
kHz
ms
300
1
tR
tF
300
1
tSU:STA
tHIGH
tHD:STA
tHD:DAT
tLOW
tSU:DAT
tSU:STO
tBUF
tAA
Clock High to Input Transition
Clock Pulse Width High
4.7
4
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tDXCX
tCHDH
tDHDL
tCLQV
tCLQX
fC
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
4
0
4.7
250
4.0
4.7
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Data Out Valid
Data Out Hold Time After Clock Low
Clock Frequency
3.5
tDH
300
fSCL
100
10
2
tWR
Write Time
tW
Note: 1. For a reSTART condition, or following a write cycle.
2. In the Multibyte Write mode only, if the accessed bytes span over two consecutive 8-byte rows (that is, if the 6 most significant
address bits are not constant) the maximum programming time is doubled to 20 ms
Table 9. DC Characteristics
(T = 0 to 70 °C; V = 3 V to 5.5 V)
A
CC
Symbol
Parameter
Test Condition
0 V ≤ VIN ≤ VCC
Min.
Max.
± 2
Unit
µA
ILI
ILI
Input Leakage Current
0 V ≤ VIN ≤ VCC
Input Leakage Current (MODE pad)
Output Leakage Current
± 10
± 2
µA
ILO
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
µA
VCC = 5 V, f = 100 kHz
(Rise/Fall time < 10 ns)
c
ICC
Supply Current
2
mA
ICC1
VIL
Supply Current (Stand-by)
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
Input Low Voltage (MODE)
Input High Voltage (MODE)
Output Low Voltage
VIN = VSS or VCC , VCC = 5 V
100
0.3 VCC
VCC + 1
0.5
µA
V
- 0.3
0.7 VCC
- 0.3
VIH
VIL
V
V
VIH
VOL
V
CC - 0.5
VCC + 1
0.4
V
IOL = 3 mA, VCC = 5 V
V
9/12
ST14C02C
Figure 10. AC Waveforms
tCHCL
tDLCL
tCLCH
SCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
START
CONDITION
SDA
STOP &
BUS FREE
INPUT CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
WRITE CYCLE
START
CONDITION
CONDITION
AI00795B
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
es of the frame (as shown in Figure 11). The orien-
tation of the die with respect to the plastic frame
notches is specified by the Customer.
One further concern, when specifying devices to
be delivered in this form, is that wafers mounted
on adhesive tape must be used within a limited pe-
riod from the mounting date:
– two months, if wafers are stored at 25°C, 55%
relative humidity
The notation used for the device number is as
shown in Table 10. For a list of available options
(speed, package, etc...) or for further information
on any aspect of this device, please contact the ST
Sales Office nearest to you.
Sawn wafers are scribed and mounted in a frame
on adhesive tape. The orientation is defined by the
position of the GND pad on the die, viewed with
active area of product visible, relative to the notch-
– six months, if wafers are stored at 4°C, 55% rel-
ative humidity
10/12
ST14C02C
Table 10. Ordering Information Scheme
Example:
ST14C02C -
D20
Delivery Form
D15 Module on Super 35 mm film
D20 Module on Super 35 mm film
W2 Unsawn wafer (275 µm ± 25 µm thickness)
W4 Unsawn wafer (180 µm ± 15 µm thickness)
S2x Sawn wafer (275 µm ± 25 µm thickness)
S4x Sawn wafer (180 µm ± 15 µm thickness)
where “x” indicates the sawing orientation, as follows (and as shown in Figure 11)
1
2
3
4
GND at top right
GND at bottom right
GND at bottom left
GND at top left
Figure 11. Sawing Orientation
VIEW: WAFER FRONT SIDE
GND
GND
GND
GND
ORIENTATION
1
2
3
4
AI02171
11/12
ST14C02C
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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ST14C02C-D20 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ST14C02C-S21 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-S22 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-S23 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-S24 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-S41 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-S42 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-S43 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-S44 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-W2 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
|
| ST14C02C-W4 | STMICROELECTRONICS | Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM | 获取价格 |
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