ST1S14 [STMICROELECTRONICS]
Power good open collector output;
| 型号： | ST1S14 |
| 厂家： | 
ST |
| 描述： | Power good open collector output |
| 文件： | 总46页 (文件大小：2480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST1S14
Up to 3 A step-down switching regulator
Datasheet - production data
Applications
• Factory automation
• Printers
• DC-DC modules
• High current LED drivers
+623ꢀꢁꢂꢁH[SRVHGꢁSDG
Description
Features
The ST1S14 is a step-down monolithic power
switching regulator able to deliver up to 3 A DC
current to the load depending on the application
conditions. The high current level is also achieved
thanks to a HSOP8 package with exposed frame,
• 3 A DC output current
• Operating input voltage from 5.5 V to 48 V
• 850 kHz internally fixed switching frequency
• Internal soft-start
that allows to reduce the R
down to
th(JA)
• Power good open collector output
• Current mode architecture
approximately 40 °C/W. The output voltage can
be set from 1.22 V. The device uses an internal N-
channel DMOS transistor (with a typical R
of
• Embedded compensation network
• Zero load current operation
DS(on)
200 mΩ) as the switching element to minimize the
size of the external components. The internal
oscillator fixes the switching frequency at 850
kHz. Power good open collector output validates
the regulated output voltage as soon as it reaches
the regulation. Pulse-by-pulse current limit offers
an effective constant current short-circuit
• Internal current limiting
• Inhibit for zero current consumption
• 2 mA maximum quiescent current over
temperature range
• 250 mΩ typ. R
DS(on)
protection. Current foldback decreases overstress
in a persistent short-circuit condition.
• Thermal shutdown
Figure 1. Application schematic
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March 2013
DocID17977 Rev 2
1/46
This is information on a product in full production.
www.st.com
46
Contents
ST1S14
Contents
1
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
4.4
4.5
4.6
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
6
Additional features and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
Maximum duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Minimum output voltage over VIN range . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
6.4
GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 17
Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1
Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1.1
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/46
DocID17977 Rev 2
ST1S14
Contents
7.1.2
7.1.3
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2
7.3
7.4
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.4.1
7.4.2
7.4.3
300 mV < V < 1.22 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FB
V
< 300 mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FB
Start up phase in short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9
10
11
DocID17977 Rev 2
3/46
List of figure
ST1S14
List of figure
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Soft-start phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Soft-start block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bootstrap operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
over input voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
O_MIN
Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Transconductance embedded error amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Leading network example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Phase plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Minimum V for effective pulse-by-pulse protection over VIN . . . . . . . . . . . . . . . . . . . . . 30
FB
Figure 17. I diverging triggers hiccup protection (V = 48 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
L
IN
Figure 18. Current and frequency foldback triggered when V <300 mV (red trace) . . . . . . . . . . . . . 31
FB
Figure 19. Minimum V for effective pulse-by-pulse protection over VIN . . . . . . . . . . . . . . . . . . . . . 32
FB
Figure 20. Short-circuit current VIN = 24 V (I
Figure 21. Short-circuit current VIN = 43 V (I
= I
> I
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
L_PK
FOLD
L_PK
FOLD
Figure 22. Start up in short circuit condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23. Over current protection triggers the frequency foldback. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 24. Over current protection triggers the current and frequency foldback . . . . . . . . . . . . . . . . . 35
Figure 25. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 26. PCB layout (component side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27. PCB layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28. Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 29. Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 30. RDSon vs. temperature (VIN = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 31. VFB vs. temperature (VIN = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 32. fSW vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 33. Quiescent current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 34. Shutdown current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 35. Duty cycle max vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 36. Efficiency vs. I
(V 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
OUT
IN
Figure 37. T vs. I
(V 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
J
OUT
IN
Figure 38. Efficiency vs. I
(V 24 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IN
OUT
Figure 39. T vs. I
(V 24 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
J
OUT
IN
Figure 40. Efficiency vs. I
(V 32 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
IN
OUT
Figure 41. T vs. I
(V 32 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
J
OUT
IN
Figure 42. 1 A to 3 A load transient (V 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
IN
Figure 43. Zoom - 1 A to 3 A load transient (V 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
IN
Figure 44. Zoom - 1 A to 3 A rising edge load transient (V 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
IN
Figure 45. 1 A to 3 A falling edge load transient (V 24 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
IN
4/46
DocID17977 Rev 2
ST1S14
List of figure
Figure 46. Zoom - 1 A to 3 A rising edge load transient (V 24 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IN
Figure 47. Zoom - 1 A to 3 A falling edge load transient (V 24 V). . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IN
Figure 48. 1 A to 3 A load transient (V 32 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IN
Figure 49. Zoom - 1 A to 3 A rising edge load transient (V 32 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IN
Figure 50. Zoom - 1 A to 3 A falling edge load transient (V 32 V). . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IN
Figure 51. Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DocID17977 Rev 2
5/46
Pin settings
ST1S14
1
Pin settings
1.1
Pin connection
Figure 2. Pin connection (top view)
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4/ '.$
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1.2
Pin description
Table 1. Pin description
Description
N
Pin
Bootstrap capacitor for N-channel gate driver. Connects 100 nF low ESR
capacitor from BOOT pin to SW
1
BOOT
2
3
4
5
6
7
8
PG
EN1
FB
Power good
Enable pin active low
Feedback voltage
Enable pin active high
Ground pin
EN2
GND
VIN
Input supply pin
SW
E.p.
Switching node
Exposed pad must be connected to GND
1.3
Enable inputs
Table 2. Truth table
EN1
EN2
Device status
H
H
L
L
H
L
INH
INH
INH
ON
L
H
6/46
DocID17977 Rev 2
ST1S14
Electrical data
2
Electrical data
2.1
Maximum ratings
Table 3. Absolute maximum ratings
Parameter
Symbol
Value
Unit
VIN
VEN1
VEN2
PG
Power supply input voltage
Enable 1 voltage
-0.3 to 52
-0.3 to 7
V
V
Enable 2 voltage
-0.3 to (VIN+0.3)
-0.3 to (VIN+0.3)
-0.3 to 55
V
V
Power good
BOOT
SW
Bootstrap pin
V
Switching node
-1 to (VIN+0.3)
-0.3 to 3
V
VFB
Feedback voltage
V
TJ
Operating junction temperature range
Storage temperature range
Lead temperature (soldering 10 sec.)
-40 to 150
-65 to 150
260
°C
°C
°C
TSTG
TLEAD
2.2
2.3
Thermal data
Table 4. Thermal data
Parameter
Symbol
Value
Unit
Rth JA
Thermal resistance junction-ambient
40
° C/W
ESD protection
Symbol
Table 5. ESD protection
Test condition
Value
Unit
HBM
ESD
MM
4
kV
V
500
DocID17977 Rev 2
7/46
Electrical characteristics
ST1S14
3
Electrical characteristics
All the population tested at T = 25 °C, V =12 V, V
= 0 V, V
= V unless otherwise
EN2 CC
J
CC
EN1
specified.
The specification is guaranteed from (-40 to +125 °C) T temperature range by design,
J
characterization, and statistical correlation.
Table 6. Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Operating input
voltage range
VIN
5.5
48
V
MOSFET on
resistance
RDS(on)
ISW=1 A
0.2
4.5
0.4
5.2
Ω
Maximum limiting
current
ISW
3.7
A
tHICCUP Hiccup time
fSW Switching frequency
16
850
90
ms
kHz
%
600
1000
(1)
(1)
Duty cycle
Minimum conduction
TON MIN time of the power
element
90
90
ns
ns
Minimum conduction
TOFF MIN time of the external
diode
(1)
75
120
DC characteristics
I
LOAD=0 A
1.202
1.196
1.22
1.22
50
1.239
1.245
V
VFB
IFB
Iq
Voltage feedback
FB biasing current
Quiescent current
ILOAD=10 mA to 3 A
V
nA
mA
mA
V
FB=2 V
1.3
2
VFB=2 V, VIN=48 V
1.7
2.4
Standby quiescent
current
Iqst-by
Device OFF (see Table 2)
16
34
μA
V
0.92*
VOUT
VFB rising edge
Power good threshold
0.8*
VOUT
PG
VFB falling edge
V
PG output voltage
(open collector active)
ISINK=6 mA
0.4
V
Inhibit
8/46
DocID17977 Rev 2
ST1S14
Electrical characteristics
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Device ON
0.5
V
VIN=5.5 V to 48 V
VEN1
Enable 1 levels
Device OFF
1.5
0.7
1.5
V
μA
V
VIN=5.5 V to 48 V
Enable 1 biasing
current
IEN1
VEN1=5 V
1.6
3.5
0.5
Device ON
VIN=5.5 V to 48 V
VEN2
Enable 2 levels
Device OFF
V
VIN=5.5 V to 48 V
VEN1=0 V; VEN2=0 V
-1
-2.4
5.8
6.0
-4.5
10
μA
μA
μA
Enable 2 biasing
current
IEN2
VEN1=0 V; VEN2=12 V
VEN1=0 V; VCC=VEN2=48 V
2.7
3.0
10
Thermal shutdown
Thermal shutdown
(1)
(1)
TSHDWN
140
150
15
160
°C
°C
temperature
Thermal shutdown
hysteresis
THYS
1. Parameter guaranteed by design
DocID17977 Rev 2
9/46
Function description
ST1S14
4
Function description
The ST1S14 is based on a “peak current mode”, constant frequency control. As a
consequence the intersection between the error amplifier output and the sensed inductor
current generates the control signal to drive the power switch.
The main internal blocks shown in the block diagram in Figure 3 are:
•
•
•
•
A fully integrated sawtooth oscillator with a typical frequency of 850 kHz
A transconductance error amplifier
A high side current sense amplifier to track the inductor current
A pulse width modulator (PWM) comparator and the circuitry necessary to drive the
internal power element
•
•
Soft-start circuitry to decrease the inrush current at power-up
Current limitation circuit based on the pulse-by-pulse current protection with frequency
divider based on FB voltage and the hiccup protection
•
•
•
Bootstrap circuitry to drive the embedded N-MOS switch
A multi input inhibit block for standby operation
A circuit to implement the thermal protection function
Figure 3. Device block diagram
"//4
6).
/3#
3LOPE
2EG
"OOT 2EG
COMPENSATION
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10/46
DocID17977 Rev 2
ST1S14
Function description
4.1
Power supply and voltage reference
The internal regulator circuit consists of a start-up circuit, an internal voltage pre-regulator,
the bandgap voltage reference, and the bias block that provides current to all the blocks.
The starter supplies the start-up current to the entire device when the input voltage goes
high and the device is enabled (inhibit pin connected to ground). The pre-regulator block
supplies the bandgap cell with a pre-regulated voltage that has a very low supply voltage
noise sensitivity.
4.2
Voltage monitor
An internal block continuously senses the V , V , and V . If the monitored voltages are
cc
ref
bg
good, the regulator begins operating. There is also a hysteresis on the V (UVLO).
CC
Figure 4. Internal circuit
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4.3
Soft-start
The startup phase minimizes the inrush current and decreases the stress of the power
components at the power up. The startup takes place when VIN crosses the selected UVLO
threshold. A internal counter (2816 clks) sets the soft start time (see Figure 5).
The reference of the error amplifier is ramped smootly in 704 steps (one step every 4 clks).
A low pass filter smooths each step to minimize output discontinuity. Considering the typical
850 kHz switching frequency, the phase two duration is 3.3 msec
The device has full load current capability during the soft start time in order to charge the
output capacitor (see Figure 5).
DocID17977 Rev 2
11/46
Function description
ST1S14
Figure 5. Soft-start phases
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During normal operation a new soft start cycle takes place in case of:
•
•
•
•
HICCUP mode current protection
thermal shutdown event
UVLO event
the device is driven in INH mode
Figure 6. Soft-start block diagram
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12/46
DocID17977 Rev 2
ST1S14
Function description
4.4
Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
reference (1.222 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage.
The error amplifier is internally compensated to minimize the size of the final application.
Table 7. Uncompensated error amplifier characteristics
Description
Transconductance
Values
218 µS
93 dB
Low frequency gain
CP
CC
RC
24 pF
211 pF
200 kΩ
The error amplifier output is compared with the inductor current sense information to
perform PWM control.
4.5
4.6
Inhibit function
The inhibit feature is used to set the device in standby mode according to Table 2. When the
device is disabled, the power consumption is reduced to less than 40 µA. The EN2 pin is
also V compatible.
IN
Thermal shutdown
The shutdown block generates a signal that turns off the power stage if the temperature of
the chip goes higher than a fixed internal threshold (150±10 °C). The sensing element of the
chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A
hysteresis of approximately 15 °C keeps the device from turning on and off continuously.
DocID17977 Rev 2
13/46
Additional features and limitations
ST1S14
5
Additional features and limitations
5.1
Maximum duty cycle
The bootstrap circuitry charges, cycle-by-cycle, the external bootstrap capacitor to generate
a voltage higher than V necessary to drive the internal N-channel power element.
IN
An internal linear regulator charges the C
during the conduction time of the external
BOOT
freewheeling diode during the switching activity. The internal logic implements a minimum
OFF time of the high side switch (90 nsec typ.) to prevent the bootstrap discharge at high
duty cycle. As a consequence, the ST1S14 can operate at a maximum duty cycle of around
90 % typ.
The ST1S14 embeds the diode V required for the bootstrap operation.
D1
Figure 7. Bootstrap operation
6).
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/54
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14/46
DocID17977 Rev 2
ST1S14
Additional features and limitations
5.2
Minimum output voltage over VIN range
The minimum regulated output voltage at a given input voltage is limited by the minimum
conduction time of the power element, that is 90 nsec typ. for the ST1S14:
Equation 1
TON_MIN
---------------------
TSW
90ns
1.18μs
-----------------
= VIN ⋅
VO_MIN(VIN) = VIN ⋅ DMIN = VIN
⋅
which is plotted in Figure 14. The reference of the embedded error amplifier (1.22 V) sets
the minimum V
at low V .
O_SET
IN
Figure 8. V
over input voltage range
O_MIN
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Figure 8 shows the minimum output voltage over input voltage range to have constant
switching activity and a predictable output voltage ripple.
The regulator can, however, regulate the minimum input voltage over the entire input
voltage range but, given the 90 ns minimum conduction time of the power element, it skips
some pulses to keep the output voltage in regulation when Equation 1 is not satisfied.
This operation is not recommended at the nominal input voltage of the application mainly
because it affects the output voltage ripple, but it is generally accepted during a line
transient event.
DocID17977 Rev 2
15/46
Closing the loop
ST1S14
6
Closing the loop
Figure 9. Block diagram of the loop
6).
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RESISTOR DIVIDER
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16/46
DocID17977 Rev 2
ST1S14
Closing the loop
6.1
GCO(s) control to output transfer function
The accurate control to output transfer function for a buck peak current mode converter can
be written as:
Equation 2
s
⎛
⎝
⎞
⎠
1 + ----
ω
R0
1
z
------ ------------------------------------------------------------------------------------------------ --------------------
GCO(s) =
⋅
⋅
⋅ FH(s)
Ri
R0 ⋅ TSW
-------------------------
L
s
⎛
⎞
1 + -----
1 +
⋅ [mC ⋅ (1 – D) – 0.5]
⎝
⎠
ω
p
where R represents the load resistance, R the equivalent sensing resistor of the current
0
i
sense circuitry, ω the single pole introduced by the LC filter, and ω the zero given by the
p
z
ESR of the output capacitor.
F (s) accounts for the sampling effect performed by the PWM comparator on the output of
H
the error amplifier that introduces a double pole at one half of the switching frequency.
Equation 3
1
ω
= ----------------------------------
Z
ESR ⋅ COUT
Equation 4
mC ⋅ (1 – D) – 0.5
L ⋅ COUT ⋅ fSW
1
ω = ---------------------------------------- + ------------------------------------------------
n
RLOAD ⋅ COUT
where:
Equation 5
Se
------
Sn
⎛
mC = 1 +
⎜
⎜
⎜
Se = Vpp ⋅ fSW
⎜
⎜
⎜
⎝
V
IN – VOUT
-----------------------------
⋅ Ri
Sn
=
L
S represents the ON time slope of the sensed inductor current, and S the ON time slope
n
e
of the external ramp (V peak to peak amplitude) that implements the slope compensation
PP
to avoid sub-harmonic oscillations at duty cycle over 50 %.
The sampling effect contribution F (s) is:
H
Equation 6
1
FH(s) = ------------------------------------------
s
s2
1 + -------------------- + -----
2
ω ⋅ QP
n
ω
n
where:
DocID17977 Rev 2
17/46
Closing the loop
ST1S14
Equation 7
1
QP = ---------------------------------------------------------------
π ⋅ [mC ⋅ (1 – D) – 0.5]
6.2
Error amplifier compensation network
The ST1S14 embeds the error amplifier (see Figure 10) and a pre-defined compensation
network which is effective in stabilizing the system in most of the application conditions.
Figure 10. Transconductance embedded error amplifier
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R and C introduce a pole and a zero in the open loop gain. C does not significantly affect
C
C
P
system stability but it is useful to reduce the noise at the output of the error amplifier.
The transfer function of the error amplifier and its compensation network is:
Equation 8
AV0 ⋅ (1 + s ⋅ Rc ⋅ Cc)
A0(s) = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
s2 ⋅ R0 ⋅ (C0 + Cp) ⋅ Rc ⋅ Cc + s ⋅ (R0 ⋅ Cc + R0 ⋅ (C0 + Cp) + Rc ⋅ Cc) + 1
where A = G · R .
vo
m
o
The poles of this transfer function are (if C >> C +C ):
c
0
P
Equation 9
1
fP LF = -----------------------------------------
2 ⋅ π ⋅ R0 ⋅ Cc
18/46
DocID17977 Rev 2
ST1S14
Closing the loop
Equation 10
1
fP HF = ------------------------------------------------------------
2 ⋅ π ⋅ Rc ⋅ (C0 + Cp)
whereas the zero is defined as:
Equation 11
1
FZ = -----------------------------------------
2 ⋅ π ⋅ Rc ⋅ Cc
The embedded compensation network is R =200 K, C =24 pF, C =211 pF and C can be
C
P
C
O
considered negligible, so the singularities are:
Equation 12
fZ = 3, 77 kHz
fP LF = 3, 01 Hz
fP HF = 33, 16 kHz
6.3
Voltage divider
The contribution of a simple voltage divider is:
Equation 13
R2
GDIV(s) = --------------------
R1 + R2
Figure 11. Leading network example
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A small signal capacitor in parallel to the upper resistor (see Figure 11.) of the voltage
divider implements a leading network (f
system phase margin:
< f
), sometimes necessary to improve the
zero
pole
Equation 14
DocID17977 Rev 2
19/46
Closing the loop
ST1S14
R2
(1 + s ⋅ R1 ⋅ CR1)
-------------------- ----------------------------------------------------------------
GDIV(s) =
⋅
R1 + R2
R1 ⋅ R2
---------------------
R1 + R2
⎛
⎞
1 + s ⋅
⋅ CR1
⎝
⎠
where:
1
---------------------------------------------
fZ
=
2 ⋅ π ⋅ R1 ⋅ CR1
1
fP = ------------------------------------------------------------
R1 ⋅ R2
---------------------
2 ⋅ π ⋅
⋅ CR1
R1 + R2
fZ < fP
6.4
Total loop gain
In summary, the open loop gain can be expressed as:
Equation 15
G(s) = GDIV(s) ⋅ GCO(s) ⋅ A0(s)
Example: V = 12 V, V
= 3.3 V, R
= 2 Ω.
IN
OUT
OUT
The resistor divider is R =5.6 K, R =3.3 K.
1
2
C
=150 nF implements a leading network (f =190 kHz, f =510 kHz).
Z P
R1
Selecting L = 8.2 µH, C
diagrams are plotted respectively in Figure 12 and 13 over input voltage range (V =6
= 100 µF, and ESR = 75 mΩ, the gain and phase bode
OUT
IN
V to 48 V, I
=3 A).
OUT
Figure 12. Module plot
$0ꢄꢉꢊꢅꢀ9ꢄ
20/46
DocID17977 Rev 2
ST1S14
Closing the loop
Figure 13. Phase plot
$0ꢄꢉꢊꢅꢌ9ꢄ
The cut-off frequency and the phase margin are:
Equation 16
VIN = 6V
VIN = 12V
VIN = 48V
fC = 46 kHz
fC = 71 kHz
fC = 97 kHz
pm = 49°
pm = 62°
pm = 78°
DocID17977 Rev 2
21/46
Application information
ST1S14
7
Application information
7.1
Component selection
7.1.1
Input capacitor
The input capacitor must be able to support the maximum input operating voltage and the
maximum RMS input current.
Since step-down converters draw current from the input in pulses, the input current is
squared and the height of each pulse is equal to the output current. The input capacitor has
to absorb all this switching current, whose RMS value can be up to the load current divided
by two (worst case, with duty cycle of 50 %). For this reason, the quality of these capacitors
must be very high to minimize the power dissipation generated by the internal ESR, thereby
improving system reliability and efficiency. The critical parameter is usually the RMS current
rating, which must be higher than the RMS current flowing through the capacitor. The
maximum RMS input current (flowing through the input capacitor) is:
Equation 17
2 ⋅ D2 D2
IRMS = IO
⋅
D – ----------------- + ------
2
η
η
where ηis the expected system efficiency, D is the duty cycle, and I is the output DC
O
current. Considering η= 1 this function reaches its maximum value at D = 0.5 and the
equivalent RMS current is equal to I divided by 2. The maximum and minimum duty cycles
O
are:
Equation 18
V
OUT + VF
DMAX = ------------------------------------
INMIN – VSW
V
and
Equation 19
V
OUT + VF
DMIN = --------------------------------------
INMAX – VSW
V
Where V is the freewheeling diode forward voltage and V
the voltage drop across the
F
SW
internal PDMOS. Considering the range D
to D
, it is possible to determine the
MIN
MAX
maximum IRMS going through the input capacitor. Capacitors that may be considered are:
Electrolytic capacitors:
These are widely used due to their low cost and their availability in a wide range of
RMS current ratings.
The only drawback is that, considering ripple current rating requirements, they are
physically larger than other capacitors.
22/46
DocID17977 Rev 2
ST1S14
Application information
Ceramic capacitors:
If available for the required value and voltage rating, these capacitors usually have a
higher RMS current rating for a given physical dimension (due to very low ESR).
The drawback is the considerably high cost.
Tantalum capacitors:
Small tantalum capacitors with very low ESR are becoming more available. However,
they can occasionally burn if subjected to very high current during charge.
Therefore, it is suggested to avoid this type of capacitor for the input filter of the device
as they could be stressed by a high surge current when connected to the power supply.
Table 8. List of ceramic capacitors for the ST1S14
Manufacturer
Series
Capacitor value (µ)
Rated voltage (V)
TAIYO YUDEN
MURATA
UMK325BJ106MM-T
10
50
50
GRM42-2 X7R 475K 50
4.7
If the selected capacitor is ceramic (so neglecting the ESR contribution), the input voltage
ripple can be calculated as:
Equation 20
IO
D
η
D
η
⎛
⎝
⎞
--------------------------
CIN ⋅ fSW
---
1 – --- ⋅ D + ⋅ (1 – D)
VIN PP
=
⋅
⎠
7.1.2
Output capacitor
The output capacitor is very important to meet the output voltage ripple requirement.
Using a small inductor value is useful to reduce the size of the choke but it increases the
current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required.
Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain,
which helps to increase the phase margin of the system. If the zero goes to a very high
frequency, its effect is negligible.
Ceramic capacitors
Ceramic capacitors and very low ESR capacitors that introduce a zero outside the
designed bandwidth (f =1/(2*pi*ESR*C
, see Section 6: Closing the loop) in general
Z
OUT
should be avoided. A leading network across the upper resistor of the voltage divider is
useful to increase the phase margin and compensate the system (see Section 6.3:
Voltage divider). The effectiveness of the leading network increases at high output
voltage because the singularities become more split.
High ESR capacitors
The “high ESR capacitor” definition stands for a capacitor having an ESR value able to
introduce a zero into the designed system bandwidth, which can be, as a general rule,
up to f /5 at maximum. Tantalum or electrolytic capacitors belong to this group.
SW
Equation 21
fSW
--------
5
1
----------------------------------------------------------
fZ
=
< BW <
2 ⋅ π ⋅ ESR ⋅ COUT
DocID17977 Rev 2
23/46
Application information
ST1S14
A list of some tantalum capacitor manufacturers is provided in Table 9.
Table 9. Output capacitor selection
Manufacturer
Series
Rated voltage (V) Cap value (µF)(1)
ESR (mΩ)(1)
Nippon Chemicon
Sanyo POSCAP(2)
KZE
TAE
6.3 to 50
4 to 16
4 to 16
1
THB/C/E
----------------------------------------------------------
fZ
=
< BW
2 ⋅ π ⋅ ESR ⋅ COUT
AVX
TPS
4 to 35
1. see Section 6: Closing the loop for the selection of the output capacitor
2. POSCAP capacitors have some characteristics which are very similar to tantalum.
7.1.3
Inductor
The inductor value is very important as it fixes the ripple current flowing through the output
capacitor. The ripple current is usually fixed at 20 - 40 % of I , which is 0.6 - 1.2 A with
omax
= 3 A. The approximate inductor value is obtained using the following formula:
IOmax
Equation 22
(VIN – V
)
----------------------O----U----T----
L =
⋅ TON
ΔI
where T is the ON time of the internal switch, given by D · T. For example, with
ON
V
= 3.3 V, V = 24 V, and ΔI = 0.8 A, the inductor value is about 4.7 µH. The peak
OUT
IN O
current through the inductor is given by:
Equation 23
ΔI
IPK = IO + -----
2
and it can be observed that if the inductor value decreases, the peak current (which must be
lower than the current limit of the device) increases. So, when the peak current is fixed, a
higher inductor value allows a higher value for the output current. In Table 10, some inductor
manufacturers are listed.
Table 10. Inductor selection
Manufacturer
Series
Inductor value (µH)
Saturation current (A)
WE-HCI 7040
WE-HCI 7050
XPL 7030
1 to 4.7
4.9 to 10
2.2 to 10
20 to 7
20 to 4.0
29 to 7.2
Wurth Elektronik
Coilcraft
7.2
Layout considerations
The layout of switching DC-DC converters is very important to minimize noise and
interference. Power-generating portions of the layout are the main cause of noise and so
24/46
DocID17977 Rev 2
ST1S14
Application information
high switching current loop areas should be kept as small as possible and lead lengths as
short as possible.
High impedance paths (in particular the feedback connections) are susceptible to
interference, so they should be as far as possible from the high current paths. A layout
example is provided in Figure 14 below.
The input and output loops are minimized to avoid radiation and high frequency resonance
problems. The feedback pin connections to the external divider are very close to the device
in order to avoid pick-up noise. Another important issue is the ground plane of the board. As
the package has an exposed pad, it is very important to connect it to an extended ground
plane in order to reduce the thermal resistance junction-to-ambient.
To increase the design noise immunity, different signal and power ground should be
implemented in the layout (see Section 7.5: Application circuit). The signal ground serves
the small signal components, the device ground pin, the exposed pad, and a small filtering
capacitor connected to the VCC pin. The power ground serves the external diode and the
input filter. The different grounds are connected underneath the output capacitor. Neglecting
the current ripple contribution, the current flowing through this component is constant during
the switching activity and so this is the cleanest ground point of the buck application circuit.
Figure 14. Layout example
$0ꢄꢉꢊꢄꢅ9ꢄ
DocID17977 Rev 2
25/46
Application information
ST1S14
7.3
Thermal considerations
The dissipated power of the device is tied to three different sources:
•
Conduction losses due to the not insignificant R
, which are equal to:
DSON
Equation 24
PON = RDSON ⋅ (IOUT)2 ⋅ D
where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between V and V , but in practice it is substantially higher than this value to
OUT
IN
compensate for the losses in the overall application. For this reason, the conduction losses
related to the R increase compared to an ideal case.
DSON
•
Switching losses due to turning on and off. These are derived using the following
equation:
Equation 25
(TRISE + TFALL
----------------------------------------
⋅ FSW= VIN ⋅ IOUT ⋅ TSW_EQ ⋅ FSW
)
PSW = VIN ⋅ IOUT
⋅
2
where T
and T
represent the switching times of the power element that cause the
RISE
FALL
switching losses when driving an inductive load (see Figure 15). T
is the equivalent
SW
switching time.
Figure 15. Switching losses
$0ꢄꢉꢊꢄꢄ9ꢄ
•
Quiescent current losses.
Equation 26
PQ = VIN ⋅ IQ
26/46
DocID17977 Rev 2
ST1S14
Application information
Example:
–
–
–
V
V
= 24 V
IN
= 5 V
OUT
I
= 3 A
OUT
R
has a typical value of 0.2 Ω @ 25 °C and increases to a maximum value of 0.4 Ω@
DS(on)
125 °C. We can consider a value of 0.3 Ω.
T
is approximately 12 ns.
SW_EQ
I has a typical value of 2 mA @ V = 24 V.
Q
IN
The overall losses are:
Equation 27
PTOT = RDSON ⋅ (IOUT)2 ⋅ D + VIN ⋅ IOUT ⋅ TSW ⋅ FSW + VIN ⋅ IQ= "
= 0.3 ⋅ (3)2 ⋅ 0.137 + 24 ⋅ 3 ⋅ 12 ⋅ 10–9 ⋅ 850 ⋅ 10–3 + 24 ⋅ 2 ⋅ 10–3 ≅ 1.15W
The junction temperature of the device is:
Equation 28
TJ = TA + RthJ – A ⋅ PTOT
where T is the ambient temperature and Rth is the thermal resistance junction-to-
A
J-A
ambient. Considering that the device is mounted on board with a good ground plane, that it
has a thermal resistance junction-to-ambient (Rth ) of about 40 °C/W, and an ambient
J-A
temperature of about 40 °C:
TJ = 40 + 1.15 ⋅ 40 ≅ 86° C
7.4
Short-circuit protection
In overcurrent protection mode, when the peak current reaches the current limit, the device
disables the power element and it is able to reduce the conduction time down to the
minimum value (approximately 90 nsec typical) to keep the inductor current limited. This is
the pulse by pulse current limitation to implement constant current protection feature.
For the ST1S14, the operation of the pulse by pulse current limitation out of the soft start
time depends on the FB voltage:
•
300 mV <VFB <1.22 V: the device operates at nominal switching frequency and the
current limitation value
•
VFB < 300mV: the switching frequency is decreased five times the nominal value (170
kHz = 850 kHz/5) if the current protection is triggered. The frequency foldback helps to
prevent the current diverging at low VOUT / high input voltage. The current foldback,
which is active out of the soft start time, reduces the stress of the embedded power
element and the external power components in case of persistent short circuit at the
output. The current foldback is disabled during the soft start time to provide full current
capability to charge the output capacitor at the power-up phase.The foldback peak
current value is to 1.45 A typical. In overcurrent condition, the duty cycle is strongly
DocID17977 Rev 2
27/46
Application information
ST1S14
reduced and, in most applications, this is enough to limit the switch current to the
active current threshold, nominal or foldback depending on the FB voltage.
The inductor current ripple during ON and OFF phases can be written as:
•
ON phase
Equation 29
V
IN – VOUT – (DCRL + RDSON) ⋅ I
------------------------------------------------------------------------------------------
ΔIL TON
=
(TON
)
L
•
OFF phase
Equation 30
–(VD + VOUT + DCRL ⋅ I)
--------------------------------------------------------------------
(TOFF)
ΔIL TON
=
L
where V is the voltage drop across the diode, DCR is the series resistance of the inductor.
D
L
The pulse-by-pulse current limitation is effective in implementing constant current protection
when:
Equation 31
ΔIL TON = ΔIL TOFF
The overcurrent protection is operating over the entire output voltage, which goes from the
regulated output voltage (V
output.
) down to GND during heavy short circuit applied at the
O_SET
From Equation 29 and Equation 30 we can gather that the implementation of the constant
current protection becomes more critical the lower is the V and the higher is V .
OUT
IN
In fact, the voltage applied to the inductor during the OFF time becomes equal to the voltage
drop across parasitic components (typically the DCR of the inductor and the V of the free
FW
wheeling diode) when VOUT is negligible, while during T the voltage applied the inductor
ON
is maximized and it is approximately equal to V . In general the worst case scenario is
IN
heavy short-circuit at the output with maximum input voltage.
7.4.1
300 mV < V < 1.22 V
FB
The nominal output voltage can be written as:
Equation 32
R1
R1
⎛
⎝
⎞
⎛
⎞
⎠
VO_SET = VFB
⋅
1 + ------ = 1.22 ⋅ 1 + ------
⎠
R2
⎝
R2
From Equation 32 the voltage can be expressed as:
Equation 33
R1
VO_SET
⎛
⎝
⎞
1 + ------ = ------------------
⎠
R2
1.22
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DocID17977 Rev 2
ST1S14
Application information
so the output voltage is:
Equation 34
VO_SET
------------------
1.22
R1
⎛
⎝
⎞
1 + ------ = VFB ⋅
VO = VFB
⋅
⎠
R2
Equation 29 and 30, in overcurrent conditions, can be simplified to:
Equation 35
V
IN–(DCRL + RDSON) ⋅ I
VIN
--------
L
-------------------------------------------------------------------
ΔIL TON
=
(TON MIN) ≅
(90ns)
L
considering T which has already been reduced to its minimum.
ON
Equation 36
VO_SET
------------------
+ DCRL ⋅ I
⎛
⎞
– VD + VFB
⋅
–(VD + VO_MIN + DCRL ⋅ I)
⎝
⎠
1.22
------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
ΔIL TOFF
=
(TSW – 90ns) ≅
(1.18μs)
L
L
where T =1/f
and considering the nominal f
.
SW
SW
SW
The voltage divider introduces a gain factor K between the V
and V that affect the
FB
O_SET
effectiveness of the current protection. The worst case scenario is the minimum K, that is
the minimum output voltage, over the input voltage (Chapter 5.2: Minimum output voltage
over V range).
IN
As a consequence the minimum feedback voltage to keep the inductor current limited over
the input voltage range can be expressed making Equation 35 equal to Equation 36 and
expressing V
as given in Equation 1:
O_SET
Equation 37
1.22 ⋅ TSW
VIN ⋅ TON_MIN
⎛
⎝
⎞
--------------------------------------
VFB(VIN) = 1.22 –
⋅ (VD + (IL ⋅ DCR))
⎠
Equation 37 expresses the worst case scenario as it considers the minimum K gain of the
voltage divider over the entire input voltage range. The Figure 16 plots the Equation 37
considering the minimum value of the peak current limit given in Table 6: Electrical
characteristics on page 8.
DocID17977 Rev 2
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Application information
ST1S14
Figure 16. Minimum V for effective pulse-by-pulse protection over V
FB
IN
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As a consequence of V > 12 V the pulse-by-pulse current protection (in the worst case
IN
scenario which is the minimum V
) may not be effective to limit the inductor current to
OSET
the peak current limitation over the entire FB range 300 mV < V < 1.22 V.
FB
In fact, at higher input voltage, ΔI
may be higher than ΔI
and so the inductor
L TON
L TOFF
current could escalate. The system typically meets Equation 31 at a current level higher
than the nominal value thanks to the voltage drop across stray components.
Figure 17. I diverging triggers hiccup protection (V = 48 V)
L
IN
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In most of the application conditions the pulse-by-pulse current limitation is effective in
limiting the inductor current.
Whenever the current escalates, a second level current protection called “hiccup mode” is
enabled. In case the hiccup current level (6.2 A typ.) is triggered the switching activity is
30/46
DocID17977 Rev 2
ST1S14
Application information
prevented for 16 ms and then a new soft-start phase takes place (see Figure 17).
7.4.2
V
< 300 mV
FB
The device reduces the switching frequency by five times the nominal value when V <300
FB
mV. The frequency foldback makes the pulse-by-pulse current protection effective to keep
the current limited when the output voltage is shorted and V
negligible.
OUT
Equation 29 and 30 in overcurrent conditions can be simplified to:
Equation 38
V
IN–(DCRL + RDSON) ⋅ I
VIN
--------
L
-------------------------------------------------------------------
ΔIL TON
=
(TON MIN) ≅
(90ns)
L
considering T which has already been reduced to its minimum.
ON
Equation 39
VO_SET
------------------
+ DCRL ⋅ I
⎛
⎞
– VD + VFB
⋅
–(VD + VO_MIN + DCRL ⋅ I)
TSW
⎝
⎠
1.22
⎛
⎝
⎞
------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
ΔIL TOFF
=
----------- – 90ns ≅
(5.9μs)
⎠
L
L
5
taking into consideration the frequency foldback feature.
Figure 18. Current and frequency foldback triggered when V <300 mV (red trace)
FB
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The content given in Section 7.4.1 is valid and the equivalent expression of Equation 37 is:
DocID17977 Rev 2
31/46
Application information
Equation 40
ST1S14
1.22 ⋅ TSW
--------------------------------------
VIN ⋅ TON_MIN
1.22
5
⎛
⎝
⎞
VFB(VIN) = ----------- –
⋅ (VD + (IL ⋅ DCR))
⎠
The Figure 19 plots the Equation 40 considering the foldback current limitation threshold
(1.45A) given in Table 6: Electrical characteristics which is active out of the soft start time.
Equation 40 expresses the worst case scenario as it considers the minimum K gain of the
voltage divider over the entire input voltage range (see Figure 14).
In most of the application conditions the pulse by pulse current limitation with frequency
foldback is effective to limit the inductor current in short circuit condition. The current
foldback helps to decrease the power component stress in persistent short circuit condition
out of the sift start time.
The hiccup protection offers an additional protection against heavy short circuit condition at
very high input voltage even considering the spread of the minimum conduction time of the
power element. In case the hiccup current level (6.2 A typical) is triggered the switching
activity is prevented for 15 ms and then a new soft start phase takes place.
Figure 19. Minimum V for effective pulse-by-pulse protection over V
FB
IN
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Figure 20 shows the effectiveness of the constant current protection limiting the inductor
current to the peak current of 1.45 A typ. during a short circuit event.
32/46
DocID17977 Rev 2
ST1S14
Application information
Figure 20. Short-circuit current V = 24 V (I
= I
)
IN
L_PK
FOLD
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Figure 21 shows the operation of the constant current protection when a short-circuit is
applied at the output at the maximum input voltage. According to Figure 20, the maximum
inductor current escalates over the foldback current limitation.
Figure 21. Short-circuit current V = 43 V (I
> I
)
IN
L_PK
FOLD
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7.4.3
Start up phase in short circuit condition
The start up phase in short circuit condition rapresents a preparatory example to show the
current protection strategy.
Figure 25 shows the first switching pulses at power up when the switch current rises but is
lower than the current protection level, called OCP1. As a consequence the switching
frequency is not reduced.
DocID17977 Rev 2
33/46
Application information
ST1S14
Figure 22. Start up in short circuit condition
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As soon as the current escalates to the current protection threshold (OCP1) the switching
frequency is foldback 5 times the nomimal value.The OCP1 threshold is not foldback even if
the VFB v< 300 mV ( see Chapter 7.4.2) becuase the device is operating in soft start time.
Figure 23. Over current protection triggers the frequency foldback
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Out of soft start time the device support frequency and current foldback operation to keep
the siwtch current limited and reduce the stress of the power components.
34/46
DocID17977 Rev 2
ST1S14
Application information
Figure 24. Over current protection triggers the current and frequency foldback
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7.5
Application circuit
Figure 25. Demonstration board application circuit
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ꢄ
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ꢃ
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ꢋ
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Table 11. Component list
Reference
Part number
Description
Manufacturer
10 μF 50 V
(size 1210)
C2, C3
UMK325BJ106MM-T
Taiyo Yuden
100 nF 50 V
(size 0603)
C6, C6
DocID17977 Rev 2
35/46
Application information
ST1S14
Table 11. Component list (continued)
Reference
Part number
Description
Manufacturer
150 pF 50 V
(size 0603)
C7
100 μF 50 V
(size 8 x 11.5 mm)
C8
C1, C9, C10, C11
R1
EKZE500ESS101MHB5D
Nippon Chemicon
Not Mounted
4.7 KΩ
(size 0603)
2.7 KΩ
(size 0603)
R2
R3
D1
47 KΩ
(size 0603)
3 A 60 V
STPS3L60U
744314850
ST
(size SMB)
8.5 μH
SAT=4.5 A, IRMS=4 A
L1
I
Wurth
(size 7 x 6.9 x 4.8 mm)
Figure 26. PCB layout (component side)
$0ꢄꢉꢊꢄꢌ9ꢄ
36/46
DocID17977 Rev 2
ST1S14
Application information
Figure 27. PCB layout (bottom side)
$0ꢄꢉꢊꢆꢅ9ꢄ
DocID17977 Rev 2
37/46
Typical characteristics
ST1S14
8
Typical characteristics
Figure 28. Line regulation
Figure 29. Load regulation
$0ꢄꢉꢊꢆꢆ9ꢄ
$0ꢄꢉꢊꢆꢉ9ꢄ
Figure 30. R
vs. temperature (V = 12 V)
Figure 31. V vs. temperature (V = 12 V)
FB IN
DSon
IN
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$0ꢄꢉꢊꢆꢃ9ꢄ
Figure 32. f
vs. temperature
Figure 33. Quiescent current vs. temperature
SW
$0ꢄꢉꢊꢆꢈ9ꢄ
$0ꢄꢉꢊꢆꢊ9ꢄ
38/46
DocID17977 Rev 2
ST1S14
Typical characteristics
Figure 34. Shutdown current vs. temperature
Figure 35. Duty cycle max vs. temperature
$0ꢄꢉꢊꢆꢀ9ꢄ
$0ꢄꢉꢊꢆꢌ9ꢄ
Figure 36. Efficiency vs. I
(V 12 V)
Figure 37. T vs. I
(V 12 V)
OUT
IN
J
OUT IN
$0ꢄꢉꢊꢉꢄ9ꢄ
$0ꢄꢉꢊꢉꢅ9ꢄ
Figure 38. Efficiency vs. I
(V 24 V)
Figure 39. T vs. I
(V 24 V)
OUT
IN
J
OUT IN
$0ꢄꢉꢊꢉꢆ9ꢄ
$0ꢄꢉꢊꢉꢉ9ꢄ
DocID17977 Rev 2
39/46
Typical characteristics
ST1S14
Figure 40. Efficiency vs. I
(V 32 V)
Figure 41. T vs. I
(V 32 V)
OUT
IN
J
OUT IN
$0ꢄꢉꢊꢉꢋ9ꢄ
$0ꢄꢉꢊꢉꢃ9ꢄ
Figure 42. 1 A to 3 A load transient (V 12 V) Figure 43. Zoom - 1 A to 3 A load transient (V
IN
IN
12 V)
$0ꢄꢉꢊꢉꢊ9ꢄ
$0ꢄꢉꢊꢉꢈ9ꢄ
Figure 44. Zoom - 1 A to 3 A rising edge load Figure 45. 1 A to 3 A falling edge load transient
transient (V 12 V) (V 24 V)
IN
IN
$0ꢄꢉꢊꢉꢀ9ꢄ
$0ꢄꢉꢊꢉꢌ9ꢄ
40/46
DocID17977 Rev 2
ST1S14
Typical characteristics
Figure 46. Zoom - 1 A to 3 A rising edge load
transient (V 24 V)
Figure 47. Zoom - 1 A to 3 A falling edge load
transient (V 24 V)
IN
IN
$0ꢄꢉꢊꢋꢄ9ꢄ
$0ꢄꢉꢊꢋꢅ9ꢄ
Figure 48. 1 A to 3 A load transient (V 32 V)
Figure 49. Zoom - 1 A to 3 A rising edge load
transient (V 32 V)
IN
IN
$0ꢄꢉꢊꢋꢉ9ꢄ
$0ꢄꢉꢊꢋꢆ9ꢄ
Figure 50. Zoom - 1 A to 3 A falling edge load
transient (V 32 V)
IN
$0ꢄꢉꢊꢋꢋ9ꢄ
DocID17977 Rev 2
41/46
Package mechanical data
ST1S14
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions, and product status are available at www.st.com.
ECOPACK is an ST trademark.
Table 12. HSOP8 mechanical data
mm
Dim.
Min.
Typ.
Max.
A
A1
A2
b
1.75
0.15
1.25
0.38
0.17
4.80
3.10
5.80
3.80
2.20
0.51
0.25
5.00
3.50
6.20
4.00
2.60
c
D
4.90
3.30
6.00
3.90
2.40
1.27
D1
E
E1
E2
e
h
0.30
0.45
0°
0.50
0.80
8°
L
k
42/46
DocID17977 Rev 2
ST1S14
Package mechanical data
Figure 51. Package dimensions
7195016D
DocID17977 Rev 2
43/46
Order code
ST1S14
10
Order code
Table 13. Ordering information
Package
Order code
Packaging
ST1S14PHR
HSOP8 - exposed pad
Tape and reel
44/46
DocID17977 Rev 2
ST1S14
Revision history
11
Revision history
Table 14. Document revision history
Date
Revision
Changes
12-Nov-2010
1
Initial release
Updated IEN2 current limit.
04-Mar-2013
2
Updated Section 4.3: Soft-start and Section 7.4: Short-circuit
protection.
DocID17977 Rev 2
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ST1S14
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
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