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ST25C16B5TR

更新时间：2024-09-18 02:14:53

品牌：STMICROELECTRONICS

描述：16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection

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ST25C16B5TR 概述

16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection 16千位串行I2C总线的EEPROM与用户定义的块写保护

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ST24C16, ST25C16

ST24W16, ST25W16

16 Kbit Serial I C Bus EEPROM

with User-Defined Block Write Protection

1 MILLION ERASE/WRITE CYCLES, with

40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE:

– 4.5V to 5.5V for ST24x16 versions

– 2.5V to 5.5V for ST25x16 versions

HARDWARE WRITE CONTROL VERSIONS:

ST24W16 and ST25W16

TWO WIRE SERIAL INTERFACE, FULLY I²C

BUS COMPATIBLE

PSDIP8 (B)

0.25mm Frame

SO8 (M)

150mil Width

BYTE and MULTIBYTE WRITE (up to 8

BYTES) for the ST24C16

PAGE WRITE (up to 16 BYTES)

BYTE, RANDOM and SEQUENTIAL READ

MODES

SELF TIMED PROGRAMING CYCLE

Figure 1. Logic Diagram

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP

PERFORMANCES

DESCRIPTION

This specification covers a range of 16 Kbit I²C bus

EEPROM products, the ST24/25C16 and the

ST24/25W16. In the text, products are referred to

as ST24/25x16 where "x" is: "C" for Standard ver-

sion and "W" for hardware Write Control version.

The ST24/25x16 are 16 Kbit electrically erasable

programmable memories (EEPROM), organized

as 8 blocks of 256 x8 bits. These are manufactured

in STMicroelectronics’s Hi-Endurance Advanced

CMOS technology which guarantees an endur-

PB0-PB1

PRE

SDA

ST24x16

ST25x16

SCL

MODE/WC*

Table 1. Signal Names

PRE

Write Protect Enable

Protect Block Select

Serial Data Address Input/Output

Serial Clock

PB0, PB1

SDA

AI00866B

SCL

Multybyte/Page Write Mode

(C version)

MODE

V_CC

V_SS

Write Control (W version)

Supply Voltage

Ground

Note: WC signal is only available for ST24/25W16 products.

February 1999

1/17

ST24/25C16, ST24/25W16

Figure 2A. DIP Pin Connections

Figure 2B. SO8 Pin Connections

ST24x16

ST25x16

ST24x16

ST25x16

PRE

PB0

PB1

PRE

PB0

PB1

MODE/WC

SCL

SDA

AI00867B

AI00500B

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

Unit

°C

Ambient Operating Temperature

Storage Temperature

–40 to 125

–65 to 150

T_STG

°C

T_LEAD

Lead Temperature, Soldering

(SO8)

(PSDIP8)

40 sec

10 sec

215

260

°C

V_IO

Input or Output Voltages

Supply Voltage

–0.6 to 6.5

–0.3 to 6.5

4000

V_CC

Electrostatic Discharge Voltage (Human Body model) ⁽²⁾

Electrostatic Discharge Voltage (Machine model) ⁽³⁾

V_ESD

500

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and

other relevant quality documents.

2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

3. 200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d)

carry a built-in 4 bit, unique device identification

code (1010) corresponding to the I²C bus defini-

tion. The memories behave as slave devices in the

I²C protocol with all memory operations synchro-

nized by the serial clock. Read and write operations

are initiated by a STARTcondition generated by the

bus master. The START condition is followed by a

stream of 4 bits (identification code 1010), 3 block

select bits, plus one read/write bit and terminated

by an acknowledge bit. When writing data to the

ance of one million erase/write cycles with a data

retention of 40 years. The ST25x16 operates with

a power supply value as low as 2.5V. Both Plastic

Dual-in-Line and Plastic Small Outline packages

are available.

The memories are compatible with the I²C stand-

ard, two wire serial interface which uses a bi-direc-

tional data bus and serial clock. The memories

2/17

ST24/25C16, ST24/25W16

Table 3. Device Select Code

Device Code

Memory MSB Addresses

Bit

Device Select

A10

Note: The MSB b7 is sent first.

Table 4. Operating Modes

Mode

RW bit

MODE pin

Bytes

Initial Sequence

START, Device Select, RW = ’1’

Current Address Read

’1’

’0’

’1’

’0’

START, Device Select, RW = ’0’, Address,

reSTART, Device Select, RW = ’1’

As CURRENT or RANDOM Mode

START, Device Select, RW = ’0’

Random Address Read

Sequential Read

Byte Write

1 to 2048

Multibyte Write

V_IH

V_IL

Page Write

Note: X = V_IHor V_IL.

memory it responds to the 8 bits received by as-

serting an acknowledge bit during the 9th bit time.

When data is read by the bus master, it acknow-

ledges the receipt of the data bytes in the same

way. Data transfers are terminated with a STOP

condition.

Data in the 4 upper blocks of the memory may be

write protected. The protected area is programma-

ble to start on any 16 byte boundary. The block in

which the protection starts is selected by the input

pins PB0, PB1. Protection is enabled by setting a

Protect Flag bit when the PRE input pin is driven

High.

Power On Reset: V_CClock out write protect. In

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Untill the V_CC

voltage has reached the POR threshold value, the

internal reset is active: all operations are disabled

and the device will not respond to any command.

In the same way, when V_CCdrops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable V_CC

must be applied before applying any logic signal.

3/17

ST24/25C16, ST24/25W16

SIGNALS DESCRIPTION

Mode (MODE). The MODE input is available on pin

7 (see alsoWC feature) and may be driven dynami-

cally. It must be at V_ILor V_IHfor the Byte Write

mode, V_IHfor Multibyte Write mode or V_ILfor Page

Write mode. When unconnected, the MODE input

is internally read as V_IH(Multibyte Write mode).

Serial Clock (SCL). The SCL input signal is used

to synchronise all data in and out of the memory. A

resistor can be connected from the SCL line to V_CC

to act as a pull up (see Figure 3).

Serial Data (SDA). The SDAsignal is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on

the bus. Aresistor must be connected from the SDA

bus line to V_CCto act as pull up (see Figure 3).

Write Control (WC). An hardware Write Control

feature is offered only for ST24W16 and ST25W16

versions on pin 7. This feature is usefull to protect

the contents of the memory from any erroneous

erase/write cycle. The Write Control signal is used

to enable (WC at V_IH) or disable (WC at V_IL) the

internal write protection. When unconnected, the

WC input is internally read as V_IL. The devices with

this Write Control feature no longer supports the

Multibyte Write mode of operation, however all

other write modes are fully supported.

ProtectedBlock Select (PB0, PB1). PB0 and PB1

input signals select the block in the upper part of

the memory where write protection starts. These

inputs have a CMOS compatible input level.

Protect Enable (PRE). The PRE input signal, in

addition to the status of the Block Address Pointer

bit (b2, location 7FFh as in Figure 7), sets the PRE

write protection active.

Refer to the AN404 Application Note for more de-

tailed information about Write Control feature.

Figure 3. Maximum R_LValue versus Bus Capacitance (C_BUS) for an I²C Bus

SDA

BUS

MASTER

SCL

BUS

= 5V

100

200

(pF)

300

400

AI01100

BUS

4/17

ST24/25C16, ST24/25W16

Table 5. Input Parameters ⁽¹⁾(T_A= 25 °C, f = 100 kHz )

Symbol

C_IN

Parameter

Input Capacitance (SDA)

Test Condition

Min

Max

Unit

C_IN

Input Capacitance (other pins)

Z_WCL

Z_WCH

WC Input Impedance (ST24/25W16)

_IN≤ 0.3 V_CC

_IN≥ 0.7 V_CC

kΩ

500

Low-pass filter input time constant

(SDA and SCL)

t_LP

100

Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics

(T_A= 0 to 70 °C or –40 to 85 °C; V_CC= 4.5V to 5.5V or 2.5V to 5.5V)

Symbol

Parameter

Test Condition

Min

Max

Unit

I_LI

Input Leakage Current

0V ≤ V_IN≤ V_CC

±2

µA

0V ≤ V_OUT≤ V_CC

I_LO

Output Leakage Current

±2

µA

SDA in Hi-Z

_CC= 5V, f_C= 100kHz

Supply Current (ST24 series)

Supply Current (ST25 series)

µA

(Rise/Fall time < 10ns)

I_CC

V_CC= 2.5V, f_C= 100kHz

_IN= V_SSor V_CC

V_CC= 5V

100

Supply Current (Standby)

(ST24 series)

I_CC1

_IN= V_SSor V_CC

300

µA

V_CC= 5V, f_C= 100kHz

V_IN= V_SSor V_CC

V_CC= 2.5V

Supply Current (Standby)

(ST25 series)

I_CC2

_IN= V_SSor V_CC

V_CC= 2.5V, f_C= 100kHz

V_IL

V_IH

Input Low Voltage (SCL, SDA)

Input High Voltage (SCL, SDA)

–0.3

0.3 V_CC

V_CC+ 1

0.7 V_CC

Input Low Voltage

V_IL

V_IH

–0.3

0.5

(PB0 - PB1, PRE, MODE, WC)

Input High Voltage

(PB0 - PB1, PRE, MODE, WC)

_CC– 0.5

V_CC+ 1

Output Low Voltage (ST24 series)

Output Low Voltage (ST25 series)

I_OL= 3mA, V_CC= 5V

_OL= 2.1mA, V_CC= 2.5V

0.4

V_OL

5/17

ST24/25C16, ST24/25W16

Table 7. AC Characteristics

(T_A= 0 to 70 °C or –40 to 85 °C; V_CC= 4.5V to 5.5V or 2.5V to 5.5V)

Symbol

t_CH1CH2

t_CL1CL2

t_DH1DH2

t_DL1DL1

Alt

t_R

Parameter

Min

Max

Unit

µs

Clock Rise Time

Clock Fall Time

Input Rise Time

Input Fall Time

t_F

300

t_R

µs

t_F

300

(1)

t_CHDX

t_SU:STA

t_HIGH

t_HD:STA

t_HD:DAT

t_LOW

t_SU:DAT

t_SU:STO

t_BUF

t_AA

Clock High to Input Transition

Clock Pulse Width High

4.7

µs

t_CHCL

t_DLCL

t_CLDX

t_CLCH

t_DXCX

t_CHDH

t_DHDL

Input Low to Clock Low (START)

Clock Low to Input Transition

Clock Pulse Width Low

4.7

250

4.7

0.3

300

Input Transition to Clock Transition

Clock High to Input High (STOP)

Input High to Input Low (Bus Free)

Clock Low to Next Data Out Valid

Data Out Hold Time

µs

(2)

t_CLQV

3.5

t_CLQX

f_C

t_DH

f_SCL

t_WR

Clock Frequency

100

kHz

(3)

t_W

Write Time

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP

conditions.

3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant)

the maximum programming time is doubled to 20ms.

Table 8. AC Measurement Conditions

DEVICE OPERATION

I²C Bus Background

Input Rise and Fall Times

Input Pulse Voltages

≤ 50ns

The ST24/25x16 support the I²C protocol. This

protocol defines any device that sends data onto

the bus as a transmitter and any device that reads

the data as a receiver. The device that controls the

data transfer is known as the master and the other

as the slave. The master will always initiate a data

transfer and will provide the serial clock for syn-

chronisation. The ST24/25x16 are always slave

devices in all communications.

0.2V_CCto 0.8V_CC

Input and Output Timing Ref.

Voltages

0.3V_CCto 0.7V_CC

Figure 4. AC Testing Input Output Waveforms

Start Condition. START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the ST24/25x16 con-

tinuously monitor the SDA and SCL signals for a

START condition and will not respond unless one

is given.

0.8V

0.7V

0.3V

0.2V

AI00825

6/17

ST24/25C16, ST24/25W16

Figure 5. AC Waveforms

tCHCL

tDLCL

tCLCH

SCL

tDXCX

tCHDH

SDA IN

tCHDX

tCLDX

SDA

tDHDL

START

CONDITION

SDA

STOP &

BUS FREE

INPUT CHANGE

SCL

tCLQV

tCLQX

DATA VALID

SDA OUT

DATA OUTPUT

SCL

SDA IN

tCHDH

tCHDX

STOP

WRITE CYCLE

START

CONDITION

AI00795B

7/17

ST24/25C16, ST24/25W16

Figure 6. I²C Bus Protocol

SCL

SDA

START

SDA

STOP

CONDITION

INPUT CHANGE

CONDITION

SCL

SDA

ACK

MSB

START

CONDITION

SCL

SDA

MSB

ACK

STOP

CONDITION

AI00792

Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is

stable in the high state. A STOP condition termi-

nates communication between the ST24/25x16

and the bus master. A STOP condition at the end

of a Read command forces the standby state. A

STOP condition at the end of a Write command

triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal

is used to indicate a successful data transfer. The

bus transmitter, either master or slave, will release

the SDAbus after sending 8 bits of data. During the

9th clock pulse period the receiver pulls the SDA

bus low to acknowledge the receipt of the 8 bits of

data.

Data Input. During data input the ST24/25x16

samples the SDA bus signal on the rising edge of

the clock SCL. Note that for correct device opera-

tion the SDA signal must be stable during the clock

low to high transition and the data must change

ONLY when the SCL line is low.

Memory Addressing. To start communication be-

tween the bus master and the slave ST24/25x16,

the master must initiate a START condition. The 8

bits sent after a START condition are made up of a

device select of 4 bits that identifie the device type

(1010), 3 Block select bits and one bit for a READ

(RW = 1) or WRITE (RW = 0) operation.

There are three modes both for read and write.

They are summarised in Table 4 and described

hereafter. A communication between the master

and the slave is ended with a STOP condition.

8/17

ST24/25C16, ST24/25W16

Figure 7. Memory Protection

PB1

PB0

Block

Select

Protect Location

16 byte

boundary

address

Protect Flag

Enable = 0

Disable = 1

PB1 PB0

7FFh

700h

Block 7

Block 6

Block 5

Block 4

600h

500h

400h

AI00870B

Write Operations

is independant of the state of the MODE pin which

could be left floating if only this mode was to be

used. However it is not a recommended operating

mode, as this pin has to be connected to either V_IH

or V_IL, to minimize the stand-by current.

The Multibyte Write mode (only available on the

ST24/25C16 versions) is selected when the MODE

pin is at V_IHand the Page Write mode when MODE

pin is at V_IL. The MODE pin may be driven dynami-

cally with CMOS input levels.

Multibyte Write (ST24/25C16 only). For the Mul-

tibyte Write mode, the MODE pin must be at V_IH.

The Multibyte Write mode can be started from any

address in the memory. The master sends fromone

up to 8 bytes ofdata, which are each acknowledged

by the memory. The transfer is terminated by the

master generating a STOP condition. The duration

of the write cycle is t_W= 10ms maximum except

when bytes are accessed on 2 contiguous rows

(one row is 16 bytes), the programming time is then

doubled to a maximum of 20ms. Writing more than

8 bytes in the Multibyte Write mode may modify

data bytes in an adjacent row (one row is 16 bytes

long). However, the Multibyte Write can properly

write up to 16 consecutive bytes only if the first

address of these 16 bytes is the first address of the

row, the 15 following bytes being written in the 15

following bytes of this same row.

Following a START condition the master sends a

device select code with the RW bit reset to ’0’. The

memory acknowledges this and waits for a byte

address. The byte address of 8 bits provides ac-

cess to any of the 256 bytes of one memory block.

After receipt of the byte address the device again

responds with an acknowledge.

For the ST24/25W16 versions, any write command

with WC = ’1’ (during a period of time from the

START condition untill the end of the Byte Address)

will not modify data and will NOT be acknowledged

on data bytes, as in Figure 10.

Byte Write. In the Byte Write mode the master

sends one data byte, which is acknowledged by the

memory. The master then terminates the transfer

by generating a STOP condition. The Write mode

9/17

ST24/25C16, ST24/25W16

Page Write. For the Page Write mode, the MODE

pin must be at V_IL. The Page Write mode allows up

to 16 bytes to be written in a single write cycle,

provided that they are all located in the same ’row’

in the memory: that is the same Block Address bits

(b3, b2, b1 of Device Select code in Table 3) and

the same 4 MSBs in the Byte Address. The master

sends one up to 16 bytes of data, which are each

acknowledged by the memory. After each byte is

transfered, the internal byte address counter (4

Least Significant Bits only) is incremented. The

transfer is terminated by the master generating a

STOP condition. Care must be taken to avoid ad-

dress counter ’roll-over’ which could result in data

being overwritten. Note that for any write mode, the

generation by the master of the STOP condition

starts the internal memory program cycle. All inputs

are disabled until the completion of this cycle and

the memory will not respond to any request.

Minimizing System Delay by Polling On ACK.

During the internal Write cycle, the memory discon-

nects itself from the bus in order to copy the data

from the internal latches to the memory cells. The

maximum value of the Write time (t_W) is given in the

AC Characteristics table, this timing value may be

reduced by an ACK polling sequence issued by the

master.

The sequence is:

– Initial condition: a Write is in progress (see Fig-

ure 8).

– Step 1: the Master issues a START condition

followed by a Device Select byte (1st byte of

the new instruction).

– Step 2: if the memory is internally writing, no

ACK will be returned. The Master goes back

to Step1. If the memory has terminated the in-

ternal writing, it will issue an ACK indicating

that the memory is ready to receive the sec-

ond part of the instruction (the first byte of this

instruction was already sent during Step 1).

Figure 8. Write Cycle Polling using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

First byte of instruction

with RW = 0 already

decoded by ST24xxx

YES

Operation is

Addressing the

Memory

YES

Send

Byte Address

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

AI01099B

10/17

ST24/25C16, ST24/25W16

Write Protection. Data in the upper four blocks of

256 bytes of the memory may be write protected.

The memory iswrite protected betweena boundary

address and the top of memory (address

7FFh).The boundary address is user defined by

writing it in the Block Address Pointer (location

7FFh).

– select the block by hardwiring the signals PB0

& PB1;

– set the protection by writing the correct bottom

boundary address in the Address Pointer (4

MSBs of location 7FFh) with bit b2 (Protect

Flag) set to ’0’.

Note that for a correct fonctionality of the memory,

all the 4 LSBs of the Block Address Pointer must

also be programmed at ’0’. The area will be pro-

tected when the PRE input is taken High.

The Block Address Pointer is an 8 bit EEPROM

posed by 4 MSBs Address Pointer, which defines

the bottom boundary address, and 4 LSBs which

must be programmed at ’0’. This Address Pointer

can therefore address a boundary by page of 16

bytes.

Remark: The Write Protection is active if and only

if the PRE input pin is driven High and the bit 2 of

location 7FFh is set to ’0’. In all the other cases, the

memory Block will not be protected. While the PRE

input pin is read at ’0’ by the memory, the location

7FFh can be used as a normal EEPROM byte.

The block in which the Block Address Pointer de-

fines the boundary of the write protected memory

is defined by the logic level applied on the PB1 and

PB0 input pins:

Caution: Special attention must be used when

using the protect mode together with the Multibyte

Write mode (MODE input pin High). If the Multibyte

Write starts at the location right below the first byte

of the Write Protected area, then the instruction will

write over the first 7 bytes of the Write Protected

area. The area protected is therefore smaller than

the content defined in the location 7FFh, by 7 bytes.

This does not apply to the Page Write mode as the

address counter ’roll-over’ and thus cannot go

above the 16 bytes lower boundary of the protected

area.

– PB1 =’0’and PB0 =’0’ select block 4

– PB1 =’0’and PB0 =’1’ select block 5

– PB1 =’1’and PB0 =’0’ select block 6

– PB1 =’1’and PB0 =’1’ select block 7

The following sequence should be used to set the

Write Protection:

– write the data to be protected into the top of

the memory, up to, but not including, location

7FFh;

Figure 9. Write Modes Sequence (ST24/25C16)

ACK

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

R/W

ACK

BYTE ADDR

ACK

MULTIBYTE

AND

DEV SEL

DATA IN 1

DATA IN 2

PAGE WRITE

R/W

ACK

DATA IN N

AI00793

11/17

ST24/25C16, ST24/25W16

Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W16)

ACK

NO ACK

DATA IN

BYTE WRITE

DEV SEL

BYTE ADDR

R/W

ACK

NO ACK

DATA IN 1 DATA IN 2

PAGE WRITE

DEV SEL

BYTE ADDR

R/W

WC (cont'd)

NO ACK

PAGE WRITE

(cont'd)

DATA IN N

AI01161B

Read Operation

Random Address Read. A dummy write is per-

formed to load the addressinto the address counter

(see Figure 11). This is followed by another START

condition from the master and the byte address

repeated with the RW bit set to ’1’. The memory

acknowledges this and outputs the byte ad-

dressed. The master does NOT acknowledge the

byte output, but terminates the transfer with a

STOP condition.

Sequential Read. This mode can be initiated with

either a Current Address Read or a Random Ad-

dress Read. However, in this case the master

DOES acknowledge the data byte output and the

memory continues to output the next byte in se-

quence. To terminate the stream of bytes, the

master must NOT acknowledge the last byte out-

Read operations are independentof the state of the

MODE signal. On delivery, the memory content is

set at all "1’s" (or FFh).

Current Address Read. The memory has an in-

ternal byte address counter. Each time a byte is

read, this counter is incremented. For the Current

Address Read mode, following a START condition,

the master sends a memory address with the RW

bit set to ’1’. The memory acknowledges this and

outputs the byte addressed by the internal byte

address counter. This counter is then incremented.

The master does NOT acknowledge the byte out-

put, but terminates the transfer with a STOP con-

dition.

12/17

ST24/25C16, ST24/25W16

Figure 11. Read Modes Sequence

ACK

NO ACK

DATA OUT

CURRENT

ADDRESS

READ

DEV SEL

R/W

ACK

NO ACK

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

BYTE ADDR

DEV SEL *

R/W

ACK

NO ACK

SEQUENTIAL

CURRENT

READ

DEV SEL

DATA OUT 1

DATA OUT N

R/W

ACK

SEQUENTIAL

RANDOM

READ

DEV SEL *

BYTE ADDR

DEV SEL * DATA OUT 1

R/W

ACK

NO ACK

DATA OUT N

AI00794C

Note:

* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

put, but MUST generate a STOP condition. The

output data is from consecutive byte addresses,

with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address

counter will ’roll- over’andthememory willcontinue

to output data.

Acknowledge in Read Mode. In all read modes

the ST24/25x16 wait for an acknowledge during the

9th bit time. If the master does not pull the SDAline

low during this time, the ST24/25x16 terminate the

data transfer and switches to a standby state.

13/17

ST24/25C16, ST24/25W16

ORDERING INFORMATION SCHEME

Example:

ST24C16

Operating Voltage

24 4.5V to 5.5V

25 2.5V to 5.5V

Range

Package

Temperature Range

Option

Standard

PSDIP8

0.25mm Frame

0 to 70 °C

TR Tape & Reel

Packing

W Hardware

Write Control

–40 to 85 °C

SO8

150mil Width

3 ⁽¹⁾–40 to 125 °C

Note: 1. Temperature range on special request only.

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect

of this device, please contact the STMicroelectronics Sales Office nearest to you.

14/17

ST24/25C16, ST24/25W16

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

Min

3.90

0.49

3.30

0.36

1.15

0.20

9.20

–

inches

Min

Symb

Typ

Max

5.90

–

Typ

Max

0.232

–

0.154

0.019

0.130

0.014

0.045

0.008

0.362

–

5.30

0.56

1.65

0.36

9.90

–

0.209

0.022

0.065

0.014

0.390

–

7.62

2.54

0.300

0.100

6.00

–

6.70

–

0.236

–

0.264

–

7.80

–

0.307

–

10.00

3.80

0.394

0.150

3.00

0.118

PSDIP-a

Drawing is not to scale.

15/17

ST24/25C16, ST24/25W16

SO8 - 8 lead Plastic Small Outline, 150 mils body width

Min

1.35

0.10

0.33

0.19

4.80

3.80

–

inches

Min

Symb

Typ

Max

1.75

0.25

0.51

0.25

5.00

4.00

–

Typ

Max

0.069

0.010

0.020

0.010

0.197

0.157

–

0.053

0.004

0.013

0.007

0.189

0.150

–

1.27

0.050

5.80

0.25

0.40

0°

6.20

0.50

0.90

8°

0.228

0.010

0.016

0°

0.244

0.020

0.035

8°

0.10

0.004

h x 45˚

SO-a

Drawing is not to scale.

16/17

ST24/25C16, ST24/25W16

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

All other names are the property of their respective owners

Purchase of I²C Components by STMicroelectronics, conveys a license under the Philips

I²C Patent. Rights to use these components in an I²C system, is granted provided that the system conforms to

the I²C Standard Specifications as defined by Philips.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

http://www.st.com

17/17

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