ST25E64EB6TR [STMICROELECTRONICS]
SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM; 串行扩展寻址采用I2C总线兼容64K （ 8K ×8 ） EEPROM
| 型号： | ST25E64EB6TR |
| 厂家： | 
ST |
| 描述： | SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM |
| 文件： | 总16页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST24E64
ST25E64
SERIAL EXTENDED ADDRESSING COMPATIBLE
WITH I2C BUS 64K (8K x 8) EEPROM
PRELIMINARY DATA
COMPATIBLE with I2C EXTENDED
ADDRESSING
TWO WIRE SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
1 MILLION ERASE/WRITE CYCLES, OVER
the FULL SUPPLYVOLTAGE RANGE
8
8
40 YEARS DATA RETENTION
1
1
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST24E64 version
– 2.5V to 5.5V for ST25E64 version
WRITE CONTROL FEATURE
PSDIP8 (B)
0.25mm Frame
SO8 (M)
200mil Width
BYTE and PAGE WRITE (up to 32 BYTES)
BYTE, RANDOM and SEQUENTIALREAD
MODES
Figure 1. Logic Diagram
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
V
CC
DESCRIPTION
3
The ST24/25E64 are 64K bit electrically erasable
programmable memories (EEPROM), organized
as8 blocksof 1024x 8 bits.The ST25E64operates
with a power supply value as low as 2.5V. Both
PlasticDual-in-LineandPlasticSmallOutlinepack-
ages are available.
E0-E2
SDA
ST24E64
ST25E64
SCL
WC
Table 1. Signal Names
V
SS
E0 - E2
SDA
SCL
WC
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
AI01204B
Write Control
VCC
Supply Voltage
VSS
Ground
November 1996
1/16
This is preliminaryinformation on a new product now in development or undergoing evaluation.Details are subject to change without notice.
ST24E64, ST25E64
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24E64
ST25E64
ST24E64
ST25E64
E0
E1
E2
1
2
3
4
8
V
E0
E1
E2
1
2
3
4
8
V
CC
WC
CC
7
WC
7
6
5
SCL
SDA
6
5
SCL
SDA
V
V
SS
SS
AI01205B
AI01206C
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
°C
Ambient Operating Temperature
Storage Temperature
–40 to 125
–65 to 150
TSTG
°C
TLEAD
Lead Temperature, Soldering
(SO8)
(PSDIP8)
40 sec
10 sec
215
260
°C
VIO
Input or Output Voltages
Supply Voltage
–0.6 to 6.5
–0.3 to 6.5
4000
V
V
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
VESD
500
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above thoseindicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and
other relevantquality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
3. 200pF through 0Ω; EIAJ IC-121 (condition C)
DESCRIPTION (cont’d)
slave devices in the I2C protocol with all memory
operationssynchronized by the serial clock. Read
and write operations are initiated by a START
conditiongeneratedbythebus master. TheSTART
conditionis followed by a stream of 4 bits(identifi-
cation code 1010), 3 bit Chip Enable input to form
a 7 bit Device Select, plus one read/write bit and
terminatedby an acknowledgebit.
Each memory is compatible with the I2C extended
addressing standard, two wire serial interface
which uses a bi-directional data bus and serial
clock. The ST24/25E64carrya built-in 4 bit, unique
device identification code (1010) corresponding to
the I2C bus definition. The ST24/25E64behave as
2/16
ST24E64, ST25E64
Table 3. Device Select Code
Device Code
Chip Enable
RW
b0
Bit
b7
1
b6
0
b5
b4
0
b3
E2
b2
E1
b1
E0
Device Select
1
RW
Note: The MSB b7 is sent first.
Table 4. Operating Modes
Mode
RW bit
’1’
Bytes
Initial Sequence
Current Address Read
1
1
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
As CURRENT or RANDOM Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
’0’
Random Address Read
’1’
Sequential Read
Byte Write
’1’
1 to 8192
’0’
1
Page Write
’0’
32
When writing data tothe memory it respondsto the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledgesthe receiptof the data
bytes in the same way.
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3)
Serial Data (SDA). The SDA pin is bi-directional
and is usedto transferdatain or out ofthe memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus.Aresistormust beconnectedfromtheSDA
bus line to VCC to act as pull up (see Figure 3).
Data transfers are terminated with a STOP condi-
tion. In this way, up to 8 ST24/25E64 may be
connectedto the same I2C bus and selected indi-
vidually, allowing a total addressing field of 512
Kbit.
Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits of the 7
bit deviceselectcode. They maybe driven dynami-
cally or tied to VCC or VSS to establish the device
select code. Note that the VIL and VIH levels for the
inputs are CMOS, not TTL compatible.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the VCC
voltage has reached the POR threshold value, the
internal reset is active: all operationsare disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
Write Control (WC). The Write Control feature
WC is useful to protectthe contentsof the memory
from any erroneous erase/write cycle. The Write
Control signal is used to enable (WC at VIH) or
disable (WC at VIL) the internal write protection.
When pin WC is unconnected, the WC input is
internally read as VIL (see Table 5).
When WC = ’1’, Device Select and Addressbytes
are acknowledged; Data bytes are not acknow-
ledged.
SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
3/16
ST24E64, ST25E64
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus, fC = 400kHz
20
V
CC
16
R
R
L
L
12
8
SDA
SCL
C
BUS
MASTER
C
BUS
4
0
V
= 5V
CC
25
50
75
100
C
(pF)
AI01115
BUS
DEVICE OPERATION
I2C Bus Background
STOP condition at the end of a Write command
triggersthe internalEEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfuldata transfer. The
bus transmitter, either master or slave, will release
the SDAbus aftersending8 bits of data. During the
9th clock pulse the receiver pulls the SDAbus low
to acknowledge the receipt of the 8 bits of data.
Data Input. During data input the ST24/25E64
sample the SDA bus signal on the rising edge of
the clock SCL. For correct device operation the
SDA signal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL line is low.
Device Selection. To start communication be-
tween the bus master and the slave ST24/25E64,
the master must initiate a START condition. The 8
bits sent after a STARTcondition aremade up of a
deviceselectof4bitsthat identifiesthe devicetype,
3 Chip Enable bits and one bit for a READ (RW =
1) or WRITE (RW = 0) operation. There are two
modes both for read and write. These are summa-
rised inTable 4 and described hereafter.Acommu-
nicationbetweenthemaster and theslaveis ended
with a STOP condition.
The ST24/25E64supportthe extendedaddressing
I2C protocol. This protocol defines any device that
sends data onto the bus as a transmitter and any
device that reads thedataas areceiver. Thedevice
that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The ST24/25E64
are always slave devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. ASTARTcondition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25E64con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOPis identifiedbya low tohigh
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25E64
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A
4/16
ST24E64, ST25E64
Table 5. Input Parameters (1) (TA = 25 °C, f = 400 kHz )
Symbol
CIN
Parameter
Input Capacitance (SDA)
Test Condition
Min
Max
8
Unit
pF
CIN
Input Capacitance (other pins)
WC Input Impedance
6
pF
ZWCL
ZWCH
V
V
IN ≤ 0.3 VCC
IN ≥ 0.7 VCC
5
20
kΩ
kΩ
WC Input Impedance
500
Low-pass filter input time constant
(SDA and SCL)
tLP
100
ns
Note: 1. Sampled only, not 100% tested.
Table 6. DC Characteristics
(TA = –40 to 85 °C or 0 to 70 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
Input Leakage Current
(SCL, SDA, E0-E2)
ILI
0V ≤ VIN ≤ VCC
±2
µA
0V ≤ VOUT ≤ VCC
ILO
Output Leakage Current
±2
µA
SDA in Hi-Z
Supply Current (ST24 series)
Supply Current (ST25 series)
2
1
mA
mA
f
C = 400kHz
ICC
(Rise/Fall time < 30ns)
V
IN = VSS or VCC
CC = 5V
,
,
100
300
5
µA
µA
µA
µA
V
Supply Current (Standby)
(ST24 series)
ICC1
VIN = VSS or VCC
CC = 5V, fC = 400kHz
V
V
IN = VSS or VCC
CC = 2.5V
,
V
Supply Current (Standby)
(ST25 series)
ICC2
VIN = VSS or VCC
CC = 2.5V, fC = 400kHz
,
50
V
VIL
VIH
VIL
VIH
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
Input Low Voltage (E0-E2, WC)
Input High Voltage (E0-E2, WC)
Output Low Voltage
–0.3
0.7 VCC
–0.3
0.3 VCC
VCC + 1
0.5
V
V
V
V
V
V
VCC – 0.5
VCC + 1
0.4
IOL = 3mA, VCC = 5V
IOL = 2.1mA, VCC = 2.5V
VOL
Output Low Voltage (ST25 series)
0.4
5/16
ST24E64, ST25E64
Table 7. AC Characteristics
(TA = –40 to 85 °C or 0 to 70 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
tCH1CH2
tCL1CL2
Alt
tR
Parameter
Min
Max
300
300
300
300
Unit
ns
Clock Rise Time
Clock Fall Time
SDA Rise Time
SDA Fall Time
tF
ns
(1)
tDH1DH2
tR
20
20
ns
(1)
tDL1DL1
tF
ns
(2)
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tDXCX
tCHDH
tDHDL
tSU:STA
tHIGH
tHD:STA
tHD:DAT
tLOW
tSU:DAT
tSU:STO
tBUF
tAA
Clock High to Input Transition
Clock Pulse Width High
600
600
600
0
ns
ns
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
ns
µs
µs
ns
1.3
100
600
1.3
200
200
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
Data Out Hold Time
ns
µs
ns
(3)
tCLQV
tCLQX
fC
1000
tDH
ns
fSCL
tWR
Clock Frequency
400
10
kHz
ms
tW
Write Time
Notes: 1. Sampled only, not 100% tested.
2. For a reSTART condition, or following a write cycle.
3. The minimum value delays the falling/rising edge of SDAaway from SCL= 1 in order to avoid unwanted STARTand/or STOP
conditions.
AC MEASUREMENT CONDITIONS
DEVICE OPERATION (cont’d)
Memory Addressing. A data byte in the memory
is addressed through 2 bytes of address informa-
tion. The Most Significant Byte is sent first and the
Least significant Byte is sent after. The Least Sig-
nificant Byte addresses a block of 256 bytes, bits
b12,b11,b10,b9,b8 of the Most Significant Byte
selectoneblock among32 blocks(one blockis 256
bytes).
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
Most Significant Byte
0.8V
CC
X
X
X
b12
b11
b3
b10
b2
b9
b1
b8
b0
0.7V
CC
X = Don’t Care.
0.3V
CC
0.2V
CC
Least Significant Byte
AI00825
b7
b6
b5
b4
6/16
ST24E64, ST25E64
Figure 5. AC Waveforms
tCHCL
tDLCL
tCLCH
SCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
START
CONDITION
SDA
STOP &
BUS FREE
INPUT CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
tDHDL
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
WRITE CYCLE
START
CONDITION
CONDITION
AI00795
7/16
ST24E64, ST25E64
Figure 6. I2C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
Write Operations
ST24/25E64. The master then terminates the
transfer by generating a STOP condition.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
ST24/25E64 acknowledge this and waits for 2
bytes of address. These 2 address bytes (8 bits
each) provide access to any ofthe 32 blocksof 256
bytes each. Writing in the ST24/25E64 may be
inhibited if input pin WC is taken high.
For the ST24/25E64versions, any write command
with WC = ’1’ (during a period of time from the
START condition untill the end of the 2 Bytes
Address) will not modify data and will NOT be
acknowledgedon data bytes, as in Figure 9.
Page Write. The Page Write mode allows up to 32
bytes to be written in a single write cycle, provided
that theyare all located in the same rowof 32 bytes
in the memory, that is the same Address bits (b12
tob5). Themastersendsone upto32 bytesofdata,
which are eachacknowledgedbythe ST24/25E64.
After each byte is transfered, the internal byte
address counter (5 Least Significant Bits only) is
incremented. The transfer is terminated by the
master generatingaSTOPcondition.Caremust be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that for
any write mode, the generationbythe masterofthe
STOP condition starts the internal memory pro-
Byte Write. In the Byte Write mode the master
sendsonedatabyte, whichis acknowledgedby the
8/16
ST24E64, ST25E64
gram cycle. This STOP condition will trigger an
internal memory program cycle only if the STOP
condition is internally decoded right after the ACK
bit; any STOP condition decoded out of this ”10th
bit” time slot will not trigger the internal program-
mingcycle. All inputs aredisableduntil the comple-
tion of this cycle and the ST24/25E64 will not
respond to any request.
Minimizing System Delay by Polling On ACK.
During the internal Write cycle, the ST24/25E64
disable itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value oftheWrite time (tW) is given in the
AC Characteristics table, this timing value may be
reducedby an ACKpolling sequenceissued by the
master.
The sequenceis:
– Initial condition: a Write is in progress (see Fig-
ure 7).
– Step 1: the Master issues a STARTcondition
followed by a Device Select byte. (1st byte of
the newinstruction)
– Step 2: if the ST24/25E64are internally writ-
ing, no ACK will be returned. The Master goes
back to Step1. If the ST24/25E64have termi-
nated the internal writing, it will issue an ACK.
The ST24/25E64are ready to receive the sec-
ond part of the instruction (the first byte of this
instruction was already sent during Step1).
Figure 7. Write Cycle Polling using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by ST24xxx
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01099B
9/16
ST24E64, ST25E64
Figure 8. Write Modes Sequence with Write Control = 0
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont’d)
ACK
ACK
PAGE WRITE
(cont’d)
DATA IN N
AI01106
Read Operations
On delivery, the memory content is set at all ”1’s”
(or FFh).
Random Address Read. A dummy write is per-
formed to load the address into the address
counter,see Figure 10. This is followed by another
START condition from the master and the byte
address repeated with the RW bit set to ’1’. The
ST24/25E64 acknowledge this and outputs the
byte addressed. The master does NOT acknow-
ledge the byte output, but terminates the transfer
with a STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
ST24/25E64 continue to output the next byte in
Current Address Read. The ST24/25E64 have
an internal 13 bits address counter. Each time a
byte is read, this counter is incremented. For the
Current Address Read mode, following a START
condition, the master sends a Device Select with
theRWbit setto’1’.The ST24/25E64acknowledge
this and outputs the byte addressedby the internal
addresscounter.This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOPcon-
dition.
10/16
ST24E64, ST25E64
Figure 9. Write Modes Sequence with Write Control = 1
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont’d)
NO ACK
NO ACK
PAGE WRITE
(cont’d)
DATA IN N
AI01120
sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counterwill ’roll-over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25E64 wait for an acknowledge during
the 9th bit time. If the master does not pull the SDA
linelow duringthis time, the ST24/25E64terminate
the data transferand switch to a standbystate.
11/16
ST24E64, ST25E64
Figure 10. Read Modes Sequence
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105B
Note:
* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 4th byte) must be identical.
12/16
ST24E64, ST25E64
ORDERING INFORMATION SCHEME
Example:
ST24E64
M
1
TR
Operating Voltage
24 4.5V to 5.5V
25 2.5V to 5.5V
Range
Package
Temperature Range
Option
E
Extended
Addressing
B
PSDIP8
0.25mm Frame
1
6
0 to 70 °C
TR Tape & Reel
Packing
–40 to 85 °C
M
SO8
200mil Width
3 * –40 to 125 °C
Note: 3 * Temperature Range on special request only.
Parts are shipped with the memory content set at all ”1’s” (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
13/16
ST24E64, ST25E64
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
Min
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
inches
Min
Symb
Typ
Max
5.90
–
Typ
Max
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
PSDIP8
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not o scale
14/16
ST24E64, ST25E64
SO8 - 8 lead Plastic Small Outline, 200 mils body width
mm
Min
inches
Symb
Typ
Max
2.03
0.25
1.78
0.45
–
Typ
Min
Max
0.080
0.010
0.070
0.018
–
A
A1
A2
B
0.10
0.004
0.35
–
0.014
–
C
0.20
1.27
0.008
0.050
D
5.15
5.20
–
5.35
5.40
–
0.203
0.205
–
0.211
0.213
–
E
e
H
7.70
0.50
0°
8.10
0.80
10°
0.303
0.020
0°
0.319
0.031
10°
L
α
N
8
8
CP
0.10
0.004
SO8b
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale
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ST24E64, ST25E64
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent.Rights to use these components in an I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
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